drivers/hwmon/ath_mn_lm95071.h

#ifndef __ATH_MN_LM95071_H__
#define __ATH_MN_LM95071_H__

#define ATH_MN_TEMP_SENSOR_PIN (1 << 14)
#define ATH_SPI_CE_LOW  0x60000
#define ATH_SPI_CE_HIGH 0x60100
#define ATH_SPI_SC_UDELAY 200
#define ATH_MUX_SPI_CS_0 0x9  /* SPI_CS_0 signal on QCA mux. */

#define LM_MODE_SD 0xFF  /* shutdown mode */
#define LM_MODE_CC 0x00  /* continuous conversion */

#define lm_delay() udelay(ATH_SPI_SC_UDELAY)

#define lm_be_msb(_val, __i) (((_val) & (1 << (7 - __i))) >> (7 - __i))

#define lm_spi_bit_banger(_byte) do { \
  int _i; \
  for (_i = 0; _i < 8; ++_i) { \
    ath_reg_wr_nf(ATH_SPI_WRITE, ATH_SPI_CE_HIGH | lm_be_msb(_byte, _i)); \
    lm_delay(); \
    ath_reg_wr_nf(ATH_SPI_WRITE, ATH_SPI_CE_LOW | lm_be_msb(_byte, _i)); \
    lm_delay(); \
  } \
} while (0)

/*
 * Clears out signals on GPIO pins 14/5.
 */
#define lm_spi_func_clear() do { \
  ath_reg_rmw_clear(ATH_GPIO_OUT_FUNCTION1, GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MASK); \
  ath_reg_rmw_clear(ATH_GPIO_OUT_FUNCTION3, GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MASK); \
} while (0)

/* Reenables GPIO pin 5 to functions as CS_0 signal. */
#define lm_spi_func_restore() do { \
  ath_reg_rmw_set(ATH_GPIO_OUT_FUNCTION1, \
                  ATH_GPIO_OUT_FUNCTION1_ENABLE_GPIO_5(ATH_MUX_SPI_CS_0)); \
} while (0)

#define lm_spi_delay_8() lm_spi_bit_banger(0)

#define lm_spi_delay_16() do { \
  lm_spi_delay_8(); \
  lm_spi_delay_8(); \
} while (0);

#define lm_spi_rd_16() (ath_reg_rd(ATH_SPI_RD_STATUS) & 0xFFFF)

#define lm_temp_rd() ((lm_spi_rd_16()) / 4 * 3125)

#endif  // __ATH_MN_LM95071_H__