| perf-list(1) |
| ============ |
| |
| NAME |
| ---- |
| perf-list - List all symbolic event types |
| |
| SYNOPSIS |
| -------- |
| [verse] |
| 'perf list' |
| |
| DESCRIPTION |
| ----------- |
| This command displays the symbolic event types which can be selected in the |
| various perf commands with the -e option. |
| |
| RAW HARDWARE EVENT DESCRIPTOR |
| ----------------------------- |
| Even when an event is not available in a symbolic form within perf right now, |
| it can be encoded in a per processor specific way. |
| |
| For instance For x86 CPUs NNN represents the raw register encoding with the |
| layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout |
| of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344, |
| Figure 13-7 Performance Event-Select Register (PerfEvtSeln)). |
| |
| Example: |
| |
| If the Intel docs for a QM720 Core i7 describe an event as: |
| |
| Event Umask Event Mask |
| Num. Value Mnemonic Description Comment |
| |
| A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and |
| delivered by loop stream detector invert to count |
| cycles |
| |
| raw encoding of 0x1A8 can be used: |
| |
| perf stat -e r1a8 -a sleep 1 |
| perf record -e r1a8 ... |
| |
| You should refer to the processor specific documentation for getting these |
| details. Some of them are referenced in the SEE ALSO section below. |
| |
| OPTIONS |
| ------- |
| None |
| |
| SEE ALSO |
| -------- |
| linkperf:perf-stat[1], linkperf:perf-top[1], |
| linkperf:perf-record[1], |
| http://www.intel.com/Assets/PDF/manual/253669.pdf[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide], |
| http://support.amd.com/us/Processor_TechDocs/24593.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming] |
