arch/arm/boot/dts/bcm5301x.dtsi - kernel/quantenna - Git at Google

 /*
  * Broadcom BCM470X / BCM5301X ARM platform code.
  * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
  * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
  *
  * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
  *
  * Licensed under the GNU/GPL. See COPYING for details.
  */

 #include <dt-bindings/clock/bcm-nsp.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include "skeleton.dtsi"

 / {
 	interrupt-parent = <&gic>;

 	chosen {
 		stdout-path = &uart0;
 	};

 	chipcommonA {
 		compatible = "simple-bus";
 		ranges = <0x00000000 0x18000000 0x00001000>;
 		#address-cells = <1>;
 		#size-cells = <1>;

 		uart0: serial@0300 {
 			compatible = "ns16550";
 			reg = <0x0300 0x100>;
 			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&iprocslow>;
 			status = "disabled";
 		};

 		uart1: serial@0400 {
 			compatible = "ns16550";
 			reg = <0x0400 0x100>;
 			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&iprocslow>;
 			status = "disabled";
 		};
 	};

 	mpcore {
 		compatible = "simple-bus";
 		ranges = <0x00000000 0x19000000 0x00023000>;
 		#address-cells = <1>;
 		#size-cells = <1>;

 		a9pll: arm_clk@00000 {
 			#clock-cells = <0>;
 			compatible = "brcm,nsp-armpll";
 			clocks = <&osc>;
 			reg = <0x00000 0x1000>;
 		};

 		scu@20000 {
 			compatible = "arm,cortex-a9-scu";
 			reg = <0x20000 0x100>;
 		};

 		timer@20200 {
 			compatible = "arm,cortex-a9-global-timer";
 			reg = <0x20200 0x100>;
 			interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&periph_clk>;
 		};

 		local-timer@20600 {
 			compatible = "arm,cortex-a9-twd-timer";
 			reg = <0x20600 0x100>;
 			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&periph_clk>;
 		};

 		gic: interrupt-controller@21000 {
 			compatible = "arm,cortex-a9-gic";
 			#interrupt-cells = <3>;
 			#address-cells = <0>;
 			interrupt-controller;
 			reg = <0x21000 0x1000>,
 			      <0x20100 0x100>;
 		};

 		L2: cache-controller@22000 {
 			compatible = "arm,pl310-cache";
 			reg = <0x22000 0x1000>;
 			cache-unified;
 			arm,shared-override;
 			prefetch-data = <1>;
 			prefetch-instr = <1>;
 			cache-level = <2>;
 		};
 	};

 	pmu {
 		compatible = "arm,cortex-a9-pmu";
 		interrupts =
 			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 	};

 	clocks {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;

 		osc: oscillator {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <25000000>;
 		};

 		iprocmed: iprocmed {
 			#clock-cells = <0>;
 			compatible = "fixed-factor-clock";
 			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
 			clock-div = <2>;
 			clock-mult = <1>;
 		};

 		iprocslow: iprocslow {
 			#clock-cells = <0>;
 			compatible = "fixed-factor-clock";
 			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
 			clock-div = <4>;
 			clock-mult = <1>;
 		};

 		periph_clk: periph_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-factor-clock";
 			clocks = <&a9pll>;
 			clock-div = <2>;
 			clock-mult = <1>;
 		};
 	};

 	axi@18000000 {
 		compatible = "brcm,bus-axi";
 		reg = <0x18000000 0x1000>;
 		ranges = <0x00000000 0x18000000 0x00100000>;
 		#address-cells = <1>;
 		#size-cells = <1>;

 		#interrupt-cells = <1>;
 		interrupt-map-mask = <0x000fffff 0xffff>;
 		interrupt-map =
 			/* ChipCommon */
 			<0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,

 			/* PCIe Controller 0 */
 			<0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,

 			/* PCIe Controller 1 */
 			<0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,

 			/* PCIe Controller 2 */
 			<0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,

 			/* USB 2.0 Controller */
 			<0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,

 			/* USB 3.0 Controller */
 			<0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,

 			/* Ethernet Controller 0 */
 			<0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,

 			/* Ethernet Controller 1 */
 			<0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

 			/* Ethernet Controller 2 */
 			<0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,

 			/* Ethernet Controller 3 */
 			<0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,

 			/* NAND Controller */
 			<0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;

 		chipcommon: chipcommon@0 {
 			reg = <0x00000000 0x1000>;

 			gpio-controller;
 			#gpio-cells = <2>;
 		};

 		usb2: usb2@21000 {
 			reg = <0x00021000 0x1000>;

 			#address-cells = <1>;
 			#size-cells = <1>;
 		};

 		usb3: usb3@23000 {
 			reg = <0x00023000 0x1000>;

 			#address-cells = <1>;
 			#size-cells = <1>;
 		};

 		spi@29000 {
 			reg = <0x00029000 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <0>;

 			spi_nor: spi-nor@0 {
 				compatible = "jedec,spi-nor";
 				reg = <0>;
 				spi-max-frequency = <20000000>;
 				linux,part-probe = "ofpart", "bcm47xxpart";
 				status = "disabled";
 			};
 		};
 	};

 	lcpll0: lcpll0@1800c100 {
 		#clock-cells = <1>;
 		compatible = "brcm,nsp-lcpll0";
 		reg = <0x1800c100 0x14>;
 		clocks = <&osc>;
 		clock-output-names = "lcpll0", "pcie_phy", "sdio",
 				     "ddr_phy";
 	};

 	genpll: genpll@1800c140 {
 		#clock-cells = <1>;
 		compatible = "brcm,nsp-genpll";
 		reg = <0x1800c140 0x24>;
 		clocks = <&osc>;
 		clock-output-names = "genpll", "phy", "ethernetclk",
 				     "usbclk", "iprocfast", "sata1",
 				     "sata2";
 	};

 	nand: nand@18028000 {
 		compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
 		reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
 		reg-names = "nand", "iproc-idm", "iproc-ext";
 		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;

 		#address-cells = <1>;
 		#size-cells = <0>;

 		brcm,nand-has-wp;
 	};
 };
	/*
	* Broadcom BCM470X / BCM5301X ARM platform code.
	* Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
	* BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
	*
	* Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
	*
	* Licensed under the GNU/GPL. See COPYING for details.
	*/

	#include <dt-bindings/clock/bcm-nsp.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include "skeleton.dtsi"

	/ {
	interrupt-parent = <&gic>;

	chosen {
	stdout-path = &uart0;
	};

	chipcommonA {
	compatible = "simple-bus";
	ranges = <0x00000000 0x18000000 0x00001000>;
	#address-cells = <1>;
	#size-cells = <1>;

	uart0: serial@0300 {
	compatible = "ns16550";
	reg = <0x0300 0x100>;
	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&iprocslow>;
	status = "disabled";
	};

	uart1: serial@0400 {
	compatible = "ns16550";
	reg = <0x0400 0x100>;
	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&iprocslow>;
	status = "disabled";
	};
	};

	mpcore {
	compatible = "simple-bus";
	ranges = <0x00000000 0x19000000 0x00023000>;
	#address-cells = <1>;
	#size-cells = <1>;

	a9pll: arm_clk@00000 {
	#clock-cells = <0>;
	compatible = "brcm,nsp-armpll";
	clocks = <&osc>;
	reg = <0x00000 0x1000>;
	};

	scu@20000 {
	compatible = "arm,cortex-a9-scu";
	reg = <0x20000 0x100>;
	};

	timer@20200 {
	compatible = "arm,cortex-a9-global-timer";
	reg = <0x20200 0x100>;
	interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&periph_clk>;
	};

	local-timer@20600 {
	compatible = "arm,cortex-a9-twd-timer";
	reg = <0x20600 0x100>;
	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&periph_clk>;
	};

	gic: interrupt-controller@21000 {
	compatible = "arm,cortex-a9-gic";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0x21000 0x1000>,
	<0x20100 0x100>;
	};

	L2: cache-controller@22000 {
	compatible = "arm,pl310-cache";
	reg = <0x22000 0x1000>;
	cache-unified;
	arm,shared-override;
	prefetch-data = <1>;
	prefetch-instr = <1>;
	cache-level = <2>;
	};
	};

	pmu {
	compatible = "arm,cortex-a9-pmu";
	interrupts =
	<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	clocks {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	osc: oscillator {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <25000000>;
	};

	iprocmed: iprocmed {
	#clock-cells = <0>;
	compatible = "fixed-factor-clock";
	clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
	clock-div = <2>;
	clock-mult = <1>;
	};

	iprocslow: iprocslow {
	#clock-cells = <0>;
	compatible = "fixed-factor-clock";
	clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
	clock-div = <4>;
	clock-mult = <1>;
	};

	periph_clk: periph_clk {
	#clock-cells = <0>;
	compatible = "fixed-factor-clock";
	clocks = <&a9pll>;
	clock-div = <2>;
	clock-mult = <1>;
	};
	};

	axi@18000000 {
	compatible = "brcm,bus-axi";
	reg = <0x18000000 0x1000>;
	ranges = <0x00000000 0x18000000 0x00100000>;
	#address-cells = <1>;
	#size-cells = <1>;

	#interrupt-cells = <1>;
	interrupt-map-mask = <0x000fffff 0xffff>;
	interrupt-map =
	/* ChipCommon */
	<0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,

	/* PCIe Controller 0 */
	<0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	<0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
	<0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
	<0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
	<0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
	<0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,

	/* PCIe Controller 1 */
	<0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
	<0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
	<0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
	<0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
	<0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
	<0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,

	/* PCIe Controller 2 */
	<0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
	<0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
	<0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
	<0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
	<0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,

	/* USB 2.0 Controller */
	<0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,

	/* USB 3.0 Controller */
	<0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,

	/* Ethernet Controller 0 */
	<0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,

	/* Ethernet Controller 1 */
	<0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

	/* Ethernet Controller 2 */
	<0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,

	/* Ethernet Controller 3 */
	<0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,

	/* NAND Controller */
	<0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
	<0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
	<0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
	<0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
	<0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	<0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
	<0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
	<0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;

	chipcommon: chipcommon@0 {
	reg = <0x00000000 0x1000>;

	gpio-controller;
	#gpio-cells = <2>;
	};

	usb2: usb2@21000 {
	reg = <0x00021000 0x1000>;

	#address-cells = <1>;
	#size-cells = <1>;
	};

	usb3: usb3@23000 {
	reg = <0x00023000 0x1000>;

	#address-cells = <1>;
	#size-cells = <1>;
	};

	spi@29000 {
	reg = <0x00029000 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;

	spi_nor: spi-nor@0 {
	compatible = "jedec,spi-nor";
	reg = <0>;
	spi-max-frequency = <20000000>;
	linux,part-probe = "ofpart", "bcm47xxpart";
	status = "disabled";
	};
	};
	};

	lcpll0: lcpll0@1800c100 {
	#clock-cells = <1>;
	compatible = "brcm,nsp-lcpll0";
	reg = <0x1800c100 0x14>;
	clocks = <&osc>;
	clock-output-names = "lcpll0", "pcie_phy", "sdio",
	"ddr_phy";
	};

	genpll: genpll@1800c140 {
	#clock-cells = <1>;
	compatible = "brcm,nsp-genpll";
	reg = <0x1800c140 0x24>;
	clocks = <&osc>;
	clock-output-names = "genpll", "phy", "ethernetclk",
	"usbclk", "iprocfast", "sata1",
	"sata2";
	};

	nand: nand@18028000 {
	compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
	reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
	reg-names = "nand", "iproc-idm", "iproc-ext";
	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;

	#address-cells = <1>;
	#size-cells = <0>;

	brcm,nand-has-wp;
	};
	};