| /* |
| * Copyright 2014 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| */ |
| #include <linux/firmware.h> |
| #include "drmP.h" |
| #include "amdgpu.h" |
| #include "amdgpu_gfx.h" |
| #include "vi.h" |
| #include "vid.h" |
| #include "amdgpu_ucode.h" |
| #include "amdgpu_atombios.h" |
| #include "atombios_i2c.h" |
| #include "clearstate_vi.h" |
| |
| #include "gmc/gmc_8_2_d.h" |
| #include "gmc/gmc_8_2_sh_mask.h" |
| |
| #include "oss/oss_3_0_d.h" |
| #include "oss/oss_3_0_sh_mask.h" |
| |
| #include "bif/bif_5_0_d.h" |
| #include "bif/bif_5_0_sh_mask.h" |
| |
| #include "gca/gfx_8_0_d.h" |
| #include "gca/gfx_8_0_enum.h" |
| #include "gca/gfx_8_0_sh_mask.h" |
| #include "gca/gfx_8_0_enum.h" |
| |
| #include "dce/dce_10_0_d.h" |
| #include "dce/dce_10_0_sh_mask.h" |
| |
| #include "smu/smu_7_1_3_d.h" |
| |
| #define GFX8_NUM_GFX_RINGS 1 |
| #define GFX8_NUM_COMPUTE_RINGS 8 |
| |
| #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001 |
| #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001 |
| #define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002 |
| #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003 |
| |
| #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) |
| #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) |
| #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) |
| #define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT) |
| #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT) |
| #define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT) |
| #define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT) |
| #define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT) |
| #define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT) |
| |
| #define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L |
| #define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L |
| #define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L |
| #define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L |
| #define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L |
| #define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L |
| |
| /* BPM SERDES CMD */ |
| #define SET_BPM_SERDES_CMD 1 |
| #define CLE_BPM_SERDES_CMD 0 |
| |
| /* BPM Register Address*/ |
| enum { |
| BPM_REG_CGLS_EN = 0, /* Enable/Disable CGLS */ |
| BPM_REG_CGLS_ON, /* ON/OFF CGLS: shall be controlled by RLC FW */ |
| BPM_REG_CGCG_OVERRIDE, /* Set/Clear CGCG Override */ |
| BPM_REG_MGCG_OVERRIDE, /* Set/Clear MGCG Override */ |
| BPM_REG_FGCG_OVERRIDE, /* Set/Clear FGCG Override */ |
| BPM_REG_FGCG_MAX |
| }; |
| |
| #define RLC_FormatDirectRegListLength 14 |
| |
| MODULE_FIRMWARE("amdgpu/carrizo_ce.bin"); |
| MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin"); |
| MODULE_FIRMWARE("amdgpu/carrizo_me.bin"); |
| MODULE_FIRMWARE("amdgpu/carrizo_mec.bin"); |
| MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin"); |
| MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin"); |
| |
| MODULE_FIRMWARE("amdgpu/stoney_ce.bin"); |
| MODULE_FIRMWARE("amdgpu/stoney_pfp.bin"); |
| MODULE_FIRMWARE("amdgpu/stoney_me.bin"); |
| MODULE_FIRMWARE("amdgpu/stoney_mec.bin"); |
| MODULE_FIRMWARE("amdgpu/stoney_rlc.bin"); |
| |
| MODULE_FIRMWARE("amdgpu/tonga_ce.bin"); |
| MODULE_FIRMWARE("amdgpu/tonga_pfp.bin"); |
| MODULE_FIRMWARE("amdgpu/tonga_me.bin"); |
| MODULE_FIRMWARE("amdgpu/tonga_mec.bin"); |
| MODULE_FIRMWARE("amdgpu/tonga_mec2.bin"); |
| MODULE_FIRMWARE("amdgpu/tonga_rlc.bin"); |
| |
| MODULE_FIRMWARE("amdgpu/topaz_ce.bin"); |
| MODULE_FIRMWARE("amdgpu/topaz_pfp.bin"); |
| MODULE_FIRMWARE("amdgpu/topaz_me.bin"); |
| MODULE_FIRMWARE("amdgpu/topaz_mec.bin"); |
| MODULE_FIRMWARE("amdgpu/topaz_rlc.bin"); |
| |
| MODULE_FIRMWARE("amdgpu/fiji_ce.bin"); |
| MODULE_FIRMWARE("amdgpu/fiji_pfp.bin"); |
| MODULE_FIRMWARE("amdgpu/fiji_me.bin"); |
| MODULE_FIRMWARE("amdgpu/fiji_mec.bin"); |
| MODULE_FIRMWARE("amdgpu/fiji_mec2.bin"); |
| MODULE_FIRMWARE("amdgpu/fiji_rlc.bin"); |
| |
| MODULE_FIRMWARE("amdgpu/polaris11_ce.bin"); |
| MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin"); |
| MODULE_FIRMWARE("amdgpu/polaris11_me.bin"); |
| MODULE_FIRMWARE("amdgpu/polaris11_mec.bin"); |
| MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin"); |
| MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin"); |
| |
| MODULE_FIRMWARE("amdgpu/polaris10_ce.bin"); |
| MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin"); |
| MODULE_FIRMWARE("amdgpu/polaris10_me.bin"); |
| MODULE_FIRMWARE("amdgpu/polaris10_mec.bin"); |
| MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin"); |
| MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin"); |
| |
| static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = |
| { |
| {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0}, |
| {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1}, |
| {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2}, |
| {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3}, |
| {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4}, |
| {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5}, |
| {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6}, |
| {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7}, |
| {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8}, |
| {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9}, |
| {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10}, |
| {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11}, |
| {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12}, |
| {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13}, |
| {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14}, |
| {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15} |
| }; |
| |
| static const u32 golden_settings_tonga_a11[] = |
| { |
| mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208, |
| mmCB_HW_CONTROL_3, 0x00000040, 0x00000040, |
| mmDB_DEBUG2, 0xf00fffff, 0x00000400, |
| mmGB_GPU_ID, 0x0000000f, 0x00000000, |
| mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, |
| mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc, |
| mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, |
| mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, |
| mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, |
| mmTCC_CTRL, 0x00100000, 0xf31fff7f, |
| mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, |
| mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb, |
| mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b, |
| mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876, |
| mmVGT_RESET_DEBUG, 0x00000004, 0x00000004, |
| }; |
| |
| static const u32 tonga_golden_common_all[] = |
| { |
| mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012, |
| mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A, |
| mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003, |
| mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, |
| mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, |
| mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, |
| mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF |
| }; |
| |
| static const u32 tonga_mgcg_cgcg_init[] = |
| { |
| mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, |
| mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100, |
| mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, |
| mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, |
| mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, |
| mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, |
| mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, |
| mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, |
| mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, |
| mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, |
| mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, |
| mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, |
| mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, |
| mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, |
| mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, |
| mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, |
| mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, |
| mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c, |
| mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, |
| }; |
| |
| static const u32 golden_settings_polaris11_a11[] = |
| { |
| mmCB_HW_CONTROL, 0xfffdf3cf, 0x00006208, |
| mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, |
| mmDB_DEBUG2, 0xf00fffff, 0x00000400, |
| mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, |
| mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, |
| mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012, |
| mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000, |
| mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c, |
| mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c, |
| mmSQ_CONFIG, 0x07f80000, 0x07180000, |
| mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, |
| mmTCC_CTRL, 0x00100000, 0xf31fff7f, |
| mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3, |
| mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, |
| mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210, |
| mmVGT_RESET_DEBUG, 0x00000004, 0x00000004, |
| }; |
| |
| static const u32 polaris11_golden_common_all[] = |
| { |
| mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002, |
| mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, |
| mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, |
| mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, |
| mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF, |
| }; |
| |
| static const u32 golden_settings_polaris10_a11[] = |
| { |
| mmATC_MISC_CG, 0x000c0fc0, 0x000c0200, |
| mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208, |
| mmCB_HW_CONTROL_2, 0, 0x0f000000, |
| mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, |
| mmDB_DEBUG2, 0xf00fffff, 0x00000400, |
| mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, |
| mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, |
| mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012, |
| mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a, |
| mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c, |
| mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c, |
| mmSQ_CONFIG, 0x07f80000, 0x07180000, |
| mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, |
| mmTCC_CTRL, 0x00100000, 0xf31fff7f, |
| mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7, |
| mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, |
| mmVGT_RESET_DEBUG, 0x00000004, 0x00000004, |
| }; |
| |
| static const u32 polaris10_golden_common_all[] = |
| { |
| mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012, |
| mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A, |
| mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003, |
| mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, |
| mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, |
| mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, |
| mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF, |
| }; |
| |
| static const u32 fiji_golden_common_all[] = |
| { |
| mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a, |
| mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e, |
| mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003, |
| mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, |
| mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, |
| mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, |
| mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF, |
| mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009, |
| }; |
| |
| static const u32 golden_settings_fiji_a10[] = |
| { |
| mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, |
| mmDB_DEBUG2, 0xf00fffff, 0x00000400, |
| mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, |
| mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, |
| mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c, |
| mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, |
| mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, |
| mmTCC_CTRL, 0x00100000, 0xf31fff7f, |
| mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, |
| mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff, |
| mmVGT_RESET_DEBUG, 0x00000004, 0x00000004, |
| }; |
| |
| static const u32 fiji_mgcg_cgcg_init[] = |
| { |
| mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, |
| mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100, |
| mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, |
| mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, |
| mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, |
| mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, |
| mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, |
| mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, |
| mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, |
| mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, |
| mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, |
| mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, |
| mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, |
| mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, |
| mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, |
| mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c, |
| mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, |
| }; |
| |
| static const u32 golden_settings_iceland_a11[] = |
| { |
| mmCB_HW_CONTROL_3, 0x00000040, 0x00000040, |
| mmDB_DEBUG2, 0xf00fffff, 0x00000400, |
| mmDB_DEBUG3, 0xc0000000, 0xc0000000, |
| mmGB_GPU_ID, 0x0000000f, 0x00000000, |
| mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, |
| mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, |
| mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002, |
| mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000, |
| mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, |
| mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, |
| mmTCC_CTRL, 0x00100000, 0xf31fff7f, |
| mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, |
| mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1, |
| mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, |
| mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010, |
| }; |
| |
| static const u32 iceland_golden_common_all[] = |
| { |
| mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002, |
| mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000, |
| mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001, |
| mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, |
| mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, |
| mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, |
| mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF |
| }; |
| |
| static const u32 iceland_mgcg_cgcg_init[] = |
| { |
| mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, |
| mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100, |
| mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100, |
| mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100, |
| mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, |
| mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, |
| mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, |
| mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, |
| mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, |
| mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, |
| mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, |
| mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100, |
| mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, |
| mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, |
| mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, |
| mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, |
| mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87, |
| mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87, |
| mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, |
| mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, |
| mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c, |
| }; |
| |
| static const u32 cz_golden_settings_a11[] = |
| { |
| mmCB_HW_CONTROL_3, 0x00000040, 0x00000040, |
| mmDB_DEBUG2, 0xf00fffff, 0x00000400, |
| mmGB_GPU_ID, 0x0000000f, 0x00000000, |
| mmPA_SC_ENHANCE, 0xffffffff, 0x00000001, |
| mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, |
| mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, |
| mmTA_CNTL_AUX, 0x000f000f, 0x00010000, |
| mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, |
| mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3, |
| mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302 |
| }; |
| |
| static const u32 cz_golden_common_all[] = |
| { |
| mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002, |
| mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000, |
| mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001, |
| mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, |
| mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, |
| mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, |
| mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF |
| }; |
| |
| static const u32 cz_mgcg_cgcg_init[] = |
| { |
| mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, |
| mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, |
| mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, |
| mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, |
| mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, |
| mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, |
| mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, |
| mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, |
| mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, |
| mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, |
| mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, |
| mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, |
| mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, |
| mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, |
| mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, |
| mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, |
| mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, |
| mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, |
| mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, |
| }; |
| |
| static const u32 stoney_golden_settings_a11[] = |
| { |
| mmDB_DEBUG2, 0xf00fffff, 0x00000400, |
| mmGB_GPU_ID, 0x0000000f, 0x00000000, |
| mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, |
| mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, |
| mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c, |
| mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, |
| mmTCC_CTRL, 0x00100000, 0xf31fff7f, |
| mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, |
| mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1, |
| mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010, |
| }; |
| |
| static const u32 stoney_golden_common_all[] = |
| { |
| mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000, |
| mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000, |
| mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001, |
| mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, |
| mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, |
| mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, |
| mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF, |
| }; |
| |
| static const u32 stoney_mgcg_cgcg_init[] = |
| { |
| mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, |
| mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201, |
| mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201, |
| mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, |
| mmATC_MISC_CG, 0xffffffff, 0x000c0200, |
| }; |
| |
| static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev); |
| static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev); |
| static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev); |
| static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev); |
| static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev); |
| static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev); |
| |
| static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) |
| { |
| switch (adev->asic_type) { |
| case CHIP_TOPAZ: |
| amdgpu_program_register_sequence(adev, |
| iceland_mgcg_cgcg_init, |
| (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); |
| amdgpu_program_register_sequence(adev, |
| golden_settings_iceland_a11, |
| (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); |
| amdgpu_program_register_sequence(adev, |
| iceland_golden_common_all, |
| (const u32)ARRAY_SIZE(iceland_golden_common_all)); |
| break; |
| case CHIP_FIJI: |
| amdgpu_program_register_sequence(adev, |
| fiji_mgcg_cgcg_init, |
| (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); |
| amdgpu_program_register_sequence(adev, |
| golden_settings_fiji_a10, |
| (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); |
| amdgpu_program_register_sequence(adev, |
| fiji_golden_common_all, |
| (const u32)ARRAY_SIZE(fiji_golden_common_all)); |
| break; |
| |
| case CHIP_TONGA: |
| amdgpu_program_register_sequence(adev, |
| tonga_mgcg_cgcg_init, |
| (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); |
| amdgpu_program_register_sequence(adev, |
| golden_settings_tonga_a11, |
| (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); |
| amdgpu_program_register_sequence(adev, |
| tonga_golden_common_all, |
| (const u32)ARRAY_SIZE(tonga_golden_common_all)); |
| break; |
| case CHIP_POLARIS11: |
| amdgpu_program_register_sequence(adev, |
| golden_settings_polaris11_a11, |
| (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); |
| amdgpu_program_register_sequence(adev, |
| polaris11_golden_common_all, |
| (const u32)ARRAY_SIZE(polaris11_golden_common_all)); |
| break; |
| case CHIP_POLARIS10: |
| amdgpu_program_register_sequence(adev, |
| golden_settings_polaris10_a11, |
| (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); |
| amdgpu_program_register_sequence(adev, |
| polaris10_golden_common_all, |
| (const u32)ARRAY_SIZE(polaris10_golden_common_all)); |
| WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C); |
| if (adev->pdev->revision == 0xc7) { |
| amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1E, 0xDD); |
| amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1F, 0xD0); |
| } |
| break; |
| case CHIP_CARRIZO: |
| amdgpu_program_register_sequence(adev, |
| cz_mgcg_cgcg_init, |
| (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); |
| amdgpu_program_register_sequence(adev, |
| cz_golden_settings_a11, |
| (const u32)ARRAY_SIZE(cz_golden_settings_a11)); |
| amdgpu_program_register_sequence(adev, |
| cz_golden_common_all, |
| (const u32)ARRAY_SIZE(cz_golden_common_all)); |
| break; |
| case CHIP_STONEY: |
| amdgpu_program_register_sequence(adev, |
| stoney_mgcg_cgcg_init, |
| (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); |
| amdgpu_program_register_sequence(adev, |
| stoney_golden_settings_a11, |
| (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); |
| amdgpu_program_register_sequence(adev, |
| stoney_golden_common_all, |
| (const u32)ARRAY_SIZE(stoney_golden_common_all)); |
| break; |
| default: |
| break; |
| } |
| } |
| |
| static void gfx_v8_0_scratch_init(struct amdgpu_device *adev) |
| { |
| int i; |
| |
| adev->gfx.scratch.num_reg = 7; |
| adev->gfx.scratch.reg_base = mmSCRATCH_REG0; |
| for (i = 0; i < adev->gfx.scratch.num_reg; i++) { |
| adev->gfx.scratch.free[i] = true; |
| adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i; |
| } |
| } |
| |
| static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring) |
| { |
| struct amdgpu_device *adev = ring->adev; |
| uint32_t scratch; |
| uint32_t tmp = 0; |
| unsigned i; |
| int r; |
| |
| r = amdgpu_gfx_scratch_get(adev, &scratch); |
| if (r) { |
| DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); |
| return r; |
| } |
| WREG32(scratch, 0xCAFEDEAD); |
| r = amdgpu_ring_alloc(ring, 3); |
| if (r) { |
| DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", |
| ring->idx, r); |
| amdgpu_gfx_scratch_free(adev, scratch); |
| return r; |
| } |
| amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); |
| amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); |
| amdgpu_ring_write(ring, 0xDEADBEEF); |
| amdgpu_ring_commit(ring); |
| |
| for (i = 0; i < adev->usec_timeout; i++) { |
| tmp = RREG32(scratch); |
| if (tmp == 0xDEADBEEF) |
| break; |
| DRM_UDELAY(1); |
| } |
| if (i < adev->usec_timeout) { |
| DRM_INFO("ring test on %d succeeded in %d usecs\n", |
| ring->idx, i); |
| } else { |
| DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", |
| ring->idx, scratch, tmp); |
| r = -EINVAL; |
| } |
| amdgpu_gfx_scratch_free(adev, scratch); |
| return r; |
| } |
| |
| static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring) |
| { |
| struct amdgpu_device *adev = ring->adev; |
| struct amdgpu_ib ib; |
| struct fence *f = NULL; |
| uint32_t scratch; |
| uint32_t tmp = 0; |
| unsigned i; |
| int r; |
| |
| r = amdgpu_gfx_scratch_get(adev, &scratch); |
| if (r) { |
| DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r); |
| return r; |
| } |
| WREG32(scratch, 0xCAFEDEAD); |
| memset(&ib, 0, sizeof(ib)); |
| r = amdgpu_ib_get(adev, NULL, 256, &ib); |
| if (r) { |
| DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); |
| goto err1; |
| } |
| ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); |
| ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); |
| ib.ptr[2] = 0xDEADBEEF; |
| ib.length_dw = 3; |
| |
| r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f); |
| if (r) |
| goto err2; |
| |
| r = fence_wait(f, false); |
| if (r) { |
| DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); |
| goto err2; |
| } |
| for (i = 0; i < adev->usec_timeout; i++) { |
| tmp = RREG32(scratch); |
| if (tmp == 0xDEADBEEF) |
| break; |
| DRM_UDELAY(1); |
| } |
| if (i < adev->usec_timeout) { |
| DRM_INFO("ib test on ring %d succeeded in %u usecs\n", |
| ring->idx, i); |
| goto err2; |
| } else { |
| DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", |
| scratch, tmp); |
| r = -EINVAL; |
| } |
| err2: |
| fence_put(f); |
| amdgpu_ib_free(adev, &ib, NULL); |
| fence_put(f); |
| err1: |
| amdgpu_gfx_scratch_free(adev, scratch); |
| return r; |
| } |
| |
| |
| static void gfx_v8_0_free_microcode(struct amdgpu_device *adev) { |
| release_firmware(adev->gfx.pfp_fw); |
| adev->gfx.pfp_fw = NULL; |
| release_firmware(adev->gfx.me_fw); |
| adev->gfx.me_fw = NULL; |
| release_firmware(adev->gfx.ce_fw); |
| adev->gfx.ce_fw = NULL; |
| release_firmware(adev->gfx.rlc_fw); |
| adev->gfx.rlc_fw = NULL; |
| release_firmware(adev->gfx.mec_fw); |
| adev->gfx.mec_fw = NULL; |
| if ((adev->asic_type != CHIP_STONEY) && |
| (adev->asic_type != CHIP_TOPAZ)) |
| release_firmware(adev->gfx.mec2_fw); |
| adev->gfx.mec2_fw = NULL; |
| |
| kfree(adev->gfx.rlc.register_list_format); |
| } |
| |
| static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) |
| { |
| const char *chip_name; |
| char fw_name[30]; |
| int err; |
| struct amdgpu_firmware_info *info = NULL; |
| const struct common_firmware_header *header = NULL; |
| const struct gfx_firmware_header_v1_0 *cp_hdr; |
| const struct rlc_firmware_header_v2_0 *rlc_hdr; |
| unsigned int *tmp = NULL, i; |
| |
| DRM_DEBUG("\n"); |
| |
| switch (adev->asic_type) { |
| case CHIP_TOPAZ: |
| chip_name = "topaz"; |
| break; |
| case CHIP_TONGA: |
| chip_name = "tonga"; |
| break; |
| case CHIP_CARRIZO: |
| chip_name = "carrizo"; |
| break; |
| case CHIP_FIJI: |
| chip_name = "fiji"; |
| break; |
| case CHIP_POLARIS11: |
| chip_name = "polaris11"; |
| break; |
| case CHIP_POLARIS10: |
| chip_name = "polaris10"; |
| break; |
| case CHIP_STONEY: |
| chip_name = "stoney"; |
| break; |
| default: |
| BUG(); |
| } |
| |
| snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); |
| err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); |
| if (err) |
| goto out; |
| err = amdgpu_ucode_validate(adev->gfx.pfp_fw); |
| if (err) |
| goto out; |
| cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; |
| adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); |
| adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); |
| |
| snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); |
| err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); |
| if (err) |
| goto out; |
| err = amdgpu_ucode_validate(adev->gfx.me_fw); |
| if (err) |
| goto out; |
| cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; |
| adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); |
| adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); |
| |
| snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); |
| err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); |
| if (err) |
| goto out; |
| err = amdgpu_ucode_validate(adev->gfx.ce_fw); |
| if (err) |
| goto out; |
| cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; |
| adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); |
| adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); |
| |
| snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); |
| err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); |
| if (err) |
| goto out; |
| err = amdgpu_ucode_validate(adev->gfx.rlc_fw); |
| rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; |
| adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); |
| adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); |
| |
| adev->gfx.rlc.save_and_restore_offset = |
| le32_to_cpu(rlc_hdr->save_and_restore_offset); |
| adev->gfx.rlc.clear_state_descriptor_offset = |
| le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); |
| adev->gfx.rlc.avail_scratch_ram_locations = |
| le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); |
| adev->gfx.rlc.reg_restore_list_size = |
| le32_to_cpu(rlc_hdr->reg_restore_list_size); |
| adev->gfx.rlc.reg_list_format_start = |
| le32_to_cpu(rlc_hdr->reg_list_format_start); |
| adev->gfx.rlc.reg_list_format_separate_start = |
| le32_to_cpu(rlc_hdr->reg_list_format_separate_start); |
| adev->gfx.rlc.starting_offsets_start = |
| le32_to_cpu(rlc_hdr->starting_offsets_start); |
| adev->gfx.rlc.reg_list_format_size_bytes = |
| le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); |
| adev->gfx.rlc.reg_list_size_bytes = |
| le32_to_cpu(rlc_hdr->reg_list_size_bytes); |
| |
| adev->gfx.rlc.register_list_format = |
| kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + |
| adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); |
| |
| if (!adev->gfx.rlc.register_list_format) { |
| err = -ENOMEM; |
| goto out; |
| } |
| |
| tmp = (unsigned int *)((uintptr_t)rlc_hdr + |
| le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); |
| for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) |
| adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); |
| |
| adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; |
| |
| tmp = (unsigned int *)((uintptr_t)rlc_hdr + |
| le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); |
| for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) |
| adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); |
| |
| snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); |
| err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); |
| if (err) |
| goto out; |
| err = amdgpu_ucode_validate(adev->gfx.mec_fw); |
| if (err) |
| goto out; |
| cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; |
| adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); |
| adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); |
| |
| if ((adev->asic_type != CHIP_STONEY) && |
| (adev->asic_type != CHIP_TOPAZ)) { |
| snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); |
| err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); |
| if (!err) { |
| err = amdgpu_ucode_validate(adev->gfx.mec2_fw); |
| if (err) |
| goto out; |
| cp_hdr = (const struct gfx_firmware_header_v1_0 *) |
| adev->gfx.mec2_fw->data; |
| adev->gfx.mec2_fw_version = |
| le32_to_cpu(cp_hdr->header.ucode_version); |
| adev->gfx.mec2_feature_version = |
| le32_to_cpu(cp_hdr->ucode_feature_version); |
| } else { |
| err = 0; |
| adev->gfx.mec2_fw = NULL; |
| } |
| } |
| |
| if (adev->firmware.smu_load) { |
| info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; |
| info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; |
| info->fw = adev->gfx.pfp_fw; |
| header = (const struct common_firmware_header *)info->fw->data; |
| adev->firmware.fw_size += |
| ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); |
| |
| info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; |
| info->ucode_id = AMDGPU_UCODE_ID_CP_ME; |
| info->fw = adev->gfx.me_fw; |
| header = (const struct common_firmware_header *)info->fw->data; |
| adev->firmware.fw_size += |
| ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); |
| |
| info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; |
| info->ucode_id = AMDGPU_UCODE_ID_CP_CE; |
| info->fw = adev->gfx.ce_fw; |
| header = (const struct common_firmware_header *)info->fw->data; |
| adev->firmware.fw_size += |
| ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); |
| |
| info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; |
| info->ucode_id = AMDGPU_UCODE_ID_RLC_G; |
| info->fw = adev->gfx.rlc_fw; |
| header = (const struct common_firmware_header *)info->fw->data; |
| adev->firmware.fw_size += |
| ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); |
| |
| info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; |
| info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; |
| info->fw = adev->gfx.mec_fw; |
| header = (const struct common_firmware_header *)info->fw->data; |
| adev->firmware.fw_size += |
| ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); |
| |
| if (adev->gfx.mec2_fw) { |
| info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; |
| info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; |
| info->fw = adev->gfx.mec2_fw; |
| header = (const struct common_firmware_header *)info->fw->data; |
| adev->firmware.fw_size += |
| ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); |
| } |
| |
| } |
| |
| out: |
| if (err) { |
| dev_err(adev->dev, |
| "gfx8: Failed to load firmware \"%s\"\n", |
| fw_name); |
| release_firmware(adev->gfx.pfp_fw); |
| adev->gfx.pfp_fw = NULL; |
| release_firmware(adev->gfx.me_fw); |
| adev->gfx.me_fw = NULL; |
| release_firmware(adev->gfx.ce_fw); |
| adev->gfx.ce_fw = NULL; |
| release_firmware(adev->gfx.rlc_fw); |
| adev->gfx.rlc_fw = NULL; |
| release_firmware(adev->gfx.mec_fw); |
| adev->gfx.mec_fw = NULL; |
| release_firmware(adev->gfx.mec2_fw); |
| adev->gfx.mec2_fw = NULL; |
| } |
| return err; |
| } |
| |
| static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev, |
| volatile u32 *buffer) |
| { |
| u32 count = 0, i; |
| const struct cs_section_def *sect = NULL; |
| const struct cs_extent_def *ext = NULL; |
| |
| if (adev->gfx.rlc.cs_data == NULL) |
| return; |
| if (buffer == NULL) |
| return; |
| |
| buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
| buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); |
| |
| buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); |
| buffer[count++] = cpu_to_le32(0x80000000); |
| buffer[count++] = cpu_to_le32(0x80000000); |
| |
| for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { |
| for (ext = sect->section; ext->extent != NULL; ++ext) { |
| if (sect->id == SECT_CONTEXT) { |
| buffer[count++] = |
| cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); |
| buffer[count++] = cpu_to_le32(ext->reg_index - |
| PACKET3_SET_CONTEXT_REG_START); |
| for (i = 0; i < ext->reg_count; i++) |
| buffer[count++] = cpu_to_le32(ext->extent[i]); |
| } else { |
| return; |
| } |
| } |
| } |
| |
| buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
| buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - |
| PACKET3_SET_CONTEXT_REG_START); |
| switch (adev->asic_type) { |
| case CHIP_TONGA: |
| case CHIP_POLARIS10: |
| buffer[count++] = cpu_to_le32(0x16000012); |
| buffer[count++] = cpu_to_le32(0x0000002A); |
| break; |
| case CHIP_POLARIS11: |
| buffer[count++] = cpu_to_le32(0x16000012); |
| buffer[count++] = cpu_to_le32(0x00000000); |
| break; |
| case CHIP_FIJI: |
| buffer[count++] = cpu_to_le32(0x3a00161a); |
| buffer[count++] = cpu_to_le32(0x0000002e); |
| break; |
| case CHIP_TOPAZ: |
| case CHIP_CARRIZO: |
| buffer[count++] = cpu_to_le32(0x00000002); |
| buffer[count++] = cpu_to_le32(0x00000000); |
| break; |
| case CHIP_STONEY: |
| buffer[count++] = cpu_to_le32(0x00000000); |
| buffer[count++] = cpu_to_le32(0x00000000); |
| break; |
| default: |
| buffer[count++] = cpu_to_le32(0x00000000); |
| buffer[count++] = cpu_to_le32(0x00000000); |
| break; |
| } |
| |
| buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
| buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); |
| |
| buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); |
| buffer[count++] = cpu_to_le32(0); |
| } |
| |
| static void gfx_v8_0_rlc_fini(struct amdgpu_device *adev) |
| { |
| int r; |
| |
| /* clear state block */ |
| if (adev->gfx.rlc.clear_state_obj) { |
| r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); |
| if (unlikely(r != 0)) |
| dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r); |
| amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); |
| amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); |
| |
| amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); |
| adev->gfx.rlc.clear_state_obj = NULL; |
| } |
| } |
| |
| static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) |
| { |
| volatile u32 *dst_ptr; |
| u32 dws; |
| const struct cs_section_def *cs_data; |
| int r; |
| |
| adev->gfx.rlc.cs_data = vi_cs_data; |
| |
| cs_data = adev->gfx.rlc.cs_data; |
| |
| if (cs_data) { |
| /* clear state block */ |
| adev->gfx.rlc.clear_state_size = dws = gfx_v8_0_get_csb_size(adev); |
| |
| if (adev->gfx.rlc.clear_state_obj == NULL) { |
| r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, |
| AMDGPU_GEM_DOMAIN_VRAM, |
| AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, |
| NULL, NULL, |
| &adev->gfx.rlc.clear_state_obj); |
| if (r) { |
| dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); |
| gfx_v8_0_rlc_fini(adev); |
| return r; |
| } |
| } |
| r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); |
| if (unlikely(r != 0)) { |
| gfx_v8_0_rlc_fini(adev); |
| return r; |
| } |
| r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM, |
| &adev->gfx.rlc.clear_state_gpu_addr); |
| if (r) { |
| amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); |
| dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r); |
| gfx_v8_0_rlc_fini(adev); |
| return r; |
| } |
| |
| r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr); |
| if (r) { |
| dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r); |
| gfx_v8_0_rlc_fini(adev); |
| return r; |
| } |
| /* set up the cs buffer */ |
| dst_ptr = adev->gfx.rlc.cs_ptr; |
| gfx_v8_0_get_csb_buffer(adev, dst_ptr); |
| amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); |
| amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); |
| } |
| |
| return 0; |
| } |
| |
| static void gfx_v8_0_mec_fini(struct amdgpu_device *adev) |
| { |
| int r; |
| |
| if (adev->gfx.mec.hpd_eop_obj) { |
| r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); |
| if (unlikely(r != 0)) |
| dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r); |
| amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj); |
| amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); |
| |
| amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj); |
| adev->gfx.mec.hpd_eop_obj = NULL; |
| } |
| } |
| |
| #define MEC_HPD_SIZE 2048 |
| |
| static int gfx_v8_0_mec_init(struct amdgpu_device *adev) |
| { |
| int r; |
| u32 *hpd; |
| |
| /* |
| * we assign only 1 pipe because all other pipes will |
| * be handled by KFD |
| */ |
| adev->gfx.mec.num_mec = 1; |
| adev->gfx.mec.num_pipe = 1; |
| adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8; |
| |
| if (adev->gfx.mec.hpd_eop_obj == NULL) { |
| r = amdgpu_bo_create(adev, |
| adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2, |
| PAGE_SIZE, true, |
| AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, |
| &adev->gfx.mec.hpd_eop_obj); |
| if (r) { |
| dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); |
| return r; |
| } |
| } |
| |
| r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); |
| if (unlikely(r != 0)) { |
| gfx_v8_0_mec_fini(adev); |
| return r; |
| } |
| r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT, |
| &adev->gfx.mec.hpd_eop_gpu_addr); |
| if (r) { |
| dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r); |
| gfx_v8_0_mec_fini(adev); |
| return r; |
| } |
| r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd); |
| if (r) { |
| dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r); |
| gfx_v8_0_mec_fini(adev); |
| return r; |
| } |
| |
| memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2); |
| |
| amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); |
| amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); |
| |
| return 0; |
| } |
| |
| static const u32 vgpr_init_compute_shader[] = |
| { |
| 0x7e000209, 0x7e020208, |
| 0x7e040207, 0x7e060206, |
| 0x7e080205, 0x7e0a0204, |
| 0x7e0c0203, 0x7e0e0202, |
| 0x7e100201, 0x7e120200, |
| 0x7e140209, 0x7e160208, |
| 0x7e180207, 0x7e1a0206, |
| 0x7e1c0205, 0x7e1e0204, |
| 0x7e200203, 0x7e220202, |
| 0x7e240201, 0x7e260200, |
| 0x7e280209, 0x7e2a0208, |
| 0x7e2c0207, 0x7e2e0206, |
| 0x7e300205, 0x7e320204, |
| 0x7e340203, 0x7e360202, |
| 0x7e380201, 0x7e3a0200, |
| 0x7e3c0209, 0x7e3e0208, |
| 0x7e400207, 0x7e420206, |
| 0x7e440205, 0x7e460204, |
| 0x7e480203, 0x7e4a0202, |
| 0x7e4c0201, 0x7e4e0200, |
| 0x7e500209, 0x7e520208, |
| 0x7e540207, 0x7e560206, |
| 0x7e580205, 0x7e5a0204, |
| 0x7e5c0203, 0x7e5e0202, |
| 0x7e600201, 0x7e620200, |
| 0x7e640209, 0x7e660208, |
| 0x7e680207, 0x7e6a0206, |
| 0x7e6c0205, 0x7e6e0204, |
| 0x7e700203, 0x7e720202, |
| 0x7e740201, 0x7e760200, |
| 0x7e780209, 0x7e7a0208, |
| 0x7e7c0207, 0x7e7e0206, |
| 0xbf8a0000, 0xbf810000, |
| }; |
| |
| static const u32 sgpr_init_compute_shader[] = |
| { |
| 0xbe8a0100, 0xbe8c0102, |
| 0xbe8e0104, 0xbe900106, |
| 0xbe920108, 0xbe940100, |
| 0xbe960102, 0xbe980104, |
| 0xbe9a0106, 0xbe9c0108, |
| 0xbe9e0100, 0xbea00102, |
| 0xbea20104, 0xbea40106, |
| 0xbea60108, 0xbea80100, |
| 0xbeaa0102, 0xbeac0104, |
| 0xbeae0106, 0xbeb00108, |
| 0xbeb20100, 0xbeb40102, |
| 0xbeb60104, 0xbeb80106, |
| 0xbeba0108, 0xbebc0100, |
| 0xbebe0102, 0xbec00104, |
| 0xbec20106, 0xbec40108, |
| 0xbec60100, 0xbec80102, |
| 0xbee60004, 0xbee70005, |
| 0xbeea0006, 0xbeeb0007, |
| 0xbee80008, 0xbee90009, |
| 0xbefc0000, 0xbf8a0000, |
| 0xbf810000, 0x00000000, |
| }; |
| |
| static const u32 vgpr_init_regs[] = |
| { |
| mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff, |
| mmCOMPUTE_RESOURCE_LIMITS, 0, |
| mmCOMPUTE_NUM_THREAD_X, 256*4, |
| mmCOMPUTE_NUM_THREAD_Y, 1, |
| mmCOMPUTE_NUM_THREAD_Z, 1, |
| mmCOMPUTE_PGM_RSRC2, 20, |
| mmCOMPUTE_USER_DATA_0, 0xedcedc00, |
| mmCOMPUTE_USER_DATA_1, 0xedcedc01, |
| mmCOMPUTE_USER_DATA_2, 0xedcedc02, |
| mmCOMPUTE_USER_DATA_3, 0xedcedc03, |
| mmCOMPUTE_USER_DATA_4, 0xedcedc04, |
| mmCOMPUTE_USER_DATA_5, 0xedcedc05, |
| mmCOMPUTE_USER_DATA_6, 0xedcedc06, |
| mmCOMPUTE_USER_DATA_7, 0xedcedc07, |
| mmCOMPUTE_USER_DATA_8, 0xedcedc08, |
| mmCOMPUTE_USER_DATA_9, 0xedcedc09, |
| }; |
| |
| static const u32 sgpr1_init_regs[] = |
| { |
| mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f, |
| mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, |
| mmCOMPUTE_NUM_THREAD_X, 256*5, |
| mmCOMPUTE_NUM_THREAD_Y, 1, |
| mmCOMPUTE_NUM_THREAD_Z, 1, |
| mmCOMPUTE_PGM_RSRC2, 20, |
| mmCOMPUTE_USER_DATA_0, 0xedcedc00, |
| mmCOMPUTE_USER_DATA_1, 0xedcedc01, |
| mmCOMPUTE_USER_DATA_2, 0xedcedc02, |
| mmCOMPUTE_USER_DATA_3, 0xedcedc03, |
| mmCOMPUTE_USER_DATA_4, 0xedcedc04, |
| mmCOMPUTE_USER_DATA_5, 0xedcedc05, |
| mmCOMPUTE_USER_DATA_6, 0xedcedc06, |
| mmCOMPUTE_USER_DATA_7, 0xedcedc07, |
| mmCOMPUTE_USER_DATA_8, 0xedcedc08, |
| mmCOMPUTE_USER_DATA_9, 0xedcedc09, |
| }; |
| |
| static const u32 sgpr2_init_regs[] = |
| { |
| mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0, |
| mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, |
| mmCOMPUTE_NUM_THREAD_X, 256*5, |
| mmCOMPUTE_NUM_THREAD_Y, 1, |
| mmCOMPUTE_NUM_THREAD_Z, 1, |
| mmCOMPUTE_PGM_RSRC2, 20, |
| mmCOMPUTE_USER_DATA_0, 0xedcedc00, |
| mmCOMPUTE_USER_DATA_1, 0xedcedc01, |
| mmCOMPUTE_USER_DATA_2, 0xedcedc02, |
| mmCOMPUTE_USER_DATA_3, 0xedcedc03, |
| mmCOMPUTE_USER_DATA_4, 0xedcedc04, |
| mmCOMPUTE_USER_DATA_5, 0xedcedc05, |
| mmCOMPUTE_USER_DATA_6, 0xedcedc06, |
| mmCOMPUTE_USER_DATA_7, 0xedcedc07, |
| mmCOMPUTE_USER_DATA_8, 0xedcedc08, |
| mmCOMPUTE_USER_DATA_9, 0xedcedc09, |
| }; |
| |
| static const u32 sec_ded_counter_registers[] = |
| { |
| mmCPC_EDC_ATC_CNT, |
| mmCPC_EDC_SCRATCH_CNT, |
| mmCPC_EDC_UCODE_CNT, |
| mmCPF_EDC_ATC_CNT, |
| mmCPF_EDC_ROQ_CNT, |
| mmCPF_EDC_TAG_CNT, |
| mmCPG_EDC_ATC_CNT, |
| mmCPG_EDC_DMA_CNT, |
| mmCPG_EDC_TAG_CNT, |
| mmDC_EDC_CSINVOC_CNT, |
| mmDC_EDC_RESTORE_CNT, |
| mmDC_EDC_STATE_CNT, |
| mmGDS_EDC_CNT, |
| mmGDS_EDC_GRBM_CNT, |
| mmGDS_EDC_OA_DED, |
| mmSPI_EDC_CNT, |
| mmSQC_ATC_EDC_GATCL1_CNT, |
| mmSQC_EDC_CNT, |
| mmSQ_EDC_DED_CNT, |
| mmSQ_EDC_INFO, |
| mmSQ_EDC_SEC_CNT, |
| mmTCC_EDC_CNT, |
| mmTCP_ATC_EDC_GATCL1_CNT, |
| mmTCP_EDC_CNT, |
| mmTD_EDC_CNT |
| }; |
| |
| static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) |
| { |
| struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; |
| struct amdgpu_ib ib; |
| struct fence *f = NULL; |
| int r, i; |
| u32 tmp; |
| unsigned total_size, vgpr_offset, sgpr_offset; |
| u64 gpu_addr; |
| |
| /* only supported on CZ */ |
| if (adev->asic_type != CHIP_CARRIZO) |
| return 0; |
| |
| /* bail if the compute ring is not ready */ |
| if (!ring->ready) |
| return 0; |
| |
| tmp = RREG32(mmGB_EDC_MODE); |
| WREG32(mmGB_EDC_MODE, 0); |
| |
| total_size = |
| (((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4; |
| total_size += |
| (((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4; |
| total_size += |
| (((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4; |
| total_size = ALIGN(total_size, 256); |
| vgpr_offset = total_size; |
| total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256); |
| sgpr_offset = total_size; |
| total_size += sizeof(sgpr_init_compute_shader); |
| |
| /* allocate an indirect buffer to put the commands in */ |
| memset(&ib, 0, sizeof(ib)); |
| r = amdgpu_ib_get(adev, NULL, total_size, &ib); |
| if (r) { |
| DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); |
| return r; |
| } |
| |
| /* load the compute shaders */ |
| for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++) |
| ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i]; |
| |
| for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++) |
| ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i]; |
| |
| /* init the ib length to 0 */ |
| ib.length_dw = 0; |
| |
| /* VGPR */ |
| /* write the register state for the compute dispatch */ |
| for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) { |
| ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); |
| ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START; |
| ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1]; |
| } |
| /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ |
| gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8; |
| ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); |
| ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START; |
| ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); |
| ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); |
| |
| /* write dispatch packet */ |
| ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); |
| ib.ptr[ib.length_dw++] = 8; /* x */ |
| ib.ptr[ib.length_dw++] = 1; /* y */ |
| ib.ptr[ib.length_dw++] = 1; /* z */ |
| ib.ptr[ib.length_dw++] = |
| REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); |
| |
| /* write CS partial flush packet */ |
| ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); |
| ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); |
| |
| /* SGPR1 */ |
| /* write the register state for the compute dispatch */ |
| for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) { |
| ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); |
| ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START; |
| ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1]; |
| } |
| /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ |
| gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; |
| ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); |
| ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START; |
| ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); |
| ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); |
| |
| /* write dispatch packet */ |
| ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); |
| ib.ptr[ib.length_dw++] = 8; /* x */ |
| ib.ptr[ib.length_dw++] = 1; /* y */ |
| ib.ptr[ib.length_dw++] = 1; /* z */ |
| ib.ptr[ib.length_dw++] = |
| REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); |
| |
| /* write CS partial flush packet */ |
| ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); |
| ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); |
| |
| /* SGPR2 */ |
| /* write the register state for the compute dispatch */ |
| for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) { |
| ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); |
| ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START; |
| ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1]; |
| } |
| /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ |
| gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; |
| ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); |
| ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START; |
| ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); |
| ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); |
| |
| /* write dispatch packet */ |
| ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); |
| ib.ptr[ib.length_dw++] = 8; /* x */ |
| ib.ptr[ib.length_dw++] = 1; /* y */ |
| ib.ptr[ib.length_dw++] = 1; /* z */ |
| ib.ptr[ib.length_dw++] = |
| REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); |
| |
| /* write CS partial flush packet */ |
| ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); |
| ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); |
| |
| /* shedule the ib on the ring */ |
| r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f); |
| if (r) { |
| DRM_ERROR("amdgpu: ib submit failed (%d).\n", r); |
| goto fail; |
| } |
| |
| /* wait for the GPU to finish processing the IB */ |
| r = fence_wait(f, false); |
| if (r) { |
| DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); |
| goto fail; |
| } |
| |
| tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2); |
| tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1); |
| WREG32(mmGB_EDC_MODE, tmp); |
| |
| tmp = RREG32(mmCC_GC_EDC_CONFIG); |
| tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1; |
| WREG32(mmCC_GC_EDC_CONFIG, tmp); |
| |
| |
| /* read back registers to clear the counters */ |
| for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) |
| RREG32(sec_ded_counter_registers[i]); |
| |
| fail: |
| fence_put(f); |
| amdgpu_ib_free(adev, &ib, NULL); |
| fence_put(f); |
| |
| return r; |
| } |
| |
| static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev) |
| { |
| u32 gb_addr_config; |
| u32 mc_shared_chmap, mc_arb_ramcfg; |
| u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map; |
| u32 tmp; |
| int ret; |
| |
| switch (adev->asic_type) { |
| case CHIP_TOPAZ: |
| adev->gfx.config.max_shader_engines = 1; |
| adev->gfx.config.max_tile_pipes = 2; |
| adev->gfx.config.max_cu_per_sh = 6; |
| adev->gfx.config.max_sh_per_se = 1; |
| adev->gfx.config.max_backends_per_se = 2; |
| adev->gfx.config.max_texture_channel_caches = 2; |
| adev->gfx.config.max_gprs = 256; |
| adev->gfx.config.max_gs_threads = 32; |
| adev->gfx.config.max_hw_contexts = 8; |
| |
| adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
| adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
| adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
| adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; |
| gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN; |
| break; |
| case CHIP_FIJI: |
| adev->gfx.config.max_shader_engines = 4; |
| adev->gfx.config.max_tile_pipes = 16; |
| adev->gfx.config.max_cu_per_sh = 16; |
| adev->gfx.config.max_sh_per_se = 1; |
| adev->gfx.config.max_backends_per_se = 4; |
| adev->gfx.config.max_texture_channel_caches = 16; |
| adev->gfx.config.max_gprs = 256; |
| adev->gfx.config.max_gs_threads = 32; |
| adev->gfx.config.max_hw_contexts = 8; |
| |
| adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
| adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
| adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
| adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; |
| gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; |
| break; |
| case CHIP_POLARIS11: |
| ret = amdgpu_atombios_get_gfx_info(adev); |
| if (ret) |
| return ret; |
| adev->gfx.config.max_gprs = 256; |
| adev->gfx.config.max_gs_threads = 32; |
| adev->gfx.config.max_hw_contexts = 8; |
| |
| adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
| adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
| adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
| adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; |
| gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN; |
| break; |
| case CHIP_POLARIS10: |
| ret = amdgpu_atombios_get_gfx_info(adev); |
| if (ret) |
| return ret; |
| adev->gfx.config.max_gprs = 256; |
| adev->gfx.config.max_gs_threads = 32; |
| adev->gfx.config.max_hw_contexts = 8; |
| |
| adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
| adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
| adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
| adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; |
| gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; |
| break; |
| case CHIP_TONGA: |
| adev->gfx.config.max_shader_engines = 4; |
| adev->gfx.config.max_tile_pipes = 8; |
| adev->gfx.config.max_cu_per_sh = 8; |
| adev->gfx.config.max_sh_per_se = 1; |
| adev->gfx.config.max_backends_per_se = 2; |
| adev->gfx.config.max_texture_channel_caches = 8; |
| adev->gfx.config.max_gprs = 256; |
| adev->gfx.config.max_gs_threads = 32; |
| adev->gfx.config.max_hw_contexts = 8; |
| |
| adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
| adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
| adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
| adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; |
| gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; |
| break; |
| case CHIP_CARRIZO: |
| adev->gfx.config.max_shader_engines = 1; |
| adev->gfx.config.max_tile_pipes = 2; |
| adev->gfx.config.max_sh_per_se = 1; |
| adev->gfx.config.max_backends_per_se = 2; |
| |
| switch (adev->pdev->revision) { |
| case 0xc4: |
| case 0x84: |
| case 0xc8: |
| case 0xcc: |
| case 0xe1: |
| case 0xe3: |
| /* B10 */ |
| adev->gfx.config.max_cu_per_sh = 8; |
| break; |
| case 0xc5: |
| case 0x81: |
| case 0x85: |
| case 0xc9: |
| case 0xcd: |
| case 0xe2: |
| case 0xe4: |
| /* B8 */ |
| adev->gfx.config.max_cu_per_sh = 6; |
| break; |
| case 0xc6: |
| case 0xca: |
| case 0xce: |
| case 0x88: |
| /* B6 */ |
| adev->gfx.config.max_cu_per_sh = 6; |
| break; |
| case 0xc7: |
| case 0x87: |
| case 0xcb: |
| case 0xe5: |
| case 0x89: |
| default: |
| /* B4 */ |
| adev->gfx.config.max_cu_per_sh = 4; |
| break; |
| } |
| |
| adev->gfx.config.max_texture_channel_caches = 2; |
| adev->gfx.config.max_gprs = 256; |
| adev->gfx.config.max_gs_threads = 32; |
| adev->gfx.config.max_hw_contexts = 8; |
| |
| adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
| adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
| adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
| adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; |
| gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN; |
| break; |
| case CHIP_STONEY: |
| adev->gfx.config.max_shader_engines = 1; |
| adev->gfx.config.max_tile_pipes = 2; |
| adev->gfx.config.max_sh_per_se = 1; |
| adev->gfx.config.max_backends_per_se = 1; |
| |
| switch (adev->pdev->revision) { |
| case 0xc0: |
| case 0xc1: |
| case 0xc2: |
| case 0xc4: |
| case 0xc8: |
| case 0xc9: |
| adev->gfx.config.max_cu_per_sh = 3; |
| break; |
| case 0xd0: |
| case 0xd1: |
| case 0xd2: |
| default: |
| adev->gfx.config.max_cu_per_sh = 2; |
| break; |
| } |
| |
| adev->gfx.config.max_texture_channel_caches = 2; |
| adev->gfx.config.max_gprs = 256; |
| adev->gfx.config.max_gs_threads = 16; |
| adev->gfx.config.max_hw_contexts = 8; |
| |
| adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
| adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
| adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
| adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; |
| gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN; |
| break; |
| default: |
| adev->gfx.config.max_shader_engines = 2; |
| adev->gfx.config.max_tile_pipes = 4; |
| adev->gfx.config.max_cu_per_sh = 2; |
| adev->gfx.config.max_sh_per_se = 1; |
| adev->gfx.config.max_backends_per_se = 2; |
| adev->gfx.config.max_texture_channel_caches = 4; |
| adev->gfx.config.max_gprs = 256; |
| adev->gfx.config.max_gs_threads = 32; |
| adev->gfx.config.max_hw_contexts = 8; |
| |
| adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
| adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
| adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
| adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; |
| gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; |
| break; |
| } |
| |
| mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); |
| adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); |
| mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; |
| |
| adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; |
| adev->gfx.config.mem_max_burst_length_bytes = 256; |
| if (adev->flags & AMD_IS_APU) { |
| /* Get memory bank mapping mode. */ |
| tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); |
| dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); |
| dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); |
| |
| tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); |
| dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); |
| dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); |
| |
| /* Validate settings in case only one DIMM installed. */ |
| if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12)) |
| dimm00_addr_map = 0; |
| if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12)) |
| dimm01_addr_map = 0; |
| if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12)) |
| dimm10_addr_map = 0; |
| if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12)) |
| dimm11_addr_map = 0; |
| |
| /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */ |
| /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */ |
| if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11)) |
| adev->gfx.config.mem_row_size_in_kb = 2; |
| else |
| adev->gfx.config.mem_row_size_in_kb = 1; |
| } else { |
| tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS); |
| adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; |
| if (adev->gfx.config.mem_row_size_in_kb > 4) |
| adev->gfx.config.mem_row_size_in_kb = 4; |
| } |
| |
| adev->gfx.config.shader_engine_tile_size = 32; |
| adev->gfx.config.num_gpus = 1; |
| adev->gfx.config.multi_gpu_tile_size = 64; |
| |
| /* fix up row size */ |
| switch (adev->gfx.config.mem_row_size_in_kb) { |
| case 1: |
| default: |
| gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0); |
| break; |
| case 2: |
| gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1); |
| break; |
| case 4: |
| gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2); |
| break; |
| } |
| adev->gfx.config.gb_addr_config = gb_addr_config; |
| |
| return 0; |
| } |
| |
| static int gfx_v8_0_sw_init(void *handle) |
| { |
| int i, r; |
| struct amdgpu_ring *ring; |
| struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| |
| /* EOP Event */ |
| r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq); |
| if (r) |
| return r; |
| |
| /* Privileged reg */ |
| r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq); |
| if (r) |
| return r; |
| |
| /* Privileged inst */ |
| r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq); |
| if (r) |
| return r; |
| |
| adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; |
| |
| gfx_v8_0_scratch_init(adev); |
| |
| r = gfx_v8_0_init_microcode(adev); |
| if (r) { |
| DRM_ERROR("Failed to load gfx firmware!\n"); |
| return r; |
| } |
| |
| r = gfx_v8_0_rlc_init(adev); |
| if (r) { |
| DRM_ERROR("Failed to init rlc BOs!\n"); |
| return r; |
| } |
| |
| r = gfx_v8_0_mec_init(adev); |
| if (r) { |
| DRM_ERROR("Failed to init MEC BOs!\n"); |
| return r; |
| } |
| |
| /* set up the gfx ring */ |
| for (i = 0; i < adev->gfx.num_gfx_rings; i++) { |
| ring = &adev->gfx.gfx_ring[i]; |
| ring->ring_obj = NULL; |
| sprintf(ring->name, "gfx"); |
| /* no gfx doorbells on iceland */ |
| if (adev->asic_type != CHIP_TOPAZ) { |
| ring->use_doorbell = true; |
| ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0; |
| } |
| |
| r = amdgpu_ring_init(adev, ring, 1024, |
| PACKET3(PACKET3_NOP, 0x3FFF), 0xf, |
| &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP, |
| AMDGPU_RING_TYPE_GFX); |
| if (r) |
| return r; |
| } |
| |
| /* set up the compute queues */ |
| for (i = 0; i < adev->gfx.num_compute_rings; i++) { |
| unsigned irq_type; |
| |
| /* max 32 queues per MEC */ |
| if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { |
| DRM_ERROR("Too many (%d) compute rings!\n", i); |
| break; |
| } |
| ring = &adev->gfx.compute_ring[i]; |
| ring->ring_obj = NULL; |
| ring->use_doorbell = true; |
| ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i; |
| ring->me = 1; /* first MEC */ |
| ring->pipe = i / 8; |
| ring->queue = i % 8; |
| sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); |
| irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; |
| /* type-2 packets are deprecated on MEC, use type-3 instead */ |
| r = amdgpu_ring_init(adev, ring, 1024, |
| PACKET3(PACKET3_NOP, 0x3FFF), 0xf, |
| &adev->gfx.eop_irq, irq_type, |
| AMDGPU_RING_TYPE_COMPUTE); |
| if (r) |
| return r; |
| } |
| |
| /* reserve GDS, GWS and OA resource for gfx */ |
| r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size, |
| PAGE_SIZE, true, |
| AMDGPU_GEM_DOMAIN_GDS, 0, NULL, |
| NULL, &adev->gds.gds_gfx_bo); |
| if (r) |
| return r; |
| |
| r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size, |
| PAGE_SIZE, true, |
| AMDGPU_GEM_DOMAIN_GWS, 0, NULL, |
| NULL, &adev->gds.gws_gfx_bo); |
| if (r) |
| return r; |
| |
| r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size, |
| PAGE_SIZE, true, |
| AMDGPU_GEM_DOMAIN_OA, 0, NULL, |
| NULL, &adev->gds.oa_gfx_bo); |
| if (r) |
| return r; |
| |
| adev->gfx.ce_ram_size = 0x8000; |
| |
| r = gfx_v8_0_gpu_early_init(adev); |
| if (r) |
| return r; |
| |
| return 0; |
| } |
| |
| static int gfx_v8_0_sw_fini(void *handle) |
| { |
| int i; |
| struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| |
| amdgpu_bo_unref(&adev->gds.oa_gfx_bo); |
| amdgpu_bo_unref(&adev->gds.gws_gfx_bo); |
| amdgpu_bo_unref(&adev->gds.gds_gfx_bo); |
| |
| for (i = 0; i < adev->gfx.num_gfx_rings; i++) |
| amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); |
| for (i = 0; i < adev->gfx.num_compute_rings; i++) |
| amdgpu_ring_fini(&adev->gfx.compute_ring[i]); |
| |
| gfx_v8_0_mec_fini(adev); |
| |
| gfx_v8_0_rlc_fini(adev); |
| |
| gfx_v8_0_free_microcode(adev); |
| |
| return 0; |
| } |
| |
| static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev) |
| { |
| uint32_t *modearray, *mod2array; |
| const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); |
| const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); |
| u32 reg_offset; |
| |
| modearray = adev->gfx.config.tile_mode_array; |
| mod2array = adev->gfx.config.macrotile_mode_array; |
| |
| for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) |
| modearray[reg_offset] = 0; |
| |
| for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) |
| mod2array[reg_offset] = 0; |
| |
| switch (adev->asic_type) { |
| case CHIP_TOPAZ: |
| modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | |
| PIPE_CONFIG(ADDR_SURF_P2)); |
| modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P2) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| |
| mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| |
| for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) |
| if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 && |
| reg_offset != 23) |
| WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); |
| |
| for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) |
| if (reg_offset != 7) |
| WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); |
| |
| break; |
| case CHIP_FIJI: |
| modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)); |
| modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| |
| mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| NUM_BANKS(ADDR_SURF_4_BANK)); |
| |
| for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) |
| WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); |
| |
| for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) |
| if (reg_offset != 7) |
| WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); |
| |
| break; |
| case CHIP_TONGA: |
| modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)); |
| modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| |
| mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| NUM_BANKS(ADDR_SURF_4_BANK)); |
| mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| NUM_BANKS(ADDR_SURF_4_BANK)); |
| |
| for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) |
| WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); |
| |
| for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) |
| if (reg_offset != 7) |
| WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); |
| |
| break; |
| case CHIP_POLARIS11: |
| modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16)); |
| modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
|
