| /dts-v1/; |
| |
| #include "skeleton.dtsi" |
| #include <dt-bindings/clock/qcom,gcc-ipq806x.h> |
| #include <dt-bindings/clock/qcom,lcc-ipq806x.h> |
| #include <dt-bindings/soc/qcom,gsbi.h> |
| |
| / { |
| model = "Qualcomm IPQ8064"; |
| compatible = "qcom,ipq8064"; |
| interrupt-parent = <&intc>; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| compatible = "qcom,krait"; |
| enable-method = "qcom,kpss-acc-v1"; |
| device_type = "cpu"; |
| reg = <0>; |
| next-level-cache = <&L2>; |
| qcom,acc = <&acc0>; |
| qcom,saw = <&saw0>; |
| }; |
| |
| cpu@1 { |
| compatible = "qcom,krait"; |
| enable-method = "qcom,kpss-acc-v1"; |
| device_type = "cpu"; |
| reg = <1>; |
| next-level-cache = <&L2>; |
| qcom,acc = <&acc1>; |
| qcom,saw = <&saw1>; |
| }; |
| |
| L2: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| }; |
| }; |
| |
| cpu-pmu { |
| compatible = "qcom,krait-pmu"; |
| interrupts = <1 10 0x304>; |
| }; |
| |
| reserved-memory { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| nss@40000000 { |
| reg = <0x40000000 0x1000000>; |
| no-map; |
| }; |
| |
| smem@41000000 { |
| reg = <0x41000000 0x200000>; |
| no-map; |
| }; |
| }; |
| |
| clocks { |
| cxo_board { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <19200000>; |
| }; |
| |
| pxo_board { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <27000000>; |
| }; |
| |
| sleep_clk: sleep_clk { |
| compatible = "fixed-clock"; |
| clock-frequency = <32768>; |
| #clock-cells = <0>; |
| }; |
| }; |
| |
| soc: soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| compatible = "simple-bus"; |
| |
| lpass@28100000 { |
| compatible = "qcom,lpass-cpu"; |
| status = "disabled"; |
| clocks = <&lcc AHBIX_CLK>, |
| <&lcc MI2S_OSR_CLK>, |
| <&lcc MI2S_BIT_CLK>; |
| clock-names = "ahbix-clk", |
| "mi2s-osr-clk", |
| "mi2s-bit-clk"; |
| interrupts = <0 85 1>; |
| interrupt-names = "lpass-irq-lpaif"; |
| reg = <0x28100000 0x10000>; |
| reg-names = "lpass-lpaif"; |
| }; |
| |
| qcom_pinmux: pinmux@800000 { |
| compatible = "qcom,ipq8064-pinctrl"; |
| reg = <0x800000 0x4000>; |
| |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = <0 16 0x4>; |
| }; |
| |
| intc: interrupt-controller@2000000 { |
| compatible = "qcom,msm-qgic2"; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| reg = <0x02000000 0x1000>, |
| <0x02002000 0x1000>; |
| }; |
| |
| timer@200a000 { |
| compatible = "qcom,kpss-timer", "qcom,msm-timer"; |
| interrupts = <1 1 0x301>, |
| <1 2 0x301>, |
| <1 3 0x301>, |
| <1 4 0x301>, |
| <1 5 0x301>; |
| reg = <0x0200a000 0x100>; |
| clock-frequency = <25000000>, |
| <32768>; |
| clocks = <&sleep_clk>; |
| clock-names = "sleep"; |
| cpu-offset = <0x80000>; |
| }; |
| |
| acc0: clock-controller@2088000 { |
| compatible = "qcom,kpss-acc-v1"; |
| reg = <0x02088000 0x1000>, <0x02008000 0x1000>; |
| }; |
| |
| acc1: clock-controller@2098000 { |
| compatible = "qcom,kpss-acc-v1"; |
| reg = <0x02098000 0x1000>, <0x02008000 0x1000>; |
| }; |
| |
| saw0: regulator@2089000 { |
| compatible = "qcom,saw2"; |
| reg = <0x02089000 0x1000>, <0x02009000 0x1000>; |
| regulator; |
| }; |
| |
| saw1: regulator@2099000 { |
| compatible = "qcom,saw2"; |
| reg = <0x02099000 0x1000>, <0x02009000 0x1000>; |
| regulator; |
| }; |
| |
| gsbi2: gsbi@12480000 { |
| compatible = "qcom,gsbi-v1.0.0"; |
| cell-index = <2>; |
| reg = <0x12480000 0x100>; |
| clocks = <&gcc GSBI2_H_CLK>; |
| clock-names = "iface"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| status = "disabled"; |
| |
| syscon-tcsr = <&tcsr>; |
| |
| serial@12490000 { |
| compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; |
| reg = <0x12490000 0x1000>, |
| <0x12480000 0x1000>; |
| interrupts = <0 195 0x0>; |
| clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; |
| clock-names = "core", "iface"; |
| status = "disabled"; |
| }; |
| |
| i2c@124a0000 { |
| compatible = "qcom,i2c-qup-v1.1.1"; |
| reg = <0x124a0000 0x1000>; |
| interrupts = <0 196 0>; |
| |
| clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; |
| clock-names = "core", "iface"; |
| status = "disabled"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| }; |
| |
| gsbi4: gsbi@16300000 { |
| compatible = "qcom,gsbi-v1.0.0"; |
| cell-index = <4>; |
| reg = <0x16300000 0x100>; |
| clocks = <&gcc GSBI4_H_CLK>; |
| clock-names = "iface"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| status = "disabled"; |
| |
| syscon-tcsr = <&tcsr>; |
| |
| gsbi4_serial: serial@16340000 { |
| compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; |
| reg = <0x16340000 0x1000>, |
| <0x16300000 0x1000>; |
| interrupts = <0 152 0x0>; |
| clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; |
| clock-names = "core", "iface"; |
| status = "disabled"; |
| }; |
| |
| i2c@16380000 { |
| compatible = "qcom,i2c-qup-v1.1.1"; |
| reg = <0x16380000 0x1000>; |
| interrupts = <0 153 0>; |
| |
| clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; |
| clock-names = "core", "iface"; |
| status = "disabled"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| |
| gsbi5: gsbi@1a200000 { |
| compatible = "qcom,gsbi-v1.0.0"; |
| cell-index = <5>; |
| reg = <0x1a200000 0x100>; |
| clocks = <&gcc GSBI5_H_CLK>; |
| clock-names = "iface"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| status = "disabled"; |
| |
| syscon-tcsr = <&tcsr>; |
| |
| serial@1a240000 { |
| compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; |
| reg = <0x1a240000 0x1000>, |
| <0x1a200000 0x1000>; |
| interrupts = <0 154 0x0>; |
| clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; |
| clock-names = "core", "iface"; |
| status = "disabled"; |
| }; |
| |
| i2c@1a280000 { |
| compatible = "qcom,i2c-qup-v1.1.1"; |
| reg = <0x1a280000 0x1000>; |
| interrupts = <0 155 0>; |
| |
| clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; |
| clock-names = "core", "iface"; |
| status = "disabled"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| spi@1a280000 { |
| compatible = "qcom,spi-qup-v1.1.1"; |
| reg = <0x1a280000 0x1000>; |
| interrupts = <0 155 0>; |
| |
| clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; |
| clock-names = "core", "iface"; |
| status = "disabled"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| |
| sata_phy: sata-phy@1b400000 { |
| compatible = "qcom,ipq806x-sata-phy"; |
| reg = <0x1b400000 0x200>; |
| |
| clocks = <&gcc SATA_PHY_CFG_CLK>; |
| clock-names = "cfg"; |
| |
| #phy-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| sata@29000000 { |
| compatible = "qcom,ipq806x-ahci", "generic-ahci"; |
| reg = <0x29000000 0x180>; |
| |
| interrupts = <0 209 0x0>; |
| |
| clocks = <&gcc SFAB_SATA_S_H_CLK>, |
| <&gcc SATA_H_CLK>, |
| <&gcc SATA_A_CLK>, |
| <&gcc SATA_RXOOB_CLK>, |
| <&gcc SATA_PMALIVE_CLK>; |
| clock-names = "slave_face", "iface", "core", |
| "rxoob", "pmalive"; |
| |
| assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; |
| assigned-clock-rates = <100000000>, <100000000>; |
| |
| phys = <&sata_phy>; |
| phy-names = "sata-phy"; |
| status = "disabled"; |
| }; |
| |
| qcom,ssbi@500000 { |
| compatible = "qcom,ssbi"; |
| reg = <0x00500000 0x1000>; |
| qcom,controller-type = "pmic-arbiter"; |
| }; |
| |
| gcc: clock-controller@900000 { |
| compatible = "qcom,gcc-ipq8064"; |
| reg = <0x00900000 0x4000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| tcsr: syscon@1a400000 { |
| compatible = "qcom,tcsr-ipq8064", "syscon"; |
| reg = <0x1a400000 0x100>; |
| }; |
| |
| lcc: clock-controller@28000000 { |
| compatible = "qcom,lcc-ipq8064"; |
| reg = <0x28000000 0x1000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| }; |
| }; |
