| /* |
| * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| */ |
| /dts-v1/; |
| |
| #include "dra74x.dtsi" |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/clk/ti-dra7-atl.h> |
| #include <dt-bindings/input/input.h> |
| |
| / { |
| model = "TI DRA742"; |
| compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; |
| |
| memory { |
| device_type = "memory"; |
| reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */ |
| }; |
| |
| evm_3v3_sd: fixedregulator-sd { |
| compatible = "regulator-fixed"; |
| regulator-name = "evm_3v3_sd"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| enable-active-high; |
| gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; |
| }; |
| |
| evm_3v3_sw: fixedregulator-evm_3v3_sw { |
| compatible = "regulator-fixed"; |
| regulator-name = "evm_3v3_sw"; |
| vin-supply = <&sysen1>; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| }; |
| |
| aic_dvdd: fixedregulator-aic_dvdd { |
| /* TPS77018DBVT */ |
| compatible = "regulator-fixed"; |
| regulator-name = "aic_dvdd"; |
| vin-supply = <&evm_3v3_sw>; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| }; |
| |
| extcon_usb1: extcon_usb1 { |
| compatible = "linux,extcon-usb-gpio"; |
| id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; |
| }; |
| |
| extcon_usb2: extcon_usb2 { |
| compatible = "linux,extcon-usb-gpio"; |
| id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; |
| }; |
| |
| vtt_fixed: fixedregulator-vtt { |
| compatible = "regulator-fixed"; |
| regulator-name = "vtt_fixed"; |
| regulator-min-microvolt = <1350000>; |
| regulator-max-microvolt = <1350000>; |
| regulator-always-on; |
| regulator-boot-on; |
| enable-active-high; |
| vin-supply = <&sysen2>; |
| gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; |
| }; |
| |
| sound0: sound0 { |
| compatible = "simple-audio-card"; |
| simple-audio-card,name = "DRA7xx-EVM"; |
| simple-audio-card,widgets = |
| "Headphone", "Headphone Jack", |
| "Line", "Line Out", |
| "Microphone", "Mic Jack", |
| "Line", "Line In"; |
| simple-audio-card,routing = |
| "Headphone Jack", "HPLOUT", |
| "Headphone Jack", "HPROUT", |
| "Line Out", "LLOUT", |
| "Line Out", "RLOUT", |
| "MIC3L", "Mic Jack", |
| "MIC3R", "Mic Jack", |
| "Mic Jack", "Mic Bias", |
| "LINE1L", "Line In", |
| "LINE1R", "Line In"; |
| simple-audio-card,format = "dsp_b"; |
| simple-audio-card,bitclock-master = <&sound0_master>; |
| simple-audio-card,frame-master = <&sound0_master>; |
| simple-audio-card,bitclock-inversion; |
| |
| sound0_master: simple-audio-card,cpu { |
| sound-dai = <&mcasp3>; |
| system-clock-frequency = <5644800>; |
| }; |
| |
| simple-audio-card,codec { |
| sound-dai = <&tlv320aic3106>; |
| clocks = <&atl_clkin2_ck>; |
| }; |
| }; |
| |
| leds { |
| compatible = "gpio-leds"; |
| led@0 { |
| label = "dra7:usr1"; |
| gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>; |
| default-state = "off"; |
| }; |
| |
| led@1 { |
| label = "dra7:usr2"; |
| gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>; |
| default-state = "off"; |
| }; |
| |
| led@2 { |
| label = "dra7:usr3"; |
| gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>; |
| default-state = "off"; |
| }; |
| |
| led@3 { |
| label = "dra7:usr4"; |
| gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>; |
| default-state = "off"; |
| }; |
| }; |
| |
| gpio_keys { |
| compatible = "gpio-keys"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| autorepeat; |
| |
| USER1 { |
| label = "btnUser1"; |
| linux,code = <BTN_0>; |
| gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>; |
| }; |
| |
| USER2 { |
| label = "btnUser2"; |
| linux,code = <BTN_1>; |
| gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>; |
| }; |
| }; |
| }; |
| |
| &dra7_pmx_core { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&vtt_pin>; |
| |
| vtt_pin: pinmux_vtt_pin { |
| pinctrl-single,pins = < |
| DRA7XX_CORE_IOPAD(0x37b4, PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */ |
| >; |
| }; |
| |
| i2c1_pins: pinmux_i2c1_pins { |
| pinctrl-single,pins = < |
| DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda */ |
| DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl */ |
| >; |
| }; |
| |
| i2c2_pins: pinmux_i2c2_pins { |
| pinctrl-single,pins = < |
| DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ |
| DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ |
| >; |
| }; |
| |
| i2c3_pins: pinmux_i2c3_pins { |
| pinctrl-single,pins = < |
| DRA7XX_CORE_IOPAD(0x3688, PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */ |
| DRA7XX_CORE_IOPAD(0x368c, PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */ |
| >; |
| }; |
| |
| mcspi1_pins: pinmux_mcspi1_pins { |
| pinctrl-single,pins = < |
| DRA7XX_CORE_IOPAD(0x37a4, PIN_INPUT | MUX_MODE0) /* spi1_sclk */ |
| DRA7XX_CORE_IOPAD(0x37a8, PIN_INPUT | MUX_MODE0) /* spi1_d1 */ |
| DRA7XX_CORE_IOPAD(0x37ac, PIN_INPUT | MUX_MODE0) /* spi1_d0 */ |
| DRA7XX_CORE_IOPAD(0x37b0, PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */ |
| DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */ |
| DRA7XX_CORE_IOPAD(0x37bc, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */ |
| >; |
| }; |
| |
| mcspi2_pins: pinmux_mcspi2_pins { |
| pinctrl-single,pins = < |
| DRA7XX_CORE_IOPAD(0x37c0, PIN_INPUT | MUX_MODE0) /* spi2_sclk */ |
| DRA7XX_CORE_IOPAD(0x37c4, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ |
| DRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ |
| DRA7XX_CORE_IOPAD(0x37cc, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */ |
| >; |
| }; |
| |
| uart1_pins: pinmux_uart1_pins { |
| pinctrl-single,pins = < |
| DRA7XX_CORE_IOPAD(0x37e0, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */ |
| DRA7XX_CORE_IOPAD(0x37e4, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */ |
| DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT | MUX_MODE3) /* uart1_ctsn */ |
| DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT | MUX_MODE3) /* uart1_rtsn */ |
| >; |
| }; |
| |
| uart2_pins: pinmux_uart2_pins { |
| pinctrl-single,pins = < |
| DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT | MUX_MODE0) /* uart2_rxd */ |
| DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT | MUX_MODE0) /* uart2_txd */ |
| DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT | MUX_MODE0) /* uart2_ctsn */ |
| DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT | MUX_MODE0) /* uart2_rtsn */ |
| >; |
| }; |
| |
| uart3_pins: pinmux_uart3_pins { |
| pinctrl-single,pins = < |
| DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ |
| DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ |
| >; |
| }; |
| |
| usb1_pins: pinmux_usb1_pins { |
| pinctrl-single,pins = < |
| DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ |
| >; |
| }; |
| |
| usb2_pins: pinmux_usb2_pins { |
| pinctrl-single,pins = < |
| DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ |
| >; |
| }; |
| |
| nand_flash_x16: nand_flash_x16 { |
| /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch |
| * So NAND flash requires following switch settings: |
| * SW5.1 (NAND_BOOTn) = ON (LOW) |
| * SW5.9 (GPMC_WPN) = OFF (HIGH) |
| */ |
| pinctrl-single,pins = < |
| DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ |
| DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ |
| DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ |
| DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ |
| DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ |
| DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ |
| DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ |
| DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ |
| DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ |
| DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ |
| DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ |
| DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ |
| DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ |
| DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ |
| DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ |
| DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ |
| DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */ |
| DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ |
| DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */ |
| DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ |
| DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ |
| DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */ |
| >; |
| }; |
| |
| cpsw_default: cpsw_default { |
| pinctrl-single,pins = < |
| /* Slave 1 */ |
| DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */ |
| DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */ |
| DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */ |
| DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */ |
| DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */ |
| DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */ |
| DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */ |
| DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */ |
| DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */ |
| DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */ |
| DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */ |
| DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */ |
| |
| /* Slave 2 */ |
| DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ |
| DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ |
| DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ |
| DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ |
| DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ |
| DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ |
| DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ |
| DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ |
| DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ |
| DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ |
| DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ |
| DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ |
| >; |
| |
| }; |
| |
| cpsw_sleep: cpsw_sleep { |
| pinctrl-single,pins = < |
| /* Slave 1 */ |
| DRA7XX_CORE_IOPAD(0x3650, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x3654, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x3658, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x365c, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x3660, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x3664, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x3668, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x366c, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x3670, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x3674, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x3678, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x367c, MUX_MODE15) |
| |
| /* Slave 2 */ |
| DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15) |
| >; |
| }; |
| |
| davinci_mdio_default: davinci_mdio_default { |
| pinctrl-single,pins = < |
| DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ |
| DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ |
| >; |
| }; |
| |
| davinci_mdio_sleep: davinci_mdio_sleep { |
| pinctrl-single,pins = < |
| DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15) |
| >; |
| }; |
| |
| dcan1_pins_default: dcan1_pins_default { |
| pinctrl-single,pins = < |
| DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ |
| DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ |
| >; |
| }; |
| |
| dcan1_pins_sleep: dcan1_pins_sleep { |
| pinctrl-single,pins = < |
| DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ |
| DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ |
| >; |
| }; |
| |
| atl_pins: pinmux_atl_pins { |
| pinctrl-single,pins = < |
| DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */ |
| DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */ |
| >; |
| }; |
| |
| mcasp3_pins: pinmux_mcasp3_pins { |
| pinctrl-single,pins = < |
| DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */ |
| DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */ |
| DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */ |
| DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */ |
| >; |
| }; |
| |
| mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins { |
| pinctrl-single,pins = < |
| DRA7XX_CORE_IOPAD(0x3724, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x3728, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x372c, MUX_MODE15) |
| DRA7XX_CORE_IOPAD(0x3730, MUX_MODE15) |
| >; |
| }; |
| }; |
| |
| &i2c1 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c1_pins>; |
| clock-frequency = <400000>; |
| |
| tps659038: tps659038@58 { |
| compatible = "ti,tps659038"; |
| reg = <0x58>; |
| |
| tps659038_pmic { |
| compatible = "ti,tps659038-pmic"; |
| |
| regulators { |
| smps123_reg: smps123 { |
| /* VDD_MPU */ |
| regulator-name = "smps123"; |
| regulator-min-microvolt = < 850000>; |
| regulator-max-microvolt = <1250000>; |
| regulator-always-on; |
| regulator-boot-on; |
| }; |
| |
| smps45_reg: smps45 { |
| /* VDD_DSPEVE */ |
| regulator-name = "smps45"; |
| regulator-min-microvolt = < 850000>; |
| regulator-max-microvolt = <1250000>; |
| regulator-always-on; |
| regulator-boot-on; |
| }; |
| |
| smps6_reg: smps6 { |
| /* VDD_GPU - over VDD_SMPS6 */ |
| regulator-name = "smps6"; |
| regulator-min-microvolt = <850000>; |
| regulator-max-microvolt = <1250000>; |
| regulator-always-on; |
| regulator-boot-on; |
| }; |
| |
| smps7_reg: smps7 { |
| /* CORE_VDD */ |
| regulator-name = "smps7"; |
| regulator-min-microvolt = <850000>; |
| regulator-max-microvolt = <1150000>; |
| regulator-always-on; |
| regulator-boot-on; |
| }; |
| |
| smps8_reg: smps8 { |
| /* VDD_IVAHD */ |
| regulator-name = "smps8"; |
| regulator-min-microvolt = < 850000>; |
| regulator-max-microvolt = <1250000>; |
| regulator-always-on; |
| regulator-boot-on; |
| }; |
| |
| smps9_reg: smps9 { |
| /* VDDS1V8 */ |
| regulator-name = "smps9"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-always-on; |
| regulator-boot-on; |
| }; |
| |
| ldo1_reg: ldo1 { |
| /* LDO1_OUT --> SDIO */ |
| regulator-name = "ldo1"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| regulator-boot-on; |
| }; |
| |
| ldo2_reg: ldo2 { |
| /* VDD_RTCIO */ |
| /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ |
| regulator-name = "ldo2"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| regulator-boot-on; |
| }; |
| |
| ldo3_reg: ldo3 { |
| /* VDDA_1V8_PHY */ |
| regulator-name = "ldo3"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-always-on; |
| regulator-boot-on; |
| }; |
| |
| ldo9_reg: ldo9 { |
| /* VDD_RTC */ |
| regulator-name = "ldo9"; |
| regulator-min-microvolt = <1050000>; |
| regulator-max-microvolt = <1050000>; |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-allow-bypass; |
| }; |
| |
| ldoln_reg: ldoln { |
| /* VDDA_1V8_PLL */ |
| regulator-name = "ldoln"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-always-on; |
| regulator-boot-on; |
| }; |
| |
| ldousb_reg: ldousb { |
| /* VDDA_3V_USB: VDDA_USBHS33 */ |
| regulator-name = "ldousb"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| }; |
| |
| /* REGEN1 is unused */ |
| |
| regen2: regen2 { |
| /* Needed for PMIC internal resources */ |
| regulator-name = "regen2"; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| /* REGEN3 is unused */ |
| |
| sysen1: sysen1 { |
| /* PMIC_REGEN_3V3 */ |
| regulator-name = "sysen1"; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| sysen2: sysen2 { |
| /* PMIC_REGEN_DDR */ |
| regulator-name = "sysen2"; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| }; |
| |
| pcf_lcd: gpio@20 { |
| compatible = "ti,pcf8575", "nxp,pcf8575"; |
| reg = <0x20>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&gpio6>; |
| interrupts = <11 IRQ_TYPE_EDGE_FALLING>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| pcf_gpio_21: gpio@21 { |
| compatible = "ti,pcf8575", "nxp,pcf8575"; |
| reg = <0x21>; |
| lines-initial-states = <0x1408>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&gpio6>; |
| interrupts = <11 IRQ_TYPE_EDGE_FALLING>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| tlv320aic3106: tlv320aic3106@19 { |
| #sound-dai-cells = <0>; |
| compatible = "ti,tlv320aic3106"; |
| reg = <0x19>; |
| adc-settle-ms = <40>; |
| ai3x-micbias-vg = <1>; /* 2.0V */ |
| status = "okay"; |
| |
| /* Regulators */ |
| AVDD-supply = <&evm_3v3_sw>; |
| IOVDD-supply = <&evm_3v3_sw>; |
| DRVDD-supply = <&evm_3v3_sw>; |
| DVDD-supply = <&aic_dvdd>; |
| }; |
| }; |
| |
| &i2c2 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c2_pins>; |
| clock-frequency = <400000>; |
| |
| pcf_hdmi: gpio@26 { |
| compatible = "ti,pcf8575", "nxp,pcf8575"; |
| reg = <0x26>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| p1 { |
| /* vin6_sel_s0: high: VIN6, low: audio */ |
| gpio-hog; |
| gpios = <1 GPIO_ACTIVE_HIGH>; |
| output-low; |
| line-name = "vin6_sel_s0"; |
| }; |
| }; |
| }; |
| |
| &i2c3 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c3_pins>; |
| clock-frequency = <400000>; |
| }; |
| |
| &mcspi1 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mcspi1_pins>; |
| }; |
| |
| &mcspi2 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mcspi2_pins>; |
| }; |
| |
| &uart1 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart1_pins>; |
| interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, |
| <&dra7_pmx_core 0x3e0>; |
| }; |
| |
| &uart2 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart2_pins>; |
| }; |
| |
| &uart3 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart3_pins>; |
| }; |
| |
| &mmc1 { |
| status = "okay"; |
| vmmc-supply = <&evm_3v3_sd>; |
| vmmc_aux-supply = <&ldo1_reg>; |
| bus-width = <4>; |
| /* |
| * SDCD signal is not being used here - using the fact that GPIO mode |
| * is always hardwired. |
| */ |
| cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; |
| }; |
| |
| &mmc2 { |
| status = "okay"; |
| vmmc-supply = <&evm_3v3_sw>; |
| bus-width = <8>; |
| }; |
| |
| &cpu0 { |
| cpu0-supply = <&smps123_reg>; |
| }; |
| |
| &qspi { |
| status = "okay"; |
| |
| spi-max-frequency = <64000000>; |
| m25p80@0 { |
| compatible = "s25fl256s1"; |
| spi-max-frequency = <64000000>; |
| reg = <0>; |
| spi-tx-bus-width = <1>; |
| spi-rx-bus-width = <4>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| /* MTD partition table. |
| * The ROM checks the first four physical blocks |
| * for a valid file to boot and the flash here is |
| * 64KiB block size. |
| */ |
| partition@0 { |
| label = "QSPI.SPL"; |
| reg = <0x00000000 0x000010000>; |
| }; |
| partition@1 { |
| label = "QSPI.SPL.backup1"; |
| reg = <0x00010000 0x00010000>; |
| }; |
| partition@2 { |
| label = "QSPI.SPL.backup2"; |
| reg = <0x00020000 0x00010000>; |
| }; |
| partition@3 { |
| label = "QSPI.SPL.backup3"; |
| reg = <0x00030000 0x00010000>; |
| }; |
| partition@4 { |
| label = "QSPI.u-boot"; |
| reg = <0x00040000 0x00100000>; |
| }; |
| partition@5 { |
| label = "QSPI.u-boot-spl-os"; |
| reg = <0x00140000 0x00080000>; |
| }; |
| partition@6 { |
| label = "QSPI.u-boot-env"; |
| reg = <0x001c0000 0x00010000>; |
| }; |
| partition@7 { |
| label = "QSPI.u-boot-env.backup1"; |
| reg = <0x001d0000 0x0010000>; |
| }; |
| partition@8 { |
| label = "QSPI.kernel"; |
| reg = <0x001e0000 0x0800000>; |
| }; |
| partition@9 { |
| label = "QSPI.file-system"; |
| reg = <0x009e0000 0x01620000>; |
| }; |
| }; |
| }; |
| |
| &omap_dwc3_1 { |
| extcon = <&extcon_usb1>; |
| }; |
| |
| &omap_dwc3_2 { |
| extcon = <&extcon_usb2>; |
| }; |
| |
| &usb1 { |
| dr_mode = "peripheral"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&usb1_pins>; |
| }; |
| |
| &usb2 { |
| dr_mode = "host"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&usb2_pins>; |
| }; |
| |
| &elm { |
| status = "okay"; |
| }; |
| |
| &gpmc { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&nand_flash_x16>; |
| ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ |
| nand@0,0 { |
| compatible = "ti,omap2-nand"; |
| reg = <0 0 4>; /* device IO registers */ |
| interrupt-parent = <&gpmc>; |
| interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ |
| <1 IRQ_TYPE_NONE>; /* termcount */ |
| rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ |
| ti,nand-ecc-opt = "bch8"; |
| ti,elm-id = <&elm>; |
| nand-bus-width = <16>; |
| gpmc,device-width = <2>; |
| gpmc,sync-clk-ps = <0>; |
| gpmc,cs-on-ns = <0>; |
| gpmc,cs-rd-off-ns = <80>; |
| gpmc,cs-wr-off-ns = <80>; |
| gpmc,adv-on-ns = <0>; |
| gpmc,adv-rd-off-ns = <60>; |
| gpmc,adv-wr-off-ns = <60>; |
| gpmc,we-on-ns = <10>; |
| gpmc,we-off-ns = <50>; |
| gpmc,oe-on-ns = <4>; |
| gpmc,oe-off-ns = <40>; |
| gpmc,access-ns = <40>; |
| gpmc,wr-access-ns = <80>; |
| gpmc,rd-cycle-ns = <80>; |
| gpmc,wr-cycle-ns = <80>; |
| gpmc,bus-turnaround-ns = <0>; |
| gpmc,cycle2cycle-delay-ns = <0>; |
| gpmc,clk-activation-ns = <0>; |
| gpmc,wr-data-mux-bus-ns = <0>; |
| /* MTD partition table */ |
| /* All SPL-* partitions are sized to minimal length |
| * which can be independently programmable. For |
| * NAND flash this is equal to size of erase-block */ |
| #address-cells = <1>; |
| #size-cells = <1>; |
| partition@0 { |
| label = "NAND.SPL"; |
| reg = <0x00000000 0x000020000>; |
| }; |
| partition@1 { |
| label = "NAND.SPL.backup1"; |
| reg = <0x00020000 0x00020000>; |
| }; |
| partition@2 { |
| label = "NAND.SPL.backup2"; |
| reg = <0x00040000 0x00020000>; |
| }; |
| partition@3 { |
| label = "NAND.SPL.backup3"; |
| reg = <0x00060000 0x00020000>; |
| }; |
| partition@4 { |
| label = "NAND.u-boot-spl-os"; |
| reg = <0x00080000 0x00040000>; |
| }; |
| partition@5 { |
| label = "NAND.u-boot"; |
| reg = <0x000c0000 0x00100000>; |
| }; |
| partition@6 { |
| label = "NAND.u-boot-env"; |
| reg = <0x001c0000 0x00020000>; |
| }; |
| partition@7 { |
| label = "NAND.u-boot-env.backup1"; |
| reg = <0x001e0000 0x00020000>; |
| }; |
| partition@8 { |
| label = "NAND.kernel"; |
| reg = <0x00200000 0x00800000>; |
| }; |
| partition@9 { |
| label = "NAND.file-system"; |
| reg = <0x00a00000 0x0f600000>; |
| }; |
| }; |
| }; |
| |
| &usb2_phy1 { |
| phy-supply = <&ldousb_reg>; |
| }; |
| |
| &usb2_phy2 { |
| phy-supply = <&ldousb_reg>; |
| }; |
| |
| &gpio7 { |
| ti,no-reset-on-init; |
| ti,no-idle-on-init; |
| }; |
| |
| &mac { |
| status = "okay"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&cpsw_default>; |
| pinctrl-1 = <&cpsw_sleep>; |
| dual_emac; |
| }; |
| |
| &cpsw_emac0 { |
| phy_id = <&davinci_mdio>, <2>; |
| phy-mode = "rgmii"; |
| dual_emac_res_vlan = <1>; |
| }; |
| |
| &cpsw_emac1 { |
| phy_id = <&davinci_mdio>, <3>; |
| phy-mode = "rgmii"; |
| dual_emac_res_vlan = <2>; |
| }; |
| |
| &davinci_mdio { |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&davinci_mdio_default>; |
| pinctrl-1 = <&davinci_mdio_sleep>; |
| }; |
| |
| &dcan1 { |
| status = "ok"; |
| pinctrl-names = "default", "sleep", "active"; |
| pinctrl-0 = <&dcan1_pins_sleep>; |
| pinctrl-1 = <&dcan1_pins_sleep>; |
| pinctrl-2 = <&dcan1_pins_default>; |
| }; |
| |
| &atl { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&atl_pins>; |
| |
| assigned-clocks = <&abe_dpll_sys_clk_mux>, |
| <&atl_gfclk_mux>, |
| <&dpll_abe_ck>, |
| <&dpll_abe_m2x2_ck>, |
| <&atl_clkin2_ck>; |
| assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; |
| assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; |
| |
| status = "okay"; |
| |
| atl2 { |
| bws = <DRA7_ATL_WS_MCASP2_FSX>; |
| aws = <DRA7_ATL_WS_MCASP3_FSX>; |
| }; |
| }; |
| |
| &mcasp3 { |
| #sound-dai-cells = <0>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&mcasp3_pins>; |
| pinctrl-1 = <&mcasp3_sleep_pins>; |
| |
| assigned-clocks = <&mcasp3_ahclkx_mux>; |
| assigned-clock-parents = <&atl_clkin2_ck>; |
| |
| status = "okay"; |
| |
| op-mode = <0>; /* MCASP_IIS_MODE */ |
| tdm-slots = <2>; |
| /* 4 serializer */ |
| serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ |
| 1 2 0 0 |
| >; |
| tx-num-evt = <32>; |
| rx-num-evt = <32>; |
| }; |
| |
| &mailbox5 { |
| status = "okay"; |
| mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { |
| status = "okay"; |
| }; |
| mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { |
| status = "okay"; |
| }; |
| }; |
| |
| &mailbox6 { |
| status = "okay"; |
| mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { |
| status = "okay"; |
| }; |
| mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { |
| status = "okay"; |
| }; |
| }; |
