| Device Tree Clock bindings for arch-sunxi |
| |
| This binding uses the common clock binding[1]. |
| |
| [1] Documentation/devicetree/bindings/clock/clock-bindings.txt |
| |
| Required properties: |
| - compatible : shall be one of the following: |
| "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator |
| "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4 |
| "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31 |
| "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23 |
| "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80 |
| "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock |
| "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock |
| "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31 |
| "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80 |
| "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock |
| "allwinner,sun4i-a10-axi-clk" - for the AXI clock |
| "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23 |
| "allwinner,sun4i-a10-gates-clk" - for generic gates on all compatible SoCs |
| "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates |
| "allwinner,sun4i-a10-ahb-clk" - for the AHB clock |
| "allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13 |
| "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80 |
| "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10 |
| "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13 |
| "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s |
| "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20 |
| "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31 |
| "allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80 |
| "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31 |
| "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3 |
| "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 |
| "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23 |
| "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80 |
| "allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80 |
| "allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80 |
| "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock |
| "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31 |
| "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23 |
| "allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80 |
| "allwinner,sun8i-a83t-apb0-gates-clk" - for the APB0 gates on A83T |
| "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10 |
| "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13 |
| "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s |
| "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31 |
| "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20 |
| "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23 |
| "allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3 |
| "allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80 |
| "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock |
| "allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80 |
| "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10 |
| "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13 |
| "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s |
| "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31 |
| "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20 |
| "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23 |
| "allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80 |
| "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 |
| "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23 |
| "allwinner,sun8i-a83t-bus-gates-clk" - for the bus gates on A83T |
| "allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3 |
| "allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80 |
| "allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10 |
| "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13 |
| "allwinner,sun4i-a10-mmc-clk" - for the MMC clock |
| "allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80 |
| "allwinner,sun9i-a80-mmc-config-clk" - for mmc gates + resets on A80 |
| "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks |
| "allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80 |
| "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23 |
| "allwinner,sun7i-a20-out-clk" - for the external output clocks |
| "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31 |
| "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20 |
| "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13 |
| "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31 |
| "allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23 |
| "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3 |
| "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 |
| "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 |
| "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock |
| |
| Required properties for all clocks: |
| - reg : shall be the control register address for the clock. |
| - clocks : shall be the input parent clock(s) phandle for the clock. For |
| multiplexed clocks, the list order must match the hardware |
| programming order. |
| - #clock-cells : from common clock binding; shall be set to 0 except for |
| the following compatibles where it shall be set to 1: |
| "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk", |
| "allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk", |
| "allwinner,*-usb-clk", "allwinner,*-mmc-clk", |
| "allwinner,*-mmc-config-clk" |
| - clock-output-names : shall be the corresponding names of the outputs. |
| If the clock module only has one output, the name shall be the |
| module name. |
| |
| And "allwinner,*-usb-clk" clocks also require: |
| - reset-cells : shall be set to 1 |
| |
| The "allwinner,sun4i-a10-ve-clk" clock also requires: |
| - reset-cells : shall be set to 0 |
| |
| The "allwinner,sun9i-a80-mmc-config-clk" clock also requires: |
| - #reset-cells : shall be set to 1 |
| - resets : shall be the reset control phandle for the mmc block. |
| |
| For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate |
| dummy clocks at 25 MHz and 125 MHz, respectively. See example. |
| |
| Clock consumers should specify the desired clocks they use with a |
| "clocks" phandle cell. Consumers that are using a gated clock should |
| provide an additional ID in their clock property. This ID is the |
| offset of the bit controlling this particular gate in the register. |
| For the other clocks with "#clock-cells" = 1, the additional ID shall |
| refer to the index of the output. |
| |
| For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output |
| is the normal PLL6 output, or "pll6". The second output is rate doubled |
| PLL6, or "pll6x2". |
| |
| The "allwinner,*-mmc-clk" clocks have three different outputs: the |
| main clock, with the ID 0, and the output and sample clocks, with the |
| IDs 1 and 2, respectively. |
| |
| The "allwinner,sun9i-a80-mmc-config-clk" clock has one clock/reset output |
| per mmc controller. The number of outputs is determined by the size of |
| the address block, which is related to the overall mmc block. |
| |
| For example: |
| |
| osc24M: clk@01c20050 { |
| #clock-cells = <0>; |
| compatible = "allwinner,sun4i-a10-osc-clk"; |
| reg = <0x01c20050 0x4>; |
| clocks = <&osc24M_fixed>; |
| clock-output-names = "osc24M"; |
| }; |
| |
| pll1: clk@01c20000 { |
| #clock-cells = <0>; |
| compatible = "allwinner,sun4i-a10-pll1-clk"; |
| reg = <0x01c20000 0x4>; |
| clocks = <&osc24M>; |
| clock-output-names = "pll1"; |
| }; |
| |
| pll5: clk@01c20020 { |
| #clock-cells = <1>; |
| compatible = "allwinner,sun4i-pll5-clk"; |
| reg = <0x01c20020 0x4>; |
| clocks = <&osc24M>; |
| clock-output-names = "pll5_ddr", "pll5_other"; |
| }; |
| |
| pll6: clk@01c20028 { |
| #clock-cells = <1>; |
| compatible = "allwinner,sun6i-a31-pll6-clk"; |
| reg = <0x01c20028 0x4>; |
| clocks = <&osc24M>; |
| clock-output-names = "pll6", "pll6x2"; |
| }; |
| |
| cpu: cpu@01c20054 { |
| #clock-cells = <0>; |
| compatible = "allwinner,sun4i-a10-cpu-clk"; |
| reg = <0x01c20054 0x4>; |
| clocks = <&osc32k>, <&osc24M>, <&pll1>; |
| clock-output-names = "cpu"; |
| }; |
| |
| mmc0_clk: clk@01c20088 { |
| #clock-cells = <1>; |
| compatible = "allwinner,sun4i-a10-mmc-clk"; |
| reg = <0x01c20088 0x4>; |
| clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| clock-output-names = "mmc0", "mmc0_output", "mmc0_sample"; |
| }; |
| |
| mii_phy_tx_clk: clk@2 { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <25000000>; |
| clock-output-names = "mii_phy_tx"; |
| }; |
| |
| gmac_int_tx_clk: clk@3 { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <125000000>; |
| clock-output-names = "gmac_int_tx"; |
| }; |
| |
| gmac_clk: clk@01c20164 { |
| #clock-cells = <0>; |
| compatible = "allwinner,sun7i-a20-gmac-clk"; |
| reg = <0x01c20164 0x4>; |
| /* |
| * The first clock must be fixed at 25MHz; |
| * the second clock must be fixed at 125MHz |
| */ |
| clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; |
| clock-output-names = "gmac"; |
| }; |
| |
| mmc_config_clk: clk@01c13000 { |
| compatible = "allwinner,sun9i-a80-mmc-config-clk"; |
| reg = <0x01c13000 0x10>; |
| clocks = <&ahb0_gates 8>; |
| clock-names = "ahb"; |
| resets = <&ahb0_resets 8>; |
| reset-names = "ahb"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| clock-output-names = "mmc0_config", "mmc1_config", |
| "mmc2_config", "mmc3_config"; |
| }; |
