| /* |
| * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC |
| * |
| * Copyright (C) 2015, Applied Micro Circuits Corporation |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation; either version 2 of |
| * the License, or (at your option) any later version. |
| */ |
| |
| / { |
| compatible = "apm,xgene-shadowcat"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| cpu@000 { |
| device_type = "cpu"; |
| compatible = "apm,strega", "arm,armv8"; |
| reg = <0x0 0x000>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| next-level-cache = <&xgene_L2_0>; |
| }; |
| cpu@001 { |
| device_type = "cpu"; |
| compatible = "apm,strega", "arm,armv8"; |
| reg = <0x0 0x001>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| next-level-cache = <&xgene_L2_0>; |
| }; |
| cpu@100 { |
| device_type = "cpu"; |
| compatible = "apm,strega", "arm,armv8"; |
| reg = <0x0 0x100>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| next-level-cache = <&xgene_L2_1>; |
| }; |
| cpu@101 { |
| device_type = "cpu"; |
| compatible = "apm,strega", "arm,armv8"; |
| reg = <0x0 0x101>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| next-level-cache = <&xgene_L2_1>; |
| }; |
| cpu@200 { |
| device_type = "cpu"; |
| compatible = "apm,strega", "arm,armv8"; |
| reg = <0x0 0x200>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| next-level-cache = <&xgene_L2_2>; |
| }; |
| cpu@201 { |
| device_type = "cpu"; |
| compatible = "apm,strega", "arm,armv8"; |
| reg = <0x0 0x201>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| next-level-cache = <&xgene_L2_2>; |
| }; |
| cpu@300 { |
| device_type = "cpu"; |
| compatible = "apm,strega", "arm,armv8"; |
| reg = <0x0 0x300>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| next-level-cache = <&xgene_L2_3>; |
| }; |
| cpu@301 { |
| device_type = "cpu"; |
| compatible = "apm,strega", "arm,armv8"; |
| reg = <0x0 0x301>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| next-level-cache = <&xgene_L2_3>; |
| }; |
| xgene_L2_0: l2-cache-0 { |
| compatible = "cache"; |
| }; |
| xgene_L2_1: l2-cache-1 { |
| compatible = "cache"; |
| }; |
| xgene_L2_2: l2-cache-2 { |
| compatible = "cache"; |
| }; |
| xgene_L2_3: l2-cache-3 { |
| compatible = "cache"; |
| }; |
| }; |
| |
| gic: interrupt-controller@78090000 { |
| compatible = "arm,cortex-a15-gic"; |
| #interrupt-cells = <3>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| interrupt-controller; |
| interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ |
| ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */ |
| reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */ |
| <0x0 0x780A0000 0x0 0x20000>, /* GIC CPU */ |
| <0x0 0x780C0000 0x0 0x10000>, /* GIC VCPU Control */ |
| <0x0 0x780E0000 0x0 0x20000>; /* GIC VCPU */ |
| v2m0: v2m@0x00000 { |
| compatible = "arm,gic-v2m-frame"; |
| msi-controller; |
| reg = <0x0 0x0 0x0 0x1000>; |
| }; |
| v2m1: v2m@0x10000 { |
| compatible = "arm,gic-v2m-frame"; |
| msi-controller; |
| reg = <0x0 0x10000 0x0 0x1000>; |
| }; |
| v2m2: v2m@0x20000 { |
| compatible = "arm,gic-v2m-frame"; |
| msi-controller; |
| reg = <0x0 0x20000 0x0 0x1000>; |
| }; |
| v2m3: v2m@0x30000 { |
| compatible = "arm,gic-v2m-frame"; |
| msi-controller; |
| reg = <0x0 0x30000 0x0 0x1000>; |
| }; |
| v2m4: v2m@0x40000 { |
| compatible = "arm,gic-v2m-frame"; |
| msi-controller; |
| reg = <0x0 0x40000 0x0 0x1000>; |
| }; |
| v2m5: v2m@0x50000 { |
| compatible = "arm,gic-v2m-frame"; |
| msi-controller; |
| reg = <0x0 0x50000 0x0 0x1000>; |
| }; |
| v2m6: v2m@0x60000 { |
| compatible = "arm,gic-v2m-frame"; |
| msi-controller; |
| reg = <0x0 0x60000 0x0 0x1000>; |
| }; |
| v2m7: v2m@0x70000 { |
| compatible = "arm,gic-v2m-frame"; |
| msi-controller; |
| reg = <0x0 0x70000 0x0 0x1000>; |
| }; |
| v2m8: v2m@0x80000 { |
| compatible = "arm,gic-v2m-frame"; |
| msi-controller; |
| reg = <0x0 0x80000 0x0 0x1000>; |
| }; |
| v2m9: v2m@0x90000 { |
| compatible = "arm,gic-v2m-frame"; |
| msi-controller; |
| reg = <0x0 0x90000 0x0 0x1000>; |
| }; |
| v2m10: v2m@0xA0000 { |
| compatible = "arm,gic-v2m-frame"; |
| msi-controller; |
| reg = <0x0 0xA0000 0x0 0x1000>; |
| }; |
| v2m11: v2m@0xB0000 { |
| compatible = "arm,gic-v2m-frame"; |
| msi-controller; |
| reg = <0x0 0xB0000 0x0 0x1000>; |
| }; |
| v2m12: v2m@0xC0000 { |
| compatible = "arm,gic-v2m-frame"; |
| msi-controller; |
| reg = <0x0 0xC0000 0x0 0x1000>; |
| }; |
| v2m13: v2m@0xD0000 { |
| compatible = "arm,gic-v2m-frame"; |
| msi-controller; |
| reg = <0x0 0xD0000 0x0 0x1000>; |
| }; |
| v2m14: v2m@0xE0000 { |
| compatible = "arm,gic-v2m-frame"; |
| msi-controller; |
| reg = <0x0 0xE0000 0x0 0x1000>; |
| }; |
| v2m15: v2m@0xF0000 { |
| compatible = "arm,gic-v2m-frame"; |
| msi-controller; |
| reg = <0x0 0xF0000 0x0 0x1000>; |
| }; |
| }; |
| |
| pmu { |
| compatible = "arm,armv8-pmuv3"; |
| interrupts = <1 12 0xff04>; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <1 0 0xff04>, /* Secure Phys IRQ */ |
| <1 13 0xff04>, /* Non-secure Phys IRQ */ |
| <1 14 0xff04>, /* Virt IRQ */ |
| <1 15 0xff04>; /* Hyp IRQ */ |
| clock-frequency = <50000000>; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| clocks { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| refclk: refclk { |
| compatible = "fixed-clock"; |
| #clock-cells = <1>; |
| clock-frequency = <100000000>; |
| clock-output-names = "refclk"; |
| }; |
| |
| socpll: socpll@17000120 { |
| compatible = "apm,xgene-socpll-v2-clock"; |
| #clock-cells = <1>; |
| clocks = <&refclk 0>; |
| reg = <0x0 0x17000120 0x0 0x1000>; |
| clock-output-names = "socpll"; |
| }; |
| |
| socplldiv2: socplldiv2 { |
| compatible = "fixed-factor-clock"; |
| #clock-cells = <1>; |
| clocks = <&socpll 0>; |
| clock-mult = <1>; |
| clock-div = <2>; |
| clock-output-names = "socplldiv2"; |
| }; |
| |
| ahbclk: ahbclk@17000000 { |
| compatible = "apm,xgene-device-clock"; |
| #clock-cells = <1>; |
| clocks = <&socplldiv2 0>; |
| reg = <0x0 0x17000000 0x0 0x2000>; |
| reg-names = "div-reg"; |
| divider-offset = <0x164>; |
| divider-width = <0x5>; |
| divider-shift = <0x0>; |
| clock-output-names = "ahbclk"; |
| }; |
| |
| sbapbclk: sbapbclk@1704c000 { |
| compatible = "apm,xgene-device-clock"; |
| #clock-cells = <1>; |
| clocks = <&ahbclk 0>; |
| reg = <0x0 0x1704c000 0x0 0x2000>; |
| reg-names = "div-reg"; |
| divider-offset = <0x10>; |
| divider-width = <0x2>; |
| divider-shift = <0x0>; |
| clock-output-names = "sbapbclk"; |
| }; |
| |
| sdioclk: sdioclk@1f2ac000 { |
| compatible = "apm,xgene-device-clock"; |
| #clock-cells = <1>; |
| clocks = <&socplldiv2 0>; |
| reg = <0x0 0x1f2ac000 0x0 0x1000 |
| 0x0 0x17000000 0x0 0x2000>; |
| reg-names = "csr-reg", "div-reg"; |
| csr-offset = <0x0>; |
| csr-mask = <0x2>; |
| enable-offset = <0x8>; |
| enable-mask = <0x2>; |
| divider-offset = <0x178>; |
| divider-width = <0x8>; |
| divider-shift = <0x0>; |
| clock-output-names = "sdioclk"; |
| }; |
| |
| pcie0clk: pcie0clk@1f2bc000 { |
| compatible = "apm,xgene-device-clock"; |
| #clock-cells = <1>; |
| clocks = <&socplldiv2 0>; |
| reg = <0x0 0x1f2bc000 0x0 0x1000>; |
| reg-names = "csr-reg"; |
| clock-output-names = "pcie0clk"; |
| }; |
| |
| pcie1clk: pcie1clk@1f2cc000 { |
| compatible = "apm,xgene-device-clock"; |
| #clock-cells = <1>; |
| clocks = <&socplldiv2 0>; |
| reg = <0x0 0x1f2cc000 0x0 0x1000>; |
| reg-names = "csr-reg"; |
| clock-output-names = "pcie1clk"; |
| }; |
| |
| xge0clk: xge0clk@1f61c000 { |
| compatible = "apm,xgene-device-clock"; |
| #clock-cells = <1>; |
| clocks = <&socplldiv2 0>; |
| reg = <0x0 0x1f61c000 0x0 0x1000>; |
| reg-names = "csr-reg"; |
| enable-mask = <0x3>; |
| csr-mask = <0x3>; |
| clock-output-names = "xge0clk"; |
| }; |
| |
| xge1clk: xge1clk@1f62c000 { |
| compatible = "apm,xgene-device-clock"; |
| #clock-cells = <1>; |
| clocks = <&socplldiv2 0>; |
| reg = <0x0 0x1f62c000 0x0 0x1000>; |
| reg-names = "csr-reg"; |
| enable-mask = <0x3>; |
| csr-mask = <0x3>; |
| clock-output-names = "xge1clk"; |
| }; |
| |
| rngpkaclk: rngpkaclk@17000000 { |
| compatible = "apm,xgene-device-clock"; |
| #clock-cells = <1>; |
| clocks = <&socplldiv2 0>; |
| reg = <0x0 0x17000000 0x0 0x2000>; |
| reg-names = "csr-reg"; |
| csr-offset = <0xc>; |
| csr-mask = <0x10>; |
| enable-offset = <0x10>; |
| enable-mask = <0x10>; |
| clock-output-names = "rngpkaclk"; |
| }; |
| |
| i2c4clk: i2c4clk@1704c000 { |
| compatible = "apm,xgene-device-clock"; |
| #clock-cells = <1>; |
| clocks = <&sbapbclk 0>; |
| reg = <0x0 0x1704c000 0x0 0x1000>; |
| reg-names = "csr-reg"; |
| csr-offset = <0x0>; |
| csr-mask = <0x40>; |
| enable-offset = <0x8>; |
| enable-mask = <0x40>; |
| clock-output-names = "i2c4clk"; |
| }; |
| }; |
| |
| scu: system-clk-controller@17000000 { |
| compatible = "apm,xgene-scu","syscon"; |
| reg = <0x0 0x17000000 0x0 0x400>; |
| }; |
| |
| reboot: reboot@17000014 { |
| compatible = "syscon-reboot"; |
| regmap = <&scu>; |
| offset = <0x14>; |
| mask = <0x1>; |
| }; |
| |
| csw: csw@7e200000 { |
| compatible = "apm,xgene-csw", "syscon"; |
| reg = <0x0 0x7e200000 0x0 0x1000>; |
| }; |
| |
| mcba: mcba@7e700000 { |
| compatible = "apm,xgene-mcb", "syscon"; |
| reg = <0x0 0x7e700000 0x0 0x1000>; |
| }; |
| |
| mcbb: mcbb@7e720000 { |
| compatible = "apm,xgene-mcb", "syscon"; |
| reg = <0x0 0x7e720000 0x0 0x1000>; |
| }; |
| |
| efuse: efuse@1054a000 { |
| compatible = "apm,xgene-efuse", "syscon"; |
| reg = <0x0 0x1054a000 0x0 0x20>; |
| }; |
| |
| edac@78800000 { |
| compatible = "apm,xgene-edac"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| regmap-csw = <&csw>; |
| regmap-mcba = <&mcba>; |
| regmap-mcbb = <&mcbb>; |
| regmap-efuse = <&efuse>; |
| reg = <0x0 0x78800000 0x0 0x100>; |
| interrupts = <0x0 0x20 0x4>, |
| <0x0 0x21 0x4>, |
| <0x0 0x27 0x4>; |
| |
| edacmc@7e800000 { |
| compatible = "apm,xgene-edac-mc"; |
| reg = <0x0 0x7e800000 0x0 0x1000>; |
| memory-controller = <0>; |
| }; |
| |
| edacmc@7e840000 { |
| compatible = "apm,xgene-edac-mc"; |
| reg = <0x0 0x7e840000 0x0 0x1000>; |
| memory-controller = <1>; |
| }; |
| |
| edacmc@7e880000 { |
| compatible = "apm,xgene-edac-mc"; |
| reg = <0x0 0x7e880000 0x0 0x1000>; |
| memory-controller = <2>; |
| }; |
| |
| edacmc@7e8c0000 { |
| compatible = "apm,xgene-edac-mc"; |
| reg = <0x0 0x7e8c0000 0x0 0x1000>; |
| memory-controller = <3>; |
| }; |
| |
| edacpmd@7c000000 { |
| compatible = "apm,xgene-edac-pmd"; |
| reg = <0x0 0x7c000000 0x0 0x200000>; |
| pmd-controller = <0>; |
| }; |
| |
| edacpmd@7c200000 { |
| compatible = "apm,xgene-edac-pmd"; |
| reg = <0x0 0x7c200000 0x0 0x200000>; |
| pmd-controller = <1>; |
| }; |
| |
| edacpmd@7c400000 { |
| compatible = "apm,xgene-edac-pmd"; |
| reg = <0x0 0x7c400000 0x0 0x200000>; |
| pmd-controller = <2>; |
| }; |
| |
| edacpmd@7c600000 { |
| compatible = "apm,xgene-edac-pmd"; |
| reg = <0x0 0x7c600000 0x0 0x200000>; |
| pmd-controller = <3>; |
| }; |
| |
| edacl3@7e600000 { |
| compatible = "apm,xgene-edac-l3-v2"; |
| reg = <0x0 0x7e600000 0x0 0x1000>; |
| }; |
| |
| edacsoc@7e930000 { |
| compatible = "apm,xgene-edac-soc"; |
| reg = <0x0 0x7e930000 0x0 0x1000>; |
| }; |
| }; |
| |
| mailbox: mailbox@10540000 { |
| compatible = "apm,xgene-slimpro-mbox"; |
| reg = <0x0 0x10540000 0x0 0x8000>; |
| #mbox-cells = <1>; |
| interrupts = <0x0 0x0 0x4 |
| 0x0 0x1 0x4 |
| 0x0 0x2 0x4 |
| 0x0 0x3 0x4 |
| 0x0 0x4 0x4 |
| 0x0 0x5 0x4 |
| 0x0 0x6 0x4 |
| 0x0 0x7 0x4>; |
| }; |
| |
| i2cslimpro { |
| compatible = "apm,xgene-slimpro-i2c"; |
| mboxes = <&mailbox 0>; |
| }; |
| |
| serial0: serial@10600000 { |
| device_type = "serial"; |
| compatible = "ns16550"; |
| reg = <0 0x10600000 0x0 0x1000>; |
| reg-shift = <2>; |
| clock-frequency = <10000000>; |
| interrupt-parent = <&gic>; |
| interrupts = <0x0 0x4c 0x4>; |
| }; |
| |
| /* Do not change dwusb name, coded for backward compatibility */ |
| usb0: dwusb@19000000 { |
| status = "disabled"; |
| compatible = "snps,dwc3"; |
| reg = <0x0 0x19000000 0x0 0x100000>; |
| interrupts = <0x0 0x5d 0x4>; |
| dma-coherent; |
| dr_mode = "host"; |
| }; |
| |
| pcie0: pcie@1f2b0000 { |
| status = "disabled"; |
| device_type = "pci"; |
| compatible = "apm,xgene-pcie", "apm,xgene2-pcie"; |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ |
| 0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */ |
| reg-names = "csr", "cfg"; |
| ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */ |
| 0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000 /* mem */ |
| 0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */ |
| dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
| 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; |
| interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
| interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x1 |
| 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x1 |
| 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x1 |
| 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x1>; |
| dma-coherent; |
| clocks = <&pcie0clk 0>; |
| msi-parent = <&v2m0>; |
| }; |
| |
| pcie1: pcie@1f2c0000 { |
| status = "disabled"; |
| device_type = "pci"; |
| compatible = "apm,xgene-pcie", "apm,xgene2-pcie"; |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ |
| 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ |
| reg-names = "csr", "cfg"; |
| ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */ |
| 0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000 /* mem */ |
| 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ |
| dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
| 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; |
| interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
| interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x1 |
| 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x1 |
| 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x1 |
| 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x1>; |
| dma-coherent; |
| clocks = <&pcie1clk 0>; |
| msi-parent = <&v2m0>; |
| }; |
| |
| sata1: sata@1a000000 { |
| compatible = "apm,xgene-ahci-v2"; |
| reg = <0x0 0x1a000000 0x0 0x1000>, |
| <0x0 0x1f200000 0x0 0x1000>, |
| <0x0 0x1f20d000 0x0 0x1000>, |
| <0x0 0x1f20e000 0x0 0x1000>; |
| interrupts = <0x0 0x5a 0x4>; |
| dma-coherent; |
| }; |
| |
| sata2: sata@1a200000 { |
| compatible = "apm,xgene-ahci-v2"; |
| reg = <0x0 0x1a200000 0x0 0x1000>, |
| <0x0 0x1f210000 0x0 0x1000>, |
| <0x0 0x1f21d000 0x0 0x1000>, |
| <0x0 0x1f21e000 0x0 0x1000>; |
| interrupts = <0x0 0x5b 0x4>; |
| dma-coherent; |
| }; |
| |
| sata3: sata@1a400000 { |
| compatible = "apm,xgene-ahci-v2"; |
| reg = <0x0 0x1a400000 0x0 0x1000>, |
| <0x0 0x1f220000 0x0 0x1000>, |
| <0x0 0x1f22d000 0x0 0x1000>, |
| <0x0 0x1f22e000 0x0 0x1000>; |
| interrupts = <0x0 0x5c 0x4>; |
| dma-coherent; |
| }; |
| |
| mmc0: mmc@1c000000 { |
| compatible = "arasan,sdhci-4.9a"; |
| reg = <0x0 0x1c000000 0x0 0x100>; |
| interrupts = <0x0 0x49 0x4>; |
| dma-coherent; |
| no-1-8-v; |
| clock-names = "clk_xin", "clk_ahb"; |
| clocks = <&sdioclk 0>, <&ahbclk 0>; |
| }; |
| |
| gfcgpio: gpio@1f63c000 { |
| compatible = "apm,xgene-gpio"; |
| reg = <0x0 0x1f63c000 0x0 0x40>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| dwgpio: gpio@1c024000 { |
| compatible = "snps,dw-apb-gpio"; |
| reg = <0x0 0x1c024000 0x0 0x1000>; |
| reg-io-width = <4>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| porta: gpio-controller@0 { |
| compatible = "snps,dw-apb-gpio-port"; |
| gpio-controller; |
| snps,nr-gpios = <32>; |
| reg = <0>; |
| }; |
| }; |
| |
| sbgpio: gpio@17001000{ |
| compatible = "apm,xgene-gpio-sb"; |
| reg = <0x0 0x17001000 0x0 0x400>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| interrupts = <0x0 0x28 0x1>, |
| <0x0 0x29 0x1>, |
| <0x0 0x2a 0x1>, |
| <0x0 0x2b 0x1>, |
| <0x0 0x2c 0x1>, |
| <0x0 0x2d 0x1>, |
| <0x0 0x2e 0x1>, |
| <0x0 0x2f 0x1>; |
| interrupt-parent = <&gic>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| apm,nr-gpios = <22>; |
| apm,nr-irqs = <8>; |
| apm,irq-start = <8>; |
| }; |
| |
| sgenet0: ethernet@1f610000 { |
| compatible = "apm,xgene2-sgenet"; |
| status = "disabled"; |
| reg = <0x0 0x1f610000 0x0 0x10000>, |
| <0x0 0x1f600000 0x0 0Xd100>, |
| <0x0 0x20000000 0x0 0X20000>; |
| interrupts = <0 96 4>, |
| <0 97 4>; |
| dma-coherent; |
| clocks = <&xge0clk 0>; |
| local-mac-address = [00 01 73 00 00 01]; |
| phy-connection-type = "sgmii"; |
| }; |
| |
| xgenet1: ethernet@1f620000 { |
| compatible = "apm,xgene2-xgenet"; |
| status = "disabled"; |
| reg = <0x0 0x1f620000 0x0 0x10000>, |
| <0x0 0x1f600000 0x0 0Xd100>, |
| <0x0 0x20000000 0x0 0X220000>; |
| interrupts = <0 108 4>, |
| <0 109 4>, |
| <0 110 4>, |
| <0 111 4>, |
| <0 112 4>, |
| <0 113 4>, |
| <0 114 4>, |
| <0 115 4>; |
| channel = <12>; |
| port-id = <1>; |
| dma-coherent; |
| clocks = <&xge1clk 0>; |
| local-mac-address = [00 01 73 00 00 02]; |
| phy-connection-type = "xgmii"; |
| }; |
| |
| rng: rng@10520000 { |
| compatible = "apm,xgene-rng"; |
| reg = <0x0 0x10520000 0x0 0x100>; |
| interrupts = <0x0 0x41 0x4>; |
| clocks = <&rngpkaclk 0>; |
| }; |
| |
| i2c1: i2c@10511000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "snps,designware-i2c"; |
| reg = <0x0 0x10511000 0x0 0x1000>; |
| interrupts = <0 0x45 0x4>; |
| #clock-cells = <1>; |
| clocks = <&sbapbclk 0>; |
| bus_num = <1>; |
| }; |
| |
| i2c4: i2c@10640000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "snps,designware-i2c"; |
| reg = <0x0 0x10640000 0x0 0x1000>; |
| interrupts = <0 0x3A 0x4>; |
| clocks = <&i2c4clk 0>; |
| bus_num = <4>; |
| }; |
| }; |
| }; |
