blob: 4b41fefde5651855c9a858651bb402be7f141739 [file] [log] [blame]
Ke Dong32248e72012-09-26 19:22:56 -07001#include <Copyright.h>
2
3/********************************************************************************
4* msApiDefs.h
5*
6* DESCRIPTION:
7* API definitions for QuarterDeck Device
8*
9* DEPENDENCIES:
10*
11* FILE REVISION NUMBER:
12*
13*******************************************************************************/
14
15#ifndef __msApiDefs_h
16#define __msApiDefs_h
17
18#ifdef __cplusplus
19extern "C" {
20#endif
21#include <msApiTypes.h>
22/* Debug function */
23#ifdef DEBUG_QD
24#define DBG_INFO(x) gtDbgPrint x
25#else
26#define DBG_INFO(x);
27#endif /* DEBUG_QD */
28
29typedef GT_U32 GT_SEM;
30
31#define ETHERNET_HEADER_SIZE GT_ETHERNET_HEADER_SIZE
32#define IS_MULTICAST_MAC GT_IS_MULTICAST_MAC
33#define IS_BROADCAST_MAC GT_IS_BROADCAST_MAC
34
35#define GT_INVALID_PHY 0xFF
36#define GT_INVALID_PORT 0xFF
37#define GT_INVALID_PORT_VEC 0xFFFFFFFF
38
39#define GT_UNUSED_PARAM(_a) (_a)=(_a)
40
41/*
42 * Logical Port value based on a Port
43 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
44 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
45 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
46 * |0| reserved | port |
47 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
48 *
49 *
50 * The following macros should be used to extract specific info
51 * from a Logical Port index
52 */
53typedef GT_U32 GT_LPORT;
54typedef GT_U32 GT_ETYPE;
55
56
57/* Define the different device type that may exist in system */
58typedef enum
59{
60 GT_88E6021 = 0x021,
61 GT_88E6051 = 0x051,
62 GT_88E6052 = 0x052,
63 GT_88E6060 = 0x060,
64 GT_88E6063 = 0x153,
65 GT_FH_VPN = 0xF53,
66 GT_FF_EG = 0xF91,
67 GT_FF_HG = 0xF93,
68
69 GT_88E6083 = 0x083,
70
71 GT_88E6181 = 0x1A0,
72
73 GT_88E6153 = 0x1A1,
74 GT_88E6183 = 0x1A3,
75
76 GT_88E6093 = 0x093,
77 GT_88E6092 = 0x097,
78 GT_88E6045 = 0x094,
79 GT_88E6095 = 0x095,
80
81 GT_88E6152 = 0x1A4,
82 GT_88E6155 = 0x1A5,
83 GT_88E6182 = 0x1A6,
84 GT_88E6185 = 0x1A7,
85
86 GT_88E6121 = 0x104,
87 GT_88E6122 = 0x105,
88 GT_88E6131 = 0x106,
89 GT_88E6108 = 0x107,
90
91 GT_88E6031 = 0x031,
92 GT_88E6035 = 0x035,
93 GT_88E6055 = 0x055,
94 GT_88E6061 = 0x061,
95 GT_88E6065 = 0x065,
96
97 GT_88E6046 = 0x048,
98 GT_88E6047 = 0x049,
99 GT_88E6085 = 0x04A,
100 GT_88E6096 = 0x098,
101 GT_88E6097 = 0x099,
102
103 GT_88E6123 = 0x121,
104 GT_88E6140 = 0x141,
105 GT_88E6161 = 0x161,
106 GT_88E6165 = 0x165,
107
108 GT_88E6351 = 0x375,
109 GT_88E6175 = 0x175,
110 GT_88E6125 = 0x124, /* was 88E6124 */
111 GT_88E6171 = 0x171,
112 GT_88E6321 = 0x324, /* was 88E6325 */
113 GT_88E6350 = 0x371, /* was 88E6371 */
114 GT_KW2_INT = 0x044 /* Internal Swiych in KW2 */
115
116}GT_DEVICE;
117
118
119/* Definition for the revision number of the device */
120typedef enum
121{
122 GT_REV_0 = 0,
123 GT_REV_1,
124 GT_REV_2,
125 GT_REV_3
126}GT_DEVICE_REV;
127
128
129/* ToDo: No Used */
130typedef enum
131{
132 INTR_MODE_DISABLE =0,
133 INTR_MODE_ENABLE
134}INTERRUPT_MODE;
135
136/* Definition for the Port Speed */
137typedef enum
138{
139 PORT_SPEED_10_MBPS = 0,
140 PORT_SPEED_100_MBPS = 1,
141 PORT_SPEED_200_MBPS = 2, /* valid only if device support */
142 PORT_SPEED_1000_MBPS = 2 , /* valid only if device support */
143 PORT_SPEED_UNKNOWN = 3
144} GT_PORT_SPEED_MODE;
145
146/* Definition for the forced Port Speed */
147typedef enum
148{
149 PORT_FORCE_SPEED_10_MBPS = 0,
150 PORT_FORCE_SPEED_100_MBPS = 1,
151 PORT_FORCE_SPEED_200_MBPS = 2, /* valid only if device support */
152 PORT_FORCE_SPEED_1000_MBPS = 2, /* valid only if device support */
153 PORT_DO_NOT_FORCE_SPEED =3
154} GT_PORT_FORCED_SPEED_MODE;
155
156/* Definition for the forced Port Duplex mode */
157typedef enum
158{
159 PORT_DO_NOT_FORCE_DUPLEX,
160 PORT_FORCE_FULL_DUPLEX,
161 PORT_FORCE_HALF_DUPLEX
162} GT_PORT_FORCED_DUPLEX_MODE;
163
164/* Definition for the forced Port Link */
165typedef enum
166{
167 PORT_DO_NOT_FORCE_LINK,
168 PORT_FORCE_LINK_UP,
169 PORT_FORCE_LINK_DOWN
170} GT_PORT_FORCED_LINK_MODE;
171
172/* Definition for the forced flow control mode */
173typedef enum
174{
175 PORT_DO_NOT_FORCE_FC,
176 PORT_FORCE_FC_ENABLED,
177 PORT_FORCE_FC_DISABLED
178} GT_PORT_FORCED_FC_MODE;
179
180/* Definition for the PPU state */
181typedef enum
182{
183 PPU_STATE_DISABLED_AT_RESET,
184 PPU_STATE_ACTIVE,
185 PPU_STATE_DISABLED_AFTER_RESET,
186 PPU_STATE_POLLING
187} GT_PPU_STATE;
188
189
190/*
191 * Typedef: enum GT_PORT_CONFIG_MODE
192 *
193 * Description: Defines port's interface type configuration mode determined at
194 * reset. This definition may not represent the device under use.
195 * Please refer to the device datasheet for detailed information.
196 *
197 */
198typedef enum
199{
200 PORTCFG_GMII_125MHZ = 0, /* Px_GTXCLK = 125MHz, 1000BASE */
201 PORTCFG_FD_MII_0MHZ = 1, /* Px_GTXCLK = 0 MHz, Power Save */
202 PORTCFG_FDHD_MII_25MHZ = 2, /* Px_GTXCLK = 25MHz, 100BASE */
203 PORTCFG_FDHD_MII_2_5MHZ = 3, /* Px_GTXCLK = 2.5MHz, 10BASE */
204 PORTCFG_FD_SERDES = 4, /* Default value */
205 PORTCFG_FD_1000BASE_X = 5,
206 PORTCFG_MGMII = 6, /* duplex, speed determined by the PPU */
207 PORTCFG_DISABLED = 7
208} GT_PORT_CONFIG_MODE;
209
210
211typedef enum
212{
213 GT_SA_FILTERING_DISABLE = 0,
214 GT_SA_DROP_ON_LOCK,
215 GT_SA_DROP_ON_UNLOCK,
216 GT_SA_DROP_TO_CPU
217} GT_SA_FILTERING;
218
219
220/* Definition for the Ingree/Egress Frame Mode */
221typedef enum
222{
223 GT_FRAME_MODE_NORMAL = 0, /* Normal Network */
224 GT_FRAME_MODE_DSA, /* Distributed Switch Architecture */
225 GT_FRAME_MODE_PROVIDER, /* Provider */
226 GT_FRAME_MODE_ETHER_TYPE_DSA /* Ether Type DSA */
227} GT_FRAME_MODE;
228
229/*
230 * Typedef: enum GT_JUMBO_MODE
231 *
232 * Description: Defines Jumbo Frame Size allowed to be tx and rx
233 *
234 * Fields:
235 * GT_JUMBO_MODE_1522 - Rx and Tx frames with max byte of 1522.
236 * GT_JUMBO_MODE_2048 - Rx and Tx frames with max byte of 2048.
237 * GT_JUMBO_MODE_10240 - Rx and Tx frames with max byte of 10240.
238 *
239 */
240typedef enum
241{
242 GT_JUMBO_MODE_1522 = 0,
243 GT_JUMBO_MODE_2048,
244 GT_JUMBO_MODE_10240
245} GT_JUMBO_MODE;
246
247
248/*
249 * Typedef: enum GT_PRI_OVERRIDE
250 *
251 * Description: Defines the priority override
252 *
253 * Fields:
254 * PRI_OVERRIDE_NONE - Normal frame priority processing occurs.
255 * PRI_OVERRIDE_FRAME_QUEUE -
256 * Both frame and queue overrides take place on the frame.
257 * PRI_OVERRIDE_FRAME -
258 * Overwite the frame's FPri (frame priority).
259 * If the frame egresses tagged, the priority in the frame will be
260 * the overwritten priority value.
261 * PRI_OVERRIDE_QUEUE -
262 * Overwite the frame's QPri (queue priority).
263 * QPri is used internally to map the frame to one of the egress
264 * queues inside the switch.
265 *
266 */
267typedef enum
268{
269 PRI_OVERRIDE_NONE = 0,
270 PRI_OVERRIDE_FRAME_QUEUE,
271 PRI_OVERRIDE_FRAME,
272 PRI_OVERRIDE_QUEUE
273} GT_PRI_OVERRIDE;
274
275
276/*
277 * Typedef: enum GT_FRAME_POLICY
278 *
279 * Description: Defines the policy of the frame
280 *
281 * Fields:
282 * FRAME_POLICY_NONE - Normal frame switching
283 * FRAME_POLICY_MIRROR - Mirror(copy) frame to the MirrorDest port
284 * FRAME_POLICY_TRAP - Trap(re-direct) frame to the CPUDest port
285 * FRAME_POLICY_DISCARD - Discard(filter) the frame
286 *
287 */
288typedef enum
289{
290 FRAME_POLICY_NONE = 0,
291 FRAME_POLICY_MIRROR,
292 FRAME_POLICY_TRAP,
293 FRAME_POLICY_DISCARD
294} GT_FRAME_POLICY;
295
296
297/*
298 * Typedef: enum GT_POLICY_TYPE
299 *
300 * Description: Defines the policy type
301 *
302 * Fields:
303 * POLICY_TYPE_DA - Policy based on Destination Address
304 * POLICY_TYPE_SA - Policy based on Source Address
305 * POLICY_TYPE_VTU - Policy based on VID
306 * POLICY_TYPE_ETYPE - based on Ether Type of a frame
307 * POLICY_TYPE_PPPoE - Policy for the frame with Ether Type of 0x8863
308 * POLICY_TYPE_VBAS - Policy for the frame with Ether Type of 0x8200
309 * POLICY_TYPE_OPT82 - Policy for the frame with DHCP Option 82
310 * POLICY_TYPE_UDP - Policy for the frame with Broadcast IPv4 UDP or
311 * Multicast IPv6 UDP
312 */
313typedef enum
314{
315 POLICY_TYPE_DA,
316 POLICY_TYPE_SA,
317 POLICY_TYPE_VTU,
318 POLICY_TYPE_ETYPE,
319 POLICY_TYPE_PPPoE,
320 POLICY_TYPE_VBAS,
321 POLICY_TYPE_OPT82,
322 POLICY_TYPE_UDP
323} GT_POLICY_TYPE;
324
325
326/*
327 * Typedef: enum GT_PRI_OVERRIDE_FTYPE
328 *
329 * Description: Definition of the frame type for priority override
330 *
331 * Fields:
332 * FTYPE_DSA_TO_CPU_BPDU -
333 * Used on multicast DSA To_CPU frames with a Code of 0x0 (BPDU/MGMT).
334 * Not used on non-DSA Control frames.
335 * FTYPE_DSA_TO_CPU_F2R -
336 * Used on DSA To_CPU frames with a Code of 0x1 (Frame to Register
337 * Reply). Not used on non-DSA Control frames.
338 * FTYPE_DSA_TO_CPU_IGMP -
339 * Used on DSA To_CPU frames with a Code of 0x2 (IGMP/MLD Trap)
340 * and on non-DSA Control frames that are IGMP or MLD trapped
341 * FTYPE_DSA_TO_CPU_TRAP -
342 * Used on DSA To_CPU frames with a Code of 0x3 (Policy Trap) and
343 * on non-DSA Control frames that are Policy Trapped
344 * FTYPE_DSA_TO_CPU_ARP -
345 * Used on DSA To_CPU frames with a Code of 0x4 (ARP Mirror) and
346 * on non-DSA Control frames that are ARP Mirrored (see gprtSetARPtoCPU API).
347 * FTYPE_DSA_TO_CPU_MIRROR -
348 * Used on DSA To_CPU frames with a Code of 0x5 (Policy Mirror) and
349 * on non-DSA Control frames that are Policy Mirrored (see gprtSetPolicy API).
350 * FTYPE_DSA_TO_CPU_RESERVED -
351 * Used on DSA To_CPU frames with a Code of 0x6 (Reserved). Not
352 * used on non-DSA Control frames.
353 * FTYPE_DSA_TO_CPU_UCAST_MGMT -
354 * Used on unicast DSA To_CPU frames with a Code of 0x0 (unicast
355 * MGMT). Not used on non-DSA Control frames.
356 * FTYPE_DSA_FROM_CPU -
357 * Used on DSA From_CPU frames. Not used on non-DSA Control frame
358 * FTYPE_DSA_CROSS_CHIP_FC -
359 * Used on DSA Cross Chip Flow Control frames (To_Sniffer Flow
360 * Control). Not used on non-DSA Control frames.
361 * FTYPE_DSA_CROSS_CHIP_EGRESS_MON -
362 * Used on DSA Cross Chip Egress Monitor frames (To_Sniffer Tx).
363 * Not used on non-DSA Control frames.
364 * FTYPE_DSA_CROSS_CHIP_INGRESS_MON -
365 * Used on DSA Cross Chip Ingress Monitor frames (To_Sniffer Rx).
366 * Not used on non-DSA Control frames.
367 * FTYPE_PORT_ETYPE_MATCH -
368 * Used on normal network ports (see gprtSetFrameMode API)
369 * on frames whose Ethertype matches the port's PortEType register.
370 * Not used on non-DSA Control frames.
371 * FTYPE_BCAST_NON_DSA_CONTROL -
372 * Used on Non-DSA Control frames that contain a Broadcast
373 * destination address. Not used on DSA Control frames.
374 * FTYPE_PPPoE_NON_DSA_CONTROL -
375 * Used on Non-DSA Control frames that contain an Ether Type 0x8863
376 * (i.e., PPPoE frames). Not used on DSA Control frames.
377 * FTYPE_IP_NON_DSA_CONTROL -
378 * Used on Non-DSA Control frames that contain an IPv4 or IPv6 Ether
379 * Type. Not used on DSA Control frames.
380 */
381typedef enum
382{
383 FTYPE_DSA_TO_CPU_BPDU = 0,
384 FTYPE_DSA_TO_CPU_F2R,
385 FTYPE_DSA_TO_CPU_IGMP,
386 FTYPE_DSA_TO_CPU_TRAP,
387 FTYPE_DSA_TO_CPU_ARP,
388 FTYPE_DSA_TO_CPU_MIRROR,
389 FTYPE_DSA_TO_CPU_RESERVED,
390 FTYPE_DSA_TO_CPU_UCAST_MGMT,
391 FTYPE_DSA_FROM_CPU,
392 FTYPE_DSA_CROSS_CHIP_FC,
393 FTYPE_DSA_CROSS_CHIP_EGRESS_MON,
394 FTYPE_DSA_CROSS_CHIP_INGRESS_MON,
395 FTYPE_PORT_ETYPE_MATCH,
396 FTYPE_BCAST_NON_DSA_CONTROL,
397 FTYPE_PPPoE_NON_DSA_CONTROL,
398 FTYPE_IP_NON_DSA_CONTROL
399} GT_PRI_OVERRIDE_FTYPE;
400
401
402/*
403 * Typedef: struct GT_QPRI_TBL_ENTRY
404 *
405 * Description: This structure is used for the entry of Queue Priority Override
406 * Table.
407 *
408 * Fields:
409 * qPriEn - GT_TRUE to enable Queue Priority, GT_FALSE otherwise
410 * qPriority - priority to be overridden ( 0 ~ 3 ) only if qPriEn is GT_TRUE
411 * When qPriEn is GT_FALSE, qPriority should be ignored.
412 *
413 * Notes: If device does not support qPriAvbEn, qPriAvbEn and qAvbPriority fields
414 * will be ignored.
415 */
416typedef struct
417{
418 GT_BOOL qPriEn;
419 GT_U32 qPriority;
420}GT_QPRI_TBL_ENTRY;
421
422
423/*
424 * Typedef: struct GT_FPRI_TBL_ENTRY
425 *
426 * Description: This structure is used for the entry of Frame Priority Override
427 * Table.
428 *
429 * Fields:
430 * fPriEn - GT_TRUE to enable Frame Priority, GT_FALSE otherwise
431 * fPriority - priority to be overridden ( 0 ~ 7 ) only if fPriEn is GT_TRUE
432 * When fPriEn is GT_FALSE, fPriority should be ignored.
433 */
434typedef struct
435{
436 GT_BOOL fPriEn;
437 GT_U32 fPriority;
438}GT_FPRI_TBL_ENTRY;
439
440
441/* Maximam number of ports a switch may have. */
442#define MAX_SWITCH_PORTS 11
443#define VERSION_MAX_LEN 30
444#define MAX_QOS_WEIGHTS 128
445
446/*
447 * Typedef: struct GT_QoS_WEIGHT
448 *
449 * Description: This structure is used for Programmable Round Robin Weights.
450 *
451 * Fields:
452 * len - length of the valid queue data
453 * queue - upto 128 queue data
454 */
455typedef struct
456{
457 GT_U32 len;
458 GT_U8 queue[MAX_QOS_WEIGHTS];
459}GT_QoS_WEIGHT;
460
461
462
463/*
464 * Typedef: struct GT_VERSION
465 *
466 * Description: This struct holds the package version.
467 *
468 * Fields:
469 * version - string array holding the version.
470 *
471 */
472typedef struct
473{
474 GT_U8 version[VERSION_MAX_LEN];
475}GT_VERSION;
476
477
478/*
479 * typedef: struct GT_RMU
480 *
481 * Description: This struct holds the Remote Management Unit mode.
482 *
483 * Fields:
484 * rmuEn - enable or disable RMU
485 * port - logical port where RMU is enabled
486 */
487typedef struct
488{
489 GT_BOOL rmuEn;
490 GT_LPORT port;
491} GT_RMU;
492
493
494
495/*
496 * Typedef:
497 *
498 * Description: Defines the different sizes of the Mac address table.
499 *
500 * Fields:
501 * ATU_SIZE_256 - 256 entries Mac address table.
502 * ATU_SIZE_512 - 512 entries Mac address table.
503 * ATU_SIZE_1024 - 1024 entries Mac address table.
504 * ATU_SIZE_2048 - 2048 entries Mac address table.
505 * ATU_SIZE_4096 - 4096 entries Mac address table.
506 * ATU_SIZE_8192 - 8192 entries Mac address table.
507 *
508 */
509typedef enum
510{
511 ATU_SIZE_256,
512 ATU_SIZE_512,
513 ATU_SIZE_1024,
514 ATU_SIZE_2048,
515 ATU_SIZE_4096,
516 ATU_SIZE_8192
517}ATU_SIZE;
518
519
520/*
521 * typedef: enum GT_PORT_STP_STATE
522 *
523 * Description: Enumeration of the port spanning tree state.
524 *
525 * Enumerations:
526 * GT_PORT_DISABLE - port is disabled.
527 * GT_PORT_BLOCKING - port is in blocking/listening state.
528 * GT_PORT_LEARNING - port is in learning state.
529 * GT_PORT_FORWARDING - port is in forwarding state.
530 */
531typedef enum
532{
533 GT_PORT_DISABLE = 0,
534 GT_PORT_BLOCKING,
535 GT_PORT_LEARNING,
536 GT_PORT_FORWARDING
537} GT_PORT_STP_STATE;
538
539
540/*
541 * typedef: enum GT_EGRESS_MODE
542 *
543 * Description: Enumeration of the port egress mode.
544 *
545 * Enumerations:
546 * GT_UNMODIFY_EGRESS - frames are transmited unmodified.
547 * GT_TAGGED_EGRESS - all frames are transmited tagged.
548 * GT_UNTAGGED_EGRESS - all frames are transmited untagged.
549 * GT_ADD_TAG - always add a tag. (or double tag)
550 */
551typedef enum
552{
553 GT_UNMODIFY_EGRESS = 0,
554 GT_UNTAGGED_EGRESS,
555 GT_TAGGED_EGRESS,
556 GT_ADD_TAG
557} GT_EGRESS_MODE;
558
559/* typedef: enum GT_DOT1Q_MODE */
560
561typedef enum
562{
563 GT_DISABLE = 0,
564 GT_FALLBACK,
565 GT_CHECK,
566 GT_SECURE
567} GT_DOT1Q_MODE;
568
569
570/* typedef: enum GT_SW_MODE */
571
572typedef enum
573{
574 GT_CPU_ATTATCHED = 0, /* ports come up disabled */
575 GT_BACKOFF, /* EEPROM attac mode with old half duplex backoff mode */
576 GT_STAND_ALONE, /* ports come up enabled, ignore EEPROM */
577 GT_EEPROM_ATTATCHED /* EEPROM defined prot states */
578} GT_SW_MODE;
579
580
581/*
582 * Typedef: enum GT_ATU_OPERARION
583 *
584 * Description: Defines the different ATU and VTU operations
585 *
586 * Fields:
587 * FLUSH_ALL - Flush all entries.
588 * FLUSH_UNLOCKED - Flush all unlocked entries in ATU.
589 * LOAD_PURGE_ENTRY - Load / Purge entry.
590 * GET_NEXT_ENTRY - Get next ATU or VTU entry.
591 * FLUSH_ALL_IN_DB - Flush all entries in a particular DBNum.
592 * FLUSH_UNLOCKED_IN_DB - Flush all unlocked entries in a particular DBNum.
593 * SERVICE_VIOLATONS - sevice violations of VTU
594 *
595 */
596typedef enum
597{
598 FLUSH_ALL = 1, /* for both atu and vtu */
599 FLUSH_UNLOCKED, /* for atu only */
600 LOAD_PURGE_ENTRY, /* for both atu and vtu */
601 GET_NEXT_ENTRY, /* for both atu and vtu */
602 FLUSH_ALL_IN_DB, /* for atu only */
603 FLUSH_UNLOCKED_IN_DB, /* for atu only */
604 SERVICE_VIOLATIONS /* for vtu only */
605} GT_ATU_OPERATION, GT_VTU_OPERATION;
606
607
608/*
609 * typedef: enum GT_FLUSH_CMD
610 *
611 * Description: Enumeration of the address translation unit flush operation.
612 *
613 * Enumerations:
614 * GT_FLUSH_ALL - flush all entries.
615 * GT_FLUSH_ALL_UNBLK - flush all unblocked (or unlocked).
616 * GT_FLUSH_ALL_UNLOCKED - flush all unblocked (or unlocked).
617 */
618typedef enum
619{
620 GT_FLUSH_ALL = 1,
621 GT_FLUSH_ALL_UNBLK = 2,
622 GT_FLUSH_ALL_UNLOCKED = 2
623}GT_FLUSH_CMD;
624
625/*
626 * typedef: enum GT_MOVE_CMD
627 *
628 * Description: Enumeration of the address translation unit move or remove operation.
629 * When destination port is set to 0xF, Remove operation occurs.
630 *
631 * Enumerations:
632 * GT_MOVE_ALL - move all entries.
633 * GT_MOVE_ALL_UNBLK - move all unblocked (or unlocked).
634 * GT_MOVE_ALL_UNLOCKED - move all unblocked (or unlocked).
635 */
636typedef enum
637{
638 GT_MOVE_ALL = 1,
639 GT_MOVE_ALL_UNBLK = 2,
640 GT_MOVE_ALL_UNLOCKED = 2
641}GT_MOVE_CMD;
642
643
644/*
645 * typedef: enum GT_ATU_UC_STATE
646 *
647 * Description:
648 * Enumeration of the address translation unit entry state of unicast
649 * entris.
650 *
651 * Enumerations:
652 * GT_UC_INVALID - invalid entry.
653 * GT_UC_DYNAMIC - unicast dynamic entry.
654 * GT_UC_NO_PRI_TO_CPU_STATIC_NRL
655 * - static unicast entry that will be forwarded to CPU without
656 * forcing priority and without rate limiting.
657 * GT_UC_TO_CPU_STATIC_NRL
658 * - static unicast entry that will be forwarded to CPU without
659 * rate limiting.
660 * GT_UC_NO_PRI_STATIC_NRL
661 * - static unicast entry without forcing priority and without.
662 * rate limiting.
663 * GT_UC_NO_PRI_STATIC_AVB_ENTRY
664 * - static unicast AVB entry without forcing priority if MacAvb is enabled.
665 * GT_UC_STATIC_NRL - static unicast entry without rate limiting.
666 * GT_UC_STATIC_AVB_ENTRY - static unicast AVB entry if MacAvb is enabled .
667 * GT_UC_NO_PRI_TO_CPU_STATIC
668 * - static unicast entry that will be forwarded to CPU without
669 * forcing priority.
670 * GT_UC_TO_CPU_STATIC - static unicast entry that will be forwarded to CPU.
671 * GT_UC_NO_PRI_STATIC - static unicast entry without forcing priority.
672 * GT_UC_STATIC - static unicast entry.
673 *
674 * Note: Please refer to the device datasheet for detailed unicast entry states
675 * that are supported by the device.
676 */
677typedef enum
678{
679 GT_UC_INVALID = 0,
680 GT_UC_DYNAMIC = 0x1,
681
682 GT_UC_NO_PRI_TO_CPU_STATIC_NRL = 0x8,
683 GT_UC_TO_CPU_STATIC_NRL = 0x9,
684 GT_UC_NO_PRI_STATIC_NRL = 0xA,
685 GT_UC_NO_PRI_STATIC_AVB_ENTRY = 0xA,
686 GT_UC_STATIC_NRL = 0xB,
687 GT_UC_STATIC_AVB_ENTRY = 0xB,
688
689 GT_UC_NO_PRI_TO_CPU_STATIC = 0xC,
690 GT_UC_TO_CPU_STATIC = 0xD,
691 GT_UC_NO_PRI_STATIC = 0xE,
692 GT_UC_STATIC = 0xF
693} GT_ATU_UC_STATE;
694
695
696/*
697 * typedef: enum GT_ATU_MC_STATE
698 *
699 * Description:
700 * Enumeration of the address translation unit entry state of multicast
701 * entris.
702 *
703 * Enumerations:
704 * GT_MC_INVALID - invalid entry.
705 * GT_MC_MGM_STATIC - static multicast management entries.
706 * GT_MC_STATIC - static multicast regular entris.
707 * GT_MC_STATIC_AVB_ENTRY- static AVB entry if MacAvb is enalbed.
708 * GT_MC_PRIO_MGM_STATIC - static multicast management entries with
709 * priority.
710 * GT_MC_PRIO_STATIC - static multicast regular entris with priority.
711 * GT_MC_PRIO_STATIC_AVB_ENTRY - static multicast AVB Entry with priority if MacAvb is enabled
712 * GT_MC_PRIO_STATIC_UNLIMITED_RATE - static multicast regular entris with priority
713 * and without rate limiting.
714 * GT_MC_MGM_STATIC_UNLIMITED_RATE - static multicast management entries without
715 * rate limiting.
716 * GT_MC_STATIC_UNLIMITED_RATE - static multicast regular entris without
717 * rate limiting.
718 * GT_MC_PRIO_MGM_STATIC_UNLIMITED_RATE - static multicast management entries with
719 * priority and without rate limiting.
720 *
721 * Note: Please refer to the device datasheet for detailed multicast entry states
722 * that are supported by the device.
723 */
724typedef enum
725{
726 GT_MC_INVALID = 0,
727 GT_MC_MGM_STATIC_UNLIMITED_RATE = 0x4,
728 GT_MC_STATIC_UNLIMITED_RATE = 0x5,
729 GT_MC_STATIC_AVB_ENTRY = 0x5,
730 GT_MC_MGM_STATIC = 0x6,
731 GT_MC_STATIC = 0x7,
732 GT_MC_PRIO_MGM_STATIC_UNLIMITED_RATE = 0xC,
733 GT_MC_PRIO_STATIC_UNLIMITED_RATE = 0xD,
734 GT_MC_PRIO_STATIC_AVB_ENTRY = 0xD,
735 GT_MC_PRIO_MGM_STATIC = 0xE,
736 GT_MC_PRIO_STATIC = 0xF
737} GT_ATU_MC_STATE;
738
739
740/*
741 * typedef: struct GT_ATU_EXT_PRI
742 *
743 * Description:
744 * Extanded priority information for the address tarnslaton unit entry.
745 *
746 * macFPri data is used to override the frame priority on any frame associated
747 * with this MAC, if the useMacFPri is GT_TRUE and the port's SA and/or
748 * DA FPriOverride are enabled. SA Frame Priority Overrides can only occur on
749 * MAC addresses that are Static or where the Port is Locked, and where the port
750 * is mapped source port for the MAC address.
751 *
752 * macQPri data is used to override the queue priority on any frame associated
753 * with this MAC, if the EntryState indicates Queue Priority Override and the
754 * port's SA and/or DA QPriOverride are enabled.
755 *
756 * Fields:
757 * useMacFPri - Use MAC frame priority override. When this is GT_TRUE,
758 * MacFPri data can be used to override the frame priority on
759 * any frame associated with this MAC.
760 * macFPri - MAC frame priority data (0 ~ 7).
761 * macQPri - MAC queue priority data (0 ~ 3).
762 *
763 * Comment:
764 * Please refer to the device datasheet to find out if this feature is supported.
765 * When this structure is implemented, the followings are the devices supporting
766 * this feature:
767 * 88E6065, 88E6035, and 88E6055 support all extanded priority data.
768 * 88E6061 and 88E6031 support only macQPri data
769 */
770typedef struct
771{
772 GT_BOOL useMacFPri;
773 GT_U8 macFPri;
774 GT_U8 macQPri;
775} GT_ATU_EXT_PRI;
776
777
778/*
779 * typedef: struct GT_ATU_ENTRY
780 *
781 * Description: address tarnslaton unit Entry
782 *
783 * Fields:
784 * macAddr - mac address
785 * trunkMember- GT_TRUE if entry belongs to a Trunk. This field will be
786 * ignored if device does not support Trunk.
787 * portVec - port Vector.
788 * If trunkMember field is GT_TRUE, this value represents trunk ID.
789 * prio - entry priority.
790 * entryState - the entry state.
791 * DBNum - ATU MAC Address Database number. If multiple address
792 * databases are not being used, DBNum should be zero.
793 * If multiple address databases are being used, this value
794 * should be set to the desired address database number.
795 * exPrio - extanded priority information. If device support extanded
796 * priority, prio field should be ignored.
797 *
798 * Comment:
799 * The entryState union Type is determine according to the Mac Type.
800 */
801typedef struct
802{
803 GT_ETHERADDR macAddr;
804 GT_BOOL trunkMember;
805 GT_U32 portVec;
806 GT_U8 prio;
807 GT_U8 reserved;
808 GT_U16 DBNum;
809 union
810 {
811 GT_ATU_UC_STATE ucEntryState;
812 GT_ATU_MC_STATE mcEntryState;
813 } entryState;
814 GT_ATU_EXT_PRI exPrio;
815} GT_ATU_ENTRY;
816
817
818/*
819 * typedef: struct GT_VTU_DATA
820 *
821 * Description: VLAN tarnslaton unit Data Register
822 *
823 * Fields:
824 * memberTagP - Membership and Egress Tagging
825 * memberTagP[0] is for Port 0, MemberTagP[1] is for port 1, and so on
826 *
827 * Comment:
828 * MAX_SWITCH_PORTS is 10 for Octane.
829 * In the case of FullSail, there are 3 ports. So, the rest 7 is ignored in memeberTagP
830 */
831typedef struct
832{
833 GT_U8 memberTagP[MAX_SWITCH_PORTS];
834 GT_U8 portStateP[MAX_SWITCH_PORTS];
835} GT_VTU_DATA;
836
837/*
838 * definition for MEMBER_TAG
839 */
840#define MEMBER_EGRESS_UNMODIFIED 0
841#define NOT_A_MEMBER 1
842#define MEMBER_EGRESS_UNTAGGED 2
843#define MEMBER_EGRESS_TAGGED 3
844
845/*
846 * typedef: struct GT_VTU_EXT_INFO
847 *
848 * Description:
849 * Extanded VTU Entry information for Priority Override and Non Rate Limit.
850 * Frame Priority is used to as the tag's PRI bits if the frame egresses
851 * the switch tagged. The egresss queue the frame is switch into is not
852 * modified by the Frame Priority Override.
853 * Queue Priority is used to determine the egress queue the frame is
854 * switched into. If the frame egresses tagged, the priority in the frame
855 * will not be modified by a Queue Priority Override.
856 * NonRateLimit for VID is used to indicate any frames associated with this
857 * VID are to bypass ingress and egress rate limiting, if the ingress
858 * port's VID NRateLimit is also enabled.
859 *
860 * Fields:
861 * useVIDFPri - Use VID frame priority override. When this is GT_TRUE and
862 * VIDFPriOverride of the ingress port of the frame is enabled,
863 * vidFPri data is used to override the frame priority on
864 * any frame associated with this VID.
865 * vidFPri - VID frame priority data (0 ~ 7).
866 * useVIDQPri - Use VID queue priority override. When this is GT_TRUE and
867 * VIDQPriOverride of the ingress port of the frame is enabled,
868 * vidQPri data can be used to override the queue priority on
869 * any frame associated with this VID.
870 * vidQPri - VID queue priority data (0 ~ 3).
871 * vidNRateLimit - bypass rate ingress and egress limiting
872 *
873 * Comment:
874 * Please refer to the device datasheet to find out if this feature is supported.
875 * When this structure is implemented, the followings are the devices supporting
876 * this feature:
877 * 88E6065, 88E6035, and 88E6055 support all data.
878 * 88E6061 and 88E6031 support only vidNRateLimit.
879 */
880typedef struct
881{
882 GT_BOOL useVIDFPri;
883 GT_U8 vidFPri;
884 GT_BOOL useVIDQPri;
885 GT_U8 vidQPri;
886 GT_BOOL vidNRateLimit;
887} GT_VTU_EXT_INFO;
888
889
890/*
891 * typedef: struct GT_VTU_ENTRY
892 *
893 * Description: VLAN tarnslaton unit Entry
894 * Each field in the structure is device specific, i.e., some fields may not
895 * be supported by the used switch device. In such case, those fields are
896 * ignored by the DSDT driver. Please refer to the datasheet for the list of
897 * supported fields.
898 *
899 * Fields:
900 * DBNum - database number or FID (forwarding information database)
901 * vid - VLAN ID
902 * vtuData - VTU data
903 * vidPriOverride - override the priority on any frame associated with this VID
904 * vidPriority - VID Priority bits (0 ~ 7)
905 * sid - 802.1s Port State Database ID
906 * vidPolicy - indicate that the frame with this VID uses VID Policy
907 * (see gprtSetPolicy API).
908 * vidExInfo - extanded information for VTU entry. If the device supports extanded
909 * information, vidPriorityOverride and vidPriority values are
910 * ignored.
911 */
912typedef struct
913{
914 GT_U16 DBNum;
915 GT_U16 vid;
916 GT_VTU_DATA vtuData;
917 GT_BOOL vidPriOverride;
918 GT_U8 vidPriority;
919 GT_U8 sid;
920 GT_BOOL vidPolicy;
921 GT_VTU_EXT_INFO vidExInfo;
922} GT_VTU_ENTRY;
923
924
925/*
926 * Typedef: enum GT_STU_OPERARION
927 *
928 * Description: Defines the STU operations
929 *
930 * Fields:
931 * LOAD_PURGE_STU_ENTRY - Load / Purge entry.
932 * GET_NEXT_STU_ENTRY - Get next STU entry.
933 *
934 */
935typedef enum
936{
937 LOAD_PURGE_STU_ENTRY = 5,
938 GET_NEXT_STU_ENTRY =6
939} GT_STU_OPERATION;
940
941
942/*
943 * typedef: struct GT_STU_ENTRY
944 *
945 * Description: 802.1s Port State Information Database (STU) Entry
946 *
947 * Fields:
948 * sid - STU ID
949 * portState - Per VLAN Port States for each port.
950 */
951typedef struct
952{
953 GT_U16 sid;
954 GT_PORT_STP_STATE portState[MAX_SWITCH_PORTS];
955} GT_STU_ENTRY;
956
957
958/*
959 * typedef: struct GT_VTU_INT_STATUS
960 *
961 * Description: VLAN tarnslaton unit interrupt status
962 *
963 * Fields:
964 * intCause - VTU Interrupt Cause
965 * GT_VTU_FULL_VIOLATION,GT_MEMEBER_VIOLATION,or
966 * GT_MISS_VIOLATION
967 * SPID - source port number
968 * if intCause is GT_VTU_FULL_VIOLATION, it means nothing
969 * vid - VLAN ID
970 * if intCause is GT_VTU_FULL_VIOLATION, it means nothing
971 */
972typedef struct
973{
974 GT_U16 vtuIntCause;
975 GT_U8 spid;
976 GT_U16 vid;
977} GT_VTU_INT_STATUS;
978
979/*
980 * typedef: struct GT_ATU_INT_STATUS
981 *
982 * Description: VLAN tarnslaton unit interrupt status
983 *
984 * Fields:
985 * intCause - ATU Interrupt Cause
986 * GT_FULL_VIOLATION,GT_MEMEBER_VIOLATION,
987 * GT_MISS_VIOLATION, GT_AGE_VIOLATION, or
988 * GT_AGE_OUT_VIOLATION
989 * SPID - source port number
990 * if intCause is GT_FULL_VIOLATION, it means nothing
991 * DBNum - DB Num (or FID)
992 * if intCause is GT_FULL_VIOLATION, it means nothing
993 * macAddr - MAC Address
994 */
995typedef struct
996{
997 GT_U16 atuIntCause;
998 GT_U8 spid;
999 GT_U8 dbNum;
1000 GT_ETHERADDR macAddr;
1001} GT_ATU_INT_STATUS;
1002
1003/*
1004* Definition for VTU interrupt
1005*/
1006#define GT_MEMBER_VIOLATION 0x4
1007#define GT_MISS_VIOLATION 0x2
1008#define GT_VTU_FULL_VIOLATION 0x1
1009/*
1010* Definitions for ATU interrupt in Gigabit switch are the same as
1011* the ones for VTU interrupt. Here we just redefine the FULL_VIOLATION for
1012* both VTU and ATU.
1013*/
1014#define GT_FULL_VIOLATION 0x1
1015
1016#define GT_AGE_VIOLATION 0x8
1017#define GT_AGE_OUT_VIOLATION 0x10
1018
1019
1020/*
1021 * Typedef: enum GT_PVT_OPERATION
1022 *
1023 * Description: Defines the PVT (Cross Chip Port VLAN Table) Operation type
1024 *
1025 * Fields:
1026 * PVT_INITIALIZE - Initialize all resources to the inital state
1027 * PVT_WRITE - Write to the selected PVT entry
1028 * PVT_READ - Read from the selected PVT entry
1029 */
1030typedef enum
1031{
1032 PVT_INITIALIZE = 0x1,
1033 PVT_WRITE = 0x3,
1034 PVT_READ = 0x4
1035} GT_PVT_OPERATION;
1036
1037
1038/*
1039 * typedef: struct GT_PVT_OP_DATA
1040 *
1041 * Description: data required by PVT (Cross Chip Port VLAN Table) Operation
1042 *
1043 * Fields:
1044 * pvtAddr - pointer to the desired entry of PVT
1045 * pvtData - Cross Chip Port VLAN data for the entry pointed by pvtAddr
1046 */
1047typedef struct
1048{
1049 GT_U32 pvtAddr;
1050 GT_U32 pvtData;
1051} GT_PVT_OP_DATA;
1052
1053
1054/*
1055 * typedef: enum GT_PIRL_FC_DEASSERT
1056 *
1057 * Description: Enumeration of the port flow control de-assertion mode on PIRL.
1058 *
1059 * Enumerations:
1060 * GT_PIRL_FC_DEASSERT_EMPTY -
1061 * De-assert when the ingress rate resource has become empty
1062 * GT_PIRL_FC_DEASSERT_CBS_LIMIT -
1063 * De-assert when the ingress rate resource has enough room as
1064 * specified by the CBSLimit.
1065 */
1066typedef enum
1067{
1068 GT_PIRL_FC_DEASSERT_EMPTY = 0,
1069 GT_PIRL_FC_DEASSERT_CBS_LIMIT
1070} GT_PIRL_FC_DEASSERT;
1071
1072
1073/*
1074 * typedef: enum GT_PIRL_ELIMIT_MODE
1075 *
1076 * Description: Enumeration of the port egress rate limit counting mode.
1077 *
1078 * Enumerations:
1079 * GT_PIRL_ELIMIT_FRAME -
1080 * Count the number of frames
1081 * GT_PIRL_ELIMIT_LAYER1 -
1082 * Count all Layer 1 bytes:
1083 * Preamble (8bytes) + Frame's DA to CRC + IFG (12bytes)
1084 * GT_PIRL_ELIMIT_LAYER2 -
1085 * Count all Layer 2 bytes: Frame's DA to CRC
1086 * GT_PIRL_ELIMIT_LAYER3 -
1087 * Count all Layer 3 bytes:
1088 * Frame's DA to CRC - 18 - 4 (if frame is tagged)
1089 */
1090typedef enum
1091{
1092 GT_PIRL_ELIMIT_FRAME = 0,
1093 GT_PIRL_ELIMIT_LAYER1,
1094 GT_PIRL_ELIMIT_LAYER2,
1095 GT_PIRL_ELIMIT_LAYER3
1096} GT_PIRL_ELIMIT_MODE;
1097
1098
1099/* typedef: enum GT_RATE_LIMIT_MODE
1100 * The ingress limit mode in the rate control register (0xA)
1101 */
1102
1103typedef enum
1104{
1105 GT_LIMT_ALL = 0, /* limit and count all frames */
1106 GT_LIMIT_FLOOD, /* limit and count Broadcast, Multicast and flooded unicast frames */
1107 GT_LIMIT_BRDCST_MLTCST, /* limit and count Broadcast and Multicast frames */
1108 GT_LIMIT_BRDCST /* limit and count Broadcast frames */
1109} GT_RATE_LIMIT_MODE;
1110
1111/* typedef: enum GT_PRI0_RATE
1112 * The ingress data rate limit for priority 0 frames
1113 */
1114
1115typedef enum
1116{
1117 GT_NO_LIMIT = 0, /* Not limited */
1118 GT_128K, /* 128K bits/sec */
1119 GT_256K, /* 256K bits/sec */
1120 GT_512K, /* 512 bits/sec */
1121 GT_1M, /* 1M bits/sec */
1122 GT_2M, /* 2M bits/sec */
1123 GT_4M, /* 4M bits/sec */
1124 GT_8M, /* 8M bits/sec */
1125 GT_16M, /* 16M bits/sec, Note: supported only by Gigabit Ethernet Switch */
1126 GT_32M, /* 32M bits/sec, Note: supported only by Gigabit Ethernet Switch */
1127 GT_64M, /* 64M bits/sec, Note: supported only by Gigabit Ethernet Switch */
1128 GT_128M, /* 128M bits/sec, Note: supported only by Gigabit Ethernet Switch */
1129 GT_256M /* 256M bits/sec, Note: supported only by Gigabit Ethernet Switch */
1130} GT_PRI0_RATE,GT_EGRESS_RATE;
1131
1132
1133/*
1134 * Typedef: union GT_ERATE_TYPE
1135 *
1136 * Description: Egress Rate
1137 *
1138 * Fields:
1139 * definedRate - GT_EGRESS_RATE enum type should be used on the following devices:
1140 * 88E6218, 88E6318, 88E6063, 88E6083, 88E6181, 88E6183, 88E6093
1141 * 88E6095, 88E6185, 88E6108, 88E6065, 88E6061, and their variations.
1142 * kbRate - rate in kbps that should be used on the following devices:
1143 * 88E6097, 88E6096 with count mode of non frame, such as
1144 * ALL_LAYER1, ALL_LAYER2, and ALL_LAYER3
1145 * 64kbps ~ 1Mbps : increments of 64kbps,
1146 * 1Mbps ~ 100Mbps : increments of 1Mbps, and
1147 * 100Mbps ~ 1000Mbps: increments of 10Mbps
1148 * Therefore, the valid values are:
1149 * 64, 128, 192, 256, 320, 384,..., 960,
1150 * 1000, 2000, 3000, 4000, ..., 100000,
1151 * 110000, 120000, 130000, ..., 1000000.
1152 * fRate - frame per second that should be used on the following devices:
1153 * 88E6097, 88E6096 with count mode of frame (GT_PIRL_COUNT_FRAME)
1154 */
1155typedef union
1156{
1157 GT_EGRESS_RATE definedRate;
1158 GT_U32 kbRate;
1159 GT_U32 fRate;
1160} GT_ERATE_TYPE;
1161
1162/*
1163 * Formula for Rate Limit of Gigabit Switch family and Enhanced FastEthernet Switch
1164 */
1165#define GT_GET_RATE_LIMIT(_kbps) \
1166 ((_kbps)?(8000000 / (28 * (_kbps))):0)
1167#define GT_GET_RATE_LIMIT2(_kbps) \
1168 ((_kbps)?(8000000 / (32 * (_kbps)) + (8000000 % (32 * (_kbps))?1:0)):0)
1169#define GT_GET_RATE_LIMIT3(_kbps) \
1170 ((_kbps)?(8000000 / (40 * (_kbps)) + (8000000 % (40 * (_kbps))?1:0)):0)
1171
1172#define MAX_RATE_LIMIT 256000 /* unit of Kbps */
1173#define MIN_RATE_LIMIT 65 /* unit of Kbps */
1174
1175
1176#define GT_GET_RATE_LIMIT_PER_FRAME(_frames, _dec) \
1177 ((_frames)?(1000000000 / (32 * (_frames)) + (1000000000 % (32 * (_frames))?1:0)):0)
1178
1179#define GT_GET_RATE_LIMIT_PER_BYTE(_kbps, _dec) \
1180 ((_kbps)?((8000000*(_dec)) / (32 * (_kbps)) + ((8000000*(_dec)) % (32 * (_kbps))?1:0)):0)
1181
1182/*
1183 * typedef: enum GT_BURST_SIZE
1184 * The ingress data rate limit burst size windows selection
1185 */
1186
1187typedef enum
1188{
1189 GT_BURST_SIZE_12K = 0, /* 12K byte burst size */
1190 GT_BURST_SIZE_24K, /* 24K byte burst size */
1191 GT_BURST_SIZE_48K, /* 48K byte burst size */
1192 GT_BURST_SIZE_96K /* 96K byte burst size */
1193} GT_BURST_SIZE;
1194
1195/*
1196 * typedef: enum GT_BURST_RATE
1197 * The ingress data rate limit based on burst size
1198 */
1199
1200typedef enum
1201{
1202 GT_BURST_NO_LIMIT = 0, /* Not limited */
1203 GT_BURST_64K, /* 64K bits/sec */
1204 GT_BURST_128K, /* 128K bits/sec */
1205 GT_BURST_256K, /* 256K bits/sec */
1206 GT_BURST_384K, /* 384K bits/sec */
1207 GT_BURST_512K, /* 512 bits/sec */
1208 GT_BURST_640K, /* 640K bits/sec */
1209 GT_BURST_768K, /* 768K bits/sec */
1210 GT_BURST_896K, /* 896K bits/sec */
1211 GT_BURST_1M, /* 1M bits/sec */
1212 GT_BURST_1500K, /* 1.5M bits/sec */
1213 GT_BURST_2M, /* 2M bits/sec */
1214 GT_BURST_4M, /* 4M bits/sec */
1215 GT_BURST_8M, /* 8M bits/sec */
1216 GT_BURST_16M, /* 16M bits/sec */
1217 GT_BURST_32M, /* 32M bits/sec */
1218 GT_BURST_64M, /* 64M bits/sec */
1219 GT_BURST_128M, /* 128M bits/sec */
1220 GT_BURST_256M /* 256M bits/sec */
1221} GT_BURST_RATE;
1222
1223/*
1224 * Formula for burst based Rate Limit
1225 */
1226#define GT_GET_BURST_RATE_LIMIT(_bsize,_kbps) \
1227 ((_kbps)?(((_bsize)+1)*8000000 / (32 * (_kbps)) + \
1228 (((_bsize)+1)*8000000 % (32 * (_kbps))?1:0)) \
1229 :0)
1230
1231/*
1232 * Typedef: enum GT_PIRL_OPERATION
1233 *
1234 * Description: Defines the PIRL (Port Ingress Rate Limit) Operation type
1235 *
1236 * Fields:
1237 * PIRL_INIT_ALL_RESOURCE - Initialize all resources to the inital state
1238 * PIRL_INIT_RESOURCE - Initialize selected resources to the inital state
1239 * PIRL_WRITE_RESOURCE - Write to the selected resource/register
1240 * PIRL_READ_RESOURCE - Read from the selected resource/register
1241 */
1242typedef enum
1243{
1244 PIRL_INIT_ALL_RESOURCE = 0x1,
1245 PIRL_INIT_RESOURCE = 0x2,
1246 PIRL_WRITE_RESOURCE = 0x3,
1247 PIRL_READ_RESOURCE = 0x4
1248} GT_PIRL_OPERATION, GT_PIRL2_OPERATION;
1249
1250
1251/*
1252 * typedef: struct GT_PIRL_OP_DATA
1253 *
1254 * Description: data required by PIRL Operation
1255 *
1256 * Fields:
1257 * irlUnit - Ingress Rate Limit Unit that defines one of IRL resources.
1258 * irlReg - Ingress Rate Limit Register.
1259 * irlData - Ingress Rate Limit Data.
1260 */
1261typedef struct
1262{
1263 GT_U32 irlUnit;
1264 GT_U32 irlReg;
1265 GT_U32 irlData;
1266} GT_PIRL_OP_DATA;
1267
1268/*
1269 * typedef: struct GT_PIRL2_OP_DATA
1270 *
1271 * Description: data required by PIRL Operation
1272 *
1273 * Fields:
1274 * irlPort - Ingress Rate Limiting port (physical port number).
1275 * irlRes - Ingress Rate Limit Resource.
1276 * irlReg - Ingress Rate Limit Register.
1277 * irlData - Ingress Rate Limit Data.
1278 */
1279typedef struct
1280{
1281 GT_U32 irlPort;
1282 GT_U32 irlRes;
1283 GT_U32 irlReg;
1284 GT_U32 irlData;
1285} GT_PIRL2_OP_DATA;
1286
1287/*
1288 * Typedef: enum GT_PIRL_ACTION
1289 *
1290 * Description: Defines the Action that should be taken when
1291 * there there are not enough tokens to accept the entire incoming frame
1292 *
1293 * Fields:
1294 * PIRL_ACTION_ACCEPT - accept the frame
1295 * PIRL_ACTION_USE_LIMIT_ACTION - use ESB Limit Action
1296 */
1297typedef enum
1298{
1299 PIRL_ACTION_USE_LIMIT_ACTION = 0x0,
1300 PIRL_ACTION_ACCEPT = 0x1
1301} GT_PIRL_ACTION;
1302
1303/*
1304 * Typedef: enum GT_ESB_LIMIT_ACTION
1305 *
1306 * Description: Defines the ESB Limit Action that should be taken when
1307 * the incoming port information rate exceeds the EBS_Limit.
1308 *
1309 * Fields:
1310 * ESB_LIMIT_ACTION_DROP - drop packets
1311 * ESB_LIMIT_ACTION_FC - send flow control packet
1312 */
1313typedef enum
1314{
1315 ESB_LIMIT_ACTION_DROP = 0x0,
1316 ESB_LIMIT_ACTION_FC = 0x1
1317} GT_ESB_LIMIT_ACTION;
1318
1319
1320/*
1321 * Typedef: enum GT_BUCKET_RATE_TYPE
1322 *
1323 * Description: Defines the Bucket Rate Type
1324 *
1325 * Fields:
1326 * BUCKET_TYPE_TRAFFIC_BASED - bucket is traffic type based
1327 * BUCKET_TYPE_RATE_BASED - bucket is rate based
1328 */
1329typedef enum
1330{
1331 BUCKET_TYPE_TRAFFIC_BASED = 0x0,
1332 BUCKET_TYPE_RATE_BASED = 0x1
1333} GT_BUCKET_RATE_TYPE;
1334
1335/*
1336 * Definition for GT_BUCKET_TYPE_TRAFFIC_BASED
1337 *
1338 * Description: Defines the Traffic Type that is used when Bucket Rate Type
1339 * is traffic type based (BUCKET_TYPE_TRAFFIC_BASED).
1340 * Please refer to the device datasheet in order to check which traffic
1341 * types are supported.
1342 *
1343 * Definition:
1344 * BUCKET_TRAFFIC_UNKNOWN_UNICAST - unknown unicast frame
1345 * BUCKET_TRAFFIC_UNKNOWN_MULTICAST- unknown multicast frame
1346 * BUCKET_TRAFFIC_BROADCAST - broadcast frame
1347 * BUCKET_TRAFFIC_MULTICAST - multicast frame
1348 * BUCKET_TRAFFIC_UNICAST - unicast frame
1349 * BUCKET_TRAFFIC_MGMT_FRAME - management frame
1350 * BUCKET_TRAFFIC_ARP - arp frame
1351 * BUCKET_TRAFFIC_TCP_DATA - TCP Data
1352 * BUCKET_TRAFFIC_TCP_CTRL - TCP Ctrl (if any of the TCP Flags[5:0] are set)
1353 * BUCKET_TRAFFIC_UDP - UDP
1354 * BUCKET_TRAFFIC_NON_TCPUDP - covers IGMP,ICMP,GRE,IGRP,L2TP
1355 * BUCKET_TRAFFIC_IMS - Ingress Monitor Source
1356 * BUCKET_TRAFFIC_POLICY_MIRROR - Policy Mirror
1357 * BUCKET_TRAFFIC_PLICY_TRAP - Policy Trap
1358 */
1359#define BUCKET_TRAFFIC_UNKNOWN_UNICAST 0x01
1360#define BUCKET_TRAFFIC_UNKNOWN_MULTICAST 0x02
1361#define BUCKET_TRAFFIC_BROADCAST 0x04
1362#define BUCKET_TRAFFIC_MULTICAST 0x08
1363#define BUCKET_TRAFFIC_UNICAST 0x10
1364#define BUCKET_TRAFFIC_MGMT_FRAME 0x20
1365#define BUCKET_TRAFFIC_ARP 0x40
1366#define BUCKET_TRAFFIC_TCP_DATA 0x100
1367#define BUCKET_TRAFFIC_TCP_CTRL 0x200
1368#define BUCKET_TRAFFIC_UDP 0x400
1369#define BUCKET_TRAFFIC_NON_TCPUDP 0x800
1370#define BUCKET_TRAFFIC_IMS 0x1000
1371#define BUCKET_TRAFFIC_POLICY_MIRROR 0x2000
1372#define BUCKET_TRAFFIC_PLICY_TRAP 0x4000
1373
1374/*
1375 * typedef: enum GT_PIRL_COUNT_MODE
1376 *
1377 * Description: Enumeration of the port egress rate limit counting mode.
1378 *
1379 * Enumerations:
1380 * GT_PIRL_COUNT_ALL_LAYER1 -
1381 * Count all Layer 1 bytes:
1382 * Preamble (8bytes) + Frame's DA to CRC + IFG (12bytes)
1383 * GT_PIRL_COUNT_ALL_LAYER2 -
1384 * Count all Layer 2 bytes: Frame's DA to CRC
1385 * GT_PIRL_COUNT_ALL_LAYER3 -
1386 * Count all Layer 3 bytes:
1387 * Frame's DA to CRC - 18 - 4 (if frame is tagged)
1388 */
1389typedef enum
1390{
1391 GT_PIRL_COUNT_ALL_LAYER1 = 0,
1392 GT_PIRL_COUNT_ALL_LAYER2,
1393 GT_PIRL_COUNT_ALL_LAYER3
1394} GT_PIRL_COUNT_MODE;
1395
1396/*
1397 * typedef: enum GT_PIRL2_COUNT_MODE
1398 *
1399 * Description: Enumeration of the port egress rate limit counting mode.
1400 *
1401 * Enumerations:
1402 * GT_PIRL2_COUNT_FRAME -
1403 * Count the number of frames
1404 * GT_PIRL2_COUNT_ALL_LAYER1 -
1405 * Count all Layer 1 bytes:
1406 * Preamble (8bytes) + Frame's DA to CRC + IFG (12bytes)
1407 * GT_PIRL2_COUNT_ALL_LAYER2 -
1408 * Count all Layer 2 bytes: Frame's DA to CRC
1409 * GT_PIRL2_COUNT_ALL_LAYER3 -
1410 * Count all Layer 3 bytes:
1411 * Frame's DA to CRC - 18 - 4 (if frame is tagged)
1412 */
1413typedef enum
1414{
1415 GT_PIRL2_COUNT_FRAME = 0,
1416 GT_PIRL2_COUNT_ALL_LAYER1,
1417 GT_PIRL2_COUNT_ALL_LAYER2,
1418 GT_PIRL2_COUNT_ALL_LAYER3
1419} GT_PIRL2_COUNT_MODE;
1420
1421
1422
1423/*
1424 * typedef: struct GT_PIRL_RESOURCE
1425 *
1426 * Description: data structure that represents a PIRL Resource
1427 *
1428 * Fields:
1429 * accountQConf - account discarded frames due to queue congestion
1430 * accountFiltered - account filtered frames
1431 * ebsLimitAction - action should be taken when the incoming rate exceeds
1432 * the ebsLimit.
1433 * ESB_LIMIT_ACTION_DROP - drop packets
1434 * ESB_LIMIT_ACTION_FC - send flow control packet
1435 * ebsLimit - Excess Burst Size limit ( 0 ~ 0xFFFFFF)
1436 * cbsLimit - Committed BUrst Size limit (expected to be 2kBytes)
1437 * bktRateFactor - bucket rate factor = bucketDecrement/updateInterval,
1438 * where updateInterval indicates the rate at which the
1439 * bucket needs to be updated with tokens, or 1/CIR,
1440 * where CIR is the committed information rate in kbps.
1441 * bucketDecrement indicates the amount of tokens that
1442 * need to be removed per each bucket decrement.
1443 * bktIncrement - the amount of tokens that need to be added for each
1444 * byte of packet information.
1445 * bktRateType - bucket is either rate based or traffic type based.
1446 * BUCKET_TYPE_RATE_BASED, or
1447 * BUCKET_TYPE_TRAFFIC_BASED
1448 * bktTypeMask - used if bktRateType is BUCKET_TYPE_TRAFFIC_BASED.
1449 * any combination of the following definitions:
1450 * BUCKET_TRAFFIC_UNKNOWN_UNICAST,
1451 * BUCKET_TRAFFIC_UNKNOWN_MULTICAST,
1452 * BUCKET_TRAFFIC_BROADCAST,
1453 * BUCKET_TRAFFIC_MULTICAST,
1454 * BUCKET_TRAFFIC_UNICAST,
1455 * BUCKET_TRAFFIC_MGMT_FRAME, and
1456 * BUCKET_TRAFFIC_ARP
1457 * byteTobeCounted - bytes to be counted for accounting
1458 * GT_PIRL_COUNT_ALL_LAYER1,
1459 * GT_PIRL_COUNT_ALL_LAYER2, or
1460 * GT_PIRL_COUNT_ALL_LAYER3
1461 *
1462 */
1463typedef struct
1464{
1465 GT_BOOL accountQConf;
1466 GT_BOOL accountFiltered;
1467 GT_ESB_LIMIT_ACTION ebsLimitAction;
1468 GT_U32 ebsLimit;
1469 GT_U32 cbsLimit;
1470 GT_U32 bktRateFactor;
1471 GT_U32 bktIncrement;
1472 GT_BUCKET_RATE_TYPE bktRateType;
1473 GT_U32 bktTypeMask;
1474 GT_PIRL_COUNT_MODE byteTobeCounted;
1475} GT_PIRL_RESOURCE;
1476
1477/*
1478 * typedef: struct GT_PIRL_CUSTOM_RATE_LIMIT
1479 *
1480 * Description: The parameters that decides Ingress Rate Limit vary depending on
1481 * the application. Since DSDT driver cannot cover all the cases,
1482 * this structure is provided for the custom parameter setting.
1483 * However, in most cases, user may ingore this structure by setting
1484 * isValid to GT_FALSE. If Ingress Rate Limit is too much off from
1485 * the expected rate, please contact FAE and gets the correct ebsLimit,
1486 * cbsLimit,bktIncrement, and bktRateFactor value and use this structure
1487 * to do custom parameter setting.
1488 *
1489 * isValid - If GT_TRUE, the paramers in this structure are used
1490 * to program PIRL Resource's Rate Limit. And ingressRate
1491 * in GT_PIRL_BUCKET_DATA structure are ignored.
1492 * If GT_FALSE, ingressRate in GT_PIRL_BUCKET_DATA structure
1493 * is used for Resource's Rate Limit.
1494 * ebsLimit - Excess Burst Size limit ( 0 ~ 0xFFFFFF)
1495 * cbsLimit - Committed Burst Size limit (expected to be 2kBytes)
1496 * bktIncrement - the amount of tokens that need to be added for each
1497 * byte of packet information.
1498 * bktRateFactor - bucket rate factor = bucketDecrement/updateInterval,
1499 * where updateInterval indicates the rate at which the
1500 * bucket needs to be updated with tokens, or 1/CIR,
1501 * where CIR is the committed information rate in kbps.
1502 * bucketDecrement indicates the amount of tokens that
1503 * need to be removed per each bucket decrement.
1504*/
1505typedef struct
1506{
1507 GT_BOOL isValid;
1508 GT_U32 ebsLimit;
1509 GT_U32 cbsLimit;
1510 GT_U32 bktIncrement;
1511 GT_U32 bktRateFactor;
1512} GT_PIRL_CUSTOM_RATE_LIMIT;
1513
1514/*
1515 * typedef: struct GT_PIRL_BUCKET_DATA
1516 *
1517 * Description: data structure for PIRL Bucket programing that is resource based
1518 *
1519 * Fields:
1520 * ingressRate - commited ingress rate in kbps.
1521 * 64kbps ~ 1Mbps : increments of 64kbps,
1522 * 1Mbps ~ 100Mbps : increments of 1Mbps, and
1523 * 100Mbps ~ 200Mbps : increments of 10Mbps
1524 * Therefore, the valid values are:
1525 * 64, 128, 192, 256, 320, 384,..., 960,
1526 * 1000, 2000, 3000, 4000, ..., 100000,
1527 * 110000, 120000, 130000, ..., 200000.
1528 * customSetup - custom ingress rate parameter setup. please refer to
1529 * GT_PIRL_CUSTOM_RATE_LIMIT structure.
1530 * accountQConf - account discarded frames due to queue congestion
1531 * accountFiltered - account filtered frames
1532 * esbLimitAction - action should be taken when the incoming rate exceeds
1533 * the limit.
1534 * ESB_LIMIT_ACTION_DROP - drop packets
1535 * ESB_LIMIT_ACTION_FC - send flow control packet
1536 * fcDeassertMode - port flow control de-assertion mode when limitAction is
1537 * set to ESB_LIMIT_ACTION_FC.
1538 * fcDeassertMode[0] for port 0, fcDeassertMode[1] for
1539 * port 1, etc. If port x does not share the bucket,
1540 * fcDeassertMode[x] data will be ignored.
1541 * GT_PIRL_FC_DEASSERT_EMPTY -
1542 * De-assert when the ingress rate resource has
1543 * become empty.
1544 * GT_PIRL_FC_DEASSERT_CBS_LIMIT -
1545 * De-assert when the ingress rate resource has
1546 * enough room as specified by the CBSLimit.
1547 * bktRateType - bucket is either rate based or traffic type based.
1548 * BUCKET_TYPE_RATE_BASED, or
1549 * BUCKET_TYPE_TRAFFIC_BASED
1550 * bktTypeMask - used if bktRateType is BUCKET_TYPE_TRAFFIC_BASED.
1551 * any combination of the following definitions:
1552 * BUCKET_TRAFFIC_UNKNOWN_UNICAST,
1553 * BUCKET_TRAFFIC_UNKNOWN_MULTICAST,
1554 * BUCKET_TRAFFIC_BROADCAST,
1555 * BUCKET_TRAFFIC_MULTICAST,
1556 * BUCKET_TRAFFIC_UNICAST,
1557 * BUCKET_TRAFFIC_MGMT_FRAME, and
1558 * BUCKET_TRAFFIC_ARP
1559 * byteTobeCounted - bytes to be counted for accounting
1560 * GT_PIRL_COUNT_ALL_LAYER1,
1561 * GT_PIRL_COUNT_ALL_LAYER2, or
1562 * GT_PIRL_COUNT_ALL_LAYER3
1563 *
1564 */
1565typedef struct
1566{
1567 GT_U32 ingressRate;
1568 GT_PIRL_CUSTOM_RATE_LIMIT customSetup;
1569 GT_BOOL accountQConf;
1570 GT_BOOL accountFiltered;
1571 GT_ESB_LIMIT_ACTION ebsLimitAction;
1572 GT_PIRL_FC_DEASSERT fcDeassertMode[MAX_SWITCH_PORTS];
1573 GT_BUCKET_RATE_TYPE bktRateType;
1574 GT_U32 bktTypeMask;
1575 GT_PIRL_COUNT_MODE byteTobeCounted;
1576} GT_PIRL_DATA;
1577
1578
1579/*
1580 * typedef: struct GT_PIRL2_RESOURCE
1581 *
1582 * Description: data structure that represents a PIRL Resource
1583 *
1584 * Fields:
1585 * accountQConf - account discarded frames due to queue congestion
1586 * accountFiltered - account filtered frames
1587 * mgmtNrlEn - exclude management frame from ingress rate limiting calculation
1588 * saNrlEn - exclude from ingress rate limiting calculation if the SA of the
1589 * frame is in ATU with EntryState that indicates Non Rate Limited.
1590 * daNrlEn - exclude from ingress rate limiting calculation if the DA of the
1591 * frame is in ATU with EntryState that indicates Non Rate Limited.
1592 * samplingMode - sample one out of so many frames/bytes for a stream of frames
1593 * actionMode - action should be taken when there are not enough tokens
1594 * to accept the entire incoming frame
1595 * PIRL_ACTION_ACCEPT - accept the frame
1596 * PIRL_ACTION_USE_LIMIT_ACTION - use limitAction
1597 * ebsLimitAction - action should be taken when the incoming rate exceeds
1598 * the ebsLimit.
1599 * ESB_LIMIT_ACTION_DROP - drop packets
1600 * ESB_LIMIT_ACTION_FC - send flow control packet
1601 * ebsLimit - Excess Burst Size limit ( 0 ~ 0xFFFFFF)
1602 * cbsLimit - Committed BUrst Size limit (expected to be 2kBytes)
1603 * bktRateFactor - bucket rate factor = bucketDecrement/updateInterval,
1604 * where updateInterval indicates the rate at which the
1605 * bucket needs to be updated with tokens, or 1/CIR,
1606 * where CIR is the committed information rate in kbps.
1607 * bucketDecrement indicates the amount of tokens that
1608 * need to be removed per each bucket decrement.
1609 * bktIncrement - the amount of tokens that need to be added for each
1610 * byte of packet information.
1611 * fcDeassertMode - flow control de-assertion mode when limitAction is
1612 * set to ESB_LIMIT_ACTION_FC.
1613 * GT_PIRL_FC_DEASSERT_EMPTY -
1614 * De-assert when the ingress rate resource has
1615 * become empty.
1616 * GT_PIRL_FC_DEASSERT_CBS_LIMIT -
1617 * De-assert when the ingress rate resource has
1618 * enough room as specified by the CBSLimit.
1619 * bktRateType - bucket is either rate based or traffic type based.
1620 * BUCKET_TYPE_RATE_BASED, or
1621 * BUCKET_TYPE_TRAFFIC_BASED
1622 * priORpt - determine the incoming frames that get rate limited using
1623 * this ingress rate resource.
1624 * GT_TRUE - typeMask OR priMask
1625 * GT_FALSE - typeMask AND priMask
1626 * priMask - priority bit mask that each bit indicates one of the four
1627 * queue priorities. Setting each one of these bits indicates
1628 * that this particular rate resource is slated to account for
1629 * incoming frames with the enabled bits' priority.
1630 * bktTypeMask - used if bktRateType is BUCKET_TYPE_TRAFFIC_BASED.
1631 * any combination of the following definitions:
1632 * BUCKET_TRAFFIC_UNKNOWN_UNICAST,
1633 * BUCKET_TRAFFIC_UNKNOWN_MULTICAST,
1634 * BUCKET_TRAFFIC_BROADCAST,
1635 * BUCKET_TRAFFIC_MULTICAST,
1636 * BUCKET_TRAFFIC_UNICAST,
1637 * BUCKET_TRAFFIC_MGMT_FRAME,
1638 * BUCKET_TRAFFIC_ARP,
1639 * BUCKET_TRAFFIC_TCP_DATA,
1640 * BUCKET_TRAFFIC_TCP_CTRL,
1641 * BUCKET_TRAFFIC_UDP,
1642 * BUCKET_TRAFFIC_NON_TCPUDP,
1643 * BUCKET_TRAFFIC_IMS,
1644 * BUCKET_TRAFFIC_POLICY_MIRROR, and
1645 * BUCKET_TRAFFIC_PLICY_TRAP
1646 * byteTobeCounted - bytes to be counted for accounting
1647 * GT_PIRL2_COUNT_FRAME,
1648 * GT_PIRL2_COUNT_ALL_LAYER1,
1649 * GT_PIRL2_COUNT_ALL_LAYER2, or
1650 * GT_PIRL2_COUNT_ALL_LAYER3
1651 *
1652 */
1653typedef struct
1654{
1655 GT_BOOL accountQConf;
1656 GT_BOOL accountFiltered;
1657 GT_BOOL mgmtNrlEn;
1658 GT_BOOL saNrlEn;
1659 GT_BOOL daNrlEn;
1660 GT_BOOL samplingMode;
1661 GT_PIRL_ACTION actionMode;
1662 GT_ESB_LIMIT_ACTION ebsLimitAction;
1663 GT_U32 ebsLimit;
1664 GT_U32 cbsLimit;
1665 GT_U32 bktRateFactor;
1666 GT_U32 bktIncrement;
1667 GT_PIRL_FC_DEASSERT fcDeassertMode;
1668 GT_BUCKET_RATE_TYPE bktRateType;
1669 GT_BOOL priORpt;
1670 GT_U32 priMask;
1671 GT_U32 bktTypeMask;
1672 GT_PIRL2_COUNT_MODE byteTobeCounted;
1673} GT_PIRL2_RESOURCE;
1674
1675
1676/*
1677 * typedef: struct GT_PIRL2_BUCKET_DATA
1678 *
1679 * Description: data structure for PIRL2 Bucket programing that is port based.
1680 *
1681 * Fields:
1682 * ingressRate - commited ingress rate in kbps.
1683 * 64kbps ~ 1Mbps : increments of 64kbps,
1684 * 1Mbps ~ 100Mbps : increments of 1Mbps, and
1685 * 100Mbps ~ 200Mbps : increments of 10Mbps
1686 * Therefore, the valid values are:
1687 * 64, 128, 192, 256, 320, 384,..., 960,
1688 * 1000, 2000, 3000, 4000, ..., 100000,
1689 * 110000, 120000, 130000, ..., 200000.
1690 * customSetup - custom ingress rate parameter setup. please refer to
1691 * GT_PIRL_CUSTOM_RATE_LIMIT structure.
1692 * accountQConf - account discarded frames due to queue congestion
1693 * accountFiltered - account filtered frames
1694 * mgmtNrlEn - exclude management frame from ingress rate limiting calculation
1695 * saNrlEn - exclude from ingress rate limiting calculation if the SA of the
1696 * frame is in ATU with EntryState that indicates Non Rate Limited.
1697 * daNrlEn - exclude from ingress rate limiting calculation if the DA of the
1698 * frame is in ATU with EntryState that indicates Non Rate Limited.
1699 * samplingMode - sample one out of so many frames/bytes for a stream of frames
1700 * actionMode - action should be taken when there are not enough tokens
1701 * to accept the entire incoming frame
1702 * PIRL_ACTION_ACCEPT - accept the frame
1703 * PIRL_ACTION_USE_LIMIT_ACTION - use limitAction
1704 * ebsLimitAction - action should be taken when the incoming rate exceeds
1705 * the limit.
1706 * ESB_LIMIT_ACTION_DROP - drop packets
1707 * ESB_LIMIT_ACTION_FC - send flow control packet
1708 * fcDeassertMode - flow control de-assertion mode when limitAction is
1709 * set to ESB_LIMIT_ACTION_FC.
1710 * GT_PIRL_FC_DEASSERT_EMPTY -
1711 * De-assert when the ingress rate resource has
1712 * become empty.
1713 * GT_PIRL_FC_DEASSERT_CBS_LIMIT -
1714 * De-assert when the ingress rate resource has
1715 * enough room as specified by the CBSLimit.
1716 * bktRateType - bucket is either rate based or traffic type based.
1717 * BUCKET_TYPE_RATE_BASED, or
1718 * BUCKET_TYPE_TRAFFIC_BASED
1719 * priORpt - determine the incoming frames that get rate limited using
1720 * this ingress rate resource.
1721 * GT_TRUE - typeMask OR priMask
1722 * GT_FALSE - typeMask AND priMask
1723 * priMask - priority bit mask that each bit indicates one of the four
1724 * queue priorities. Setting each one of these bits indicates
1725 * that this particular rate resource is slated to account for
1726 * incoming frames with the enabled bits' priority.
1727 * bktTypeMask - used if bktRateType is BUCKET_TYPE_TRAFFIC_BASED.
1728 * any combination of the following definitions:
1729 * BUCKET_TRAFFIC_UNKNOWN_UNICAST,
1730 * BUCKET_TRAFFIC_UNKNOWN_MULTICAST,
1731 * BUCKET_TRAFFIC_BROADCAST,
1732 * BUCKET_TRAFFIC_MULTICAST,
1733 * BUCKET_TRAFFIC_UNICAST,
1734 * BUCKET_TRAFFIC_MGMT_FRAME,
1735 * BUCKET_TRAFFIC_ARP,
1736 * BUCKET_TRAFFIC_TCP_DATA,
1737 * BUCKET_TRAFFIC_TCP_CTRL,
1738 * BUCKET_TRAFFIC_UDP,
1739 * BUCKET_TRAFFIC_NON_TCPUDP,
1740 * BUCKET_TRAFFIC_IMS,
1741 * BUCKET_TRAFFIC_POLICY_MIRROR, and
1742 * BUCKET_TRAFFIC_PLICY_TRAP
1743 * byteTobeCounted - bytes to be counted for accounting
1744 * GT_PIRL2_COUNT_FRAME,
1745 * GT_PIRL2_COUNT_ALL_LAYER1,
1746 * GT_PIRL2_COUNT_ALL_LAYER2, or
1747 * GT_PIRL2_COUNT_ALL_LAYER3
1748 *
1749 */
1750typedef struct
1751{
1752 GT_U32 ingressRate;
1753 GT_PIRL_CUSTOM_RATE_LIMIT customSetup;
1754 GT_BOOL accountQConf;
1755 GT_BOOL accountFiltered;
1756 GT_BOOL mgmtNrlEn;
1757 GT_BOOL saNrlEn;
1758 GT_BOOL daNrlEn;
1759 GT_BOOL samplingMode;
1760 GT_PIRL_ACTION actionMode;
1761 GT_ESB_LIMIT_ACTION ebsLimitAction;
1762 GT_PIRL_FC_DEASSERT fcDeassertMode;
1763 GT_BUCKET_RATE_TYPE bktRateType;
1764 GT_BOOL priORpt;
1765 GT_U32 priMask;
1766 GT_U32 bktTypeMask;
1767 GT_PIRL2_COUNT_MODE byteTobeCounted;
1768} GT_PIRL2_DATA;
1769
1770
1771
1772/*
1773 * typedef: struct GT_PIRL_CUSTOM_TSM_CFG
1774 *
1775 * Description: The parameters that decides Ingress Rate Limit for AVB frames vary
1776 * depending on the application. Since DSDT driver cannot cover all the cases,
1777 * this structure is provided for the custom parameter setting.
1778 * However, in most cases, user may ingore this structure by setting
1779 * isValid to GT_FALSE. If Ingress Rate Limit is too much off from
1780 * the expected rate, please contact FAE and gets the correct ebsLimit,
1781 * cbsLimit, CTS interval, and action mode value and use this structure
1782 * to do custom parameter setting.
1783 *
1784 * isValid - If GT_TRUE, the paramers in this structure are used
1785 * to program PIRL Resource's Rate Limit. And ingressRate
1786 * in GT_PIRL_TSM_DATA structure are ignored.
1787 * If GT_FALSE, ingressRate in GT_PIRL_TSM_DATA structure
1788 * is used for Resource's Rate Limit.
1789 * ebsLimit - Excess Burst Size limit (0 ~ 0xFFFF)
1790 * cbsLimit - Committed Burst Size limit (0 ~ 0xFFFF)
1791 * ctsIntv - Class Time Slot Interval
1792 * 0 - interval is 62.5us
1793 * 1 - interval is 125us
1794 * 2 - interval is 250us
1795 * 3 - interval is 1000us
1796 * actionMode - action should be taken when there are not enough tokens
1797 * to accept the entire incoming frame
1798 * PIRL_ACTION_ACCEPT - accept the frame
1799 * PIRL_ACTION_USE_LIMIT_ACTION - use limitAction
1800*/
1801typedef struct
1802{
1803 GT_BOOL isValid;
1804 GT_U32 ebsLimit;
1805 GT_U32 cbsLimit;
1806 GT_U32 ctsIntv;
1807 GT_PIRL_ACTION actionMode;
1808} GT_PIRL_CUSTOM_TSM_CFG;
1809
1810
1811/*
1812 * typedef: struct GT_PIRL2_TSM_DATA
1813 *
1814 * Description: data structure for PIRL2 TSM Ingress Rate Limit.
1815 *
1816 * Fields:
1817 * ebsLimit - Excess Burst Size limit (0 ~ 0xFFFF)
1818 * cbsLimit - Committed Burst Size limit (0 ~ 0xFFFF)
1819 * ctsIntv - Class Time Slot Interval
1820 * 0 - interval is 62.5us
1821 * 1 - interval is 125us
1822 * 2 - interval is 250us
1823 * 3 - interval is 1000us
1824 * actionMode - action should be taken when there are not enough tokens
1825 * to accept the entire incoming frame
1826 * PIRL_ACTION_ACCEPT - accept the frame
1827 * PIRL_ACTION_USE_LIMIT_ACTION - use limitAction
1828 * mgmtNrlEn - exclude management frame from ingress rate limiting calculation
1829 * priMask - priority bit mask that each bit indicates one of the four
1830 * queue priorities. Setting each one of these bits indicates
1831 * that this particular rate resource is slated to account for
1832 * incoming frames with the enabled bits' priority.
1833 *
1834 */
1835typedef struct
1836{
1837 GT_BOOL tsmMode;
1838 GT_U32 ebsLimit;
1839 GT_U32 cbsLimit;
1840 GT_U32 ctsIntv;
1841 GT_PIRL_ACTION actionMode;
1842 GT_BOOL mgmtNrlEn;
1843 GT_U32 priMask;
1844} GT_PIRL2_TSM_RESOURCE;
1845
1846
1847
1848/*
1849 * typedef: struct GT_PIRL2_TSM_DATA
1850 *
1851 * Description: data structure for PIRL2 TSM Ingress Rate Limit.
1852 *
1853 * Fields:
1854 * tsmMode - enable/disable TSM mode.
1855 * The following fields are ignored if diable
1856 * ingressRate - commited ingress rate in kbps.(min 64 for 64kbps)
1857 * customSetup - custom ingress rate parameter setup. please refer to
1858 * GT_PIRL_CUSTOM_TSM_CFG structure.
1859 * mgmtNrlEn - exclude management frame from ingress rate limiting calculation
1860 * priMask - priority bit mask that each bit indicates one of the four
1861 * queue priorities. Setting each one of these bits indicates
1862 * that this particular rate resource is slated to account for
1863 * incoming frames with the enabled bits' priority.
1864 *
1865 */
1866typedef struct
1867{
1868 GT_BOOL tsmMode;
1869 GT_U32 ingressRate;
1870 GT_PIRL_CUSTOM_TSM_CFG customSetup;
1871 GT_BOOL mgmtNrlEn;
1872 GT_U32 priMask;
1873} GT_PIRL2_TSM_DATA;
1874
1875
1876
1877#define MAX_PTP_CONSECUTIVE_READ 4
1878
1879/*
1880 * Typedef: enum GT_PTP_OPERATION
1881 *
1882 * Description: Defines the PTP (Precise Time Protocol) Operation type
1883 *
1884 * Fields:
1885 * PTP_WRITE_DATA - Write data to the PTP register
1886 * PTP_READ_DATA - Read data from PTP register
1887 * PTP_READ_MULTIPLE_DATA - Read multiple data from PTP register
1888 * PTP_READ_TIMESTAMP_DATA - Read timestamp data from PTP register
1889 * valid bit will be reset after read
1890 */
1891typedef enum
1892{
1893 PTP_WRITE_DATA = 0x3,
1894 PTP_READ_DATA = 0x4,
1895 PTP_READ_MULTIPLE_DATA = 0x6,
1896 PTP_READ_TIMESTAMP_DATA = 0x8,
1897} GT_PTP_OPERATION;
1898
1899
1900/*
1901 * Typedef: enum GT_PTP_SPEC
1902 *
1903 * Description: Defines the PTP (Precise Time Protocol) SPEC type
1904 *
1905 * Fields:
1906 * PTP_IEEE_1588 - IEEE 1588
1907 * PTP_IEEE_802_1AS - IEEE 802.1as
1908 */
1909typedef enum
1910{
1911 PTP_IEEE_1588 = 0x0,
1912 PTP_IEEE_802_1AS = 0x1
1913} GT_PTP_SPEC;
1914
1915
1916/*
1917 * typedef: struct GT_PTP_OP_DATA
1918 *
1919 * Description: data required by PTP Operation
1920 *
1921 * Fields:
1922 * ptpPort - physical port of the device
1923 * ptpAddr - register address
1924 * ptpData - data for ptp register.
1925 * ptpMultiData- used for multiple read operation.
1926 * nData - number of data to be read on multiple read operation.
1927 */
1928typedef struct
1929{
1930 GT_U32 ptpPort;
1931 GT_U32 ptpBlock;
1932 GT_U32 ptpAddr;
1933 GT_U32 ptpData;
1934 GT_U32 ptpMultiData[MAX_PTP_CONSECUTIVE_READ];
1935 GT_U32 nData;
1936} GT_PTP_OP_DATA;
1937
1938
1939/*
1940 * typedef: struct GT_PTP_CONFIG
1941 *
1942 * Description: PTP configuration parameters
1943 *
1944 * Fields:
1945 * ptpEType - PTP Ether Type
1946 * msgIdTSEn - Message IDs that needs time stamp
1947 * tsArrPtr - Time stamp arrival time counter pointer (either Arr0Time or Arr1Time)
1948 * ptpArrIntEn - PTP port arrival interrupt enable
1949 * ptpDepIntEn - PTP port departure interrupt enable
1950 * transSpec - This is to differentiate between various timing protocols.
1951 * msgIdStartBit - Message ID starting bit in the PTP common header
1952 * disTSOverwrite - disable time stamp counter overwriting until the corresponding
1953 * timer valid bit is cleared.
1954 */
1955typedef struct
1956{
1957 GT_U32 ptpEType;
1958 GT_U32 msgIdTSEn;
1959 GT_U32 tsArrPtr;
1960 GT_U32 ptpArrIntEn;
1961 GT_U32 ptpDepIntEn;
1962 GT_PTP_SPEC transSpec;
1963 GT_U32 msgIdStartBit;
1964 GT_BOOL disTSOverwrite;
1965} GT_PTP_CONFIG;
1966
1967
1968/*
1969 * typedef: struct GT_PTP_GLOBAL_CONFIG
1970 *
1971 * Description: PTP global configuration parameters
1972 *
1973 * Fields:
1974 * ptpEType - PTP Ether Type
1975 * msgIdTSEn - Message IDs that needs time stamp
1976 * tsArrPtr - Time stamp arrival time counter pointer (either Arr0Time or Arr1Time)
1977 */
1978typedef struct
1979{
1980 GT_U32 ptpEType;
1981 GT_U32 msgIdTSEn;
1982 GT_U32 tsArrPtr;
1983} GT_PTP_GLOBAL_CONFIG;
1984
1985
1986/*
1987 * typedef: struct GT_PTP_PORT_CONFIG
1988 *
1989 * Description: PTP configuration parameters for each port
1990 *
1991 * Fields:
1992 * transSpec - This is to differentiate between various timing protocols.
1993 * disTSpec - Disable Transport specific check
1994 * etJump - offset to Ether type start address in bytes
1995 * ipJump - offset to IP header start address counting from Ether type offset
1996 * ptpArrIntEn - PTP port arrival interrupt enable
1997 * ptpDepIntEn - PTP port departure interrupt enable
1998 * disTSOverwrite - disable time stamp counter overwriting until the corresponding
1999 * timer valid bit is cleared.
2000 */
2001typedef struct
2002{
2003 GT_PTP_SPEC transSpec;
2004 GT_BOOL disTSpec;
2005 GT_U32 etJump;
2006 GT_U32 ipJump;
2007 GT_BOOL ptpArrIntEn;
2008 GT_BOOL ptpDepIntEn;
2009 GT_BOOL disTSOverwrite;
2010} GT_PTP_PORT_CONFIG;
2011
2012
2013/*
2014 * Typedef: enum GT_PTP_TIME
2015 *
2016 * Description: Defines the PTP Time to be read
2017 *
2018 * Fields:
2019 * PTP_WRITE_DATA - Write data to the PTP register
2020 * PTP_READ_DATA - Read data from PTP register
2021 * PTP_READ_MULTIPLE_DATA - Read multiple data from PTP register
2022 */
2023typedef enum
2024{
2025 PTP_ARR0_TIME = 0x0,
2026 PTP_ARR1_TIME = 0x1,
2027 PTP_DEP_TIME = 0x2
2028} GT_PTP_TIME;
2029
2030
2031/*
2032 * Typedef: enum GT_PTP_INT_STATUS
2033 *
2034 * Description: Defines the PTP Port interrupt status for time stamp
2035 *
2036 * Fields:
2037 * PTP_INT_NORMAL - No error condition occurred
2038 * PTP_INT_OVERWRITE - PTP logic has to process more than one PTP frame
2039 * that needs time stamping before the current read.
2040 * Only the latest one is saved.
2041 * PTP_INT_DROP - PTP logic has to process more than one PTP frame
2042 * that needs time stamping before the current read.
2043 * Only the oldest one is saved.
2044 *
2045 */
2046typedef enum
2047{
2048 PTP_INT_NORMAL = 0x0,
2049 PTP_INT_OVERWRITE = 0x1,
2050 PTP_INT_DROP = 0x2
2051} GT_PTP_INT_STATUS;
2052
2053
2054/*
2055 * typedef: struct GT_PTP_TS_STATUS
2056 *
2057 * Description: PTP port status of time stamp
2058 *
2059 * Fields:
2060 * isValid - time stamp is valid
2061 * status - time stamp error status
2062 * timeStamped - time stamp value of a PTP frame that needs to be time stamped
2063 * ptpSeqId - sequence ID of the frame whose time stamp information has been captured
2064 */
2065typedef struct
2066{
2067 GT_BOOL isValid;
2068 GT_U32 timeStamped;
2069 GT_U32 ptpSeqId;
2070 GT_PTP_INT_STATUS status;
2071} GT_PTP_TS_STATUS;
2072
2073
2074/*
2075 * typedef: struct GT_PTP_PORT_DISCARD_STATS
2076 *
2077 * Description: PTP port discard statistics. The counter (4 bit wide) wraps around after 15.
2078 *
2079 * Fields:
2080 * tsDepDisCtr - PTP departure frame discard counter for PTP frames that need time stamping.
2081 * ntsDepDisCtr - PTP departure frame discard counter for PTP frames that do not need time stamping.
2082 * tsArrDisCtr - PTP arrival frame discard counter for PTP frames that need time stamping.
2083 * ntsArrDisCtr - PTP arrival frame discard counter for PTP frames that do not need time stamping.
2084 */
2085typedef struct
2086{
2087 GT_U32 tsDepDisCtr;
2088 GT_U32 ntsDepDisCtr;
2089 GT_U32 tsArrDisCtr;
2090 GT_U32 ntsArrDisCtr;
2091} GT_PTP_PORT_DISCARD_STATS;
2092
2093
2094#ifdef CONFIG_AVB_FPGA
2095
2096typedef enum
2097{
2098 PTP_CLOCK_SRC_AD_DEVICE = 0, /* PTP Clock source is from A/D device */
2099 PTP_CLOCK_SRC_FPGA /* PTP Clock source is from Cesium FPGA */
2100} GT_PTP_CLOCK_SRC;
2101
2102typedef enum
2103{
2104 PTP_P9_MODE_GMII = 0, /* Port 9 uses GMII connect to 88E1111 */
2105 PTP_P9_MODE_MII, /* Port 9 uses MII connect to 88E1111 */
2106 PTP_P9_MODE_MII_CONNECTOR, /* Port 9 connect to MII connector */
2107 PTP_P9_MODE_JUMPER /* Use Jumper setup */
2108} GT_PTP_P9_MODE;
2109
2110typedef enum
2111{
2112 GT_PTP_SIGN_NEGATIVE = 0, /* apply Minus sign to the Duty Cycle */
2113 GT_PTP_SIGN_PLUS /* apply Plus sign to the Duty Cycle */
2114} GT_PTP_SIGN;
2115
2116typedef struct
2117{
2118 GT_PTP_SIGN adjSign; /* determine the plus/minus sign of the duty cycle adj */
2119 GT_U32 cycleStep; /* number of steps which will be applied in adjusting the duty cycle high time
2120 of the 8KHz clock cycle.
2121 valid values are 0 ~ 7 */
2122 GT_U32 cycleInterval; /* define the interval of clock cycles for which a duty cycle adj will occur */
2123 GT_U32 cycleAdjust; /* define the number of 8KHz clock cycles for which duty cycle adj will occur
2124 within each PTP clock clycle interval.
2125 Note that (cycleAdjust <= cycleInterval) for proper operation */
2126} GT_PTP_CLOCK_ADJUSTMENT;
2127
2128#endif
2129
2130/*
2131 * typedef: struct GT_TAI_EVENT_CONFIG
2132 *
2133 * Description: TAI event capture configuration parameters
2134 *
2135 * Fields:
2136 * eventOverwrite - event capture overwrite
2137 * eventCtrStart - event counter start
2138 * intEn - event capture interrupt enable
2139 */
2140typedef struct
2141{
2142 GT_BOOL eventOverwrite;
2143 GT_BOOL eventCtrStart;
2144 GT_BOOL intEn;
2145} GT_TAI_EVENT_CONFIG;
2146
2147
2148/*
2149 * typedef: struct GT_TAI_EVENT_STATUS
2150 *
2151 * Description: TAI event capture status
2152 *
2153 * Fields:
2154 * isValid - eventTime is valid
2155 * eventTime - PTP global time when event is registered.
2156 * eventCtr - event capture counter. increamented only if eventCtrStart is set.
2157 * eventErr - isValid is already set when a new event is observed.
2158 */
2159typedef struct
2160{
2161 GT_BOOL isValid;
2162 GT_U32 eventTime;
2163 GT_U32 eventCtr;
2164 GT_BOOL eventErr;
2165} GT_TAI_EVENT_STATUS;
2166
2167
2168typedef enum
2169{
2170 GT_TAI_TRIG_PERIODIC_PURSE = 0, /* generate periodic purse */
2171 GT_TAI_TRIG_ON_GIVEN_TIME /* generate purse when
2172 PTP global time matches with given time */
2173} GT_TAI_TRIG_MODE;
2174
2175
2176/*
2177 * typedef: struct GT_TAI_TRIGGER_CONFIG
2178 *
2179 * Description: TAI trigger generator configuration parameters
2180 *
2181 * Fields:
2182 * intEn - trigger generator interrupt enable
2183 * mode - trigger mode, either GT_TAI_TRIG_PERIODIC_PURSE or
2184 * GT_TAI_TRIG_ON_GIVEN_TIME
2185 * trigGenAmt - if mode is GT_TAI_TRIG_PERIODIC_PURSE,
2186 * this value is used as a clock period in TSClkPer increments
2187 * If mode is GT_TAI_TRIG_ON_GIVEN_TIME,
2188 * this value is used to compare with PTP global time.
2189 * pulseWidth - pulse width in units of TSClkPer.
2190 * this value should be 1 ~ 0xF. If it's 0, no changes made.
2191 * this value is valid only in GT_TAI_TRIG_ON_GIVEN_TIME mode.
2192 * trigClkComp - trigger mode clock compensation amount in pico sec.
2193 * this value is valid only in GT_TAI_TRIG_PERIODIC_PURSE mode.
2194 */
2195typedef struct
2196{
2197 GT_BOOL intEn;
2198 GT_TAI_TRIG_MODE mode;
2199 GT_U32 trigGenAmt;
2200 GT_U32 pulseWidth;
2201 GT_U32 trigClkComp;
2202} GT_TAI_TRIGGER_CONFIG;
2203
2204
2205typedef enum
2206{
2207 GT_AVB_HI_FPRI, /* AVB Hi Frame Priority */
2208 GT_AVB_HI_QPRI, /* AVB Hi Queue Priority */
2209 GT_AVB_LO_FPRI, /* AVB Lo Frame Priority */
2210 GT_AVB_LO_QPRI, /* AVB Lo Queue Priority */
2211 GT_LEGACY_HI_FPRI, /* Legacy Hi Frame Priority */
2212 GT_LEGACY_HI_QPRI, /* Legacy Hi Queue Priority */
2213 GT_LEGACY_LO_FPRI, /* Legacy Lo Frame Priority */
2214 GT_LEGACY_LO_QPRI /* Legacy Lo Queue Priority */
2215} GT_AVB_PRI_TYPE;
2216
2217
2218typedef enum
2219{
2220 GT_AVB_LEGACY_MODE, /* all frames entering the port are considered
2221 legacy */
2222 GT_AVB_STANDARD_AVB_MODE, /* any tagged frame that ends up with an AVB frame
2223 priority is considered AVB */
2224 GT_AVB_ENHANCED_AVB_MODE, /* any frame that ends up with an AVB frame priority
2225 whose DA is contained in the ATU with an AVB Entry
2226 state is considered AVB */
2227 GT_AVB_SECURE_AVB_MODE /* any frame that ends up with an AVB frame priority
2228 whose DA is contained in the ATU with an AVB
2229 entry state and whose DPV has this source port's
2230 bit set to a one is considered AVB. */
2231} GT_AVB_MODE;
2232
2233
2234/*
2235 * Typedef: enum GT_AVB_FRAME_POLICY
2236 *
2237 * Description: Defines the policy of the frame
2238 *
2239 * Fields:
2240 * AVB_FRAME_POLICY_NONE - Normal frame switching
2241 * AVB_FRAME_POLICY_MIRROR - Mirror(copy) frame to the MirrorDest port
2242 * AVB_FRAME_POLICY_TRAP - Trap(re-direct) frame to the CPUDest port
2243 *
2244 */
2245typedef enum
2246{
2247 AVB_FRAME_POLICY_NONE = 0,
2248 AVB_FRAME_POLICY_MIRROR,
2249 AVB_FRAME_POLICY_TRAP
2250} GT_AVB_FRAME_POLICY;
2251
2252
2253/*
2254 * Typedef: enum GT_AVB_FRAME_TYPE
2255 *
2256 * Description:
2257 * Defines the AVB frame type.
2258 * AVB Hi Frame is one that DA of the frame is contained in the ATU with an
2259 * Entry State that indicates AVB with priority override where the overridden
2260 * priority equals the Hi AVB frame priority(refer to gavbGetPriority API) and
2261 * when the port's DA AvbOverride is enabled.
2262 * AVB Lo Frame is one that DA of the frame is contained in the ATU with an
2263 * Entry State that indicates AVB with priority override where the overridden
2264 * priority equals the Lo AVB frame priority(refer to gavbGetPriority API) and
2265 * when the port's DA AvbOverride is enabled.
2266 *
2267 * Fields:
2268 * AVB_HI_FRAME - AVB Hi Frame
2269 * AVB_LO_FRAME - AVB Lo Frame
2270 */
2271typedef enum
2272{
2273 AVB_HI_FRAME,
2274 AVB_LO_FRAME
2275} GT_AVB_FRAME_TYPE;
2276
2277
2278/*
2279 * typedef: enum GT_EVENT_TYPE
2280 *
2281 * Description: Enumeration of the available hardware driven events.
2282 *
2283 * Enumerations:
2284 * GT_AVB_INT - AVB Interrupt Enable
2285 * GT_DEVICE_INT - Device Interrupt (GT_DEVICE_INT_TYPE) Enable
2286 * GT_STATS_DONE - Statistics Operation Done interrrupt Enable
2287 * GT_VTU_PROB - VLAN Problem/Violation Interrupt Enable
2288 * GT_VTU_DONE - VALN Table Operation Done Interrupt Enable
2289 * GT_ATU_PROB - ATU Problem/Violation Interrupt Enable, for Gigabit Switch
2290 * GT_ATU_FULL - ATU full interrupt enable, for Fast Ethernet Switch
2291 * GT_ATU_DONE - ATU Done interrupt enable.
2292 * GT_PHY_INT - PHY interrupt enable, for Fast Ethernet Switch
2293 * GT_EE_INT - EEPROM Done interrupt enable.
2294 */
2295#define GT_AVB_INT 0x100
2296#define GT_DEVICE_INT 0x80
2297#define GT_STATS_DONE 0x40
2298#define GT_VTU_PROB 0x20
2299#define GT_VTU_DONE 0x10
2300#define GT_ATU_PROB 0x8
2301#define GT_ATU_FULL 0x8
2302#define GT_ATU_DONE 0x4
2303#define GT_PHY_INTERRUPT 0x2 /* Device may not support PHY Int. Please refer to datasheet. */
2304#define GT_EE_INTERRUPT 0x1
2305
2306#define GT_INT_MASK \
2307 (GT_AVB_INT | GT_DEVICE_INT | GT_STATS_DONE | GT_VTU_PROB | GT_VTU_DONE | GT_ATU_FULL | \
2308 GT_ATU_DONE | GT_PHY_INTERRUPT | GT_EE_INTERRUPT)
2309#define GT_NO_INTERNAL_PHY_INT_MASK \
2310 (GT_AVB_INT | GT_DEVICE_INT | GT_STATS_DONE | GT_VTU_PROB | GT_VTU_DONE | GT_ATU_PROB | \
2311 GT_ATU_DONE | GT_EE_INTERRUPT)
2312
2313
2314/*
2315 * typedef: struct GT_DEV_EVENT
2316 *
2317 * Description: Device interrupt status
2318 *
2319 * Fields:
2320 * event - Device Interrupts to be enabled
2321 * GT_DEV_INT_WATCHDOG, GT_DEV_INT_JAMLIMIT,
2322 * GT_DEV_INT_DUPLEX_MISMATCH, and/or GT_DEV_INT_SERDES_LINK
2323 * portList - SERDES port list where GT_DEV_INT_SERDES_LINK interrupt needs
2324 * to be asserted. It's in vector format, Bit 10 is for port 10,
2325 * Bit 9 is for port 9, etc.
2326 * valid only if GT_DEV_INT_SERDES_LINK bit is set.
2327 * phyList - Phy list where GT_DEV_INT_PHY interrupt needs to be asserted.
2328 * It's in vector format, Bit 0 is for port 0,
2329 * Bit 1 is for port 1, etc.
2330 * valid only if GT_DEV_INT_PHY bit is set.
2331 */
2332typedef struct
2333{
2334 GT_U32 event;
2335 GT_U32 portList;
2336 GT_U32 phyList;
2337} GT_DEV_EVENT;
2338
2339
2340/*
2341 * typedef: struct GT_DEV_INT_STATUS
2342 *
2343 * Description: Device interrupt status
2344 *
2345 * Fields:
2346 * intCause - Device Interrupt Cause
2347 * GT_DEV_INT_WATCHDOG, GT_DEV_INT_JAMLIMIT,
2348 * GT_DEV_INT_DUPLEX_MISMATCH, and/or GT_DEV_INT_SERDES_LINK
2349 * port - logical port where GT_DEV_INT_DUPLEX_MISMATCH occurred.
2350 * valid only if GT_DEV_INT_DUPLEX_MISMATCH is set.
2351 * linkInt - SERDES port list where GT_DEV_INT_SERDES_LINK interrupt is
2352 * asserted. It's in vector format, Bit 10 is for port 10,
2353 * Bit 9 is for port 9, etc.
2354 * valid only if GT_DEV_INT_SERDES_LINK bit is set.
2355 * These bits are only valid of the port that is in 1000Base-X mode.
2356 */
2357typedef struct
2358{
2359 GT_U32 devIntCause;
2360 GT_LPORT port;
2361 GT_U32 linkInt;
2362 GT_U32 phyInt;
2363} GT_DEV_INT_STATUS;
2364
2365
2366/*
2367* GT_DEVICE_INT
2368*
2369* Description: Enumeration of Device interrupt
2370* GT_DEV_INT_WATCHDOG - WatchDog event interrupt (WatchDog event can be
2371* configured with gwdSetEvent API)
2372* GT_DEV_INT_JAMLIMIT - any of the ports detect an Ingress Jam Limit violation
2373* (gprtSetPauseLimitIn API)
2374* GT_DEV_INT_DUPLEX_MISMATCH - any of the ports detect a duplex mismatch
2375* (i.e., the local port is in half duplex mode while
2376* the link partner is in full duplex mode)
2377* GT_DEV_INT_SERDES_LINK - SERDES link chage interrupt.
2378* An interrupt occurs when a SERDES port changes link
2379* status (link up or link down)
2380*/
2381
2382#define GT_DEV_INT_WATCHDOG 0x8
2383#define GT_DEV_INT_JAMLIMIT 0x4
2384#define GT_DEV_INT_DUPLEX_MISMATCH 0x2
2385#define GT_DEV_INT_SERDES_LINK 0x1
2386#define GT_DEV_INT_PHY 0x10
2387
2388/*
2389* GT_WATCHDOG_EVENT
2390*
2391* Description: Enumeration of WatchDog event
2392* GT_WD_QC - Queue Controller Watch Dog enable.
2393* When enabled, the QC's watch dog circuit checks for link
2394* list errors and any errors found in the QC.
2395* GT_WD_EGRESS - Egress Watch Dog enable.
2396* When enabled, each port's egress circuit checks for problems
2397* between the port and the Queue Controller.
2398* GT_WD_FORCE - Force a Watch Dog event.
2399*/
2400
2401#define GT_WD_QC 0x1
2402#define GT_WD_EGRESS 0x2
2403#define GT_WD_FORCE 0x4
2404
2405
2406/*
2407* typedef: struct GT_WD_EVENT_HISTORY
2408*
2409* Description: WatchDog Event History (cleared only by a hardware reset)
2410* wdEvent - When it's set to GT_TRUE, some enabled Watch Dog event occurred.
2411* The following events are possible:
2412* QC WatchDog Event (GT_WD_QC)
2413* Egress WatchDog Event (GT_WD_EGRESS)
2414* Forced WatchDog Event (GT_WD_FORCE)
2415* egressEvent-If any port's egress logic detects an egress watch dog issue,
2416* this field is set to GT_TRUE, regardless of the enabling GT_WD_EGRESS
2417* event.
2418*/
2419typedef struct
2420{
2421 GT_BOOL wdEvent;
2422 GT_BOOL egressEvent;
2423} GT_WD_EVENT_HISTORY;
2424
2425
2426/*
2427* typedef: enum GT_PHY_INT
2428*
2429* Description: Enumeration of PHY interrupt
2430*/
2431
2432#define GT_SPEED_CHANGED 0x4000
2433#define GT_DUPLEX_CHANGED 0x2000
2434#define GT_PAGE_RECEIVED 0x1000
2435#define GT_AUTO_NEG_COMPLETED 0x800
2436#define GT_LINK_STATUS_CHANGED 0x400
2437#define GT_SYMBOL_ERROR 0x200
2438#define GT_FALSE_CARRIER 0x100
2439#define GT_FIFO_FLOW 0x80
2440#define GT_CROSSOVER_CHANGED 0x40
2441#define GT_POLARITY_CHANGED 0x2
2442#define GT_JABBER 0x1
2443
2444#define GT_AUTO_NEG_ERROR 0x8000
2445#define GT_DOWNSHIFT_DETECT 0x20
2446#define GT_ENERGY_DETECT 0x10
2447
2448/*
2449* typedef: enum GT_PHY_AUTO_MODE
2450*
2451* Description: Enumeration of Autonegotiation mode.
2452* Auto for both speed and duplex.
2453* Auto for speed only and Full duplex.
2454* Auto for speed only and Half duplex. (1000Mbps is not supported)
2455* Auto for duplex only and speed 1000Mbps.
2456* Auto for duplex only and speed 100Mbps.
2457* Auto for duplex only and speed 10Mbps.
2458* 1000Mbps Full duplex.
2459* 100Mbps Full duplex.
2460* 100Mbps Half duplex.
2461* 10Mbps Full duplex.
2462* 10Mbps Half duplex.
2463*/
2464
2465typedef enum
2466{
2467 SPEED_AUTO_DUPLEX_AUTO,
2468 SPEED_1000_DUPLEX_AUTO,
2469 SPEED_100_DUPLEX_AUTO,
2470 SPEED_10_DUPLEX_AUTO,
2471 SPEED_AUTO_DUPLEX_FULL,
2472 SPEED_AUTO_DUPLEX_HALF,
2473 SPEED_1000_DUPLEX_FULL,
2474 SPEED_1000_DUPLEX_HALF,
2475 SPEED_100_DUPLEX_FULL,
2476 SPEED_100_DUPLEX_HALF,
2477 SPEED_10_DUPLEX_FULL,
2478 SPEED_10_DUPLEX_HALF
2479}GT_PHY_AUTO_MODE;
2480
2481
2482/*
2483* typedef: enum GT_PHY_PAUSE_MODE
2484*
2485* Description: Enumeration of Pause Mode in the Phy.
2486*
2487* Enumerations:
2488* GT_PHY_NO_PAUSE - disable pause
2489* GT_PHY_PAUSE - support pause
2490* GT_PHY_ASYMMETRIC_PAUSE - support asymmetric pause
2491* GT_PHY_BOTH_PAUSE - support both pause and asymmetric pause
2492*/
2493typedef enum
2494{
2495 GT_PHY_NO_PAUSE = 0,
2496 GT_PHY_PAUSE,
2497 GT_PHY_ASYMMETRIC_PAUSE,
2498 GT_PHY_BOTH_PAUSE
2499} GT_PHY_PAUSE_MODE;
2500
2501
2502/*
2503* typedef: enum GT_PHY_SPEED
2504*
2505* Description: Enumeration of Phy Speed
2506*
2507* Enumerations:
2508* PHY_SPEED_10_MBPS - 10Mbps
2509* PHY_SPEED_100_MBPS - 100Mbps
2510* PHY_SPEED_1000_MBPS - 1000Mbps
2511*/
2512typedef enum
2513{
2514 PHY_SPEED_10_MBPS,
2515 PHY_SPEED_100_MBPS,
2516 PHY_SPEED_1000_MBPS
2517} GT_PHY_SPEED;
2518
2519/*
2520* typedef: enum GT_PHY_LOOPBACK_MODE
2521*
2522* Description: Enumeration of Phy loopback mode
2523*
2524* Enumerations:
2525 PHY_INTERNAL_LOOPBACK: internal loopback mode
2526 PHY_EXTERNAL_LOOPBACK:external loopback mode
2527*/
2528typedef enum
2529{
2530 PHY_INTERNAL_LOOPBACK,
2531 PHY_EXTERNAL_LOOPBACK
2532} GT_PHY_LOOPBACK_MODE;
2533
2534/*
2535* typedef: enum GT_MIRROR_MODE
2536*
2537* Description: Enumeration of Phy Speed
2538*
2539* Enumerations:
2540* SW_MIRROR_INGRESS - mirror ingress packets to destination port
2541* SW_MIRROR_EGRESS - mirror egress packets to destination port
2542*/
2543typedef enum
2544{
2545 SW_MIRROR_INGRESS,
2546 SW_MIRROR_EGRESS
2547} GT_MIRROR_MODE;
2548
2549
2550/*
2551* typedef: enum GT_SERDES_MODE
2552*
2553* Description: Enumeration of Serdes mode
2554*
2555* Enumerations:
2556* PHY_SERDES_100FX - 100 FX
2557* PHY_SERDES_1000X - 1000 X
2558* PHY_SERDES_SGMII_PHY - SGMII PHY
2559* PHY_SERDES_SGMII_MAC - SGMII MAC
2560*/
2561typedef enum
2562{
2563 PHY_SERDES_100FX = 0,
2564 PHY_SERDES_1000X,
2565 PHY_SERDES_SGMII_PHY,
2566 PHY_SERDES_SGMII_MAC
2567} GT_SERDES_MODE;
2568
2569
2570/*
2571* typedef: enum GT_EDETECT_MODE
2572*
2573* Description: Enumeration of Energy Detect mode
2574*
2575* Enumerations:
2576* GT_EDETECT_OFF - Energy Detect disabled
2577* GT_EDETECT_SENSE_PULSE - Energy Detect enabled with sense and pulse
2578* GT_EDETECT_SENSE - Energy Detect enabled only with sense
2579*/
2580typedef enum
2581{
2582 GT_EDETECT_OFF = 0,
2583 GT_EDETECT_SENSE_PULSE,
2584 GT_EDETECT_SENSE
2585} GT_EDETECT_MODE;
2586
2587/*
2588 * typedef: enum GT_INGRESS_MODE
2589 *
2590 * Description: Enumeration of the port ingress mode.
2591 *
2592 * Enumerations:
2593 * GT_UNMODIFY_INGRESS - frames are receive unmodified.
2594 * GT_TRAILER_INGRESS - all frames are received with trailer.
2595 * GT_UNTAGGED_INGRESS - remove tag on receive (for double tagging).
2596 * GT_CPUPORT_INGRESS - no trailer. used to identify the CPU port for IGMP/MLD Snooping
2597 */
2598typedef enum
2599{
2600 GT_UNMODIFY_INGRESS = 0, /* 0x00 */
2601 GT_TRAILER_INGRESS, /* 0x01 */
2602 GT_UNTAGGED_INGRESS, /* 0x10 */
2603 GT_CPUPORT_INGRESS /* 0x11 */
2604} GT_INGRESS_MODE;
2605
2606
2607/*
2608 * typedef: enum GT_EGRESS_FLOOD
2609 *
2610 * Description: Enumeration of the port ingress mode.
2611 *
2612 * Enumerations:
2613 * GT_BLOCK_EGRESS_UNKNOWN - do not egress frame with unknown DA
2614 * GT_BLOCK_EGRESS_UNKNOWN_MULTICAST - do not egress frame with unknown multicast DA
2615 * GT_BLOCK_EGRESS_UNKNOWN_UNIICAST - do not egress frame with unknown unicast DA
2616 * GT_BLOCK_EGRESS_NONE - egress all frames with unknown DA
2617 */
2618typedef enum
2619{
2620 GT_BLOCK_EGRESS_UNKNOWN = 0,
2621 GT_BLOCK_EGRESS_UNKNOWN_MULTICAST,
2622 GT_BLOCK_EGRESS_UNKNOWN_UNICAST,
2623 GT_BLOCK_EGRESS_NONE
2624} GT_EGRESS_FLOOD;
2625
2626
2627/*
2628 * typedef: enum GT_MC_RATE
2629 *
2630 * Description: Enumeration of the port ingress mode.
2631 *
2632 * Enumerations:
2633 * GT_MC_3_PERCENT_RL - multicast rate is limited to 3 percent.
2634 * GT_MC_6_PERCENT_RL - multicast rate is limited to 6 percent.
2635 * GT_MC_12_PERCENT_RL - multicast rate is limited to 12 percent.
2636 * GT_MC_100_PERCENT_RL - unlimited multicast rate.
2637 */
2638typedef enum
2639{
2640 GT_MC_3_PERCENT_RL = 0,
2641 GT_MC_6_PERCENT_RL,
2642 GT_MC_12_PERCENT_RL,
2643 GT_MC_100_PERCENT_RL,
2644} GT_MC_RATE;
2645
2646
2647/*
2648 * typedef: enum GT_INGRESS_RATE_MODE
2649 *
2650 * Description: Enumeration of the port ingress rate limit mode.
2651 *
2652 * Enumerations:
2653 * GT_RATE_PRI_BASE - Priority based rate limiting
2654 * GT_RATE_BURST_BASE - Burst Size based rate limiting
2655 */
2656typedef enum
2657{
2658 GT_RATE_PRI_BASE = 0,
2659 GT_RATE_BURST_BASE
2660} GT_INGRESS_RATE_MODE;
2661
2662
2663/*
2664 * typedef: enum GT_PORT_SCHED_MODE
2665 *
2666 * Description: Enumeration of port scheduling mode
2667 *
2668 * Fields:
2669 * GT_PORT_SCHED_WEIGHTED_RRB - use 8,4,2,1 weighted fair scheduling
2670 * GT_PORT_SCHED_STRICT_PRI - use a strict priority scheme
2671 * GT_PORT_SCHED_STRICT_PRI3 - use a strict for priority 3 and weighted
2672 * round robin for the priority 2,1,and 0
2673 * GT_PORT_SCHED_STRICT_PRI2_3 - use a strict for priority 2,3 and weighted
2674 * round robin for the priority 1,and 0
2675 *
2676 * Comment:
2677 */
2678typedef enum
2679{
2680 GT_PORT_SCHED_WEIGHTED_RRB = 0,
2681 GT_PORT_SCHED_STRICT_PRI,
2682 GT_PORT_SCHED_STRICT_PRI3,
2683 GT_PORT_SCHED_STRICT_PRI2_3
2684} GT_PORT_SCHED_MODE;
2685
2686
2687/*
2688 * typedef: struct GT_PORT_STAT
2689 *
2690 * Description: port statistic struct.
2691 *
2692 * Fields:
2693 * rxCtr - port receive counter.
2694 * txCtr - port transmit counter.
2695 * dropped - dropped frame counter.
2696 *
2697 * Comment:
2698 * dropped frame counter is supported by only limited devices.
2699 * At this moment, 88E6061/88E6065 are the devices supporting
2700 * dropped frame counter.
2701 */
2702typedef struct
2703{
2704 GT_U16 rxCtr;
2705 GT_U16 txCtr;
2706 GT_U16 dropped;
2707} GT_PORT_STAT;
2708
2709/*
2710 * typedef: struct GT_PORT_STAT2
2711 *
2712 * Description: port statistic struct.
2713 *
2714 * Fields:
2715 * inDiscardLo - InDiscards Low Frame Counter
2716 * inDiscardHi - InDiscards High Frame Counter
2717 * inFiltered - InFiltered Frame Counter
2718 * outFiltered - OutFiltered Frame Counter
2719 *
2720 * Comment:
2721 */
2722typedef struct
2723{
2724 GT_U16 inDiscardLo;
2725 GT_U16 inDiscardHi;
2726 GT_U16 inFiltered;
2727 GT_U16 outFiltered;
2728} GT_PORT_STAT2;
2729
2730
2731/*
2732 ** typedef: struct GT_PORT_Q_COUNTERS
2733 **
2734 ** Description: port queue statistic struct.
2735 **
2736 ** Fields:
2737 ** OutQ_Size - port egress queue size coi
2738 ** Rsv_Size - ingress reserved e counter
2739 **
2740 **/
2741typedef struct
2742{
2743 GT_U16 OutQ_Size;
2744 GT_U16 Rsv_Size;
2745} GT_PORT_Q_STAT;
2746
2747/*
2748 * typedef: enum GT_CTR_MODE
2749 *
2750 * Description: Enumeration of the port counters mode.
2751 *
2752 * Enumerations:
2753 * GT_CTR_ALL - In this mode the counters counts Rx receive and transmit
2754 * frames.
2755 * GT_CTR_ERRORS - In this mode the counters counts Rx Errors and collisions.
2756 */
2757typedef enum
2758{
2759 GT_CTR_ALL = 0,
2760 GT_CTR_ERRORS,
2761} GT_CTR_MODE;
2762
2763typedef struct _GT_QD_DEV GT_QD_DEV;
2764
2765/*
2766 * semaphore related definitions.
2767 * User Applications may register Semaphore functions using following definitions
2768 */
2769typedef enum
2770{
2771 GT_SEM_EMPTY,
2772 GT_SEM_FULL
2773} GT_SEM_BEGIN_STATE;
2774
2775typedef GT_SEM (*FGT_SEM_CREATE)(
2776 GT_SEM_BEGIN_STATE state);
2777typedef GT_STATUS (*FGT_SEM_DELETE)(
2778 GT_SEM semId);
2779typedef GT_STATUS (*FGT_SEM_TAKE)(
2780 GT_SEM semId, GT_U32 timOut);
2781typedef GT_STATUS (*FGT_SEM_GIVE)(
2782 GT_SEM semId);
2783
2784typedef struct
2785{
2786 FGT_SEM_CREATE semCreate; /* create semapore */
2787 FGT_SEM_DELETE semDelete; /* delete the semapore */
2788 FGT_SEM_TAKE semTake; /* try to get a semapore */
2789 FGT_SEM_GIVE semGive; /* return semaphore */
2790}GT_SEM_ROUTINES;
2791
2792/*
2793 * definitions for registering MII access functions.
2794 *
2795*/
2796typedef GT_BOOL (*FGT_READ_MII)(
2797 GT_QD_DEV* dev,
2798 unsigned int phyAddr,
2799 unsigned int miiReg,
2800 unsigned int* value);
2801typedef GT_BOOL (*FGT_WRITE_MII)(
2802 GT_QD_DEV* dev,
2803 unsigned int phyAddr,
2804 unsigned int miiReg,
2805 unsigned int value);
2806typedef GT_BOOL (*FGT_INT_HANDLER)(
2807 GT_QD_DEV* dev,
2808 GT_U16*);
2809
2810typedef struct _BSP_FUNCTIONS
2811{
2812 FGT_READ_MII readMii; /* read MII Registers */
2813 FGT_WRITE_MII writeMii; /* write MII Registers */
2814 FGT_SEM_CREATE semCreate; /* create semapore */
2815 FGT_SEM_DELETE semDelete; /* delete the semapore */
2816 FGT_SEM_TAKE semTake; /* try to get a semapore */
2817 FGT_SEM_GIVE semGive; /* return semaphore */
2818}BSP_FUNCTIONS;
2819
2820
2821/*
2822 * Type definition for MIB counter operation
2823*/
2824typedef enum
2825{
2826 STATS_FLUSH_ALL, /* Flush all counters for all ports */
2827 STATS_FLUSH_PORT, /* Flush all counters for a port */
2828 STATS_READ_COUNTER, /* Read a specific counter from a port */
2829 STATS_READ_REALTIME_COUNTER, /* Read a realtime counter from a port */
2830 STATS_READ_ALL /* Read all counters from a port */
2831
2832} GT_STATS_OPERATION;
2833
2834typedef struct _GT_STATS_COUNTER_SET
2835{
2836 GT_U32 InUnicasts;
2837 GT_U32 InBroadcasts;
2838 GT_U32 InPause;
2839 GT_U32 InMulticasts;
2840 GT_U32 InFCSErr;
2841 GT_U32 AlignErr;
2842 GT_U32 InGoodOctets;
2843 GT_U32 InBadOctets;
2844 GT_U32 Undersize;
2845 GT_U32 Fragments;
2846 GT_U32 In64Octets; /* 64 Octets */
2847 GT_U32 In127Octets; /* 65 to 127 Octets */
2848 GT_U32 In255Octets; /* 128 to 255 Octets */
2849 GT_U32 In511Octets; /* 256 to 511 Octets */
2850 GT_U32 In1023Octets; /* 512 to 1023 Octets */
2851 GT_U32 InMaxOctets; /* 1024 to Max Octets */
2852 GT_U32 Jabber;
2853 GT_U32 Oversize;
2854 GT_U32 InDiscards;
2855 GT_U32 Filtered;
2856 GT_U32 OutUnicasts;
2857 GT_U32 OutBroadcasts;
2858 GT_U32 OutPause;
2859 GT_U32 OutMulticasts;
2860 GT_U32 OutFCSErr;
2861 GT_U32 OutGoodOctets;
2862 GT_U32 Out64Octets; /* 64 Octets */
2863 GT_U32 Out127Octets; /* 65 to 127 Octets */
2864 GT_U32 Out255Octets; /* 128 to 255 Octets */
2865 GT_U32 Out511Octets; /* 256 to 511 Octets */
2866 GT_U32 Out1023Octets; /* 512 to 1023 Octets */
2867 GT_U32 OutMaxOctets; /* 1024 to Max Octets */
2868 GT_U32 Collisions;
2869 GT_U32 Late;
2870 GT_U32 Excessive;
2871 GT_U32 Multiple;
2872 GT_U32 Single;
2873 GT_U32 Deferred;
2874 GT_U32 OutDiscards;
2875
2876} GT_STATS_COUNTER_SET;
2877
2878
2879typedef enum
2880{
2881 STATS_InUnicasts = 0,
2882 STATS_InBroadcasts,
2883 STATS_InPause,
2884 STATS_InMulticasts,
2885 STATS_InFCSErr,
2886 STATS_AlignErr,
2887 STATS_InGoodOctets,
2888 STATS_InBadOctets,
2889 STATS_Undersize,
2890 STATS_Fragments,
2891 STATS_In64Octets,
2892 STATS_In127Octets,
2893 STATS_In255Octets,
2894 STATS_In511Octets,
2895 STATS_In1023Octets,
2896 STATS_InMaxOctets,
2897 STATS_Jabber,
2898 STATS_Oversize,
2899 STATS_InDiscards,
2900 STATS_Filtered,
2901 STATS_OutUnicasts,
2902 STATS_OutBroadcasts,
2903 STATS_OutPause,
2904 STATS_OutMulticasts,
2905 STATS_OutFCSErr,
2906 STATS_OutGoodOctets,
2907 STATS_Out64Octets,
2908 STATS_Out127Octets,
2909 STATS_Out255Octets,
2910 STATS_Out511Octets,
2911 STATS_Out1023Octets,
2912 STATS_OutMaxOctets,
2913 STATS_Collisions,
2914 STATS_Late,
2915 STATS_Excessive,
2916 STATS_Multiple,
2917 STATS_Single,
2918 STATS_Deferred,
2919 STATS_OutDiscards
2920
2921} GT_STATS_COUNTERS;
2922/*
2923 * typedef: enum GT_HISTOGRAM_MODE
2924 *
2925 * Description: Enumeration of the histogram counters mode.
2926 *
2927 * Enumerations:
2928 * GT_COUNT_RX_ONLY - In this mode, Rx Histogram Counters are counted.
2929 * GT_COUNT_TX_ONLY - In this mode, Tx Histogram Counters are counted.
2930 * GT_COUNT_RX_TX - In this mode, Rx and Tx Histogram Counters are counted.
2931 */
2932typedef enum
2933{
2934 GT_COUNT_RX_ONLY = 0,
2935 GT_COUNT_TX_ONLY,
2936 GT_COUNT_RX_TX
2937} GT_HISTOGRAM_MODE;
2938
2939/*
2940 Counter set 2 is used by 88E6183
2941*/
2942typedef struct _GT_STATS_COUNTER_SET2
2943{
2944 GT_U32 InGoodOctetsHi;
2945 GT_U32 InGoodOctetsLo;
2946 GT_U32 InBadOctets;
2947 GT_U32 OutDiscards;
2948 GT_U32 InGoodFrames;
2949 GT_U32 InBadFrames;
2950 GT_U32 InBroadcasts;
2951 GT_U32 InMulticasts;
2952 /*
2953 Histogram Counters : Rx Only, Tx Only, or both Rx and Tx
2954 (refer to Histogram Mode)
2955 */
2956 GT_U32 Octets64; /* 64 Octets */
2957 GT_U32 Octets127; /* 65 to 127 Octets */
2958 GT_U32 Octets255; /* 128 to 255 Octets */
2959 GT_U32 Octets511; /* 256 to 511 Octets */
2960 GT_U32 Octets1023; /* 512 to 1023 Octets */
2961 GT_U32 OctetsMax; /* 1024 to Max Octets */
2962 GT_U32 OutOctetsHi;
2963 GT_U32 OutOctetsLo;
2964 GT_U32 OutFrames;
2965 GT_U32 Excessive;
2966 GT_U32 OutMulticasts;
2967 GT_U32 OutBroadcasts;
2968 GT_U32 InBadMACCtrl;
2969
2970 GT_U32 OutPause;
2971 GT_U32 InPause;
2972 GT_U32 InDiscards;
2973 GT_U32 Undersize;
2974 GT_U32 Fragments;
2975 GT_U32 Oversize;
2976 GT_U32 Jabber;
2977 GT_U32 MACRcvErr;
2978 GT_U32 InFCSErr;
2979 GT_U32 Collisions;
2980 GT_U32 Late;
2981
2982} GT_STATS_COUNTER_SET2;
2983
2984
2985typedef enum
2986{
2987 STATS2_InGoodOctetsHi = 0,
2988 STATS2_InGoodOctetsLo,
2989 STATS2_InBadOctets,
2990
2991 STATS2_OutDiscards,
2992 STATS2_InGoodFrames,
2993 STATS2_InBadFrames,
2994 STATS2_InBroadcasts,
2995 STATS2_InMulticasts,
2996 STATS2_64Octets,
2997 STATS2_127Octets,
2998 STATS2_255Octets,
2999 STATS2_511Octets,
3000 STATS2_1023Octets,
3001 STATS2_MaxOctets,
3002 STATS2_OutOctetsHi,
3003 STATS2_OutOctetsLo,
3004 STATS2_OutFrames,
3005 STATS2_Excessive,
3006 STATS2_OutMulticasts,
3007 STATS2_OutBroadcasts,
3008 STATS2_InBadMACCtrl,
3009 STATS2_OutPause,
3010 STATS2_InPause,
3011 STATS2_InDiscards,
3012 STATS2_Undersize,
3013 STATS2_Fragments,
3014 STATS2_Oversize,
3015 STATS2_Jabber,
3016 STATS2_MACRcvErr,
3017 STATS2_InFCSErr,
3018 STATS2_Collisions,
3019 STATS2_Late
3020
3021} GT_STATS_COUNTERS2;
3022
3023/*
3024 Counter set 3 is used by 88E6093 and 88E6065
3025*/
3026typedef struct _GT_STATS_COUNTER_SET3
3027{
3028 GT_U32 InGoodOctetsLo; /* offset 0 */
3029 GT_U32 InGoodOctetsHi; /* offset 1, not supported by 88E6065 */
3030 GT_U32 InBadOctets; /* offset 2 */
3031 GT_U32 OutFCSErr; /* offset 3 */
3032 GT_U32 InUnicasts; /* offset 4 */
3033 GT_U32 Deferred; /* offset 5 */
3034 GT_U32 InBroadcasts; /* offset 6 */
3035 GT_U32 InMulticasts; /* offset 7 */
3036 /*
3037 Histogram Counters : Rx Only, Tx Only, or both Rx and Tx
3038 (refer to Histogram Mode)
3039 */
3040 GT_U32 Octets64; /* 64 Octets, offset 8 */
3041 GT_U32 Octets127; /* 65 to 127 Octets, offset 9 */
3042 GT_U32 Octets255; /* 128 to 255 Octets, offset 10 */
3043 GT_U32 Octets511; /* 256 to 511 Octets, offset 11 */
3044 GT_U32 Octets1023; /* 512 to 1023 Octets, offset 12 */
3045 GT_U32 OctetsMax; /* 1024 to Max Octets, offset 13 */
3046 GT_U32 OutOctetsLo; /* offset 14 */
3047 GT_U32 OutOctetsHi; /* offset 15, not supported by 88E6065 */
3048 GT_U32 OutUnicasts; /* offset 16 */
3049 GT_U32 Excessive; /* offset 17 */
3050 GT_U32 OutMulticasts; /* offset 18 */
3051 GT_U32 OutBroadcasts; /* offset 19 */
3052 GT_U32 Single; /* offset 20 */
3053
3054 GT_U32 OutPause; /* offset 21 */
3055 GT_U32 InPause; /* offset 22 */
3056 GT_U32 Multiple; /* offset 23 */
3057 GT_U32 Undersize; /* offset 24 */
3058 GT_U32 Fragments; /* offset 25 */
3059 GT_U32 Oversize; /* offset 26 */
3060 GT_U32 Jabber; /* offset 27 */
3061 GT_U32 InMACRcvErr; /* offset 28 */
3062 GT_U32 InFCSErr; /* offset 29 */
3063 GT_U32 Collisions; /* offset 30 */
3064 GT_U32 Late; /* offset 31 */
3065
3066} GT_STATS_COUNTER_SET3;
3067
3068/*
3069 PM Counter is used by 88E6093 and 88E6065
3070*/
3071typedef struct _GT_STATS_PM_COUNTER
3072{
3073 GT_STATS_COUNTER_SET3 Counterset3;
3074 GT_PORT_STAT2 Counterstat2;
3075
3076} GT_STATS_PM_COUNTER;
3077
3078
3079
3080typedef enum
3081{
3082 STATS3_InGoodOctetsLo = 0,
3083 STATS3_InGoodOctetsHi,
3084 STATS3_InBadOctets,
3085
3086 STATS3_OutFCSErr,
3087 STATS3_InUnicasts,
3088 STATS3_Deferred, /* offset 5 */
3089 STATS3_InBroadcasts,
3090 STATS3_InMulticasts,
3091 STATS3_64Octets,
3092 STATS3_127Octets,
3093 STATS3_255Octets, /* offset 10 */
3094 STATS3_511Octets,
3095 STATS3_1023Octets,
3096 STATS3_MaxOctets,
3097 STATS3_OutOctetsLo,
3098 STATS3_OutOctetsHi,
3099 STATS3_OutUnicasts, /* offset 16 */
3100 STATS3_Excessive,
3101 STATS3_OutMulticasts,
3102 STATS3_OutBroadcasts,
3103 STATS3_Single,
3104 STATS3_OutPause,
3105 STATS3_InPause,
3106 STATS3_Multiple,
3107 STATS3_Undersize, /* offset 24 */
3108 STATS3_Fragments,
3109 STATS3_Oversize,
3110 STATS3_Jabber,
3111 STATS3_InMACRcvErr,
3112 STATS3_InFCSErr,
3113 STATS3_Collisions,
3114 STATS3_Late /* offset 31 */
3115
3116} GT_STATS_COUNTERS3;
3117
3118
3119
3120/*
3121 * typedef: struct GT_1000T_MASTER_SLAVE
3122 *
3123 * Description: 1000Base-T Master/Slave Configuration
3124 *
3125 * Fields:
3126 * autoConfig - GT_TRUE for auto-config, GT_FALSE for manual setup.
3127 * masterPrefer - GT_TRUE if Master configuration is preferred.
3128 *
3129 */
3130typedef struct _GT_1000T_MASTER_SLAVE
3131{
3132 GT_BOOL autoConfig;
3133 GT_BOOL masterPrefer;
3134} GT_1000T_MASTER_SLAVE;
3135
3136
3137#define GT_MDI_PAIR_NUM 4 /* (1,2),(3,6),(4,5),(7,8) */
3138#define GT_CHANNEL_PAIR_NUM 2 /* (channel A,B),(channel C,D) */
3139
3140
3141/*
3142 * typedef: enum GT_PHY_LINK_STATUS
3143 *
3144 * Description: Enumeration of Link Status
3145 *
3146 * Enumerations:
3147 * GT_PHY_LINK_OFF - No Link
3148 * GT_PHY_LINK_COPPER - Link on Copper
3149 * GT_PHY_LINK_FIBER - Link on Fiber
3150 */
3151typedef enum
3152{
3153 GT_PHY_LINK_OFF = 0,
3154 GT_PHY_LINK_COPPER = 1,
3155 GT_PHY_LINK_FIBER = 2
3156} GT_PHY_LINK_STATUS;
3157
3158
3159/* Definition for packet generator */
3160
3161/* Payload */
3162typedef enum
3163{
3164 GT_PG_PAYLOAD_RANDOM = 0, /* Pseudo-random */
3165 GT_PG_PAYLOAD_5AA5 /* 5A,A5,5A,A5,... */
3166} GT_PG_PAYLOAD;
3167
3168/* Length */
3169typedef enum
3170{
3171 GT_PG_LENGTH_64 = 0, /* 64 bytes */
3172 GT_PG_LENGTH_1514
3173} GT_PG_LENGTH;
3174
3175/* Error */
3176typedef enum
3177{
3178 GT_PG_TX_NORMAL = 0, /* No Error */
3179 GT_PG_TX_ERROR /* Tx packets with CRC error and Symbol error */
3180} GT_PG_TX;
3181
3182/* Structure for packet generator */
3183typedef struct
3184{
3185 GT_PG_PAYLOAD payload;
3186 GT_PG_LENGTH length;
3187 GT_PG_TX tx;
3188} GT_PG;
3189
3190
3191/*
3192 * typedef: enum GT_TEST_STATUS
3193 *
3194 * Description: Enumeration of VCT test status
3195 *
3196 * Enumerations:
3197 * GT_TEST_FAIL - virtual cable test failed.
3198 * GT_NORMAL_CABLE - normal cable.
3199 * GT_IMPEDANCE_MISMATCH - impedance mismatch.
3200 * GT_OPEN_CABLE - open in cable.
3201 * GT_SHORT_CABLE - short in cable.
3202 *
3203 */
3204typedef enum
3205{
3206 GT_TEST_FAIL,
3207 GT_NORMAL_CABLE,
3208 GT_IMPEDANCE_MISMATCH,
3209 GT_OPEN_CABLE,
3210 GT_SHORT_CABLE,
3211} GT_TEST_STATUS;
3212
3213
3214/*
3215 * typedef: enum GT_NORMAL_CABLE_LEN
3216 *
3217 * Description: Enumeration for normal cable length
3218 *
3219 * Enumerations:
3220 * GT_LESS_THAN_50M - cable length less than 50 meter.
3221 * GT_50M_80M - cable length between 50 - 80 meter.
3222 * GT_80M_110M - cable length between 80 - 110 meter.
3223 * GT_110M_140M - cable length between 110 - 140 meter.
3224 * GT_MORE_THAN_140 - cable length more than 140 meter.
3225 * GT_UNKNOWN_LEN - unknown length.
3226 *
3227 */
3228typedef enum
3229{
3230 GT_LESS_THAN_50M,
3231 GT_50M_80M,
3232 GT_80M_110M,
3233 GT_110M_140M,
3234 GT_MORE_THAN_140,
3235 GT_UNKNOWN_LEN,
3236
3237} GT_NORMAL_CABLE_LEN;
3238
3239
3240/*
3241 * typedef: enum GT_CABLE_LEN
3242 *
3243 * Description: Enumeration cable length
3244 *
3245 * Enumerations:
3246 * normCableLen - cable lenght for normal cable.
3247 * errCableLen - for cable failure the estimate fault distance in meters.
3248 *
3249 */
3250typedef union
3251{
3252 GT_NORMAL_CABLE_LEN normCableLen;
3253 GT_U8 errCableLen;
3254
3255} GT_CABLE_LEN;
3256
3257/*
3258 * typedef: struct GT_CABLE_STATUS
3259 *
3260 * Description: virtual cable diagnostic status per MDI pair.
3261 *
3262 * Fields:
3263 * cableStatus - VCT cable status.
3264 * cableLen - VCT cable length.
3265 * phyType - type of phy (100M phy or Gigabit phy)
3266 */
3267typedef struct
3268{
3269 GT_TEST_STATUS cableStatus[GT_MDI_PAIR_NUM];
3270 GT_CABLE_LEN cableLen[GT_MDI_PAIR_NUM];
3271 GT_U16 phyType;
3272
3273} GT_CABLE_STATUS;
3274
3275
3276/*
3277 * typedef: enum GT_CABLE_TYPE
3278 *
3279 * Description: Enumeration of Cable Type
3280 *
3281 * Enumerations:
3282 * GT_STRAIGHT_CABLE _ straight cable
3283 * GT_CROSSOVER_CABLE - crossover cable
3284 */
3285typedef enum
3286{
3287 GT_STRAIGHT_CABLE,
3288 GT_CROSSOVER_CABLE
3289
3290} GT_CABLE_TYPE;
3291
3292
3293/*
3294 * typedef: enum GT_RX_CHANNEL
3295 *
3296 * Description: Enumeration of Receiver Channel Assignment
3297 *
3298 * Enumerations:
3299 * GT_CHANNEL_A - Channel A
3300 * GT_CHANNEL_B - Channel B
3301 * GT_CHANNEL_C - Channel C
3302 * GT_CHANNEL_D - Channel D
3303 */
3304typedef enum
3305{
3306 GT_CHANNEL_A,
3307 GT_CHANNEL_B,
3308 GT_CHANNEL_C,
3309 GT_CHANNEL_D
3310} GT_RX_CHANNEL;
3311
3312
3313/*
3314 * typedef: enum GT_POLARITY_STATUS
3315 *
3316 * Description: Enumeration of polarity status
3317 *
3318 * Enumerations:
3319 * GT_POSITIVE - positive polarity
3320 * GT_NEGATIVE - negative polarity
3321 */
3322typedef enum
3323{
3324 GT_POSITIVE,
3325 GT_NEGATIVE
3326
3327} GT_POLARITY_STATUS;
3328
3329
3330/*
3331 * typedef: struct GT_1000BT_EXTENDED_STATUS
3332 *
3333 * Description: Currently the 1000Base-T PCS can determine the cable polarity
3334 * on pairs A,B,C,D; crossover on pairs A,B and C,D; and skew among
3335 * the pares. These status enhance the capability of the virtual cable tester
3336 *
3337 * Fields:
3338 * isValid - GT_TRUE if this structure have valid information,
3339 * GT_FALSE otherwise.
3340 * It is valid only if 1000BASE-T Link is up.
3341 * pairSwap - GT_CROSSOVER_CABLE, if the cable is crossover,
3342 * GT_STRAIGHT_CABLE, otherwise
3343 * pairPolarity- GT_POSITIVE, if polarity is positive,
3344 * GT_NEGATIVE, otherwise
3345 * pairSkew - pair skew in units of ns
3346 */
3347typedef struct
3348{
3349 GT_BOOL isValid;
3350 GT_CABLE_TYPE pairSwap[GT_CHANNEL_PAIR_NUM];
3351 GT_POLARITY_STATUS pairPolarity[GT_MDI_PAIR_NUM];
3352 GT_U32 pairSkew[GT_MDI_PAIR_NUM];
3353
3354} GT_1000BT_EXTENDED_STATUS;
3355
3356
3357/*
3358 * typedef: struct GT_ADV_EXTENDED_STATUS
3359 *
3360 * Description: Currently the 1000Base-T PCS can determine the cable polarity
3361 * on pairs A,B,C,D; crossover on pairs A,B and C,D; and skew among
3362 * the pares. These status enhance the capability of the virtual cable tester
3363 *
3364 * Fields:
3365 * isValid - GT_TRUE if this structure have valid information,
3366 * GT_FALSE otherwise.
3367 * It is valid only if 1000BASE-T Link is up.
3368 * pairSwap - Receive channel assignement
3369 * pairPolarity- GT_POSITIVE, if polarity is positive,
3370 * GT_NEGATIVE, otherwise
3371 * pairSkew - pair skew in units of ns
3372 * cableLen - cable length based on DSP
3373 */
3374typedef struct
3375{
3376 GT_BOOL isValid;
3377 GT_RX_CHANNEL pairSwap[GT_MDI_PAIR_NUM];
3378 GT_POLARITY_STATUS pairPolarity[GT_MDI_PAIR_NUM];
3379 GT_U32 pairSkew[GT_MDI_PAIR_NUM];
3380 GT_U32 cableLen[GT_MDI_PAIR_NUM];
3381} GT_ADV_EXTENDED_STATUS;
3382
3383
3384/*
3385 * if isGigPhy in GT_CABLE_STATUS is not GT_TRUE, cableStatus and cableLen
3386 * will have only 2 pairs available.
3387 * One is RX Pair and the other is TX Pair.
3388 */
3389#define MDI_RX_PAIR 0 /* cableStatus[0] or cableLen[0] */
3390#define MDI_TX_PAIR 1 /* cableStatus[1] or cableLen[1] */
3391
3392/* definition for Phy Type */
3393#define PHY_100M 0 /* 10/100M phy, E3082 or E3083 */
3394#define PHY_1000M 1 /* Gigabit phy, the rest phys */
3395#define PHY_10000M 2 /* 10 Gigabit phy, unused */
3396#define PHY_1000M_B 3 /* Gigabit phy which needs work-around */
3397#define PHY_1000M_MP 4 /* Gigabit phy with multiple page mode */
3398
3399
3400/* Definition for Advance Virtual Cable Test */
3401
3402/*
3403 * typedef: enum GT_ADV_VCT_TRANS_CHAN_SEL
3404 *
3405 * Description: Enumeration of Advanced VCT Transmitter channel select
3406 *
3407 * Enumerations:
3408 * GT_ADV_VCT_NO_CROSSPAIR - Transmitter channel select is 000
3409 * GT_ADV_VCT_CROSSPAIR - Transmitter channelselect is 100/101/110/111
3410 */
3411typedef enum
3412{
3413 /* Advanced VCT Mode */
3414 GT_ADV_VCT_TCS_NO_CROSSPAIR = 0,
3415 GT_ADV_VCT_TCS_CROSSPAIR_0 = 0x4,
3416 GT_ADV_VCT_TCS_CROSSPAIR_1 = 0x5,
3417 GT_ADV_VCT_TCS_CROSSPAIR_2 = 0x6,
3418 GT_ADV_VCT_TCS_CROSSPAIR_3 = 0x7
3419} GT_ADV_VCT_TRANS_CHAN_SEL;
3420
3421
3422typedef enum
3423{
3424 /* Advanced VCT Mode */
3425 GT_ADV_VCT_SAVG_2 = 0,
3426 GT_ADV_VCT_SAVG_4 = 1,
3427 GT_ADV_VCT_SAVG_8 = 2,
3428 GT_ADV_VCT_SAVG_16 = 3,
3429 GT_ADV_VCT_SAVG_32 = 4,
3430 GT_ADV_VCT_SAVG_64 = 5,
3431 GT_ADV_VCT_SAVG_128 = 6,
3432 GT_ADV_VCT_SAVG_256 = 7
3433} GT_ADV_VCT_SAMPLE_AVG;
3434
3435typedef enum
3436{
3437 /* Advanced VCT Mode */
3438 GT_ADV_VCT_MAX_PEAK =0x00,
3439 GT_ADV_VCT_FIRST_PEAK =0x01,
3440} GT_ADV_VCT_MOD;
3441
3442
3443typedef unsigned int GT_ADV_VCT_PEAKDET_HYST;
3444
3445/*
3446 * typedef: enum GT_ADV_VCT_MODE
3447 *
3448 * Description: Enumeration of Advanced VCT Mode and Transmitter channel select
3449 *
3450 * Enumerations:
3451 * GT_ADV_VCT_FIRST_PEAK - first peak above a certain threshold is reported.
3452 * GT_ADV_VCT_MAX_PEAK - maximum peak above a certain threshold is reported.
3453 * GT_ADV_VCT_OFFSE - offset
3454 * GT_ADV_VCT_SAMPLE_POINT - sample point
3455 *
3456 * GT_ADV_VCT_NO_CROSSPAIR - Transmitter channel select is 000
3457 * GT_ADV_VCT_CROSSPAIR - Transmitter channelselect is 100/101/110/111
3458 * Example: mode = GT_ADV_VCT_FIRST_PEAK | GT_ADV_VCT_CROSSPAIR.
3459 */
3460typedef struct
3461{
3462 GT_ADV_VCT_MOD mode;
3463 GT_ADV_VCT_TRANS_CHAN_SEL transChanSel;
3464 GT_ADV_VCT_SAMPLE_AVG sampleAvg;
3465 GT_ADV_VCT_PEAKDET_HYST peakDetHyst;
3466} GT_ADV_VCT_MODE;
3467
3468
3469/*
3470 * typedef: enum GT_ADV_VCT_STATUS
3471 *
3472 * Description: Enumeration of Advanced VCT status
3473 *
3474 * Enumerations:
3475 * GT_ADV_VCT_FAIL - advanced virtual cable test failed.
3476 * cable lengh cannot be determined.
3477 * GT_ADV_VCT_NORMAL - normal cable.
3478 * cable lengh may not be determined.
3479 * GT_ADV_VCT_IMP_GREATER_THAN_115 - impedance mismatch > 115 ohms
3480 * cable lengh is valid.
3481 * GT_ADV_VCT_IMP_LESS_THAN_85 - impedance mismatch < 85 ohms
3482 * cable lengh is valid.
3483 * GT_ADV_VCT_OPEN - cable open
3484 * cable lengh is valid.
3485 * GT_ADV_VCT_SHORT - cable shorted
3486 * cable lengh is valid.
3487 * GT_ADV_VCT_CROSS_PAIR_SHORT - cross pair short.
3488 * cable lengh for each channel is valid.
3489 */
3490typedef enum
3491{
3492 GT_ADV_VCT_FAIL,
3493 GT_ADV_VCT_NORMAL,
3494 GT_ADV_VCT_IMP_GREATER_THAN_115,
3495 GT_ADV_VCT_IMP_LESS_THAN_85,
3496 GT_ADV_VCT_OPEN,
3497 GT_ADV_VCT_SHORT,
3498 GT_ADV_VCT_CROSS_PAIR_SHORT
3499} GT_ADV_VCT_STATUS;
3500
3501
3502/*
3503 * typedef: struct GT_CROSS_PAIR_LIST
3504 *
3505 * Description: strucuture for cross pair short channels.
3506 *
3507 * Fields:
3508 * channel - cross pair short channel list
3509 * channel[i] is GT_TRUE if the channel[i] is cross pair short
3510 * with the current channel under test.
3511 * dist2fault - estimated distance to the shorted location.
3512 * valid only if related channel (above) is GT_TRUE.
3513 */
3514typedef struct _GT_CROSS_SHORT_LIST
3515{
3516 GT_BOOL channel[GT_MDI_PAIR_NUM];
3517 GT_16 dist2fault[GT_MDI_PAIR_NUM];
3518} GT_CROSS_SHORT_LIST;
3519
3520
3521/*
3522 * typedef: struct GT_ADV_CABLE_STATUS
3523 *
3524 * Description: strucuture for advanced cable status.
3525 *
3526 * Fields:
3527 * cableStatus - VCT cable status for each channel.
3528 * crossShort - cross pair short list for each channel.
3529 * Valid only if relative cableStatus is GT_ADV_VCT_CROSS_PAIR_SHORT.
3530 * dist2fault - estimated distance to fault for each channel.
3531 * Valid if relative cableStatus is one of the followings:
3532 * GT_ADV_VCT_NORMAL
3533 * GT_ADV_VCT_IMP_GREATER_THAN_115
3534 * GT_ADV_VCT_IMP_LESS_THAN_85,
3535 * GT_ADV_VCT_OPEN, or
3536 * GT_ADV_VCT_SHORT
3537 */
3538typedef struct
3539{
3540 GT_ADV_VCT_STATUS cableStatus[GT_MDI_PAIR_NUM];
3541 union {
3542 GT_CROSS_SHORT_LIST crossShort;
3543 GT_16 dist2fault;
3544 }u[GT_MDI_PAIR_NUM];
3545} GT_ADV_CABLE_STATUS;
3546
3547
3548/*
3549 * Definition:
3550 * GT_LED_LINK_ACT_SPEED - off = no link, on = link, blink = activity, blink speed = link speed
3551 * GT_LED_LINK_ACT - off = no link, on = link, blink = activity
3552 * GT_LED_LINK - off = no link, on = link
3553 * GT_LED_10_LINK_ACT - off = no link, on = 10, blink = activity
3554 * GT_LED_10_LINK - off = no link, on = 10
3555 * GT_LED_100_LINK_ACT - off = no link, on = 100 link, blink = activity
3556 * GT_LED_100_LINK - off = no link, on = 100 link
3557 * GT_LED_1000_LINK_ACT - off = no link, on = 1000 link, blink = activity
3558 * GT_LED_1000_LINK - off = no link, on = 1000 link
3559 * GT_LED_10_100_LINK_ACT - off = no link, on = 10 or 100 link, blink = activity
3560 * GT_LED_10_100_LINK - off = no link, on = 10 or 100 link
3561 * GT_LED_10_1000_LINK_ACT - off = no link, on = 10 or 1000 link, blink = activity
3562 * GT_LED_10_1000_LINK - off = no link, on = 10 or 1000 link
3563 * GT_LED_100_1000_LINK_ACT- off = no link, on = 100 or 1000 link, blink = activity
3564 * GT_LED_100_1000_LINK - off = no link, on = 100 or 1000 link
3565 * GT_LED_SPECIAL - special leds
3566 * GT_LED_DUPLEX_COL - off = half duplx, on = full duplex, blink = collision
3567 * GT_LED_ACTIVITY - off = no link, blink on = activity
3568 * GT_LED_PTP_ACT - blink on = PTP activity
3569 * GT_LED_FORCE_BLINK - force blink
3570 * GT_LED_FORCE_OFF - force off
3571 * GT_LED_FORCE_ON - force on
3572*/
3573#define GT_LED_LINK_ACT_SPEED 1
3574#define GT_LED_LINK_ACT 2
3575#define GT_LED_LINK 3
3576#define GT_LED_10_LINK_ACT 4
3577#define GT_LED_10_LINK 5
3578#define GT_LED_100_LINK_ACT 6
3579#define GT_LED_100_LINK 7
3580#define GT_LED_1000_LINK_ACT 8
3581#define GT_LED_1000_LINK 9
3582#define GT_LED_10_100_LINK_ACT 10
3583#define GT_LED_10_100_LINK 11
3584#define GT_LED_10_1000_LINK_ACT 12
3585#define GT_LED_10_1000_LINK 13
3586#define GT_LED_100_1000_LINK_ACT 14
3587#define GT_LED_100_1000_LINK 15
3588#define GT_LED_SPECIAL 16
3589#define GT_LED_DUPLEX_COL 17
3590#define GT_LED_ACTIVITY 18
3591#define GT_LED_PTP_ACT 19
3592#define GT_LED_FORCE_BLINK 20
3593#define GT_LED_FORCE_OFF 21
3594#define GT_LED_FORCE_ON 22
3595#define GT_LED_RESERVE 23
3596
3597
3598/*
3599 * typedef: enum GT_LED_CFG
3600 *
3601 * Description: Enumeration for LED configuration type
3602 *
3603 * Enumerations:
3604 * GT_LED_CFG_LED0 - read/write led0 value (GT_LED_xxx definition)
3605 * GT_LED_CFG_LED1 - read/write led1 value
3606 * GT_LED_CFG_LED2 - read/write led2 value
3607 * GT_LED_CFG_LED3 - read/write led3 value
3608 * GT_LED_CFG_PULSE_STRETCH - read/write pulse stretch (0 ~ 4)
3609 * GT_LED_CFG_BLINK_RATE - read/write blink rate (0 ~ 5)
3610 * GT_LED_CFG_SPECIAL_CONTROL - read/write special control (port vector)
3611 */
3612typedef enum
3613{
3614 GT_LED_CFG_LED0,
3615 GT_LED_CFG_LED1,
3616 GT_LED_CFG_LED2,
3617 GT_LED_CFG_LED3,
3618 GT_LED_CFG_PULSE_STRETCH,
3619 GT_LED_CFG_BLINK_RATE,
3620 GT_LED_CFG_SPECIAL_CONTROL
3621} GT_LED_CFG;
3622
3623
3624/*
3625 * typedef: enum GT_AVB_RECOVERED_CLOCK
3626 *
3627 * Description: Enumeration for recovered clock type
3628 *
3629 * Enumerations:
3630 * GT_PRIMARY_RECOVERED_CLOCK - primary recovered clock
3631 * GT_SECONDARY_RECOVERED_CLOCK - secondary recovered clock
3632 */
3633typedef enum
3634{
3635 GT_PRIMARY_RECOVERED_CLOCK,
3636 GT_SECONDARY_RECOVERED_CLOCK
3637} GT_AVB_RECOVERED_CLOCK;
3638
3639
3640/* Define QAV interrupt bits */
3641
3642#define GT_QAV_INT_STATUS_ENQ_LMT_BIT 0x8000 /* EnQ Limit Interrupt Enable */
3643#define GT_QAV_INT_STATUS_ISO_DEL_BIT 0x0400 /* Iso Delay Interrupt Enable */
3644#define GT_QAV_INT_STATUS_ISO_DIS_BIT 0x0200 /* Iso Discard Interrupt Enable */
3645#define GT_QAV_INT_STATUS_ISO_LIMIT_EX_BIT 0x0100 /* Iso Packet Memory Exceeded Interrupt Enable */
3646
3647#define GT_QAV_INT_ENABLE_ENQ_LMT_BIT 0x80 /* EnQ Limit Interrupt Enable */
3648#define GT_QAV_INT_ENABLE_ISO_DEL_BIT 0x04 /* Iso Delay Interrupt Enable */
3649#define GT_QAV_INT_ENABLE_ISO_DIS_BIT 0x02 /* Iso Discard Interrupt Enable */
3650#define GT_QAV_INT_ENABLE_ISO_LIMIT_EX_BIT 0x01 /* Iso Packet Memory Exceeded Interrupt Enable */
3651
3652
3653/*
3654 * Typedef: enum GT_EEPROM_OPERATION
3655 *
3656 * Description: Defines the EEPROM Operation type
3657 *
3658 * Fields:
3659 * PTP_WRITE_DATA - Write data to the EEPROM register
3660 * PTP_READ_DATA - Read data from EEPROM register
3661 * PTP_RESTART - Restart EEPROM oprition
3662 */
3663typedef enum
3664{
3665 GT_EEPROM_NO_OP = 0x0,
3666 GT_EEPROM_WRITE_DATA = 0x3,
3667 GT_EEPROM_READ_DATA = 0x4,
3668 GT_EEPROM_RESTART = 0x6,
3669 GT_EEPROM_HALT = 0x7,
3670} GT_EEPROM_OPERATION;
3671
3672
3673/*
3674 * typedef: struct GT_EEPROM_OP_DATA
3675 *
3676 * Description: data required by EEPROM Operation
3677 *
3678 * Fields:
3679 * eepromPort - physical port of the device
3680 * eepromAddr - register address
3681 * eepromData - data for ptp register.
3682 */
3683typedef struct
3684{
3685 GT_U32 eepromPort;
3686 GT_U32 eepromBlock;
3687 GT_U32 eepromAddr;
3688 GT_U32 eepromData;
3689} GT_EEPROM_OP_DATA;
3690
3691#define GT_EEPROM_OP_ST_RUNNING_MASK 0x800
3692#define GT_EEPROM_OP_ST_WRITE_EN_MASK 0x400
3693
3694#define GT_SCRAT_MISC_REG_SCRAT_0 0x00 /* Scratch Byte 0 */
3695#define GT_SCRAT_MISC_REG_SCRAT_1 0x01 /* Scratch Byte 1 */
3696#define GT_SCRAT_MISC_REG_GPIO_CFG 0x60 /* GPIO Configuration */
3697 /* 0x61 = Reserved for future use */
3698#define GT_SCRAT_MISC_REG_GPIO_DIR 0x62 /* GPIO Direction */
3699#define GT_SCRAT_MISC_REG_GPIO_DAT 0x63 /* GPIO Data */
3700#define GT_SCRAT_MISC_REG_CFG_DAT0 0x70 /* CONFIG Data 0 */
3701#define GT_SCRAT_MISC_REG_CFG_DAT1 0x71 /* CONFIG Data 1 */
3702#define GT_SCRAT_MISC_REG_CFG_DAT2 0x72 /* CONFIG Data 2 */
3703#define GT_SCRAT_MISC_REG_CFG_DAT3 0x73 /* CONFIG Data 3 */
3704#define GT_SCRAT_MISC_REG_SYNCE 0x7C /* SyncE & TAICLK125Â’s Drive */
3705#define GT_SCRAT_MISC_REG_P5_CLK 0x7D /* P5Â’s & CLK125Â’s Clock Drive */
3706#define GT_SCRAT_MISC_REG_P6_CLK 0x7E /* P6Â’s Clock Drive */
3707#define GT_SCRAT_MISC_REG_EEPROM 0x7F /* EEPROM Pad drive */
3708#define GT_SCRAT_MISC_REG_MAX 0x80 /* Maximun register pointer */
3709
3710#define GT_GPIO_BIT_0 0x1
3711#define GT_GPIO_BIT_1 0x2
3712#define GT_GPIO_BIT_2 0x4
3713#define GT_GPIO_BIT_3 0x8
3714#define GT_GPIO_BIT_4 0x10
3715#define GT_GPIO_BIT_5 0x20
3716#define GT_GPIO_BIT_6 0x40
3717
3718typedef struct
3719{
3720 GT_U8 user : 3;
3721 GT_U8 addr : 5;
3722}GT_CONFIG_DATA_0;
3723
3724typedef struct
3725{
3726 GT_U8 led : 2;
3727 GT_U8 fourcol : 1;
3728 GT_U8 normCx : 1;
3729 GT_U8 jumbo : 1;
3730 GT_U8 ee_we : 1;
3731 GT_U8 fd_flow : 1;
3732 GT_U8 hd_flow : 1;
3733}GT_CONFIG_DATA_1;
3734
3735typedef struct
3736{
3737 GT_U8 p5_mod : 3;
3738 GT_U8 bit4 : 1;
3739 GT_U8 p6_mod : 3;
3740}GT_CONFIG_DATA_2;
3741
3742typedef struct
3743{
3744 GT_U8 rmu_mod : 2;
3745}GT_CONFIG_DATA_3;
3746
3747typedef struct
3748{
3749 union {
3750 GT_U8 Byte;
3751 GT_CONFIG_DATA_0 Data;
3752 } cfgData0;
3753 union {
3754 GT_U8 Byte;
3755 GT_CONFIG_DATA_0 Data;
3756 } cfgData1;
3757 union {
3758 GT_U8 Byte;
3759 GT_CONFIG_DATA_0 Data;
3760 } cfgData2;
3761 union {
3762 GT_U8 Byte;
3763 GT_CONFIG_DATA_0 Data;
3764 } cfgData3;
3765}GT_CONFIG_DATA;
3766
3767
3768/* definition for Trunking */
3769#define IS_TRUNK_ID_VALID(_dev, _id) (((_id) < 16) ? 1 : 0)
3770
3771
3772/* definition for device scan mode */
3773#define SMI_AUTO_SCAN_MODE 0 /* Scan 0 or 0x10 base address to find the QD */
3774#define SMI_MANUAL_MODE 1 /* Use QD located at manually defined base addr */
3775#define SMI_MULTI_ADDR_MODE 2 /* Use QD at base addr and use indirect access */
3776typedef struct
3777{
3778 GT_U32 scanMode; /* check definition for device scan mode */
3779 GT_U32 baseAddr; /* meaningful if scanMode is not SMI_AUTO_SCAN_MODE */
3780} GT_SCAN_MODE;
3781
3782
3783#define GT_SKIP_INIT_SETUP 0x736b6970
3784
3785/*
3786 * Typedef: struct GT_SYS_CONFIG
3787 *
3788 * Description: System configuration Parameters struct.
3789 *
3790 * Fields:
3791 * devNum - Switch Device Number
3792 * cpuPortNum - The physical port used to connect the device to CPU.
3793 * This is the port to which packets destined to CPU are
3794 * forwarded.
3795 * initPorts - Whether to initialize the ports state.
3796 * GT_FALSE - leave in default state.
3797 * GT_TRUE - Initialize to Forwarding state.
3798 * skipInitSetup - skip init setup, if value is GT_SKIP_INIT_SETUP
3799 * perform init setup, otherwise
3800 * Initializing port state is not affected by this variable.
3801 * BSPFunctions - Group of BSP specific functions.
3802 * SMI Read/Write and Semaphore Related functions.
3803 */
3804typedef struct
3805{
3806 GT_U8 devNum;
3807 GT_U8 cpuPortNum;
3808 GT_BOOL initPorts;
3809 BSP_FUNCTIONS BSPFunctions;
3810 GT_SCAN_MODE mode;
3811 GT_U32 skipInitSetup;
3812}GT_SYS_CONFIG;
3813
3814
3815
3816/*
3817 * Typedef: struct GT_QD_DEV
3818 *
3819 * Description: Includes Tapi layer switch configuration data.
3820 *
3821 * Fields:
3822 * deviceId - The device type identifier.
3823 * revision - The device revision number.
3824 * baseRegAddr - Switch Base Register address.
3825 * numOfPorts - Number of active ports.
3826 * maxPorts - max ports. This field is only for driver's use.
3827 * cpuPortNum - Logical port number whose physical port is connected to the CPU.
3828 * maxPhyNum - max configurable Phy address.
3829 * stpMode - current switch STP mode (0 none, 1 en, 2 dis)
3830 * accessMode - shows how to find and access the device.
3831 * phyAddr - SMI address used to access Switch registers(only for SMI_MULTI_ADDR_MODE).
3832 * validPortVec - valid port list in vector format
3833 * validPhyVec - valid phy list in vector format
3834 * validSerdesVec - valid serdes list in vector format
3835 * devGroup - the device group
3836 * devName - name of the device
3837 * devStorage - driver internal use (hold various temp information)
3838 * multiAddrSem - Semaphore for Accessing SMI Device
3839 * atuRegsSem - Semaphore for ATU access
3840 * vtuRegsSem - Semaphore for VTU access
3841 * statsRegsSem - Semaphore for RMON counter access
3842 * pirlRegsSem - Semaphore for PIRL Resource access
3843 * ptpRegsSem - Semaphore for PTP Resource access
3844 * tblRegsSem - Semaphore for various Table Resource access,
3845 * such as Trunk Tables and Device Table
3846 * eepromRegsSem - Semaphore for eeprom control access
3847 * phyRegsSem - Semaphore for PHY Device access
3848 * fgtReadMii - platform specific SMI register Read function
3849 * fgtWriteMii - platform specific SMI register Write function
3850 * semCreate - function to create semapore
3851 * semDelete - function to delete the semapore
3852 * semTake - function to get a semapore
3853 * semGive - function to return semaphore
3854 * appData - application data that user may use
3855 */
3856struct _GT_QD_DEV
3857{
3858 GT_DEVICE deviceId;
3859 GT_LPORT cpuPortNum;
3860 GT_U8 revision;
3861 GT_U8 devNum;
3862 GT_U8 devEnabled;
3863 GT_U8 baseRegAddr;
3864 GT_U8 numOfPorts;
3865 GT_U8 maxPorts;
3866 GT_U8 maxPhyNum;
3867 GT_U8 stpMode;
3868 GT_U8 accessMode;
3869 GT_U8 phyAddr;
3870 GT_U16 reserved;
3871 GT_U16 validPortVec;
3872 GT_U16 validPhyVec;
3873 GT_U16 validSerdesVec;
3874 GT_U16 devGroup;
3875 GT_U32 devName;
3876 GT_U32 devStorage;
3877 GT_SEM multiAddrSem;
3878 GT_SEM atuRegsSem;
3879 GT_SEM vtuRegsSem;
3880 GT_SEM statsRegsSem;
3881 GT_SEM pirlRegsSem;
3882 GT_SEM ptpRegsSem;
3883 GT_SEM tblRegsSem;
3884 GT_SEM eepromRegsSem;
3885 GT_SEM phyRegsSem;
3886
3887 FGT_READ_MII fgtReadMii;
3888 FGT_WRITE_MII fgtWriteMii;
3889
3890 FGT_SEM_CREATE semCreate; /* create semaphore */
3891 FGT_SEM_DELETE semDelete; /* delete the semaphore */
3892 FGT_SEM_TAKE semTake; /* try to get a semaphore */
3893 FGT_SEM_GIVE semGive; /* return semaphore */
3894 void* appData;
3895
3896};
3897
John Newlin2e746432013-05-31 10:38:29 -07003898/*
3899 * typedef: struct PIRL_PARA_TBL_T
3900 *
3901 * Description: PIRL parameter table structure
3902 *
3903 * Fields:
3904 * BI - bucket increment
3905 * BRF - bucket rate factor
3906 * CBS - Committed Burst Size
3907 * EBS - Excess Burst Size
3908 */
3909typedef struct {
3910 GT_U32 BI;
3911 GT_U32 BRF;
3912 GT_U32 CBS;
3913 GT_U32 EBS;
3914} PIRL_PARA_TBL_T;
3915
3916/*special rate which can not be calculated by formula*/
3917typedef enum {
3918 PIRL_RATE_NO_LIMIT = 0,
3919 PIRL_RATE_64K,
3920 PIRL_RATE_128K,
3921 PIRL_RATE_192K,
3922 PIRL_RATE_256K,
3923 PIRL_RATE_320K,
3924 PIRL_RATE_384K,
3925 PIRL_RATE_448K,
3926 PIRL_RATE_512K,
3927 PIRL_RATE_576K,
3928 PIRL_RATE_640K,
3929 PIRL_RATE_704K,
3930 PIRL_RATE_768K,
3931 PIRL_RATE_832K,
3932 PIRL_RATE_896K,
3933 PIRL_RATE_960K,
3934 PIRL_RATE_1M,
3935 PIRL_RATE_2M,
3936 PIRL_RATE_3M,
3937 PIRL_RATE_4M,
3938 PIRL_RATE_5M,
3939 PIRL_RATE_6M,
3940 PIRL_RATE_7M,
3941 PIRL_RATE_8M,
3942 PIRL_RATE_9M,
3943 PIRL_RATE_10M,
3944 PIRL_RATE_11M,
3945 PIRL_RATE_12M,
3946 PIRL_RATE_13M,
3947 PIRL_RATE_14M,
3948 PIRL_RATE_15M,
3949 PIRL_RATE_16M,
3950 PIRL_RATE_17M,
3951 PIRL_RATE_18M,
3952 PIRL_RATE_19M,
3953 PIRL_RATE_20M
3954} PIRL_SPECIAL_RATE_ENUM_T;
Ke Dong32248e72012-09-26 19:22:56 -07003955
3956#ifdef __cplusplus
3957}
3958#endif
3959
3960#endif /* __msApi_h */