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/*******************************************************************************
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*******************************************************************************/
#include "cpu/mvCpu.h"
#include "ctrlEnv/mvCtrlEnvLib.h"
#include "ctrlEnv/mvCtrlEnvRegs.h"
#include "ctrlEnv/sys/mvCpuIfRegs.h"
#include "boardEnv/mvBoardEnvSpec.h"
#include "boardEnv/mvBoardEnvLib.h"
/* defines */
#ifdef MV_DEBUG
#define DB(x) x
#else
#define DB(x)
#endif
/* locals */
/*******************************************************************************
* mvCpuClockEntryGet - Get the CPU / DDR / L2 entry index from the
* frequncies table.
*
* DESCRIPTION:
* This routine searches for a matching entry in the CPU / DDR / L2
* frequencies table according to the S@R value.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* Index of matching entry, or 0xFFFFFFFF if S@R value is not valid.
*
*******************************************************************************/
static MV_U32 mvCpuClockEntryGet(MV_VOID)
{
MV_U32 i, res = -1;
MV_U32 sar0;
MV_U32 clockSatr;
MV_CPU_ARM_CLK cpuDdrL2Tbl[] = MV_CPU_DDR_L2_CLCK_TBL;
MV_CPU_ARM_CLK cpuDdrTbl6601[] = MV6601_CPU_DDR_CLCK_TBL;
MV_U32 boardId = mvBoardIdGet();
/* Read S@R registers value */
sar0 = MV_REG_READ(MPP_SAMPLE_AT_RESET(0));
clockSatr = MSAR_CPU_DDR_L2_CLCK_EXTRACT(sar0);
/* Search for a matching entry */
i = 0;
if (boardId == RD_88F6601_MC_ID || boardId == RD_88F6601_MC2L_ID ||
boardId == DB_88F6601_BP_ID ||
GFLT300_ID == boardId || GFLT200_ID == boardId || GFLT110_ID == boardId) {
while (cpuDdrTbl6601[i].satrValue != -1) {
if (cpuDdrTbl6601[i].satrValue == clockSatr) {
res = i;
break;
}
i++;
}
} else {
while (cpuDdrL2Tbl[i].satrValue != -1) {
if (cpuDdrL2Tbl[i].satrValue == clockSatr) {
res = i;
break;
}
i++;
}
}
return res;
}
/*******************************************************************************
* mvCpuPclkGet - Get the CPU pClk (pipe clock)
*
* DESCRIPTION:
* This routine extract the CPU core clock.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* 32bit clock cycles in MHertz.
*
*******************************************************************************/
MV_U32 mvCpuPclkGet(MV_VOID)
{
#if defined(PCLCK_AUTO_DETECT)
MV_U32 idx;
MV_CPU_ARM_CLK cpuDdrL2Tbl[] = MV_CPU_DDR_L2_CLCK_TBL;
MV_CPU_ARM_CLK cpuDdrTbl6601[] = MV6601_CPU_DDR_CLCK_TBL;
MV_U32 boardId = mvBoardIdGet();
idx = mvCpuClockEntryGet();
if (idx == 0xFFFFFFFF)
return 0;
else {
if (boardId == RD_88F6601_MC_ID || boardId == RD_88F6601_MC2L_ID ||
boardId == DB_88F6601_BP_ID ||
(GFLT300_ID == boardId) || (GFLT200_ID == boardId) || (GFLT110_ID == boardId))
return cpuDdrTbl6601[idx].cpuClk;
else
return cpuDdrL2Tbl[idx].cpuClk;
}
#else
return MV_DEFAULT_PCLK
#endif
}
/*******************************************************************************
* mvCpuL2ClkGet - Get the CPU L2 (CPU bus clock)
*
* DESCRIPTION:
* This routine extract the CPU L2 clock.
*
* RETURN:
* 32bit clock cycles in Hertz.
*
*******************************************************************************/
MV_U32 mvCpuL2ClkGet(MV_VOID)
{
#ifdef L2CLK_AUTO_DETECT
MV_U32 idx;
MV_CPU_ARM_CLK cpuDdrL2Tbl[] = MV_CPU_DDR_L2_CLCK_TBL;
MV_CPU_ARM_CLK cpuDdrTbl6601[] = MV6601_CPU_DDR_CLCK_TBL;
MV_U32 boardId = mvBoardIdGet();
idx = mvCpuClockEntryGet();
if (idx == 0xFFFFFFFF)
return 0;
else {
if (boardId == RD_88F6601_MC_ID || boardId == RD_88F6601_MC2L_ID ||
boardId == RD_88F6601_MC_ID ||
(GFLT300_ID == boardId) || (GFLT200_ID == boardId) || (GFLT110_ID == boardId))
return cpuDdrTbl6601[idx].l2Clk;
else
return cpuDdrL2Tbl[idx].l2Clk;
}
#else
return MV_BOARD_DEFAULT_L2CLK;
#endif
}
/*******************************************************************************
* mvCpuL2Exists
*
* DESCRIPTION:
* This routine checks if L2 exists according to reset strap.
*
* RETURN:
* MV_TRUE if L2 exists,
* MV_FALSE otherwise.
*
*******************************************************************************/
MV_BOOL mvCpuL2Exists(MV_VOID)
{
MV_U32 sar0;
MV_U32 id = mvBoardIdGet();
if (id == RD_88F6510_SFU_ID || id == DB_88F6601_BP_ID ||
id == RD_88F6601_MC_ID || id == RD_88F6601_MC2L_ID ||
GFLT300_ID == id || GFLT200_ID == id || id == GFLT110_ID)
return MV_FALSE;
/* Read S@R register value */
sar0 = MV_REG_READ(MPP_SAMPLE_AT_RESET(0));
if (sar0 & MSAR_L2EXIST_MASK)
return MV_TRUE;
else
return MV_FALSE;
}
/*******************************************************************************
* mvCpuNameGet - Get CPU name
*
* DESCRIPTION:
* This function returns a string describing the CPU model and revision.
*
* INPUT:
* None.
*
* OUTPUT:
* pNameBuff - Buffer to contain board name string. Minimum size 32 chars.
*
* RETURN:
* None.
*******************************************************************************/
MV_VOID mvCpuNameGet(char *pNameBuff)
{
MV_U32 cpuModel;
cpuModel = mvOsCpuPartGet();
/* The CPU module is indicated in the Processor Version Register (PVR) */
switch (cpuModel) {
case CPU_PART_MRVL131:
mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell Feroceon", mvOsCpuRevGet());
break;
case CPU_PART_ARM926:
mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM926", mvOsCpuRevGet());
break;
case CPU_PART_ARM946:
mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM946", mvOsCpuRevGet());
break;
default:
mvOsSPrintf(pNameBuff, "??? (0x%04x) (Rev %d)", cpuModel, mvOsCpuRevGet());
break;
} /* switch */
return;
}
#define MV_PROC_STR_SIZE 50
static void mvCpuIfGetL2EccMode(MV_8 *buf)
{
MV_U32 regVal = MV_REG_READ(CPU_L2_CONFIG_REG);
if (regVal & BIT2)
mvOsSPrintf(buf, "L2 ECC Enabled");
else
mvOsSPrintf(buf, "L2 ECC Disabled");
}
static void mvCpuIfGetL2Mode(MV_8 *buf)
{
MV_U32 regVal = 0;
__asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
if (regVal & BIT22)
mvOsSPrintf(buf, "L2 Enabled");
else
mvOsSPrintf(buf, "L2 Disabled");
}
static void mvCpuIfGetL2PrefetchMode(MV_8 *buf)
{
MV_U32 regVal = 0;
__asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
if (regVal & BIT24)
mvOsSPrintf(buf, "L2 Prefetch Disabled");
else
mvOsSPrintf(buf, "L2 Prefetch Enabled");
}
static void mvCpuIfGetWriteAllocMode(MV_8 *buf)
{
MV_U32 regVal = 0;
__asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
if (regVal & BIT28)
mvOsSPrintf(buf, "Write Allocate Enabled");
else
mvOsSPrintf(buf, "Write Allocate Disabled");
}
static void mvCpuIfGetCpuStreamMode(MV_8 *buf)
{
MV_U32 regVal = 0;
__asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
if (regVal & BIT29)
mvOsSPrintf(buf, "CPU Streaming Enabled");
else
mvOsSPrintf(buf, "CPU Streaming Disabled");
}
static void mvCpuIfPrintCpuRegs(void)
{
MV_U32 regVal = 0;
__asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
mvOsPrintf("Extra Feature Reg = 0x%x\n", regVal);
__asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Control register */
mvOsPrintf("Control Reg = 0x%x\n", regVal);
__asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal)); /* Read ID Code register */
mvOsPrintf("ID Code Reg = 0x%x\n", regVal);
__asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal)); /* Read Cache Type register */
mvOsPrintf("Cache Type Reg = 0x%x\n", regVal);
}
MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index)
{
MV_U32 count = 0;
MV_8 L2_ECC_str[MV_PROC_STR_SIZE];
MV_8 L2_En_str[MV_PROC_STR_SIZE];
MV_8 L2_Prefetch_str[MV_PROC_STR_SIZE];
MV_8 Write_Alloc_str[MV_PROC_STR_SIZE];
MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE];
if (mvCtrlModelGet() != MV_6601_DEV_ID) {
mvCpuIfGetL2Mode(L2_En_str);
mvCpuIfGetL2EccMode(L2_ECC_str);
mvCpuIfGetL2PrefetchMode(L2_Prefetch_str);
}
mvCpuIfGetWriteAllocMode(Write_Alloc_str);
mvCpuIfGetCpuStreamMode(Cpu_Stream_str);
mvCpuIfPrintCpuRegs();
if (mvCtrlModelGet() != MV_6601_DEV_ID) {
count += mvOsSPrintf(buffer + count + index, "%s\n", L2_En_str);
count += mvOsSPrintf(buffer + count + index, "%s\n", L2_ECC_str);
count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Prefetch_str);
}
count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str);
count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str);
count += mvOsSPrintf(buffer + count + index, "CPU Config Reg = 0x%08x\n", MV_REG_READ(CPU_CONFIG_REG));
if (mvCtrlModelGet() != MV_6601_DEV_ID)
count += mvOsSPrintf(buffer + count + index, "L2 Config Reg = 0x%08x\n", MV_REG_READ(CPU_L2_CONFIG_REG));
return count;
}
MV_U32 whoAmI(MV_VOID)
{
return 0;
}