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| *******************************************************************************/ |
| #ifndef __mvFeroceonCntrs_h__ |
| #define __mvFeroceonCntrs_h__ |
| |
| #include "mvTypes.h" |
| #include "mvOs.h" |
| |
| #define MV_FEROCEON_CNTRS_NUM 4 |
| #define MV_FEROCEON_CNTRS_OPS_NUM 32 |
| |
| #define MV_CPU_CNTR_SIZE 64 /* bits */ |
| |
| |
| /* internal */ |
| static INLINE int mvCpuCntrsStart(int counter, int op) |
| { |
| MV_U32 reg = (1 << op) | 0x1; /*enable */ |
| |
| switch (counter) { |
| case 0: |
| __asm__ __volatile__("mcr p15, 0, %0, c15, c12, 0" : : "r"(reg)); |
| return 0; |
| |
| case 1: |
| __asm__ __volatile__("mcr p15, 0, %0, c15, c12, 1" : : "r"(reg)); |
| return 0; |
| |
| case 2: |
| __asm__ __volatile__("mcr p15, 0, %0, c15, c12, 2" : : "r"(reg)); |
| return 0; |
| |
| case 3: |
| __asm__ __volatile__("mcr p15, 0, %0, c15, c12, 3" : : "r"(reg)); |
| return 0; |
| |
| default: |
| mvOsPrintf("error in program_counter: bad counter number (%d)\n", counter); |
| } |
| return 1; |
| } |
| |
| static INLINE void mvCpuCntrsStop(const int counter) |
| { |
| MV_U32 ll = 0; |
| |
| switch (counter) { |
| case 0: |
| MV_ASM("mcr p15, 0, %0, c15, c12, 0" : : "r"(ll)); |
| break; |
| |
| case 1: |
| MV_ASM("mcr p15, 0, %0, c15, c12, 1" : : "r"(ll)); |
| break; |
| |
| case 2: |
| MV_ASM("mcr p15, 0, %0, c15, c12, 2" : : "r"(ll)); |
| break; |
| |
| case 3: |
| MV_ASM("mcr p15, 0, %0, c15, c12, 3" : : "r"(ll)); |
| break; |
| |
| default: |
| mvOsPrintf("mv_cpu_cntrs_read: bad counter number (%d)\n", counter); |
| } |
| } |
| |
| static INLINE MV_U64 mvCpuCntrsRead(const int counter) |
| { |
| MV_U32 low = 0, high = 0; |
| |
| switch (counter) { |
| case 0: |
| MV_ASM("mrc p15, 0, %0, c15, c13, 0" : "=r"(low)); |
| MV_ASM("mrc p15, 0, %0, c15, c13, 1" : "=r"(high)); |
| break; |
| |
| case 1: |
| MV_ASM("mrc p15, 0, %0, c15, c13, 2" : "=r"(low)); |
| MV_ASM("mrc p15, 0, %0, c15, c13, 3" : "=r"(high)); |
| break; |
| |
| case 2: |
| MV_ASM("mrc p15, 0, %0, c15, c13, 4" : "=r"(low)); |
| MV_ASM("mrc p15, 0, %0, c15, c13, 5" : "=r"(high)); |
| break; |
| |
| case 3: |
| MV_ASM("mrc p15, 0, %0, c15, c13, 6" : "=r"(low)); |
| MV_ASM("mrc p15, 0, %0, c15, c13, 7" : "=r"(high)); |
| break; |
| |
| default: |
| mvOsPrintf("mv_cpu_cntrs_read: bad counter number (%d)\n", counter); |
| } |
| return (((MV_U64) high << 32) | low); |
| } |
| |
| static INLINE void mvCpuCntrsReset(void) |
| { |
| MV_U32 reg = 0; |
| |
| MV_ASM("mcr p15, 0, %0, c15, c13, 0" : : "r"(reg)); |
| MV_ASM("mcr p15, 0, %0, c15, c13, 1" : : "r"(reg)); |
| MV_ASM("mcr p15, 0, %0, c15, c13, 2" : : "r"(reg)); |
| MV_ASM("mcr p15, 0, %0, c15, c13, 3" : : "r"(reg)); |
| MV_ASM("mcr p15, 0, %0, c15, c13, 4" : : "r"(reg)); |
| MV_ASM("mcr p15, 0, %0, c15, c13, 5" : : "r"(reg)); |
| MV_ASM("mcr p15, 0, %0, c15, c13, 6" : : "r"(reg)); |
| MV_ASM("mcr p15, 0, %0, c15, c13, 7" : : "r"(reg)); |
| } |
| |
| |
| void mvCpuCntrsInit(void); |
| |
| #endif /* __mvFeroceonCntrs_h__ */ |
| |