feroceon-kw2: lower i2c bus speed to 96 khz.
I2C bus speed is derived from the following:
Fscl = Ftclk / (10 * (M + 1) * 2^(N + 1))
Current settings for M and N were based on 133 MHz Tclk, but yield a 139 KHz
Fscl with our 200 MHz Tclk.
Change-Id: Iabb10f31a209ac4e91d1edacefdea1cd82714a9a
diff --git a/arch/arm/mach-feroceon-kw2/core.c b/arch/arm/mach-feroceon-kw2/core.c
index a5cf6c7..3b1afd1 100755
--- a/arch/arm/mach-feroceon-kw2/core.c
+++ b/arch/arm/mach-feroceon-kw2/core.c
@@ -223,7 +223,7 @@
/* Platform devices list */
static struct mv64xxx_i2c_pdata kw_i2c_pdata = {
- .freq_m = 8, /* assumes 166 MHz TCLK */
+ .freq_m = 12, /* assumes 200 MHz TCLK */
.freq_n = 3,
.timeout = 1000, /* Default timeout of 1 second */
};
