arch/arm/plat-feroceon/mv_hal/neta/pnc/mvPncLb.c

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#include "mvOs.h"
#include "mvCommon.h"

#include "gbe/mvNetaRegs.h"

#include "mvPnc.h"
#include "mvTcam.h"

#ifdef MV_ETH_PNC_LB

void    mvPncLbDump(void)
{
	MV_U32	regVal;
	int i, j, rxq;

	MV_REG_WRITE(MV_PNC_LB_TBL_ACCESS_REG, 0);
	mvOsPrintf("Hash:    rxq    rxq    rxq    rxq\n");
	for (i = 0; i <= MV_PNC_LB_TBL_ADDR_MASK; i++) {
		/* Each read returns 4 hash entries */
		regVal = MV_REG_READ(MV_PNC_LB_TBL_ACCESS_REG);
		/* Extract data */
		regVal = (regVal & MV_PNC_LB_TBL_DATA_MASK) >> MV_PNC_LB_TBL_DATA_OFFS;
		mvOsPrintf("%4d:    ", (i * 4));
		for (j = 0; j < 4; j++) {
			rxq = regVal & 7;
			mvOsPrintf("%3d   ", rxq);
			regVal = regVal >> 3;
		}
		mvOsPrintf("\n");
	}
}

int    mvPncLbRxqSet(int hash, int rxq)
{
	MV_U32 regVal, entry, index;

	entry = (hash / 4) & MV_PNC_LB_TBL_ADDR_MASK;
	index = (hash & 3);

	MV_REG_WRITE(MV_PNC_LB_TBL_ACCESS_REG, entry);
	regVal = MV_REG_READ(MV_PNC_LB_TBL_ACCESS_REG);

	regVal &= ~MV_PNC_LB_TBL_ADDR_MASK;
	regVal |= entry;
	regVal &= ~((7 << (index * 3)) << MV_PNC_LB_TBL_DATA_OFFS);
	regVal |= ((rxq << (index * 3)) << MV_PNC_LB_TBL_DATA_OFFS);
	regVal |= MV_PNC_LB_TBL_WRITE_TRIG_MASK;
	MV_REG_WRITE(MV_PNC_LB_TBL_ACCESS_REG, regVal);

	return 0;
}

int		mvPncLbModeIp4(int mode)
{
	int lb;
	struct tcam_entry te;

	switch (mode) {
	case 0:
		lb = LB_DISABLE_VALUE;
		break;
	case 1:
		lb = LB_2_TUPLE_VALUE;
		break;
	case 2:
	default:
		mvOsPrintf("%s: %d - unexpected mode value\n", __func__, mode);
		return 1;
	}
	tcam_hw_read(&te, TE_IP4_EOF);
	sram_sw_set_load_balance(&te, lb);
	tcam_hw_write(&te, TE_IP4_EOF);

	return 0;
}

int	mvPncLbModeIp6(int mode)
{
	int lb;
	struct tcam_entry te;

	switch (mode) {
	case 0:
		lb = LB_DISABLE_VALUE;
		break;
	case 1:
		lb = LB_2_TUPLE_VALUE;
		break;
	case 2:
	default:
		mvOsPrintf("%s: %d - unexpected mode value\n", __func__, mode);
		return 1;
	}
	tcam_hw_read(&te, TE_IP6_EOF);
	sram_sw_set_load_balance(&te, lb);
	tcam_hw_write(&te, TE_IP6_EOF);

	return 0;
}

int	mvPncLbModeL4(int mode)
{
	int lb;
	struct tcam_entry te;

	switch (mode) {
	case 0:
		lb = LB_DISABLE_VALUE;
		break;
	case 1:
		lb = LB_2_TUPLE_VALUE;
		break;
	case 2:
		lb = LB_4_TUPLE_VALUE;
		break;
	default:
		mvOsPrintf("%s: %d - unexpected mode value\n", __func__, mode);
		return 1;
	}

#ifdef CONFIG_MV_ETH_PNC_L3_FLOW
	mvOsPrintf("%s: Not supported\n", __func__);
	return 1;
#else
	tcam_hw_read(&te, TE_L4_EOF);
	sram_sw_set_load_balance(&te, lb);
	tcam_hw_write(&te, TE_L4_EOF);
	return 0;
#endif /* CONFIG_MV_ETH_PNC_L3_FLOW */
}
#endif /* MV_ETH_PNC_LB */