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#ifndef __INCmvDramIfh
#define __INCmvDramIfh
#include "mvCommon.h"
#include "ctrlEnv/mvCtrlEnvSpec.h"
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* includes */
#include "ctrlEnv/mvCtrlEnvSpec.h"
#include "ddr2/mvDramIfRegs.h"
#include "ddr2/mvDramIfConfig.h"
#include "mvSysDdrConfig.h"
/* defines */
/* DRAM Timing parameters */
#define SDRAM_TWR 15 /* ns tWr */
#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */
#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */
#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */
#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */
#define CAL_AUTO_DETECT 0 /* Do not force CAS latancy (mvDramIfDetect) */
#define ECC_DISABLE 1 /* Force ECC to Disable */
#define ECC_ENABLE 0 /* Force ECC to ENABLE */
/* typedefs */
/* enumeration for memory types */
typedef enum _mvMemoryType {
MEM_TYPE_SDRAM,
MEM_TYPE_DDR1,
MEM_TYPE_DDR2
} MV_MEMORY_TYPE;
/* enumeration for DDR2 supported CAS Latencies */
typedef enum _mvDimmDdr2Cas {
DDR2_CL_3 = 0x08,
DDR2_CL_4 = 0x10,
DDR2_CL_5 = 0x20,
DDR2_CL_6 = 0x40,
DDR2_CL_FAULT
} MV_DIMM_DDR2_CAS;
typedef struct _mvDramBankInfo {
MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */
/* DIMM dimensions */
MV_U32 numOfRowAddr;
MV_U32 numOfColAddr;
MV_U32 dataWidth;
MV_U32 errorCheckType; /* ECC , PARITY.. */
MV_U32 sdramWidth; /* 4,8,16 or 32 */
MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */
MV_U32 burstLengthSupported;
MV_U32 numOfBanksOnEachDevice;
MV_U32 suportedCasLatencies;
MV_U32 refreshInterval;
/* DIMM timing parameters */
MV_U32 minCycleTimeAtMaxCasLatPs;
MV_U32 minCycleTimeAtMaxCasLatMinus1Ps;
MV_U32 minCycleTimeAtMaxCasLatMinus2Ps;
MV_U32 minRowPrechargeTime;
MV_U32 minRowActiveToRowActive;
MV_U32 minRasToCasDelay;
MV_U32 minRasPulseWidth;
MV_U32 minWriteRecoveryTime; /* DDR2 only */
MV_U32 minWriteToReadCmdDelay; /* DDR2 only */
MV_U32 minReadToPrechCmdDelay; /* DDR2 only */
MV_U32 minRefreshToActiveCmd; /* DDR2 only */
/* Parameters calculated from the extracted DIMM information */
MV_U32 size;
MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */
MV_U32 numberOfDevices;
/* DIMM attributes (MV_TRUE for yes) */
MV_BOOL registeredAddrAndControlInputs;
MV_BOOL registeredDQMBinputs;
} MV_DRAM_BANK_INFO;
typedef struct _mvDramIfDecWin {
MV_ADDR_WIN addrWin; /* An address window */
MV_BOOL enable; /* Address decode window is enabled/disabled */
} MV_DRAM_DEC_WIN;
#include "ddr2/spd/mvSpd.h"
/* mvDramIf.h API list */
MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin);
MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin);
MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable);
MV_BOOL mvDramIfIsTypeDdr3(void);
MV_VOID mvDramIfBasicAsmInit(MV_VOID);
MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable, MV_U32 sysClk);
MV_VOID _mvDramIfConfig(int entryNum);
MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum);
MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum);
MV_U32 mvDramIfSizeGet(MV_VOID);
MV_U32 mvDramIfCalGet(void);
MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold);
MV_VOID mvDramIfSelfRefreshSet(void);
void mvDramIfShow(void);
MV_U32 mvDramIfGetFirstCS(void);
MV_U32 mvDramIfGetCSorder(MV_U32 csOrder);
MV_U32 mvDramCsSizeGet(MV_U32 csNum);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __INCmvDramIfh */