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| ******************************************************************************/ |
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| /******************************************************************************/ |
| /** **/ |
| /** MODULE : ONU GPON **/ |
| /** **/ |
| /** FILE : eponOnuIsr.h **/ |
| /** **/ |
| /** DESCRIPTION : This file contains ONU EPON Interrupt implementation **/ |
| /** **/ |
| /****************************************************************************** |
| * * |
| * MODIFICATION HISTORY: * |
| * * |
| * 26Jan10 oren_ben_hayun created * |
| * ========================================================================== * |
| * |
| ******************************************************************************/ |
| #ifndef _ONU_EPON_ISR_H |
| #define _ONU_EPON_ISR_H |
| |
| /* Include Files |
| ------------------------------------------------------------------------------*/ |
| |
| /* Definitions |
| ------------------------------------------------------------------------------*/ |
| #define ONU_EPON_REGISTERED_LLID_0_MASK (0x0001) |
| #define ONU_EPON_REGISTERED_LLID_0_7_MASK (0x0002) |
| #define ONU_EPON_TIMESTAMP_DRIFT_MASK (0x0004) |
| #define ONU_EPON_TIMESTAMP_VALUE_MATCH_MASK (0x0008) |
| #define ONU_EPON_RX_CTRL_QUEUE_MASK (0x0010) |
| #define ONU_EPON_RX_RPRT_QUEUE_MASK (0x0020) |
| #define ONU_EPON_DS_SYNC_OK_PCS_MASK (0x0080) |
| #define ONU_EPON_XVR_SD_MASK (0x0100) |
| #define ONU_EPON_SERDES_SD_MASK (0x0200) |
| |
| #define ONU_EPON_EVENT_SHIFT (16) |
| |
| #ifdef PON_Z1 |
| |
| #define ONU_EPON_INTERRUPTS (ONU_EPON_RX_CTRL_QUEUE_MASK | \ |
| ONU_EPON_XVR_SD_MASK) |
| |
| #else /* PON_Z2 */ |
| |
| #define ONU_EPON_INTERRUPTS (ONU_EPON_RX_CTRL_QUEUE_MASK | \ |
| ONU_EPON_XVR_SD_MASK | \ |
| ONU_EPON_DS_SYNC_OK_PCS_MASK | \ |
| ONU_EPON_REGISTERED_LLID_0_MASK | \ |
| ONU_EPON_TIMESTAMP_VALUE_MATCH_MASK) |
| #endif /* PON_Z2 */ |
| |
| /* Alarms Mask */ |
| #define ONU_EPON_ALARM_MASK (ONU_EPON_SERDES_SD_MASK | \ |
| ONU_EPON_XVR_SD_MASK | \ |
| ONU_EPON_TIMESTAMP_DRIFT_MASK) |
| /* Message Types */ |
| #define ONU_EPON_RX_CTRL_MSG (1) |
| #define ONU_EPON_RX_RPRT_MSG (2) |
| |
| /* DBA Report Timer Types */ |
| #define ONU_EPON_SW_DBA_RPRT_TIMER (0) |
| #define ONU_EPON_HW_DBA_RPRT_TIMER (1) |
| |
| |
| /* Enums |
| ------------------------------------------------------------------------------*/ |
| |
| /* Typedefs |
| ------------------------------------------------------------------------------*/ |
| |
| /* Global variables |
| ------------------------------------------------------------------------------*/ |
| |
| /* Global functions |
| ------------------------------------------------------------------------------*/ |
| void onuEponIsrLowRoutine(MV_U32 *interruptEvent, MV_U32 *interruptStatus); |
| void onuEponIsrRoutine(MV_U32 interruptEvent, MV_U32 interruptStatus); |
| #ifndef PON_FPGA |
| void onuEponDgIsrRoutine(void); |
| #endif /* PON_FPGA */ |
| void onuEponIsrTimerMpcpHndl(unsigned long data); |
| void onuEponIsrTimerMpcpStateSet(MV_BOOL mode); |
| void onuEponIsrTimerMpcpIntervalSet(MV_U32 interval); |
| void onuEponIsrTimerMpcpRandomResetSet(MV_U32 checkThreshold, MV_U32 maskThreshold); |
| void onuEponIsrTimerHwReportHndl(unsigned long data); |
| void onuEponIsrTimerHwReportStateSet(MV_U32 enable, MV_U32 t0_val, MV_U32 t0_time, MV_U32 t1_val, MV_U32 t1_time); |
| void onuEponIsrTimerHoldoverHndl(unsigned long data); |
| void onuEponIsrTimerHoldoverIntervalSet(MV_U32 interval, MV_U32 state); |
| void onuEponDbaSwRprtMacTimerCfg(MV_U32 interval); |
| void onuEponIsrTimerEventMissHndl(unsigned long data); |
| void onuEponIsrTimerEventMissStateSet(MV_BOOL mode); |
| void onuEponIsrXvrResetTimerHndl(unsigned long data); |
| void onuEponIsrXvrResetStateSet(MV_BOOL mode); |
| void onuEponForceTxDownStateSet(MV_U32 txEnable, MV_U32 macId); |
| MV_BOOL onuEponForceTxDownStateGet(MV_U32 macId); |
| |
| /* Macros |
| ------------------------------------------------------------------------------*/ |
| |
| #endif /* _ONU_EPON_ISR_H */ |
| |
| |
| |