Daniel Mentz | 94787a1 | 2013-05-29 21:12:04 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/m32r/platforms/opsput/setup.c |
| 3 | * |
| 4 | * Setup routines for Renesas OPSPUT Board |
| 5 | * |
| 6 | * Copyright (c) 2002-2005 |
| 7 | * Hiroyuki Kondo, Hirokazu Takata, |
| 8 | * Hitoshi Yamamoto, Takeo Takahashi, Mamoru Sakugawa |
| 9 | * |
| 10 | * This file is subject to the terms and conditions of the GNU General |
| 11 | * Public License. See the file "COPYING" in the main directory of this |
| 12 | * archive for more details. |
| 13 | */ |
| 14 | |
| 15 | #include <linux/irq.h> |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/platform_device.h> |
| 19 | |
| 20 | #include <asm/system.h> |
| 21 | #include <asm/m32r.h> |
| 22 | #include <asm/io.h> |
| 23 | |
| 24 | /* |
| 25 | * OPSP Interrupt Control Unit (Level 1) |
| 26 | */ |
| 27 | #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long))) |
| 28 | |
| 29 | icu_data_t icu_data[OPSPUT_NUM_CPU_IRQ]; |
| 30 | |
| 31 | static void disable_opsput_irq(unsigned int irq) |
| 32 | { |
| 33 | unsigned long port, data; |
| 34 | |
| 35 | port = irq2port(irq); |
| 36 | data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7; |
| 37 | outl(data, port); |
| 38 | } |
| 39 | |
| 40 | static void enable_opsput_irq(unsigned int irq) |
| 41 | { |
| 42 | unsigned long port, data; |
| 43 | |
| 44 | port = irq2port(irq); |
| 45 | data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6; |
| 46 | outl(data, port); |
| 47 | } |
| 48 | |
| 49 | static void mask_opsput(struct irq_data *data) |
| 50 | { |
| 51 | disable_opsput_irq(data->irq); |
| 52 | } |
| 53 | |
| 54 | static void unmask_opsput(struct irq_data *data) |
| 55 | { |
| 56 | enable_opsput_irq(data->irq); |
| 57 | } |
| 58 | |
| 59 | static void shutdown_opsput(struct irq_data *data) |
| 60 | { |
| 61 | unsigned long port; |
| 62 | |
| 63 | port = irq2port(data->irq); |
| 64 | outl(M32R_ICUCR_ILEVEL7, port); |
| 65 | } |
| 66 | |
| 67 | static struct irq_chip opsput_irq_type = |
| 68 | { |
| 69 | .name = "OPSPUT-IRQ", |
| 70 | .irq_shutdown = shutdown_opsput, |
| 71 | .irq_mask = mask_opsput, |
| 72 | .irq_unmask = unmask_opsput, |
| 73 | }; |
| 74 | |
| 75 | /* |
| 76 | * Interrupt Control Unit of PLD on OPSPUT (Level 2) |
| 77 | */ |
| 78 | #define irq2pldirq(x) ((x) - OPSPUT_PLD_IRQ_BASE) |
| 79 | #define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \ |
| 80 | (((x) - 1) * sizeof(unsigned short))) |
| 81 | |
| 82 | typedef struct { |
| 83 | unsigned short icucr; /* ICU Control Register */ |
| 84 | } pld_icu_data_t; |
| 85 | |
| 86 | static pld_icu_data_t pld_icu_data[OPSPUT_NUM_PLD_IRQ]; |
| 87 | |
| 88 | static void disable_opsput_pld_irq(unsigned int irq) |
| 89 | { |
| 90 | unsigned long port, data; |
| 91 | unsigned int pldirq; |
| 92 | |
| 93 | pldirq = irq2pldirq(irq); |
| 94 | port = pldirq2port(pldirq); |
| 95 | data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7; |
| 96 | outw(data, port); |
| 97 | } |
| 98 | |
| 99 | static void enable_opsput_pld_irq(unsigned int irq) |
| 100 | { |
| 101 | unsigned long port, data; |
| 102 | unsigned int pldirq; |
| 103 | |
| 104 | pldirq = irq2pldirq(irq); |
| 105 | port = pldirq2port(pldirq); |
| 106 | data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6; |
| 107 | outw(data, port); |
| 108 | } |
| 109 | |
| 110 | static void mask_opsput_pld(struct irq_data *data) |
| 111 | { |
| 112 | disable_opsput_pld_irq(data->irq); |
| 113 | } |
| 114 | |
| 115 | static void unmask_opsput_pld(struct irq_data *data) |
| 116 | { |
| 117 | enable_opsput_pld_irq(data->irq); |
| 118 | enable_opsput_irq(M32R_IRQ_INT1); |
| 119 | } |
| 120 | |
| 121 | static void shutdown_opsput_pld(struct irq_data *data) |
| 122 | { |
| 123 | unsigned long port; |
| 124 | unsigned int pldirq; |
| 125 | |
| 126 | pldirq = irq2pldirq(data->irq); |
| 127 | port = pldirq2port(pldirq); |
| 128 | outw(PLD_ICUCR_ILEVEL7, port); |
| 129 | } |
| 130 | |
| 131 | static struct irq_chip opsput_pld_irq_type = |
| 132 | { |
| 133 | .name = "OPSPUT-PLD-IRQ", |
| 134 | .irq_shutdown = shutdown_opsput_pld, |
| 135 | .irq_mask = mask_opsput_pld, |
| 136 | .irq_unmask = unmask_opsput_pld, |
| 137 | }; |
| 138 | |
| 139 | /* |
| 140 | * Interrupt Control Unit of PLD on OPSPUT-LAN (Level 2) |
| 141 | */ |
| 142 | #define irq2lanpldirq(x) ((x) - OPSPUT_LAN_PLD_IRQ_BASE) |
| 143 | #define lanpldirq2port(x) (unsigned long)((int)OPSPUT_LAN_ICUCR1 + \ |
| 144 | (((x) - 1) * sizeof(unsigned short))) |
| 145 | |
| 146 | static pld_icu_data_t lanpld_icu_data[OPSPUT_NUM_LAN_PLD_IRQ]; |
| 147 | |
| 148 | static void disable_opsput_lanpld_irq(unsigned int irq) |
| 149 | { |
| 150 | unsigned long port, data; |
| 151 | unsigned int pldirq; |
| 152 | |
| 153 | pldirq = irq2lanpldirq(irq); |
| 154 | port = lanpldirq2port(pldirq); |
| 155 | data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7; |
| 156 | outw(data, port); |
| 157 | } |
| 158 | |
| 159 | static void enable_opsput_lanpld_irq(unsigned int irq) |
| 160 | { |
| 161 | unsigned long port, data; |
| 162 | unsigned int pldirq; |
| 163 | |
| 164 | pldirq = irq2lanpldirq(irq); |
| 165 | port = lanpldirq2port(pldirq); |
| 166 | data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6; |
| 167 | outw(data, port); |
| 168 | } |
| 169 | |
| 170 | static void mask_opsput_lanpld(struct irq_data *data) |
| 171 | { |
| 172 | disable_opsput_lanpld_irq(data->irq); |
| 173 | } |
| 174 | |
| 175 | static void unmask_opsput_lanpld(struct irq_data *data) |
| 176 | { |
| 177 | enable_opsput_lanpld_irq(data->irq); |
| 178 | enable_opsput_irq(M32R_IRQ_INT0); |
| 179 | } |
| 180 | |
| 181 | static void shutdown_opsput_lanpld(struct irq_data *data) |
| 182 | { |
| 183 | unsigned long port; |
| 184 | unsigned int pldirq; |
| 185 | |
| 186 | pldirq = irq2lanpldirq(data->irq); |
| 187 | port = lanpldirq2port(pldirq); |
| 188 | outw(PLD_ICUCR_ILEVEL7, port); |
| 189 | } |
| 190 | |
| 191 | static struct irq_chip opsput_lanpld_irq_type = |
| 192 | { |
| 193 | .name = "OPSPUT-PLD-LAN-IRQ", |
| 194 | .irq_shutdown = shutdown_opsput_lanpld, |
| 195 | .irq_mask = mask_opsput_lanpld, |
| 196 | .irq_unmask = unmask_opsput_lanpld, |
| 197 | }; |
| 198 | |
| 199 | /* |
| 200 | * Interrupt Control Unit of PLD on OPSPUT-LCD (Level 2) |
| 201 | */ |
| 202 | #define irq2lcdpldirq(x) ((x) - OPSPUT_LCD_PLD_IRQ_BASE) |
| 203 | #define lcdpldirq2port(x) (unsigned long)((int)OPSPUT_LCD_ICUCR1 + \ |
| 204 | (((x) - 1) * sizeof(unsigned short))) |
| 205 | |
| 206 | static pld_icu_data_t lcdpld_icu_data[OPSPUT_NUM_LCD_PLD_IRQ]; |
| 207 | |
| 208 | static void disable_opsput_lcdpld_irq(unsigned int irq) |
| 209 | { |
| 210 | unsigned long port, data; |
| 211 | unsigned int pldirq; |
| 212 | |
| 213 | pldirq = irq2lcdpldirq(irq); |
| 214 | port = lcdpldirq2port(pldirq); |
| 215 | data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7; |
| 216 | outw(data, port); |
| 217 | } |
| 218 | |
| 219 | static void enable_opsput_lcdpld_irq(unsigned int irq) |
| 220 | { |
| 221 | unsigned long port, data; |
| 222 | unsigned int pldirq; |
| 223 | |
| 224 | pldirq = irq2lcdpldirq(irq); |
| 225 | port = lcdpldirq2port(pldirq); |
| 226 | data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6; |
| 227 | outw(data, port); |
| 228 | } |
| 229 | |
| 230 | static void mask_opsput_lcdpld(struct irq_data *data) |
| 231 | { |
| 232 | disable_opsput_lcdpld_irq(data->irq); |
| 233 | } |
| 234 | |
| 235 | static void unmask_opsput_lcdpld(struct irq_data *data) |
| 236 | { |
| 237 | enable_opsput_lcdpld_irq(data->irq); |
| 238 | enable_opsput_irq(M32R_IRQ_INT2); |
| 239 | } |
| 240 | |
| 241 | static void shutdown_opsput_lcdpld(struct irq_data *data) |
| 242 | { |
| 243 | unsigned long port; |
| 244 | unsigned int pldirq; |
| 245 | |
| 246 | pldirq = irq2lcdpldirq(data->irq); |
| 247 | port = lcdpldirq2port(pldirq); |
| 248 | outw(PLD_ICUCR_ILEVEL7, port); |
| 249 | } |
| 250 | |
| 251 | static struct irq_chip opsput_lcdpld_irq_type = { |
| 252 | .name = "OPSPUT-PLD-LCD-IRQ", |
| 253 | .irq_shutdown = shutdown_opsput_lcdpld, |
| 254 | .irq_mask = mask_opsput_lcdpld, |
| 255 | .irq_unmask = unmask_opsput_lcdpld, |
| 256 | }; |
| 257 | |
| 258 | void __init init_IRQ(void) |
| 259 | { |
| 260 | #if defined(CONFIG_SMC91X) |
| 261 | /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/ |
| 262 | irq_set_chip_and_handler(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type, |
| 263 | handle_level_irq); |
| 264 | lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ |
| 265 | disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN); |
| 266 | #endif /* CONFIG_SMC91X */ |
| 267 | |
| 268 | /* MFT2 : system timer */ |
| 269 | irq_set_chip_and_handler(M32R_IRQ_MFT2, &opsput_irq_type, |
| 270 | handle_level_irq); |
| 271 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
| 272 | disable_opsput_irq(M32R_IRQ_MFT2); |
| 273 | |
| 274 | /* SIO0 : receive */ |
| 275 | irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type, |
| 276 | handle_level_irq); |
| 277 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
| 278 | disable_opsput_irq(M32R_IRQ_SIO0_R); |
| 279 | |
| 280 | /* SIO0 : send */ |
| 281 | irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &opsput_irq_type, |
| 282 | handle_level_irq); |
| 283 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
| 284 | disable_opsput_irq(M32R_IRQ_SIO0_S); |
| 285 | |
| 286 | /* SIO1 : receive */ |
| 287 | irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &opsput_irq_type, |
| 288 | handle_level_irq); |
| 289 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
| 290 | disable_opsput_irq(M32R_IRQ_SIO1_R); |
| 291 | |
| 292 | /* SIO1 : send */ |
| 293 | irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &opsput_irq_type, |
| 294 | handle_level_irq); |
| 295 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
| 296 | disable_opsput_irq(M32R_IRQ_SIO1_S); |
| 297 | |
| 298 | /* DMA1 : */ |
| 299 | irq_set_chip_and_handler(M32R_IRQ_DMA1, &opsput_irq_type, |
| 300 | handle_level_irq); |
| 301 | icu_data[M32R_IRQ_DMA1].icucr = 0; |
| 302 | disable_opsput_irq(M32R_IRQ_DMA1); |
| 303 | |
| 304 | #ifdef CONFIG_SERIAL_M32R_PLDSIO |
| 305 | /* INT#1: SIO0 Receive on PLD */ |
| 306 | irq_set_chip_and_handler(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type, |
| 307 | handle_level_irq); |
| 308 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; |
| 309 | disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV); |
| 310 | |
| 311 | /* INT#1: SIO0 Send on PLD */ |
| 312 | irq_set_chip_and_handler(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type, |
| 313 | handle_level_irq); |
| 314 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; |
| 315 | disable_opsput_pld_irq(PLD_IRQ_SIO0_SND); |
| 316 | #endif /* CONFIG_SERIAL_M32R_PLDSIO */ |
| 317 | |
| 318 | /* INT#1: CFC IREQ on PLD */ |
| 319 | irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &opsput_pld_irq_type, |
| 320 | handle_level_irq); |
| 321 | pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ |
| 322 | disable_opsput_pld_irq(PLD_IRQ_CFIREQ); |
| 323 | |
| 324 | /* INT#1: CFC Insert on PLD */ |
| 325 | irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type, |
| 326 | handle_level_irq); |
| 327 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ |
| 328 | disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT); |
| 329 | |
| 330 | /* INT#1: CFC Eject on PLD */ |
| 331 | irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type, |
| 332 | handle_level_irq); |
| 333 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ |
| 334 | disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT); |
| 335 | |
| 336 | /* |
| 337 | * INT0# is used for LAN, DIO |
| 338 | * We enable it here. |
| 339 | */ |
| 340 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; |
| 341 | enable_opsput_irq(M32R_IRQ_INT0); |
| 342 | |
| 343 | /* |
| 344 | * INT1# is used for UART, MMC, CF Controller in FPGA. |
| 345 | * We enable it here. |
| 346 | */ |
| 347 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; |
| 348 | enable_opsput_irq(M32R_IRQ_INT1); |
| 349 | |
| 350 | #if defined(CONFIG_USB) |
| 351 | outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ |
| 352 | irq_set_chip_and_handler(OPSPUT_LCD_IRQ_USB_INT1, |
| 353 | &opsput_lcdpld_irq_type, handle_level_irq); |
| 354 | lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ |
| 355 | disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1); |
| 356 | #endif |
| 357 | /* |
| 358 | * INT2# is used for BAT, USB, AUDIO |
| 359 | * We enable it here. |
| 360 | */ |
| 361 | icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; |
| 362 | enable_opsput_irq(M32R_IRQ_INT2); |
| 363 | |
| 364 | #if defined(CONFIG_VIDEO_M32R_AR) |
| 365 | /* |
| 366 | * INT3# is used for AR |
| 367 | */ |
| 368 | irq_set_chip_and_handler(M32R_IRQ_INT3, &opsput_irq_type, |
| 369 | handle_level_irq); |
| 370 | icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
| 371 | disable_opsput_irq(M32R_IRQ_INT3); |
| 372 | #endif /* CONFIG_VIDEO_M32R_AR */ |
| 373 | } |
| 374 | |
| 375 | #if defined(CONFIG_SMC91X) |
| 376 | |
| 377 | #define LAN_IOSTART 0x300 |
| 378 | #define LAN_IOEND 0x320 |
| 379 | static struct resource smc91x_resources[] = { |
| 380 | [0] = { |
| 381 | .start = (LAN_IOSTART), |
| 382 | .end = (LAN_IOEND), |
| 383 | .flags = IORESOURCE_MEM, |
| 384 | }, |
| 385 | [1] = { |
| 386 | .start = OPSPUT_LAN_IRQ_LAN, |
| 387 | .end = OPSPUT_LAN_IRQ_LAN, |
| 388 | .flags = IORESOURCE_IRQ, |
| 389 | } |
| 390 | }; |
| 391 | |
| 392 | static struct platform_device smc91x_device = { |
| 393 | .name = "smc91x", |
| 394 | .id = 0, |
| 395 | .num_resources = ARRAY_SIZE(smc91x_resources), |
| 396 | .resource = smc91x_resources, |
| 397 | }; |
| 398 | #endif |
| 399 | |
| 400 | #if defined(CONFIG_FB_S1D13XXX) |
| 401 | |
| 402 | #include <video/s1d13xxxfb.h> |
| 403 | #include <asm/s1d13806.h> |
| 404 | |
| 405 | static struct s1d13xxxfb_pdata s1d13xxxfb_data = { |
| 406 | .initregs = s1d13xxxfb_initregs, |
| 407 | .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs), |
| 408 | .platform_init_video = NULL, |
| 409 | #ifdef CONFIG_PM |
| 410 | .platform_suspend_video = NULL, |
| 411 | .platform_resume_video = NULL, |
| 412 | #endif |
| 413 | }; |
| 414 | |
| 415 | static struct resource s1d13xxxfb_resources[] = { |
| 416 | [0] = { |
| 417 | .start = 0x10600000UL, |
| 418 | .end = 0x1073FFFFUL, |
| 419 | .flags = IORESOURCE_MEM, |
| 420 | }, |
| 421 | [1] = { |
| 422 | .start = 0x10400000UL, |
| 423 | .end = 0x104001FFUL, |
| 424 | .flags = IORESOURCE_MEM, |
| 425 | } |
| 426 | }; |
| 427 | |
| 428 | static struct platform_device s1d13xxxfb_device = { |
| 429 | .name = S1D_DEVICENAME, |
| 430 | .id = 0, |
| 431 | .dev = { |
| 432 | .platform_data = &s1d13xxxfb_data, |
| 433 | }, |
| 434 | .num_resources = ARRAY_SIZE(s1d13xxxfb_resources), |
| 435 | .resource = s1d13xxxfb_resources, |
| 436 | }; |
| 437 | #endif |
| 438 | |
| 439 | static int __init platform_init(void) |
| 440 | { |
| 441 | #if defined(CONFIG_SMC91X) |
| 442 | platform_device_register(&smc91x_device); |
| 443 | #endif |
| 444 | #if defined(CONFIG_FB_S1D13XXX) |
| 445 | platform_device_register(&s1d13xxxfb_device); |
| 446 | #endif |
| 447 | return 0; |
| 448 | } |
| 449 | arch_initcall(platform_init); |