blob: 224e9e2f867453bd85b08b371edf888f961d6e6e [file] [log] [blame]
Daniel Mentz94787a12013-05-29 21:12:04 -07001/*
2 * linux/arch/arm/mach-at91/gpio.c
3 *
4 * Copyright (C) 2005 HP Labs
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/clk.h>
13#include <linux/errno.h>
14#include <linux/gpio.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/debugfs.h>
18#include <linux/seq_file.h>
19#include <linux/kernel.h>
20#include <linux/list.h>
21#include <linux/module.h>
22#include <linux/io.h>
23
24#include <mach/hardware.h>
25#include <mach/at91_pio.h>
26
27#include "generic.h"
28
29struct at91_gpio_chip {
30 struct gpio_chip chip;
31 struct at91_gpio_chip *next; /* Bank sharing same clock */
32 struct at91_gpio_bank *bank; /* Bank definition */
33 void __iomem *regbase; /* Base of register bank */
34};
35
36#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
37
38static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
39static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
40static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
41static int at91_gpiolib_direction_output(struct gpio_chip *chip,
42 unsigned offset, int val);
43static int at91_gpiolib_direction_input(struct gpio_chip *chip,
44 unsigned offset);
45
46#define AT91_GPIO_CHIP(name, base_gpio, nr_gpio) \
47 { \
48 .chip = { \
49 .label = name, \
50 .direction_input = at91_gpiolib_direction_input, \
51 .direction_output = at91_gpiolib_direction_output, \
52 .get = at91_gpiolib_get, \
53 .set = at91_gpiolib_set, \
54 .dbg_show = at91_gpiolib_dbg_show, \
55 .base = base_gpio, \
56 .ngpio = nr_gpio, \
57 }, \
58 }
59
60static struct at91_gpio_chip gpio_chip[] = {
61 AT91_GPIO_CHIP("A", 0x00 + PIN_BASE, 32),
62 AT91_GPIO_CHIP("B", 0x20 + PIN_BASE, 32),
63 AT91_GPIO_CHIP("C", 0x40 + PIN_BASE, 32),
64 AT91_GPIO_CHIP("D", 0x60 + PIN_BASE, 32),
65 AT91_GPIO_CHIP("E", 0x80 + PIN_BASE, 32),
66};
67
68static int gpio_banks;
69
70static inline void __iomem *pin_to_controller(unsigned pin)
71{
72 pin -= PIN_BASE;
73 pin /= 32;
74 if (likely(pin < gpio_banks))
75 return gpio_chip[pin].regbase;
76
77 return NULL;
78}
79
80static inline unsigned pin_to_mask(unsigned pin)
81{
82 pin -= PIN_BASE;
83 return 1 << (pin % 32);
84}
85
86
87/*--------------------------------------------------------------------------*/
88
89/* Not all hardware capabilities are exposed through these calls; they
90 * only encapsulate the most common features and modes. (So if you
91 * want to change signals in groups, do it directly.)
92 *
93 * Bootloaders will usually handle some of the pin multiplexing setup.
94 * The intent is certainly that by the time Linux is fully booted, all
95 * pins should have been fully initialized. These setup calls should
96 * only be used by board setup routines, or possibly in driver probe().
97 *
98 * For bootloaders doing all that setup, these calls could be inlined
99 * as NOPs so Linux won't duplicate any setup code
100 */
101
102
103/*
104 * mux the pin to the "GPIO" peripheral role.
105 */
106int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup)
107{
108 void __iomem *pio = pin_to_controller(pin);
109 unsigned mask = pin_to_mask(pin);
110
111 if (!pio)
112 return -EINVAL;
113 __raw_writel(mask, pio + PIO_IDR);
114 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
115 __raw_writel(mask, pio + PIO_PER);
116 return 0;
117}
118EXPORT_SYMBOL(at91_set_GPIO_periph);
119
120
121/*
122 * mux the pin to the "A" internal peripheral role.
123 */
124int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
125{
126 void __iomem *pio = pin_to_controller(pin);
127 unsigned mask = pin_to_mask(pin);
128
129 if (!pio)
130 return -EINVAL;
131
132 __raw_writel(mask, pio + PIO_IDR);
133 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
134 __raw_writel(mask, pio + PIO_ASR);
135 __raw_writel(mask, pio + PIO_PDR);
136 return 0;
137}
138EXPORT_SYMBOL(at91_set_A_periph);
139
140
141/*
142 * mux the pin to the "B" internal peripheral role.
143 */
144int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
145{
146 void __iomem *pio = pin_to_controller(pin);
147 unsigned mask = pin_to_mask(pin);
148
149 if (!pio)
150 return -EINVAL;
151
152 __raw_writel(mask, pio + PIO_IDR);
153 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
154 __raw_writel(mask, pio + PIO_BSR);
155 __raw_writel(mask, pio + PIO_PDR);
156 return 0;
157}
158EXPORT_SYMBOL(at91_set_B_periph);
159
160
161/*
162 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
163 * configure it for an input.
164 */
165int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
166{
167 void __iomem *pio = pin_to_controller(pin);
168 unsigned mask = pin_to_mask(pin);
169
170 if (!pio)
171 return -EINVAL;
172
173 __raw_writel(mask, pio + PIO_IDR);
174 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
175 __raw_writel(mask, pio + PIO_ODR);
176 __raw_writel(mask, pio + PIO_PER);
177 return 0;
178}
179EXPORT_SYMBOL(at91_set_gpio_input);
180
181
182/*
183 * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
184 * and configure it for an output.
185 */
186int __init_or_module at91_set_gpio_output(unsigned pin, int value)
187{
188 void __iomem *pio = pin_to_controller(pin);
189 unsigned mask = pin_to_mask(pin);
190
191 if (!pio)
192 return -EINVAL;
193
194 __raw_writel(mask, pio + PIO_IDR);
195 __raw_writel(mask, pio + PIO_PUDR);
196 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
197 __raw_writel(mask, pio + PIO_OER);
198 __raw_writel(mask, pio + PIO_PER);
199 return 0;
200}
201EXPORT_SYMBOL(at91_set_gpio_output);
202
203
204/*
205 * enable/disable the glitch filter; mostly used with IRQ handling.
206 */
207int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
208{
209 void __iomem *pio = pin_to_controller(pin);
210 unsigned mask = pin_to_mask(pin);
211
212 if (!pio)
213 return -EINVAL;
214 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
215 return 0;
216}
217EXPORT_SYMBOL(at91_set_deglitch);
218
219/*
220 * enable/disable the multi-driver; This is only valid for output and
221 * allows the output pin to run as an open collector output.
222 */
223int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
224{
225 void __iomem *pio = pin_to_controller(pin);
226 unsigned mask = pin_to_mask(pin);
227
228 if (!pio)
229 return -EINVAL;
230
231 __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
232 return 0;
233}
234EXPORT_SYMBOL(at91_set_multi_drive);
235
236/*
237 * assuming the pin is muxed as a gpio output, set its value.
238 */
239int at91_set_gpio_value(unsigned pin, int value)
240{
241 void __iomem *pio = pin_to_controller(pin);
242 unsigned mask = pin_to_mask(pin);
243
244 if (!pio)
245 return -EINVAL;
246 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
247 return 0;
248}
249EXPORT_SYMBOL(at91_set_gpio_value);
250
251
252/*
253 * read the pin's value (works even if it's not muxed as a gpio).
254 */
255int at91_get_gpio_value(unsigned pin)
256{
257 void __iomem *pio = pin_to_controller(pin);
258 unsigned mask = pin_to_mask(pin);
259 u32 pdsr;
260
261 if (!pio)
262 return -EINVAL;
263 pdsr = __raw_readl(pio + PIO_PDSR);
264 return (pdsr & mask) != 0;
265}
266EXPORT_SYMBOL(at91_get_gpio_value);
267
268/*--------------------------------------------------------------------------*/
269
270#ifdef CONFIG_PM
271
272static u32 wakeups[MAX_GPIO_BANKS];
273static u32 backups[MAX_GPIO_BANKS];
274
275static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
276{
277 unsigned mask = pin_to_mask(d->irq);
278 unsigned bank = (d->irq - PIN_BASE) / 32;
279
280 if (unlikely(bank >= MAX_GPIO_BANKS))
281 return -EINVAL;
282
283 if (state)
284 wakeups[bank] |= mask;
285 else
286 wakeups[bank] &= ~mask;
287
288 irq_set_irq_wake(gpio_chip[bank].bank->id, state);
289
290 return 0;
291}
292
293void at91_gpio_suspend(void)
294{
295 int i;
296
297 for (i = 0; i < gpio_banks; i++) {
298 void __iomem *pio = gpio_chip[i].regbase;
299
300 backups[i] = __raw_readl(pio + PIO_IMR);
301 __raw_writel(backups[i], pio + PIO_IDR);
302 __raw_writel(wakeups[i], pio + PIO_IER);
303
304 if (!wakeups[i])
305 clk_disable(gpio_chip[i].bank->clock);
306 else {
307#ifdef CONFIG_PM_DEBUG
308 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
309#endif
310 }
311 }
312}
313
314void at91_gpio_resume(void)
315{
316 int i;
317
318 for (i = 0; i < gpio_banks; i++) {
319 void __iomem *pio = gpio_chip[i].regbase;
320
321 if (!wakeups[i])
322 clk_enable(gpio_chip[i].bank->clock);
323
324 __raw_writel(wakeups[i], pio + PIO_IDR);
325 __raw_writel(backups[i], pio + PIO_IER);
326 }
327}
328
329#else
330#define gpio_irq_set_wake NULL
331#endif
332
333
334/* Several AIC controller irqs are dispatched through this GPIO handler.
335 * To use any AT91_PIN_* as an externally triggered IRQ, first call
336 * at91_set_gpio_input() then maybe enable its glitch filter.
337 * Then just request_irq() with the pin ID; it works like any ARM IRQ
338 * handler, though it always triggers on rising and falling edges.
339 *
340 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
341 * configuring them with at91_set_a_periph() or at91_set_b_periph().
342 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
343 */
344
345static void gpio_irq_mask(struct irq_data *d)
346{
347 void __iomem *pio = pin_to_controller(d->irq);
348 unsigned mask = pin_to_mask(d->irq);
349
350 if (pio)
351 __raw_writel(mask, pio + PIO_IDR);
352}
353
354static void gpio_irq_unmask(struct irq_data *d)
355{
356 void __iomem *pio = pin_to_controller(d->irq);
357 unsigned mask = pin_to_mask(d->irq);
358
359 if (pio)
360 __raw_writel(mask, pio + PIO_IER);
361}
362
363static int gpio_irq_type(struct irq_data *d, unsigned type)
364{
365 switch (type) {
366 case IRQ_TYPE_NONE:
367 case IRQ_TYPE_EDGE_BOTH:
368 return 0;
369 default:
370 return -EINVAL;
371 }
372}
373
374static struct irq_chip gpio_irqchip = {
375 .name = "GPIO",
376 .irq_disable = gpio_irq_mask,
377 .irq_mask = gpio_irq_mask,
378 .irq_unmask = gpio_irq_unmask,
379 .irq_set_type = gpio_irq_type,
380 .irq_set_wake = gpio_irq_set_wake,
381};
382
383static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
384{
385 unsigned pin;
386 struct irq_data *idata = irq_desc_get_irq_data(desc);
387 struct irq_chip *chip = irq_data_get_irq_chip(idata);
388 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
389 void __iomem *pio = at91_gpio->regbase;
390 u32 isr;
391
392 /* temporarily mask (level sensitive) parent IRQ */
393 chip->irq_ack(idata);
394 for (;;) {
395 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
396 * When there none are pending, we're finished unless we need
397 * to process multiple banks (like ID_PIOCDE on sam9263).
398 */
399 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
400 if (!isr) {
401 if (!at91_gpio->next)
402 break;
403 at91_gpio = at91_gpio->next;
404 pio = at91_gpio->regbase;
405 continue;
406 }
407
408 pin = at91_gpio->chip.base;
409
410 while (isr) {
411 if (isr & 1)
412 generic_handle_irq(pin);
413 pin++;
414 isr >>= 1;
415 }
416 }
417 chip->irq_unmask(idata);
418 /* now it may re-trigger */
419}
420
421/*--------------------------------------------------------------------------*/
422
423#ifdef CONFIG_DEBUG_FS
424
425static int at91_gpio_show(struct seq_file *s, void *unused)
426{
427 int bank, j;
428
429 /* print heading */
430 seq_printf(s, "Pin\t");
431 for (bank = 0; bank < gpio_banks; bank++) {
432 seq_printf(s, "PIO%c\t", 'A' + bank);
433 };
434 seq_printf(s, "\n\n");
435
436 /* print pin status */
437 for (j = 0; j < 32; j++) {
438 seq_printf(s, "%i:\t", j);
439
440 for (bank = 0; bank < gpio_banks; bank++) {
441 unsigned pin = PIN_BASE + (32 * bank) + j;
442 void __iomem *pio = pin_to_controller(pin);
443 unsigned mask = pin_to_mask(pin);
444
445 if (__raw_readl(pio + PIO_PSR) & mask)
446 seq_printf(s, "GPIO:%s", __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
447 else
448 seq_printf(s, "%s", __raw_readl(pio + PIO_ABSR) & mask ? "B" : "A");
449
450 seq_printf(s, "\t");
451 }
452
453 seq_printf(s, "\n");
454 }
455
456 return 0;
457}
458
459static int at91_gpio_open(struct inode *inode, struct file *file)
460{
461 return single_open(file, at91_gpio_show, NULL);
462}
463
464static const struct file_operations at91_gpio_operations = {
465 .open = at91_gpio_open,
466 .read = seq_read,
467 .llseek = seq_lseek,
468 .release = single_release,
469};
470
471static int __init at91_gpio_debugfs_init(void)
472{
473 /* /sys/kernel/debug/at91_gpio */
474 (void) debugfs_create_file("at91_gpio", S_IFREG | S_IRUGO, NULL, NULL, &at91_gpio_operations);
475 return 0;
476}
477postcore_initcall(at91_gpio_debugfs_init);
478
479#endif
480
481/*--------------------------------------------------------------------------*/
482
483/*
484 * This lock class tells lockdep that GPIO irqs are in a different
485 * category than their parents, so it won't report false recursion.
486 */
487static struct lock_class_key gpio_lock_class;
488
489/*
490 * Called from the processor-specific init to enable GPIO interrupt support.
491 */
492void __init at91_gpio_irq_setup(void)
493{
494 unsigned pioc, pin;
495 struct at91_gpio_chip *this, *prev;
496
497 for (pioc = 0, pin = PIN_BASE, this = gpio_chip, prev = NULL;
498 pioc++ < gpio_banks;
499 prev = this, this++) {
500 unsigned id = this->bank->id;
501 unsigned i;
502
503 __raw_writel(~0, this->regbase + PIO_IDR);
504
505 for (i = 0, pin = this->chip.base; i < 32; i++, pin++) {
506 irq_set_lockdep_class(pin, &gpio_lock_class);
507
508 /*
509 * Can use the "simple" and not "edge" handler since it's
510 * shorter, and the AIC handles interrupts sanely.
511 */
512 irq_set_chip_and_handler(pin, &gpio_irqchip,
513 handle_simple_irq);
514 set_irq_flags(pin, IRQF_VALID);
515 }
516
517 /* The toplevel handler handles one bank of GPIOs, except
518 * AT91SAM9263_ID_PIOCDE handles three... PIOC is first in
519 * the list, so we only set up that handler.
520 */
521 if (prev && prev->next == this)
522 continue;
523
524 irq_set_chip_data(id, this);
525 irq_set_chained_handler(id, gpio_irq_handler);
526 }
527 pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
528}
529
530/* gpiolib support */
531static int at91_gpiolib_direction_input(struct gpio_chip *chip,
532 unsigned offset)
533{
534 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
535 void __iomem *pio = at91_gpio->regbase;
536 unsigned mask = 1 << offset;
537
538 __raw_writel(mask, pio + PIO_ODR);
539 return 0;
540}
541
542static int at91_gpiolib_direction_output(struct gpio_chip *chip,
543 unsigned offset, int val)
544{
545 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
546 void __iomem *pio = at91_gpio->regbase;
547 unsigned mask = 1 << offset;
548
549 __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
550 __raw_writel(mask, pio + PIO_OER);
551 return 0;
552}
553
554static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset)
555{
556 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
557 void __iomem *pio = at91_gpio->regbase;
558 unsigned mask = 1 << offset;
559 u32 pdsr;
560
561 pdsr = __raw_readl(pio + PIO_PDSR);
562 return (pdsr & mask) != 0;
563}
564
565static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
566{
567 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
568 void __iomem *pio = at91_gpio->regbase;
569 unsigned mask = 1 << offset;
570
571 __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
572}
573
574static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
575{
576 int i;
577
578 for (i = 0; i < chip->ngpio; i++) {
579 unsigned pin = chip->base + i;
580 void __iomem *pio = pin_to_controller(pin);
581 unsigned mask = pin_to_mask(pin);
582 const char *gpio_label;
583
584 gpio_label = gpiochip_is_requested(chip, i);
585 if (gpio_label) {
586 seq_printf(s, "[%s] GPIO%s%d: ",
587 gpio_label, chip->label, i);
588 if (__raw_readl(pio + PIO_PSR) & mask)
589 seq_printf(s, "[gpio] %s\n",
590 at91_get_gpio_value(pin) ?
591 "set" : "clear");
592 else
593 seq_printf(s, "[periph %s]\n",
594 __raw_readl(pio + PIO_ABSR) &
595 mask ? "B" : "A");
596 }
597 }
598}
599
600/*
601 * Called from the processor-specific init to enable GPIO pin support.
602 */
603void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
604{
605 unsigned i;
606 struct at91_gpio_chip *at91_gpio, *last = NULL;
607
608 BUG_ON(nr_banks > MAX_GPIO_BANKS);
609
610 gpio_banks = nr_banks;
611
612 for (i = 0; i < nr_banks; i++) {
613 at91_gpio = &gpio_chip[i];
614
615 at91_gpio->bank = &data[i];
616 at91_gpio->chip.base = PIN_BASE + i * 32;
617 at91_gpio->regbase = at91_gpio->bank->offset +
618 (void __iomem *)AT91_VA_BASE_SYS;
619
620 /* enable PIO controller's clock */
621 clk_enable(at91_gpio->bank->clock);
622
623 /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
624 if (last && last->bank->id == at91_gpio->bank->id)
625 last->next = at91_gpio;
626 last = at91_gpio;
627
628 gpiochip_add(&at91_gpio->chip);
629 }
630}