Hard code FIFO depth of SPI controller to 32
The DesignWare SPI controller DW_apb_ssi can by synthesized with
different FIFO depths. Ideally, the driver would auto-detect the FIFO
depth. A less ideal approach is to specify the FIFO depth in the board
file as platform_data. The worst approach is to hard code the value in
the driver code.
The high speed and low speed SPI controllers have 32-word and 8-word
deep FIFOs, respectively. This change breaks compatibility with the low
speed SPI controller which we disabled in a previous commit.
Change-Id: I764e29fee25fc2f172dc0c08805513eea81986c2
diff --git a/include/linux/spi/designware.h b/include/linux/spi/designware.h
index cc0335b..3e25ebd 100644
--- a/include/linux/spi/designware.h
+++ b/include/linux/spi/designware.h
@@ -3,8 +3,8 @@
*/
#define CLK_NAME 10
-#define TX_FIFO_DEPTH 8
-#define RX_FIFO_DEPTH 8
+#define TX_FIFO_DEPTH 32
+#define RX_FIFO_DEPTH 32
struct spi_controller_pdata {
int use_dma;
