Avoid PLL[0-3] definition conflicts.
PLL0 - PLL3 are popular #defines in drivers.
We have had conflicting definitions in a DVB driver
and in ath9k, and will likely have more in the
future. Make the platform #define more distinctive.
Change-Id: I8f5ee24dcf3ff72b790ed01927225aaf6cd0dfa4
diff --git a/arch/arm/mach-comcerto/clock.c b/arch/arm/mach-comcerto/clock.c
index 7ef79a9..2395325 100644
--- a/arch/arm/mach-comcerto/clock.c
+++ b/arch/arm/mach-comcerto/clock.c
@@ -348,12 +348,12 @@
unsigned long ref_clk = HAL_get_ref_clk();
unsigned long pll_div = 0;
- if (pll_no < PLL3)
+ if (pll_no < C2K_CLK_PLL3)
{
//get NF, NR and OD values
switch (pll_no)
{
- case PLL0:
+ case C2K_CLK_PLL0:
m = readl(PLL0_M_LSB) & 0xff;
m |= (readl(PLL0_M_MSB) & 0x3) << 8;
p = readl(PLL0_P) & 0x3f;
@@ -362,7 +362,7 @@
pll_div = readl(PLL0_DIV_CNTRL);
break;
- case PLL1:
+ case C2K_CLK_PLL1:
m = readl(PLL1_M_LSB) & 0xff;
m |= (readl(PLL1_M_MSB) & 0x3) << 8;
p = readl(PLL1_P) & 0x3f;
@@ -371,7 +371,7 @@
pll_div = readl(PLL1_DIV_CNTRL);
break;
- case PLL2:
+ case C2K_CLK_PLL2:
m = readl(PLL2_M_LSB) & 0xff;
m |= (readl(PLL2_M_MSB) & 0x3) << 8;
p = readl(PLL2_P) & 0x3f;
@@ -397,7 +397,7 @@
pll_clk = pll_clk/pll_div;
}
- else if (pll_no == PLL3)
+ else if (pll_no == C2K_CLK_PLL3)
{
m = readl(PLL3_M_LSB) & 0xff;
m |= (readl(PLL3_M_MSB) & 0x3) << 8;
@@ -467,16 +467,16 @@
switch(pll_src)
{
- case PLL0:
+ case C2K_CLK_PLL0:
writel(readl(ctrl_reg) | (1 << 0) , ctrl_reg);
break;
- case PLL1:
+ case C2K_CLK_PLL1:
writel(readl(ctrl_reg) | (1 << 1) , ctrl_reg);
break;
- case PLL3:
+ case C2K_CLK_PLL3:
writel(readl(ctrl_reg) | (1 << 3), ctrl_reg);
break;
- case PLL2:
+ case C2K_CLK_PLL2:
default:
writel(readl(ctrl_reg) | (1 << 2), ctrl_reg);
break;
@@ -941,10 +941,10 @@
spin_lock_init(&clock_lock);
/* Determine the barebox configured pll0,pll1,pll2,pll3 rate value */
- clk_pll0.rate = HAL_get_pll_freq(PLL0);
- clk_pll1.rate = HAL_get_pll_freq(PLL1);
- clk_pll2.rate = HAL_get_pll_freq(PLL2);
- clk_pll3.rate = HAL_get_pll_freq(PLL3);
+ clk_pll0.rate = HAL_get_pll_freq(C2K_CLK_PLL0);
+ clk_pll1.rate = HAL_get_pll_freq(C2K_CLK_PLL1);
+ clk_pll2.rate = HAL_get_pll_freq(C2K_CLK_PLL2);
+ clk_pll3.rate = HAL_get_pll_freq(C2K_CLK_PLL3);
/* Set the NTG ref clock to PLL src (gemtx PLL source)
* Currently it is not set from barebox,set here.
@@ -965,13 +965,13 @@
pll_no = HAL_get_clock_pll_source(clk->clkgen_reg);
switch (pll_no)
{
- case PLL0:
+ case C2K_CLK_PLL0:
clk_set_parent(clk,&clk_pll0);
break;
- case PLL1:
+ case C2K_CLK_PLL1:
clk_set_parent(clk,&clk_pll1);
break;
- case PLL2:
+ case C2K_CLK_PLL2:
clk_set_parent(clk,&clk_pll2);
break;
default:
diff --git a/arch/arm/mach-comcerto/include/mach/comcerto-2000/clk-rst.h b/arch/arm/mach-comcerto/include/mach/comcerto-2000/clk-rst.h
index 631ea98..3cfeaff 100644
--- a/arch/arm/mach-comcerto/include/mach/comcerto-2000/clk-rst.h
+++ b/arch/arm/mach-comcerto/include/mach/comcerto-2000/clk-rst.h
@@ -143,10 +143,10 @@
#define PLL3_MFR APB_VADDR(COMCERTO_APB_CLK_BASE + 0x248)
#define PLL3_MRR APB_VADDR(COMCERTO_APB_CLK_BASE + 0x24C)
-#define PLL0 0
-#define PLL1 1
-#define PLL2 2
-#define PLL3 3
+#define C2K_CLK_PLL0 0
+#define C2K_CLK_PLL1 1
+#define C2K_CLK_PLL2 2
+#define C2K_CLK_PLL3 3
/* Device Reset Control Register (DEVICE_RST_CNTRL)*/
