Merge "Enable common interface."
diff --git a/arch/arm/mach-comcerto/board-optimus.c b/arch/arm/mach-comcerto/board-optimus.c
index 7697b80..ab72392 100644
--- a/arch/arm/mach-comcerto/board-optimus.c
+++ b/arch/arm/mach-comcerto/board-optimus.c
@@ -580,6 +580,29 @@
};
static struct comcerto_pfe_platform_data comcerto_pfe_pdata = {
+#ifdef CONFIG_GOOGLE_SPACECAST
+ .comcerto_eth_pdata[0] = {
+ .name = "wan0",
+ .device_flags = CONFIG_COMCERTO_GEMAC,
+ .mii_config = CONFIG_COMCERTO_USE_RGMII,
+ .gemac_mode = GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G,
+ .phy_flags = GEMAC_NO_PHY,
+ .gem_id = 0,
+ .mac_addr = (u8[])GEM0_MAC,
+ },
+
+ .comcerto_eth_pdata[1] = {
+ .name = "lan0",
+ .device_flags = CONFIG_COMCERTO_GEMAC,
+ .mii_config = CONFIG_COMCERTO_USE_RGMII,
+ .gemac_mode = GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G,
+ .phy_flags = GEMAC_PHY_RGMII_ADD_DELAY,
+ .bus_id = 0,
+ .phy_id = 1,
+ .gem_id = 1,
+ .mac_addr = (u8[])GEM1_MAC,
+ },
+#else
.comcerto_eth_pdata[0] = {
.name = "lan0",
.device_flags = CONFIG_COMCERTO_GEMAC,
@@ -601,6 +624,7 @@
.gem_id = 1,
.mac_addr = (u8[])GEM1_MAC,
},
+#endif
.comcerto_eth_pdata[2] = {
.name = "moca0",
@@ -620,7 +644,15 @@
*/
.comcerto_mdio_pdata[0] = {
.enabled = 1,
+ /* The bitmask .phy_mask specifies the set of PHYs to */
+ /* probe. On Optimus, the kernel controls PHY 4 (WAN */
+ /* port). On SpaceCast, it controls PHY 1 (LAN port). */
+ /* Do not waste time probing other PHYs. */
+#ifdef CONFIG_GOOGLE_SPACECAST
+ .phy_mask = 0xFFFFFFFD,
+#else
.phy_mask = 0xFFFFFFEF,
+#endif
.mdc_div = 96,
.irq = {
[4] = PHY_POLL,
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index d44ff7b..fb798eb 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -52,37 +52,42 @@
phy_write(phydev, AR8x_DEBUG_PORT_DATA, val);
}
-int ar8x_add_skew(struct phy_device *phydev)
+void ar8x_add_skew_tx(struct phy_device *phydev)
{
- int tmp, err;
+ int tmp;
+
+ /* Enable Tx delay */
+ tmp = ar8x_phy_dbg_read(phydev, AR8x_DBG_RGMII_TXCLK_CTRL);
+ tmp |= AR8x_DBG_RGMII_TXCLK_MASK;
+ ar8x_phy_dbg_write(phydev, AR8x_DBG_RGMII_TXCLK_CTRL, tmp);
+}
+
+void ar8x_add_skew_rx(struct phy_device *phydev)
+{
+ int tmp;
/* Enable Rx delay */
tmp = ar8x_phy_dbg_read(phydev, AR8x_DBG_RGMII_RXCLK_CTRL);
tmp |= AR8x_DBG_RGMII_RXCLK_MASK;
ar8x_phy_dbg_write(phydev, AR8x_DBG_RGMII_RXCLK_CTRL, tmp);
- /* Enable Tx delay */
- tmp = ar8x_phy_dbg_read(phydev, AR8x_DBG_RGMII_TXCLK_CTRL);
- tmp |= AR8x_DBG_RGMII_TXCLK_MASK;
- ar8x_phy_dbg_write(phydev, AR8x_DBG_RGMII_TXCLK_CTRL, tmp);
-
- err = genphy_restart_aneg(phydev);
-
- if (err < 0)
- return err;
-
- return 0;
}
-EXPORT_SYMBOL(ar8x_add_skew);
static int ar8x_config_init(struct phy_device *phydev)
{
int err = 0;
- if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
- err = ar8x_add_skew(phydev);
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
+ ar8x_add_skew_rx(phydev);
+ ar8x_add_skew_tx(phydev);
+ }
+ else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
+ ar8x_add_skew_rx(phydev);
+ else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
+ ar8x_add_skew_tx(phydev);
+
+ err = genphy_restart_aneg(phydev);
return err;
-
}