| /* |
| * Copyright (C) 2012-2013 Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation version 2. |
| * |
| * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
| * kind, whether express or implied; without even the implied warranty |
| * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| |
| #include "skeleton.dtsi" |
| |
| / { |
| model = "BCM11351 SoC"; |
| compatible = "brcm,bcm11351"; |
| interrupt-parent = <&gic>; |
| |
| chosen { |
| bootargs = "console=ttyS0,115200n8"; |
| }; |
| |
| gic: interrupt-controller@3ff00100 { |
| compatible = "arm,cortex-a9-gic"; |
| #interrupt-cells = <3>; |
| #address-cells = <0>; |
| interrupt-controller; |
| reg = <0x3ff01000 0x1000>, |
| <0x3ff00100 0x100>; |
| }; |
| |
| smc@0x3404c000 { |
| compatible = "brcm,bcm11351-smc", "brcm,kona-smc"; |
| reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */ |
| }; |
| |
| uart@3e000000 { |
| compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; |
| status = "disabled"; |
| reg = <0x3e000000 0x1000>; |
| clocks = <&uartb_clk>; |
| interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| }; |
| |
| uart@3e001000 { |
| compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; |
| status = "disabled"; |
| reg = <0x3e001000 0x1000>; |
| clocks = <&uartb2_clk>; |
| interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| }; |
| |
| uart@3e002000 { |
| compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; |
| status = "disabled"; |
| reg = <0x3e002000 0x1000>; |
| clocks = <&uartb3_clk>; |
| interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| }; |
| |
| uart@3e003000 { |
| compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; |
| status = "disabled"; |
| reg = <0x3e003000 0x1000>; |
| clocks = <&uartb4_clk>; |
| interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| }; |
| |
| L2: l2-cache { |
| compatible = "brcm,bcm11351-a2-pl310-cache"; |
| reg = <0x3ff20000 0x1000>; |
| cache-unified; |
| cache-level = <2>; |
| }; |
| |
| watchdog@35002f40 { |
| compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt"; |
| reg = <0x35002f40 0x6c>; |
| }; |
| |
| timer@35006000 { |
| compatible = "brcm,kona-timer"; |
| reg = <0x35006000 0x1000>; |
| interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&hub_timer_clk>; |
| }; |
| |
| gpio: gpio@35003000 { |
| compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio"; |
| reg = <0x35003000 0x800>; |
| interrupts = |
| <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| #interrupt-cells = <2>; |
| gpio-controller; |
| interrupt-controller; |
| }; |
| |
| sdio1: sdio@3f180000 { |
| compatible = "brcm,kona-sdhci"; |
| reg = <0x3f180000 0x10000>; |
| interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&sdio1_clk>; |
| status = "disabled"; |
| }; |
| |
| sdio2: sdio@3f190000 { |
| compatible = "brcm,kona-sdhci"; |
| reg = <0x3f190000 0x10000>; |
| interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&sdio2_clk>; |
| status = "disabled"; |
| }; |
| |
| sdio3: sdio@3f1a0000 { |
| compatible = "brcm,kona-sdhci"; |
| reg = <0x3f1a0000 0x10000>; |
| interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&sdio3_clk>; |
| status = "disabled"; |
| }; |
| |
| sdio4: sdio@3f1b0000 { |
| compatible = "brcm,kona-sdhci"; |
| reg = <0x3f1b0000 0x10000>; |
| interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&sdio4_clk>; |
| status = "disabled"; |
| }; |
| |
| pinctrl@35004800 { |
| compatible = "brcm,bcm11351-pinctrl"; |
| reg = <0x35004800 0x430>; |
| }; |
| |
| i2c@3e016000 { |
| compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; |
| reg = <0x3e016000 0x80>; |
| interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&bsc1_clk>; |
| status = "disabled"; |
| }; |
| |
| i2c@3e017000 { |
| compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; |
| reg = <0x3e017000 0x80>; |
| interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&bsc2_clk>; |
| status = "disabled"; |
| }; |
| |
| i2c@3e018000 { |
| compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; |
| reg = <0x3e018000 0x80>; |
| interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&bsc3_clk>; |
| status = "disabled"; |
| }; |
| |
| i2c@3500d000 { |
| compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; |
| reg = <0x3500d000 0x80>; |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&pmu_bsc_clk>; |
| status = "disabled"; |
| }; |
| |
| clocks { |
| bsc1_clk: bsc1 { |
| compatible = "fixed-clock"; |
| clock-frequency = <13000000>; |
| #clock-cells = <0>; |
| }; |
| |
| bsc2_clk: bsc2 { |
| compatible = "fixed-clock"; |
| clock-frequency = <13000000>; |
| #clock-cells = <0>; |
| }; |
| |
| bsc3_clk: bsc3 { |
| compatible = "fixed-clock"; |
| clock-frequency = <13000000>; |
| #clock-cells = <0>; |
| }; |
| |
| pmu_bsc_clk: pmu_bsc { |
| compatible = "fixed-clock"; |
| clock-frequency = <13000000>; |
| #clock-cells = <0>; |
| }; |
| |
| hub_timer_clk: hub_timer { |
| compatible = "fixed-clock"; |
| clock-frequency = <32768>; |
| #clock-cells = <0>; |
| }; |
| |
| pwm_clk: pwm { |
| compatible = "fixed-clock"; |
| clock-frequency = <26000000>; |
| #clock-cells = <0>; |
| }; |
| |
| sdio1_clk: sdio1 { |
| compatible = "fixed-clock"; |
| clock-frequency = <48000000>; |
| #clock-cells = <0>; |
| }; |
| |
| sdio2_clk: sdio2 { |
| compatible = "fixed-clock"; |
| clock-frequency = <48000000>; |
| #clock-cells = <0>; |
| }; |
| |
| sdio3_clk: sdio3 { |
| compatible = "fixed-clock"; |
| clock-frequency = <48000000>; |
| #clock-cells = <0>; |
| }; |
| |
| sdio4_clk: sdio4 { |
| compatible = "fixed-clock"; |
| clock-frequency = <48000000>; |
| #clock-cells = <0>; |
| }; |
| |
| tmon_1m_clk: tmon_1m { |
| compatible = "fixed-clock"; |
| clock-frequency = <1000000>; |
| #clock-cells = <0>; |
| }; |
| |
| uartb_clk: uartb { |
| compatible = "fixed-clock"; |
| clock-frequency = <13000000>; |
| #clock-cells = <0>; |
| }; |
| |
| uartb2_clk: uartb2 { |
| compatible = "fixed-clock"; |
| clock-frequency = <13000000>; |
| #clock-cells = <0>; |
| }; |
| |
| uartb3_clk: uartb3 { |
| compatible = "fixed-clock"; |
| clock-frequency = <13000000>; |
| #clock-cells = <0>; |
| }; |
| |
| uartb4_clk: uartb4 { |
| compatible = "fixed-clock"; |
| clock-frequency = <13000000>; |
| #clock-cells = <0>; |
| }; |
| |
| usb_otg_ahb_clk: usb_otg_ahb { |
| compatible = "fixed-clock"; |
| clock-frequency = <52000000>; |
| #clock-cells = <0>; |
| }; |
| }; |
| |
| usbotg: usb@3f120000 { |
| compatible = "snps,dwc2"; |
| reg = <0x3f120000 0x10000>; |
| interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&usb_otg_ahb_clk>; |
| clock-names = "otg"; |
| phys = <&usbphy>; |
| phy-names = "usb2-phy"; |
| status = "disabled"; |
| }; |
| |
| usbphy: usb-phy@3f130000 { |
| compatible = "brcm,kona-usb2-phy"; |
| reg = <0x3f130000 0x28>; |
| #phy-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
