| * Renesas CPG DIV6 Clock |
| |
| The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse |
| Generator (CPG). They clock input is divided by a configurable factor from 1 |
| to 64. |
| |
| Required Properties: |
| |
| - compatible: Must be one of the following |
| - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks |
| - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks |
| - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks |
| - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks |
| - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks |
| - "renesas,cpg-div6-clock" for generic DIV6 clocks |
| - reg: Base address and length of the memory resource used by the DIV6 clock |
| - clocks: Reference to the parent clock(s); either one, four, or eight |
| clocks must be specified. For clocks with multiple parents, invalid |
| settings must be specified as "<0>". |
| - #clock-cells: Must be 0 |
| - clock-output-names: The name of the clock as a free-form string |
| |
| |
| Example |
| ------- |
| |
| sdhi2_clk: sdhi2_clk@e615007c { |
| compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| reg = <0 0xe615007c 0 4>; |
| clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| <0>, <&extal2_clk>; |
| #clock-cells = <0>; |
| clock-output-names = "sdhi2ck"; |
| }; |