| /* |
| * Copyright (C) 2009 Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| */ |
| |
| #ifndef _ASM_BRCMSTB_BRCMSTB_H |
| #define _ASM_BRCMSTB_BRCMSTB_H |
| |
| #if !defined(__ASSEMBLY__) |
| |
| #include <linux/types.h> |
| #include <linux/smp.h> |
| #include <linux/device.h> |
| |
| #if defined(CONFIG_MIPS) |
| #include <linux/brcmstb/brcmapi.h> |
| #include <asm/addrspace.h> |
| #include <asm/mipsregs.h> |
| #include <asm/setup.h> |
| #include <irq.h> |
| #include <spaces.h> |
| #endif |
| |
| #endif /* !defined(__ASSEMBLY__) */ |
| |
| #if defined(CONFIG_MIPS) |
| |
| #include <asm/bmips.h> |
| #define BVIRTADDR(x) KSEG1ADDR(BPHYSADDR(x)) |
| |
| #else |
| |
| #define BRCMSTB_PERIPH_VIRT 0xfc000000 |
| #define BRCMSTB_PERIPH_PHYS 0xf0000000 |
| #define BRCMSTB_PERIPH_LENGTH 0x02000000 |
| |
| /* |
| * NOTE: for cable combo chips like 7145, this could wind up looking like: |
| * |
| * x = BCHP_UARTA_REG_START = 0x2040_6c00 (offset) |
| * BCHP_PHYSICAL_OFFSET = 0xd000_0000 (base for UBUS registers) |
| * BPHYSADDR = BCHP_PHYSICAL_OFFSET + x = 0xf040_6c00 |
| * BVIRTADDR = BRCMSTB_PERIPH_VIRT + (x & 0x0fffffff) = 0xfa406c00 |
| */ |
| #define BVIRTADDR(x) (BRCMSTB_PERIPH_VIRT + ((x) & 0x0fffffff)) |
| |
| #define BRCMRG_PERIPH_VIRT 0xe0000000 |
| #define BRCMRG_PERIPH_PHYS 0xd0000000 |
| #define BRCMRG_PERIPH_LENGTH 0x10000000 |
| |
| #endif |
| |
| /*********************************************************************** |
| * BCHP header lists |
| * |
| * NOTE: This section is autogenerated. Do not edit by hand. |
| ***********************************************************************/ |
| |
| #if defined(CONFIG_BCM3390A0) |
| #include <linux/brcmstb/3390a0/bchp_aon_ctrl.h> |
| #include <linux/brcmstb/3390a0/bchp_aon_pin_ctrl.h> |
| #include <linux/brcmstb/3390a0/bchp_aon_pm_l2.h> |
| #include <linux/brcmstb/3390a0/bchp_bspi.h> |
| #include <linux/brcmstb/3390a0/bchp_bspi_raf.h> |
| #include <linux/brcmstb/3390a0/bchp_clkgen.h> |
| #include <linux/brcmstb/3390a0/bchp_common.h> |
| #include <linux/brcmstb/3390a0/bchp_ebi.h> |
| #include <linux/brcmstb/3390a0/bchp_fpm_ctrl_fpm.h> |
| #include <linux/brcmstb/3390a0/bchp_fpm_pool_fpm.h> |
| #include <linux/brcmstb/3390a0/bchp_gio.h> |
| #include <linux/brcmstb/3390a0/bchp_gio_aon.h> |
| #include <linux/brcmstb/3390a0/bchp_hif_continuation.h> |
| #include <linux/brcmstb/3390a0/bchp_hif_cpubiuctrl.h> |
| #include <linux/brcmstb/3390a0/bchp_hif_intr2.h> |
| #include <linux/brcmstb/3390a0/bchp_hif_mspi.h> |
| #include <linux/brcmstb/3390a0/bchp_hif_spi_intr2.h> |
| #include <linux/brcmstb/3390a0/bchp_hif_top_ctrl.h> |
| #include <linux/brcmstb/3390a0/bchp_irq0.h> |
| #include <linux/brcmstb/3390a0/bchp_irq1.h> |
| #include <linux/brcmstb/3390a0/bchp_moca_hostmisc.h> |
| #include <linux/brcmstb/3390a0/bchp_nand.h> |
| #include <linux/brcmstb/3390a0/bchp_pcie_0_dma.h> |
| #include <linux/brcmstb/3390a0/bchp_pcie_0_ext_cfg.h> |
| #include <linux/brcmstb/3390a0/bchp_pcie_0_intr2.h> |
| #include <linux/brcmstb/3390a0/bchp_pcie_0_misc.h> |
| #include <linux/brcmstb/3390a0/bchp_pcie_0_misc_perst.h> |
| #include <linux/brcmstb/3390a0/bchp_pcie_0_rc_cfg_pcie.h> |
| #include <linux/brcmstb/3390a0/bchp_pcie_0_rc_cfg_type1.h> |
| #include <linux/brcmstb/3390a0/bchp_pcie_0_rc_cfg_vendor.h> |
| #include <linux/brcmstb/3390a0/bchp_pcie_0_rgr1.h> |
| #include <linux/brcmstb/3390a0/bchp_sdio_0_cfg.h> |
| #include <linux/brcmstb/3390a0/bchp_sun_top_ctrl.h> |
| #include <linux/brcmstb/3390a0/bchp_switch_acb.h> |
| #include <linux/brcmstb/3390a0/bchp_switch_core.h> |
| #include <linux/brcmstb/3390a0/bchp_switch_fcb.h> |
| #include <linux/brcmstb/3390a0/bchp_switch_indir_rw.h> |
| #include <linux/brcmstb/3390a0/bchp_switch_intrl2_0.h> |
| #include <linux/brcmstb/3390a0/bchp_switch_intrl2_1.h> |
| #include <linux/brcmstb/3390a0/bchp_switch_mdio.h> |
| #include <linux/brcmstb/3390a0/bchp_switch_reg.h> |
| #include <linux/brcmstb/3390a0/bchp_usb_ctrl.h> |
| |
| #elif defined(CONFIG_BCM7145A0) |
| #include <linux/brcmstb/7145a0/bchp_aon_ctrl.h> |
| #include <linux/brcmstb/7145a0/bchp_aon_pin_ctrl.h> |
| #include <linux/brcmstb/7145a0/bchp_aon_pm_l2.h> |
| #include <linux/brcmstb/7145a0/bchp_bspi.h> |
| #include <linux/brcmstb/7145a0/bchp_bspi_raf.h> |
| #include <linux/brcmstb/7145a0/bchp_clkgen.h> |
| #include <linux/brcmstb/7145a0/bchp_common.h> |
| #include <linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_0_0.h> |
| #include <linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_0_1.h> |
| #include <linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_1_0.h> |
| #include <linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_1_1.h> |
| #include <linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_2_0.h> |
| #include <linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_2_1.h> |
| #include <linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_3_0.h> |
| #include <linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_3_1.h> |
| #include <linux/brcmstb/7145a0/bchp_ddr34_phy_control_regs_0.h> |
| #include <linux/brcmstb/7145a0/bchp_ddr34_phy_control_regs_1.h> |
| #include <linux/brcmstb/7145a0/bchp_ebi.h> |
| #include <linux/brcmstb/7145a0/bchp_fpm_ctrl_fpm.h> |
| #include <linux/brcmstb/7145a0/bchp_fpm_pool_fpm.h> |
| #include <linux/brcmstb/7145a0/bchp_gio.h> |
| #include <linux/brcmstb/7145a0/bchp_gio_aon.h> |
| #include <linux/brcmstb/7145a0/bchp_hif_continuation.h> |
| #include <linux/brcmstb/7145a0/bchp_hif_cpubiuctrl.h> |
| #include <linux/brcmstb/7145a0/bchp_hif_intr2.h> |
| #include <linux/brcmstb/7145a0/bchp_hif_mspi.h> |
| #include <linux/brcmstb/7145a0/bchp_hif_spi_intr2.h> |
| #include <linux/brcmstb/7145a0/bchp_hif_top_ctrl.h> |
| #include <linux/brcmstb/7145a0/bchp_irq0.h> |
| #include <linux/brcmstb/7145a0/bchp_irq1.h> |
| #include <linux/brcmstb/7145a0/bchp_memc_arb_1.h> |
| #include <linux/brcmstb/7145a0/bchp_memc_ddr_0.h> |
| #include <linux/brcmstb/7145a0/bchp_memc_ddr_1.h> |
| #include <linux/brcmstb/7145a0/bchp_memc_misc_1.h> |
| #include <linux/brcmstb/7145a0/bchp_moca_hostmisc.h> |
| #include <linux/brcmstb/7145a0/bchp_nand.h> |
| #include <linux/brcmstb/7145a0/bchp_pcie_0_dma.h> |
| #include <linux/brcmstb/7145a0/bchp_pcie_0_ext_cfg.h> |
| #include <linux/brcmstb/7145a0/bchp_pcie_0_intr2.h> |
| #include <linux/brcmstb/7145a0/bchp_pcie_0_misc.h> |
| #include <linux/brcmstb/7145a0/bchp_pcie_0_misc_perst.h> |
| #include <linux/brcmstb/7145a0/bchp_pcie_0_rc_cfg_pcie.h> |
| #include <linux/brcmstb/7145a0/bchp_pcie_0_rc_cfg_type1.h> |
| #include <linux/brcmstb/7145a0/bchp_pcie_0_rc_cfg_vendor.h> |
| #include <linux/brcmstb/7145a0/bchp_pcie_0_rgr1.h> |
| #include <linux/brcmstb/7145a0/bchp_shimphy_addr_cntl_0.h> |
| #include <linux/brcmstb/7145a0/bchp_shimphy_addr_cntl_1.h> |
| #include <linux/brcmstb/7145a0/bchp_sun_top_ctrl.h> |
| #include <linux/brcmstb/7145a0/bchp_switch_acb.h> |
| #include <linux/brcmstb/7145a0/bchp_switch_core.h> |
| #include <linux/brcmstb/7145a0/bchp_switch_fcb.h> |
| #include <linux/brcmstb/7145a0/bchp_switch_indir_rw.h> |
| #include <linux/brcmstb/7145a0/bchp_switch_intrl2_0.h> |
| #include <linux/brcmstb/7145a0/bchp_switch_intrl2_1.h> |
| #include <linux/brcmstb/7145a0/bchp_switch_mdio.h> |
| #include <linux/brcmstb/7145a0/bchp_switch_reg.h> |
| #include <linux/brcmstb/7145a0/bchp_usb_ctrl.h> |
| |
| #elif defined(CONFIG_BCM7145B0) |
| #include <linux/brcmstb/7145b0/bchp_aon_ctrl.h> |
| #include <linux/brcmstb/7145b0/bchp_aon_pin_ctrl.h> |
| #include <linux/brcmstb/7145b0/bchp_aon_pm_l2.h> |
| #include <linux/brcmstb/7145b0/bchp_bspi.h> |
| #include <linux/brcmstb/7145b0/bchp_bspi_raf.h> |
| #include <linux/brcmstb/7145b0/bchp_clkgen.h> |
| #include <linux/brcmstb/7145b0/bchp_common.h> |
| #include <linux/brcmstb/7145b0/bchp_ddr34_phy_byte_lane_0_0.h> |
| #include <linux/brcmstb/7145b0/bchp_ddr34_phy_byte_lane_0_1.h> |
| #include <linux/brcmstb/7145b0/bchp_ddr34_phy_byte_lane_1_0.h> |
| #include <linux/brcmstb/7145b0/bchp_ddr34_phy_byte_lane_1_1.h> |
| #include <linux/brcmstb/7145b0/bchp_ddr34_phy_byte_lane_2_0.h> |
| #include <linux/brcmstb/7145b0/bchp_ddr34_phy_byte_lane_2_1.h> |
| #include <linux/brcmstb/7145b0/bchp_ddr34_phy_byte_lane_3_0.h> |
| #include <linux/brcmstb/7145b0/bchp_ddr34_phy_byte_lane_3_1.h> |
| #include <linux/brcmstb/7145b0/bchp_ddr34_phy_control_regs_0.h> |
| #include <linux/brcmstb/7145b0/bchp_ddr34_phy_control_regs_1.h> |
| #include <linux/brcmstb/7145b0/bchp_ebi.h> |
| #include <linux/brcmstb/7145b0/bchp_fpm_ctrl_fpm.h> |
| #include <linux/brcmstb/7145b0/bchp_fpm_pool_fpm.h> |
| #include <linux/brcmstb/7145b0/bchp_gio.h> |
| #include <linux/brcmstb/7145b0/bchp_gio_aon.h> |
| #include <linux/brcmstb/7145b0/bchp_hif_continuation.h> |
| #include <linux/brcmstb/7145b0/bchp_hif_cpubiuctrl.h> |
| #include <linux/brcmstb/7145b0/bchp_hif_intr2.h> |
| #include <linux/brcmstb/7145b0/bchp_hif_mspi.h> |
| #include <linux/brcmstb/7145b0/bchp_hif_spi_intr2.h> |
| #include <linux/brcmstb/7145b0/bchp_hif_top_ctrl.h> |
| #include <linux/brcmstb/7145b0/bchp_irq0.h> |
| #include <linux/brcmstb/7145b0/bchp_irq1.h> |
| #include <linux/brcmstb/7145b0/bchp_memc_arb_1.h> |
| #include <linux/brcmstb/7145b0/bchp_memc_ddr_0.h> |
| #include <linux/brcmstb/7145b0/bchp_memc_ddr_1.h> |
| #include <linux/brcmstb/7145b0/bchp_memc_misc_1.h> |
| #include <linux/brcmstb/7145b0/bchp_moca_hostmisc.h> |
| #include <linux/brcmstb/7145b0/bchp_nand.h> |
| #include <linux/brcmstb/7145b0/bchp_pcie_0_dma.h> |
| #include <linux/brcmstb/7145b0/bchp_pcie_0_ext_cfg.h> |
| #include <linux/brcmstb/7145b0/bchp_pcie_0_intr2.h> |
| #include <linux/brcmstb/7145b0/bchp_pcie_0_misc.h> |
| #include <linux/brcmstb/7145b0/bchp_pcie_0_misc_perst.h> |
| #include <linux/brcmstb/7145b0/bchp_pcie_0_rc_cfg_pcie.h> |
| #include <linux/brcmstb/7145b0/bchp_pcie_0_rc_cfg_type1.h> |
| #include <linux/brcmstb/7145b0/bchp_pcie_0_rc_cfg_vendor.h> |
| #include <linux/brcmstb/7145b0/bchp_pcie_0_rgr1.h> |
| #include <linux/brcmstb/7145b0/bchp_sdio_0_cfg.h> |
| #include <linux/brcmstb/7145b0/bchp_shimphy_addr_cntl_0.h> |
| #include <linux/brcmstb/7145b0/bchp_shimphy_addr_cntl_1.h> |
| #include <linux/brcmstb/7145b0/bchp_sun_top_ctrl.h> |
| #include <linux/brcmstb/7145b0/bchp_switch_acb.h> |
| #include <linux/brcmstb/7145b0/bchp_switch_core.h> |
| #include <linux/brcmstb/7145b0/bchp_switch_fcb.h> |
| #include <linux/brcmstb/7145b0/bchp_switch_indir_rw.h> |
| #include <linux/brcmstb/7145b0/bchp_switch_intrl2_0.h> |
| #include <linux/brcmstb/7145b0/bchp_switch_intrl2_1.h> |
| #include <linux/brcmstb/7145b0/bchp_switch_mdio.h> |
| #include <linux/brcmstb/7145b0/bchp_switch_reg.h> |
| #include <linux/brcmstb/7145b0/bchp_usb_ctrl.h> |
| |
| #elif defined(CONFIG_BCM7250B0) |
| #include <linux/brcmstb/7250b0/bchp_aon_ctrl.h> |
| #include <linux/brcmstb/7250b0/bchp_aon_pin_ctrl.h> |
| #include <linux/brcmstb/7250b0/bchp_aon_pm_l2.h> |
| #include <linux/brcmstb/7250b0/bchp_bspi.h> |
| #include <linux/brcmstb/7250b0/bchp_bspi_raf.h> |
| #include <linux/brcmstb/7250b0/bchp_clkgen.h> |
| #include <linux/brcmstb/7250b0/bchp_common.h> |
| #include <linux/brcmstb/7250b0/bchp_ddr34_phy_byte_lane_0_0.h> |
| #include <linux/brcmstb/7250b0/bchp_ddr34_phy_byte_lane_1_0.h> |
| #include <linux/brcmstb/7250b0/bchp_ddr34_phy_control_regs_0.h> |
| #include <linux/brcmstb/7250b0/bchp_ebi.h> |
| #include <linux/brcmstb/7250b0/bchp_gio.h> |
| #include <linux/brcmstb/7250b0/bchp_gio_aon.h> |
| #include <linux/brcmstb/7250b0/bchp_hif_continuation.h> |
| #include <linux/brcmstb/7250b0/bchp_hif_cpubiuctrl.h> |
| #include <linux/brcmstb/7250b0/bchp_hif_intr2.h> |
| #include <linux/brcmstb/7250b0/bchp_hif_mspi.h> |
| #include <linux/brcmstb/7250b0/bchp_hif_spi_intr2.h> |
| #include <linux/brcmstb/7250b0/bchp_hif_top_ctrl.h> |
| #include <linux/brcmstb/7250b0/bchp_irq0.h> |
| #include <linux/brcmstb/7250b0/bchp_irq1.h> |
| #include <linux/brcmstb/7250b0/bchp_memc_ddr_0.h> |
| #include <linux/brcmstb/7250b0/bchp_nand.h> |
| #include <linux/brcmstb/7250b0/bchp_pcie_0_dma.h> |
| #include <linux/brcmstb/7250b0/bchp_pcie_0_ext_cfg.h> |
| #include <linux/brcmstb/7250b0/bchp_pcie_0_intr2.h> |
| #include <linux/brcmstb/7250b0/bchp_pcie_0_misc.h> |
| #include <linux/brcmstb/7250b0/bchp_pcie_0_misc_perst.h> |
| #include <linux/brcmstb/7250b0/bchp_pcie_0_rc_cfg_pcie.h> |
| #include <linux/brcmstb/7250b0/bchp_pcie_0_rc_cfg_type1.h> |
| #include <linux/brcmstb/7250b0/bchp_pcie_0_rc_cfg_vendor.h> |
| #include <linux/brcmstb/7250b0/bchp_pcie_0_rgr1.h> |
| #include <linux/brcmstb/7250b0/bchp_sdio_0_cfg.h> |
| #include <linux/brcmstb/7250b0/bchp_shimphy_addr_cntl_0.h> |
| #include <linux/brcmstb/7250b0/bchp_sun_top_ctrl.h> |
| #include <linux/brcmstb/7250b0/bchp_usb_ctrl.h> |
| #include <linux/brcmstb/7250b0/bchp_xpt_bus_if.h> |
| #include <linux/brcmstb/7250b0/bchp_xpt_fe.h> |
| #include <linux/brcmstb/7250b0/bchp_xpt_memdma_mcpb.h> |
| #include <linux/brcmstb/7250b0/bchp_xpt_memdma_mcpb_ch0.h> |
| #include <linux/brcmstb/7250b0/bchp_xpt_pmu.h> |
| #include <linux/brcmstb/7250b0/bchp_xpt_security_ns.h> |
| #include <linux/brcmstb/7250b0/bchp_xpt_security_ns_intr2_0.h> |
| |
| #elif defined(CONFIG_BCM7364A0) |
| #include <linux/brcmstb/7364a0/bchp_aon_ctrl.h> |
| #include <linux/brcmstb/7364a0/bchp_aon_pin_ctrl.h> |
| #include <linux/brcmstb/7364a0/bchp_aon_pm_l2.h> |
| #include <linux/brcmstb/7364a0/bchp_bspi.h> |
| #include <linux/brcmstb/7364a0/bchp_bspi_raf.h> |
| #include <linux/brcmstb/7364a0/bchp_clkgen.h> |
| #include <linux/brcmstb/7364a0/bchp_common.h> |
| #include <linux/brcmstb/7364a0/bchp_ddr34_phy_control_regs_0.h> |
| #include <linux/brcmstb/7364a0/bchp_ebi.h> |
| #include <linux/brcmstb/7364a0/bchp_gio.h> |
| #include <linux/brcmstb/7364a0/bchp_gio_aon.h> |
| #include <linux/brcmstb/7364a0/bchp_hif_continuation.h> |
| #include <linux/brcmstb/7364a0/bchp_hif_cpubiuctrl.h> |
| #include <linux/brcmstb/7364a0/bchp_hif_intr2.h> |
| #include <linux/brcmstb/7364a0/bchp_hif_mspi.h> |
| #include <linux/brcmstb/7364a0/bchp_hif_spi_intr2.h> |
| #include <linux/brcmstb/7364a0/bchp_hif_top_ctrl.h> |
| #include <linux/brcmstb/7364a0/bchp_irq0.h> |
| #include <linux/brcmstb/7364a0/bchp_irq1.h> |
| #include <linux/brcmstb/7364a0/bchp_memc_ddr_0.h> |
| #include <linux/brcmstb/7364a0/bchp_moca_hostmisc.h> |
| #include <linux/brcmstb/7364a0/bchp_nand.h> |
| #include <linux/brcmstb/7364a0/bchp_sdio_0_cfg.h> |
| #include <linux/brcmstb/7364a0/bchp_shimphy_addr_cntl_0.h> |
| #include <linux/brcmstb/7364a0/bchp_sun_top_ctrl.h> |
| #include <linux/brcmstb/7364a0/bchp_usb_ctrl.h> |
| #include <linux/brcmstb/7364a0/bchp_xpt_bus_if.h> |
| #include <linux/brcmstb/7364a0/bchp_xpt_fe.h> |
| #include <linux/brcmstb/7364a0/bchp_xpt_memdma_mcpb.h> |
| #include <linux/brcmstb/7364a0/bchp_xpt_memdma_mcpb_ch0.h> |
| #include <linux/brcmstb/7364a0/bchp_xpt_pmu.h> |
| #include <linux/brcmstb/7364a0/bchp_xpt_security_ns.h> |
| #include <linux/brcmstb/7364a0/bchp_xpt_security_ns_intr2_0.h> |
| |
| #elif defined(CONFIG_BCM7366B0) |
| #include <linux/brcmstb/7366b0/bchp_aon_ctrl.h> |
| #include <linux/brcmstb/7366b0/bchp_aon_pin_ctrl.h> |
| #include <linux/brcmstb/7366b0/bchp_aon_pm_l2.h> |
| #include <linux/brcmstb/7366b0/bchp_bspi.h> |
| #include <linux/brcmstb/7366b0/bchp_bspi_raf.h> |
| #include <linux/brcmstb/7366b0/bchp_clkgen.h> |
| #include <linux/brcmstb/7366b0/bchp_common.h> |
| #include <linux/brcmstb/7366b0/bchp_ddr34_phy_byte_lane_0_0.h> |
| #include <linux/brcmstb/7366b0/bchp_ddr34_phy_byte_lane_1_0.h> |
| #include <linux/brcmstb/7366b0/bchp_ddr34_phy_byte_lane_2_0.h> |
| #include <linux/brcmstb/7366b0/bchp_ddr34_phy_byte_lane_3_0.h> |
| #include <linux/brcmstb/7366b0/bchp_ddr34_phy_control_regs_0.h> |
| #include <linux/brcmstb/7366b0/bchp_ebi.h> |
| #include <linux/brcmstb/7366b0/bchp_gio.h> |
| #include <linux/brcmstb/7366b0/bchp_gio_aon.h> |
| #include <linux/brcmstb/7366b0/bchp_hif_continuation.h> |
| #include <linux/brcmstb/7366b0/bchp_hif_cpubiuctrl.h> |
| #include <linux/brcmstb/7366b0/bchp_hif_intr2.h> |
| #include <linux/brcmstb/7366b0/bchp_hif_mspi.h> |
| #include <linux/brcmstb/7366b0/bchp_hif_spi_intr2.h> |
| #include <linux/brcmstb/7366b0/bchp_hif_top_ctrl.h> |
| #include <linux/brcmstb/7366b0/bchp_irq0.h> |
| #include <linux/brcmstb/7366b0/bchp_irq1.h> |
| #include <linux/brcmstb/7366b0/bchp_memc_ddr_0.h> |
| #include <linux/brcmstb/7366b0/bchp_moca_hostmisc.h> |
| #include <linux/brcmstb/7366b0/bchp_nand.h> |
| #include <linux/brcmstb/7366b0/bchp_pcie_0_dma.h> |
| #include <linux/brcmstb/7366b0/bchp_pcie_0_ext_cfg.h> |
| #include <linux/brcmstb/7366b0/bchp_pcie_0_intr2.h> |
| #include <linux/brcmstb/7366b0/bchp_pcie_0_misc.h> |
| #include <linux/brcmstb/7366b0/bchp_pcie_0_misc_perst.h> |
| #include <linux/brcmstb/7366b0/bchp_pcie_0_rc_cfg_pcie.h> |
| #include <linux/brcmstb/7366b0/bchp_pcie_0_rc_cfg_type1.h> |
| #include <linux/brcmstb/7366b0/bchp_pcie_0_rc_cfg_vendor.h> |
| #include <linux/brcmstb/7366b0/bchp_pcie_0_rgr1.h> |
| #include <linux/brcmstb/7366b0/bchp_sdio_0_cfg.h> |
| #include <linux/brcmstb/7366b0/bchp_shimphy_addr_cntl_0.h> |
| #include <linux/brcmstb/7366b0/bchp_sun_top_ctrl.h> |
| #include <linux/brcmstb/7366b0/bchp_usb_ctrl.h> |
| #include <linux/brcmstb/7366b0/bchp_xpt_bus_if.h> |
| #include <linux/brcmstb/7366b0/bchp_xpt_fe.h> |
| #include <linux/brcmstb/7366b0/bchp_xpt_memdma_mcpb.h> |
| #include <linux/brcmstb/7366b0/bchp_xpt_memdma_mcpb_ch0.h> |
| #include <linux/brcmstb/7366b0/bchp_xpt_pmu.h> |
| #include <linux/brcmstb/7366b0/bchp_xpt_security_ns.h> |
| #include <linux/brcmstb/7366b0/bchp_xpt_security_ns_intr2_0.h> |
| |
| #elif defined(CONFIG_BCM7366C0) |
| #include <linux/brcmstb/7366c0/bchp_aon_ctrl.h> |
| #include <linux/brcmstb/7366c0/bchp_aon_pin_ctrl.h> |
| #include <linux/brcmstb/7366c0/bchp_aon_pm_l2.h> |
| #include <linux/brcmstb/7366c0/bchp_bspi.h> |
| #include <linux/brcmstb/7366c0/bchp_bspi_raf.h> |
| #include <linux/brcmstb/7366c0/bchp_clkgen.h> |
| #include <linux/brcmstb/7366c0/bchp_common.h> |
| #include <linux/brcmstb/7366c0/bchp_ddr34_phy_byte_lane_0_0.h> |
| #include <linux/brcmstb/7366c0/bchp_ddr34_phy_byte_lane_1_0.h> |
| #include <linux/brcmstb/7366c0/bchp_ddr34_phy_byte_lane_2_0.h> |
| #include <linux/brcmstb/7366c0/bchp_ddr34_phy_byte_lane_3_0.h> |
| #include <linux/brcmstb/7366c0/bchp_ddr34_phy_control_regs_0.h> |
| #include <linux/brcmstb/7366c0/bchp_ebi.h> |
| #include <linux/brcmstb/7366c0/bchp_gio.h> |
| #include <linux/brcmstb/7366c0/bchp_gio_aon.h> |
| #include <linux/brcmstb/7366c0/bchp_hif_continuation.h> |
| #include <linux/brcmstb/7366c0/bchp_hif_cpubiuctrl.h> |
| #include <linux/brcmstb/7366c0/bchp_hif_intr2.h> |
| #include <linux/brcmstb/7366c0/bchp_hif_mspi.h> |
| #include <linux/brcmstb/7366c0/bchp_hif_spi_intr2.h> |
| #include <linux/brcmstb/7366c0/bchp_hif_top_ctrl.h> |
| #include <linux/brcmstb/7366c0/bchp_irq0.h> |
| #include <linux/brcmstb/7366c0/bchp_irq1.h> |
| #include <linux/brcmstb/7366c0/bchp_memc_ddr_0.h> |
| #include <linux/brcmstb/7366c0/bchp_moca_hostmisc.h> |
| #include <linux/brcmstb/7366c0/bchp_nand.h> |
| #include <linux/brcmstb/7366c0/bchp_pcie_0_dma.h> |
| #include <linux/brcmstb/7366c0/bchp_pcie_0_ext_cfg.h> |
| #include <linux/brcmstb/7366c0/bchp_pcie_0_intr2.h> |
| #include <linux/brcmstb/7366c0/bchp_pcie_0_misc.h> |
| #include <linux/brcmstb/7366c0/bchp_pcie_0_misc_perst.h> |
| #include <linux/brcmstb/7366c0/bchp_pcie_0_rc_cfg_pcie.h> |
| #include <linux/brcmstb/7366c0/bchp_pcie_0_rc_cfg_type1.h> |
| #include <linux/brcmstb/7366c0/bchp_pcie_0_rc_cfg_vendor.h> |
| #include <linux/brcmstb/7366c0/bchp_pcie_0_rgr1.h> |
| #include <linux/brcmstb/7366c0/bchp_sdio_0_cfg.h> |
| #include <linux/brcmstb/7366c0/bchp_shimphy_addr_cntl_0.h> |
| #include <linux/brcmstb/7366c0/bchp_sun_top_ctrl.h> |
| #include <linux/brcmstb/7366c0/bchp_usb_ctrl.h> |
| #include <linux/brcmstb/7366c0/bchp_xpt_bus_if.h> |
| #include <linux/brcmstb/7366c0/bchp_xpt_fe.h> |
| #include <linux/brcmstb/7366c0/bchp_xpt_memdma_mcpb.h> |
| #include <linux/brcmstb/7366c0/bchp_xpt_memdma_mcpb_ch0.h> |
| #include <linux/brcmstb/7366c0/bchp_xpt_pmu.h> |
| #include <linux/brcmstb/7366c0/bchp_xpt_security_ns.h> |
| #include <linux/brcmstb/7366c0/bchp_xpt_security_ns_intr2_0.h> |
| |
| #elif defined(CONFIG_BCM74371A0) |
| #include <linux/brcmstb/74371a0/bchp_aon_ctrl.h> |
| #include <linux/brcmstb/74371a0/bchp_aon_pin_ctrl.h> |
| #include <linux/brcmstb/74371a0/bchp_aon_pm_l2.h> |
| #include <linux/brcmstb/74371a0/bchp_bspi.h> |
| #include <linux/brcmstb/74371a0/bchp_bspi_raf.h> |
| #include <linux/brcmstb/74371a0/bchp_clkgen.h> |
| #include <linux/brcmstb/74371a0/bchp_common.h> |
| #include <linux/brcmstb/74371a0/bchp_ddr34_phy_byte_lane_0_0.h> |
| #include <linux/brcmstb/74371a0/bchp_ddr34_phy_byte_lane_1_0.h> |
| #include <linux/brcmstb/74371a0/bchp_ddr34_phy_byte_lane_2_0.h> |
| #include <linux/brcmstb/74371a0/bchp_ddr34_phy_byte_lane_3_0.h> |
| #include <linux/brcmstb/74371a0/bchp_ddr34_phy_control_regs_0.h> |
| #include <linux/brcmstb/74371a0/bchp_ebi.h> |
| #include <linux/brcmstb/74371a0/bchp_gio.h> |
| #include <linux/brcmstb/74371a0/bchp_gio_aon.h> |
| #include <linux/brcmstb/74371a0/bchp_hif_continuation.h> |
| #include <linux/brcmstb/74371a0/bchp_hif_cpubiuctrl.h> |
| #include <linux/brcmstb/74371a0/bchp_hif_intr2.h> |
| #include <linux/brcmstb/74371a0/bchp_hif_mspi.h> |
| #include <linux/brcmstb/74371a0/bchp_hif_spi_intr2.h> |
| #include <linux/brcmstb/74371a0/bchp_hif_top_ctrl.h> |
| #include <linux/brcmstb/74371a0/bchp_irq0.h> |
| #include <linux/brcmstb/74371a0/bchp_irq1.h> |
| #include <linux/brcmstb/74371a0/bchp_memc_ddr_0.h> |
| #include <linux/brcmstb/74371a0/bchp_moca_hostmisc.h> |
| #include <linux/brcmstb/74371a0/bchp_nand.h> |
| #include <linux/brcmstb/74371a0/bchp_pcie_0_dma.h> |
| #include <linux/brcmstb/74371a0/bchp_pcie_0_ext_cfg.h> |
| #include <linux/brcmstb/74371a0/bchp_pcie_0_intr2.h> |
| #include <linux/brcmstb/74371a0/bchp_pcie_0_misc.h> |
| #include <linux/brcmstb/74371a0/bchp_pcie_0_misc_perst.h> |
| #include <linux/brcmstb/74371a0/bchp_pcie_0_rc_cfg_pcie.h> |
| #include <linux/brcmstb/74371a0/bchp_pcie_0_rc_cfg_type1.h> |
| #include <linux/brcmstb/74371a0/bchp_pcie_0_rc_cfg_vendor.h> |
| #include <linux/brcmstb/74371a0/bchp_pcie_0_rgr1.h> |
| #include <linux/brcmstb/74371a0/bchp_shimphy_addr_cntl_0.h> |
| #include <linux/brcmstb/74371a0/bchp_sun_top_ctrl.h> |
| #include <linux/brcmstb/74371a0/bchp_usb_ctrl.h> |
| |
| #elif defined(CONFIG_BCM7439A0) |
| #include <linux/brcmstb/7439a0/bchp_aon_ctrl.h> |
| #include <linux/brcmstb/7439a0/bchp_aon_pin_ctrl.h> |
| #include <linux/brcmstb/7439a0/bchp_aon_pm_l2.h> |
| #include <linux/brcmstb/7439a0/bchp_bspi.h> |
| #include <linux/brcmstb/7439a0/bchp_bspi_raf.h> |
| #include <linux/brcmstb/7439a0/bchp_clkgen.h> |
| #include <linux/brcmstb/7439a0/bchp_common.h> |
| #include <linux/brcmstb/7439a0/bchp_ddr34_phy_byte_lane_0_0.h> |
| #include <linux/brcmstb/7439a0/bchp_ddr34_phy_byte_lane_1_0.h> |
| #include <linux/brcmstb/7439a0/bchp_ddr34_phy_byte_lane_2_0.h> |
| #include <linux/brcmstb/7439a0/bchp_ddr34_phy_byte_lane_3_0.h> |
| #include <linux/brcmstb/7439a0/bchp_ddr34_phy_control_regs_0.h> |
| #include <linux/brcmstb/7439a0/bchp_ebi.h> |
| #include <linux/brcmstb/7439a0/bchp_gio.h> |
| #include <linux/brcmstb/7439a0/bchp_gio_aon.h> |
| #include <linux/brcmstb/7439a0/bchp_hif_continuation.h> |
| #include <linux/brcmstb/7439a0/bchp_hif_cpubiuctrl.h> |
| #include <linux/brcmstb/7439a0/bchp_hif_intr2.h> |
| #include <linux/brcmstb/7439a0/bchp_hif_mspi.h> |
| #include <linux/brcmstb/7439a0/bchp_hif_spi_intr2.h> |
| #include <linux/brcmstb/7439a0/bchp_hif_top_ctrl.h> |
| #include <linux/brcmstb/7439a0/bchp_irq0.h> |
| #include <linux/brcmstb/7439a0/bchp_irq1.h> |
| #include <linux/brcmstb/7439a0/bchp_memc_ddr_0.h> |
| #include <linux/brcmstb/7439a0/bchp_moca_hostmisc.h> |
| #include <linux/brcmstb/7439a0/bchp_nand.h> |
| #include <linux/brcmstb/7439a0/bchp_pcie_0_dma.h> |
| #include <linux/brcmstb/7439a0/bchp_pcie_0_ext_cfg.h> |
| #include <linux/brcmstb/7439a0/bchp_pcie_0_intr2.h> |
| #include <linux/brcmstb/7439a0/bchp_pcie_0_misc.h> |
| #include <linux/brcmstb/7439a0/bchp_pcie_0_misc_perst.h> |
| #include <linux/brcmstb/7439a0/bchp_pcie_0_rc_cfg_pcie.h> |
| #include <linux/brcmstb/7439a0/bchp_pcie_0_rc_cfg_type1.h> |
| #include <linux/brcmstb/7439a0/bchp_pcie_0_rc_cfg_vendor.h> |
| #include <linux/brcmstb/7439a0/bchp_pcie_0_rgr1.h> |
| #include <linux/brcmstb/7439a0/bchp_shimphy_addr_cntl_0.h> |
| #include <linux/brcmstb/7439a0/bchp_sun_top_ctrl.h> |
| #include <linux/brcmstb/7439a0/bchp_usb_ctrl.h> |
| |
| #elif defined(CONFIG_BCM7439B0) |
| #include <linux/brcmstb/7439b0/bchp_aon_ctrl.h> |
| #include <linux/brcmstb/7439b0/bchp_aon_pin_ctrl.h> |
| #include <linux/brcmstb/7439b0/bchp_aon_pm_l2.h> |
| #include <linux/brcmstb/7439b0/bchp_bspi.h> |
| #include <linux/brcmstb/7439b0/bchp_bspi_raf.h> |
| #include <linux/brcmstb/7439b0/bchp_clkgen.h> |
| #include <linux/brcmstb/7439b0/bchp_common.h> |
| #include <linux/brcmstb/7439b0/bchp_ddr34_phy_byte_lane_0_0.h> |
| #include <linux/brcmstb/7439b0/bchp_ddr34_phy_byte_lane_1_0.h> |
| #include <linux/brcmstb/7439b0/bchp_ddr34_phy_byte_lane_2_0.h> |
| #include <linux/brcmstb/7439b0/bchp_ddr34_phy_byte_lane_3_0.h> |
| #include <linux/brcmstb/7439b0/bchp_ddr34_phy_control_regs_0.h> |
| #include <linux/brcmstb/7439b0/bchp_ebi.h> |
| #include <linux/brcmstb/7439b0/bchp_gio.h> |
| #include <linux/brcmstb/7439b0/bchp_gio_aon.h> |
| #include <linux/brcmstb/7439b0/bchp_hif_continuation.h> |
| #include <linux/brcmstb/7439b0/bchp_hif_cpubiuctrl.h> |
| #include <linux/brcmstb/7439b0/bchp_hif_intr2.h> |
| #include <linux/brcmstb/7439b0/bchp_hif_mspi.h> |
| #include <linux/brcmstb/7439b0/bchp_hif_spi_intr2.h> |
| #include <linux/brcmstb/7439b0/bchp_hif_top_ctrl.h> |
| #include <linux/brcmstb/7439b0/bchp_irq0.h> |
| #include <linux/brcmstb/7439b0/bchp_irq1.h> |
| #include <linux/brcmstb/7439b0/bchp_memc_ddr_0.h> |
| #include <linux/brcmstb/7439b0/bchp_moca_hostmisc.h> |
| #include <linux/brcmstb/7439b0/bchp_nand.h> |
| #include <linux/brcmstb/7439b0/bchp_pcie_0_dma.h> |
| #include <linux/brcmstb/7439b0/bchp_pcie_0_ext_cfg.h> |
| #include <linux/brcmstb/7439b0/bchp_pcie_0_intr2.h> |
| #include <linux/brcmstb/7439b0/bchp_pcie_0_misc.h> |
| #include <linux/brcmstb/7439b0/bchp_pcie_0_misc_perst.h> |
| #include <linux/brcmstb/7439b0/bchp_pcie_0_rc_cfg_pcie.h> |
| #include <linux/brcmstb/7439b0/bchp_pcie_0_rc_cfg_type1.h> |
| #include <linux/brcmstb/7439b0/bchp_pcie_0_rc_cfg_vendor.h> |
| #include <linux/brcmstb/7439b0/bchp_pcie_0_rgr1.h> |
| #include <linux/brcmstb/7439b0/bchp_sdio_0_cfg.h> |
| #include <linux/brcmstb/7439b0/bchp_shimphy_addr_cntl_0.h> |
| #include <linux/brcmstb/7439b0/bchp_sun_top_ctrl.h> |
| #include <linux/brcmstb/7439b0/bchp_usb_ctrl.h> |
| #include <linux/brcmstb/7439b0/bchp_xpt_bus_if.h> |
| #include <linux/brcmstb/7439b0/bchp_xpt_fe.h> |
| #include <linux/brcmstb/7439b0/bchp_xpt_memdma_mcpb.h> |
| #include <linux/brcmstb/7439b0/bchp_xpt_memdma_mcpb_ch0.h> |
| #include <linux/brcmstb/7439b0/bchp_xpt_pmu.h> |
| #include <linux/brcmstb/7439b0/bchp_xpt_security_ns.h> |
| #include <linux/brcmstb/7439b0/bchp_xpt_security_ns_intr2_0.h> |
| |
| #elif defined(CONFIG_BCM7445D0) |
| #include <linux/brcmstb/7445d0/bchp_aon_ctrl.h> |
| #include <linux/brcmstb/7445d0/bchp_aon_pin_ctrl.h> |
| #include <linux/brcmstb/7445d0/bchp_aon_pm_l2.h> |
| #include <linux/brcmstb/7445d0/bchp_bspi.h> |
| #include <linux/brcmstb/7445d0/bchp_bspi_raf.h> |
| #include <linux/brcmstb/7445d0/bchp_clkgen.h> |
| #include <linux/brcmstb/7445d0/bchp_common.h> |
| #include <linux/brcmstb/7445d0/bchp_ddr34_phy_byte_lane_0_0.h> |
| #include <linux/brcmstb/7445d0/bchp_ddr34_phy_byte_lane_0_1.h> |
| #include <linux/brcmstb/7445d0/bchp_ddr34_phy_byte_lane_0_2.h> |
| #include <linux/brcmstb/7445d0/bchp_ddr34_phy_byte_lane_1_0.h> |
| #include <linux/brcmstb/7445d0/bchp_ddr34_phy_byte_lane_1_1.h> |
| #include <linux/brcmstb/7445d0/bchp_ddr34_phy_byte_lane_1_2.h> |
| #include <linux/brcmstb/7445d0/bchp_ddr34_phy_byte_lane_2_0.h> |
| #include <linux/brcmstb/7445d0/bchp_ddr34_phy_byte_lane_2_1.h> |
| #include <linux/brcmstb/7445d0/bchp_ddr34_phy_byte_lane_2_2.h> |
| #include <linux/brcmstb/7445d0/bchp_ddr34_phy_byte_lane_3_0.h> |
| #include <linux/brcmstb/7445d0/bchp_ddr34_phy_byte_lane_3_1.h> |
| #include <linux/brcmstb/7445d0/bchp_ddr34_phy_byte_lane_3_2.h> |
| #include <linux/brcmstb/7445d0/bchp_ddr34_phy_control_regs_0.h> |
| #include <linux/brcmstb/7445d0/bchp_ddr34_phy_control_regs_1.h> |
| #include <linux/brcmstb/7445d0/bchp_ddr34_phy_control_regs_2.h> |
| #include <linux/brcmstb/7445d0/bchp_ebi.h> |
| #include <linux/brcmstb/7445d0/bchp_gio.h> |
| #include <linux/brcmstb/7445d0/bchp_gio_aon.h> |
| #include <linux/brcmstb/7445d0/bchp_hif_continuation.h> |
| #include <linux/brcmstb/7445d0/bchp_hif_cpubiuctrl.h> |
| #include <linux/brcmstb/7445d0/bchp_hif_intr2.h> |
| #include <linux/brcmstb/7445d0/bchp_hif_mspi.h> |
| #include <linux/brcmstb/7445d0/bchp_hif_spi_intr2.h> |
| #include <linux/brcmstb/7445d0/bchp_hif_top_ctrl.h> |
| #include <linux/brcmstb/7445d0/bchp_irq0.h> |
| #include <linux/brcmstb/7445d0/bchp_irq1.h> |
| #include <linux/brcmstb/7445d0/bchp_memc_arb_1.h> |
| #include <linux/brcmstb/7445d0/bchp_memc_ddr_0.h> |
| #include <linux/brcmstb/7445d0/bchp_memc_ddr_1.h> |
| #include <linux/brcmstb/7445d0/bchp_memc_ddr_2.h> |
| #include <linux/brcmstb/7445d0/bchp_memc_misc_1.h> |
| #include <linux/brcmstb/7445d0/bchp_moca_hostmisc.h> |
| #include <linux/brcmstb/7445d0/bchp_nand.h> |
| #include <linux/brcmstb/7445d0/bchp_pcie_0_dma.h> |
| #include <linux/brcmstb/7445d0/bchp_pcie_0_ext_cfg.h> |
| #include <linux/brcmstb/7445d0/bchp_pcie_0_intr2.h> |
| #include <linux/brcmstb/7445d0/bchp_pcie_0_misc.h> |
| #include <linux/brcmstb/7445d0/bchp_pcie_0_misc_perst.h> |
| #include <linux/brcmstb/7445d0/bchp_pcie_0_rc_cfg_pcie.h> |
| #include <linux/brcmstb/7445d0/bchp_pcie_0_rc_cfg_type1.h> |
| #include <linux/brcmstb/7445d0/bchp_pcie_0_rc_cfg_vendor.h> |
| #include <linux/brcmstb/7445d0/bchp_pcie_0_rgr1.h> |
| #include <linux/brcmstb/7445d0/bchp_sdio_0_cfg.h> |
| #include <linux/brcmstb/7445d0/bchp_shimphy_addr_cntl_0.h> |
| #include <linux/brcmstb/7445d0/bchp_shimphy_addr_cntl_1.h> |
| #include <linux/brcmstb/7445d0/bchp_shimphy_addr_cntl_2.h> |
| #include <linux/brcmstb/7445d0/bchp_sun_top_ctrl.h> |
| #include <linux/brcmstb/7445d0/bchp_usb_ctrl.h> |
| #include <linux/brcmstb/7445d0/bchp_xpt_bus_if.h> |
| #include <linux/brcmstb/7445d0/bchp_xpt_fe.h> |
| #include <linux/brcmstb/7445d0/bchp_xpt_memdma_mcpb.h> |
| #include <linux/brcmstb/7445d0/bchp_xpt_memdma_mcpb_ch0.h> |
| #include <linux/brcmstb/7445d0/bchp_xpt_pmu.h> |
| #include <linux/brcmstb/7445d0/bchp_xpt_security_ns.h> |
| #include <linux/brcmstb/7445d0/bchp_xpt_security_ns_intr2_0.h> |
| |
| #endif |
| |
| /* Kernel will program WKTMR to expire in 1 second */ |
| #define BRCM_STANDBY_TEST 0x01 |
| /* Wait 120s before entering standby, to allow registers to be read */ |
| #define BRCM_STANDBY_DELAY 0x02 |
| /* Show UART output at each step */ |
| #define BRCM_STANDBY_VERBOSE 0x04 |
| /* Don't enter standby - just delay for 5s then return */ |
| #define BRCM_STANDBY_NO_SLEEP 0x08 |
| /* Don't shut down MIPS PLL */ |
| #define BRCM_STANDBY_MIPS_PLL_ON 0x10 |
| /* Don't shut down DDR PLL */ |
| #define BRCM_STANDBY_DDR_PLL_ON 0x20 |
| |
| #define UPGTMR_FREQ 27000000 |
| |
| /*********************************************************************** |
| * Register access macros - sample usage: |
| * |
| * DEV_RD(0xb0404000) -> reads 0xb0404000 |
| * BDEV_RD(0x404000) -> reads 0xb0404000 |
| * BDEV_RD(BCHP_SUN_TOP_CTRL_PROD_REVISION) -> reads 0xb0404000 |
| * |
| * _RB means read back after writing. |
| ***********************************************************************/ |
| |
| #define BPHYSADDR(x) ((x) + BCHP_PHYSICAL_OFFSET) |
| |
| #if !defined(__ASSEMBLY__) |
| |
| #define DEV_RD(x) (*((volatile unsigned long *)(x))) |
| #define DEV_WR(x, y) do { *((volatile unsigned long *)(x)) = (y); } while (0) |
| #define DEV_UNSET(x, y) do { DEV_WR((x), DEV_RD(x) & ~(y)); } while (0) |
| #define DEV_SET(x, y) do { DEV_WR((x), DEV_RD(x) | (y)); } while (0) |
| |
| #define DEV_WR_RB(x, y) do { DEV_WR((x), (y)); DEV_RD(x); } while (0) |
| #define DEV_SET_RB(x, y) do { DEV_SET((x), (y)); DEV_RD(x); } while (0) |
| #define DEV_UNSET_RB(x, y) do { DEV_UNSET((x), (y)); DEV_RD(x); } while (0) |
| |
| #define BDEV_RD(x) (DEV_RD(BVIRTADDR(x))) |
| #define BDEV_WR(x, y) do { DEV_WR(BVIRTADDR(x), (y)); } while (0) |
| #define BDEV_UNSET(x, y) do { BDEV_WR((x), BDEV_RD(x) & ~(y)); } while (0) |
| #define BDEV_SET(x, y) do { BDEV_WR((x), BDEV_RD(x) | (y)); } while (0) |
| |
| #define BDEV_SET_RB(x, y) do { BDEV_SET((x), (y)); BDEV_RD(x); } while (0) |
| #define BDEV_UNSET_RB(x, y) do { BDEV_UNSET((x), (y)); BDEV_RD(x); } while (0) |
| #define BDEV_WR_RB(x, y) do { BDEV_WR((x), (y)); BDEV_RD(x); } while (0) |
| |
| #define BDEV_RD_F(reg, field) \ |
| ((BDEV_RD(BCHP_##reg) & BCHP_##reg##_##field##_MASK) >> \ |
| BCHP_##reg##_##field##_SHIFT) |
| #define BDEV_WR_F(reg, field, val) do { \ |
| BDEV_WR(BCHP_##reg, \ |
| (BDEV_RD(BCHP_##reg) & ~BCHP_##reg##_##field##_MASK) | \ |
| (((val) << BCHP_##reg##_##field##_SHIFT) & \ |
| BCHP_##reg##_##field##_MASK)); \ |
| } while (0) |
| #define BDEV_WR_F_RB(reg, field, val) do { \ |
| BDEV_WR(BCHP_##reg, \ |
| (BDEV_RD(BCHP_##reg) & ~BCHP_##reg##_##field##_MASK) | \ |
| (((val) << BCHP_##reg##_##field##_SHIFT) & \ |
| BCHP_##reg##_##field##_MASK)); \ |
| BDEV_RD(BCHP_##reg); \ |
| } while (0) |
| |
| /*********************************************************************** |
| * Platform features (based on bond options or bootloader settings) |
| ***********************************************************************/ |
| |
| extern int brcm_sata_enabled; |
| extern int brcm_pcie_enabled; |
| extern int brcm_docsis_platform; |
| extern int brcm_moca_enabled; |
| extern int brcm_usb_enabled; |
| |
| #ifdef CONFIG_BRCM_SLOW_TVM_CLOCK |
| #define BRCM_BASE_BAUD_TVM (54000000 / 16) |
| #else |
| #define BRCM_BASE_BAUD_TVM (216000000 / 16) |
| #endif |
| |
| #define BRCM_BASE_BAUD_STB (81000000 / 16) |
| #define BRCM_BASE_BAUD_PCU (192000000 / 16) |
| extern unsigned long brcm_base_baud0; |
| extern unsigned long brcm_base_baud; |
| |
| #define CFE_STRING_SIZE 64 |
| |
| extern char brcm_cfe_boardname[CFE_STRING_SIZE]; |
| |
| extern unsigned long brcm_moca_i2c_base; |
| extern unsigned long brcm_moca_rf_band; |
| |
| #define BRCM_PCI_SLOTS 16 |
| |
| /*********************************************************************** |
| * HIF L2 IRQ controller - shared by EDU, SDIO |
| ***********************************************************************/ |
| |
| #define HIF_ENABLE_IRQ(bit) do { \ |
| BDEV_WR_RB(BCHP_HIF_INTR2_CPU_MASK_CLEAR, \ |
| BCHP_HIF_INTR2_CPU_MASK_CLEAR_##bit##_INTR_MASK); \ |
| } while (0) |
| |
| #define HIF_DISABLE_IRQ(bit) do { \ |
| BDEV_WR_RB(BCHP_HIF_INTR2_CPU_MASK_SET, \ |
| BCHP_HIF_INTR2_CPU_MASK_SET_##bit##_INTR_MASK); \ |
| } while (0) |
| |
| #define HIF_TEST_IRQ(bit) \ |
| (((BDEV_RD(BCHP_HIF_INTR2_CPU_STATUS) & \ |
| ~BDEV_RD(BCHP_HIF_INTR2_CPU_MASK_STATUS)) & \ |
| BCHP_HIF_INTR2_CPU_STATUS_##bit##_INTR_MASK)) |
| |
| #define HIF_ACK_IRQ(bit) do { \ |
| BDEV_WR_RB(BCHP_HIF_INTR2_CPU_CLEAR, \ |
| BCHP_HIF_INTR2_CPU_CLEAR_##bit##_INTR_MASK); \ |
| } while (0) |
| |
| #define HIF_TRIGGER_IRQ(bit) do { \ |
| BDEV_WR_RB(BCHP_HIF_INTR2_CPU_SET, \ |
| BCHP_HIF_INTR2_CPU_SET_##bit##_INTR_MASK); \ |
| } while (0) |
| |
| /*********************************************************************** |
| * Internal (BSP/driver) APIs and definitions |
| ***********************************************************************/ |
| |
| #ifdef BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID |
| |
| /* 40nm chips */ |
| |
| #define BRCM_CHIP_ID() ({ \ |
| u32 reg = BDEV_RD(BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID); \ |
| (reg >> 28 ? reg >> 16 : reg >> 8); \ |
| }) |
| #define BRCM_PROD_ID() ({ \ |
| u32 reg = BDEV_RD(BCHP_SUN_TOP_CTRL_PRODUCT_ID); \ |
| (reg >> 28 ? reg >> 16 : reg >> 8); \ |
| }) |
| #define BRCM_CHIP_REV() \ |
| ((u32)BDEV_RD(BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID) & 0xff) |
| |
| #else |
| |
| /* 130nm, 65nm chips */ |
| |
| #define BRCM_CHIP_ID() ({ \ |
| u32 reg = BDEV_RD(BCHP_SUN_TOP_CTRL_PROD_REVISION); \ |
| (reg >> 28 ? reg >> 16 : reg >> 8); \ |
| }) |
| #define BRCM_PROD_ID() BRCM_CHIP_ID() |
| #define BRCM_CHIP_REV() \ |
| ((u32)BDEV_RD(BCHP_SUN_TOP_CTRL_PROD_REVISION) & 0xff) |
| |
| #endif |
| |
| #define __BMIPS_GET_CBR() ((unsigned long)BMIPS_GET_CBR()) |
| |
| asmlinkage void brcm_upper_tlb_setup(void); |
| void board_pinmux_setup(void); |
| void board_get_ram_size(unsigned long *dram0_mb, unsigned long *dram1_mb); |
| void brcm_wraparound_check(void); |
| |
| void ebi_restore_settings(void); |
| |
| void brcmstb_cpu_setup(void); |
| void bchip_sata3_init(void); |
| void bchip_usb_init(void); |
| void bchip_moca_init(void); |
| void bchip_check_compat(void); |
| void bchip_set_features(void); |
| void bchip_early_setup(void); |
| void brcm_machine_restart(const char *command); |
| void brcm_machine_halt(void); |
| char *brcmstb_pcibios_setup(char *str); |
| |
| void __cpuinit bmips_start_cpu_cores(void); |
| |
| void cfe_die(char *fmt, ...); |
| |
| ssize_t brcm_pm_show_cpu_div(struct device *dev, |
| struct device_attribute *attr, char *buf); |
| ssize_t brcm_pm_store_cpu_div(struct device *dev, |
| struct device_attribute *attr, const char *buf, size_t count); |
| ssize_t brcm_pm_show_cpu_pll(struct device *dev, |
| struct device_attribute *attr, char *buf); |
| ssize_t brcm_pm_store_cpu_pll(struct device *dev, |
| struct device_attribute *attr, const char *buf, size_t count); |
| |
| ssize_t brcm_pm_show_usb_power(struct device *dev, |
| struct device_attribute *attr, char *buf); |
| ssize_t brcm_pm_store_usb_power(struct device *dev, |
| struct device_attribute *attr, const char *buf, size_t count); |
| ssize_t brcm_pm_show_sata_power(struct device *dev, |
| struct device_attribute *attr, char *buf); |
| ssize_t brcm_pm_store_sata_power(struct device *dev, |
| struct device_attribute *attr, const char *buf, size_t count); |
| ssize_t brcm_pm_show_ddr_timeout(struct device *dev, |
| struct device_attribute *attr, char *buf); |
| ssize_t brcm_pm_store_ddr_timeout(struct device *dev, |
| struct device_attribute *attr, const char *buf, size_t count); |
| ssize_t brcm_pm_show_standby_flags(struct device *dev, |
| struct device_attribute *attr, char *buf); |
| ssize_t brcm_pm_store_standby_flags(struct device *dev, |
| struct device_attribute *attr, const char *buf, size_t count); |
| ssize_t brcm_pm_show_standby_timeout(struct device *dev, |
| struct device_attribute *attr, char *buf); |
| ssize_t brcm_pm_store_standby_timeout(struct device *dev, |
| struct device_attribute *attr, const char *buf, size_t count); |
| ssize_t brcm_pm_show_memc1_power(struct device *dev, |
| struct device_attribute *attr, char *buf); |
| ssize_t brcm_pm_store_memc1_power(struct device *dev, |
| struct device_attribute *attr, const char *buf, size_t count); |
| ssize_t brcm_pm_show_halt_mode(struct device *dev, |
| struct device_attribute *attr, char *buf); |
| ssize_t brcm_pm_store_halt_mode(struct device *dev, |
| struct device_attribute *attr, const char *buf, size_t count); |
| ssize_t brcm_pm_show_time_at_wakeup(struct device *dev, |
| struct device_attribute *attr, char *buf); |
| |
| #ifdef BCHP_PM_L2_CPU_STATUS |
| #define TIMER_INTR_MASK BCHP_PM_L2_CPU_STATUS_TIMER_INTR_MASK |
| #ifdef BCHP_PM_L2_CPU_STATUS_WOL_ENET_MASK |
| #define WOL_ENET_MASK BCHP_PM_L2_CPU_STATUS_WOL_ENET_MASK |
| #elif defined(BCHP_PM_L2_CPU_STATUS_WOL_MPD_MASK) |
| #define WOL_ENET_MASK (BCHP_PM_L2_CPU_STATUS_WOL_MPD_MASK | \ |
| BCHP_PM_L2_CPU_STATUS_WOL_HFB_MASK) |
| #else |
| #define WOL_ENET_MASK (0) |
| #endif |
| #ifdef BCHP_PM_L2_CPU_STATUS_WOL_MOCA_MASK |
| #define WOL_MOCA_MASK BCHP_PM_L2_CPU_STATUS_WOL_MOCA_MASK |
| #else |
| #define WOL_MOCA_MASK (0) |
| #endif |
| #else |
| #define TIMER_INTR_MASK BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK |
| #define WOL_ENET_MASK BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_MASK |
| #ifdef BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_MASK |
| #define WOL_MOCA_MASK BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_MASK |
| #else |
| #ifdef CONFIG_BCM7231B0 |
| #define WOL_MOCA_MASK BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET1_MASK |
| #else |
| #define WOL_MOCA_MASK (0) |
| #endif |
| #endif |
| #endif |
| |
| /* NMI / TP1 reset vector */ |
| extern char brcm_reset_nmi_vec[]; |
| extern char brcm_reset_nmi_vec_end[]; |
| |
| /* TP1 warm restart interrupt vector */ |
| extern char brcm_tp1_int_vec[]; |
| extern char brcm_tp1_int_vec_end[]; |
| |
| extern atomic_t brcm_unaligned_fp_count; |
| extern atomic_t brcm_rdhwr_count; /* excludes rdhwr fastpath */ |
| |
| extern unsigned long brcm_cpu_khz; |
| extern unsigned long brcm_adj_cpu_khz; |
| |
| #if defined(CONFIG_BRCMSTB_USE_MEGA_BARRIER) |
| extern void brcmstb_mega_barrier(void); |
| #endif |
| |
| /* BCMGENET device tree properties */ |
| #define BRCM_PHY_ID_AUTO 0x100 |
| #define BRCM_PHY_ID_NONE 0x101 |
| |
| #define BRCM_PHY_TYPE_INT 1 |
| #define BRCM_PHY_TYPE_EXT_MII 2 |
| #define BRCM_PHY_TYPE_EXT_RVMII 3 |
| #define BRCM_PHY_TYPE_EXT_RGMII 4 |
| #define BRCM_PHY_TYPE_EXT_RGMII_IBS 5 |
| #define BRCM_PHY_TYPE_EXT_RGMII_NO_ID 6 |
| #define BRCM_PHY_TYPE_MOCA 7 |
| |
| #endif /* !defined(__ASSEMBLY__) */ |
| |
| #endif /* _ASM_BRCMSTB_BRCMSTB_H */ |
