| /*************************************************************************** |
| * Copyright (c) 1999-2014, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Wed Jul 23 03:11:43 2014 |
| * Full Compile MD5 Checksum a68bc62e9dd3be19fcad480c369d60fd |
| * (minus title and desc) |
| * MD5 Checksum 14382795d76d8497c2dd1bcf3f5d36da |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: $ |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_SUN_TOP_CTRL_H__ |
| #define BCHP_SUN_TOP_CTRL_H__ |
| |
| /*************************************************************************** |
| *SUN_TOP_CTRL - Top Control registers |
| ***************************************************************************/ |
| #define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID 0x00404000 /* Chip family ID */ |
| #define BCHP_SUN_TOP_CTRL_PRODUCT_ID 0x00404004 /* Product Revision ID */ |
| #define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0 0x0040401c /* Strapping values */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1 0x00404020 /* Strapping values */ |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS 0x00404024 /* Bond option value register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0 0x00404028 /* OTP option test register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1 0x0040402c /* OTP option test register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0 0x00404030 /* OTP option status register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1 0x00404034 /* OTP option status register */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0 0x00404038 /* Semaphore channel 0 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1 0x0040403c /* Semaphore channel 1 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2 0x00404040 /* Semaphore channel 2 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3 0x00404044 /* Semaphore channel 3 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4 0x00404048 /* Semaphore channel 4 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5 0x0040404c /* Semaphore channel 5 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6 0x00404050 /* Semaphore channel 6 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7 0x00404054 /* Semaphore channel 7 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8 0x00404058 /* Semaphore channel 8 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9 0x0040405c /* Semaphore channel 9 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10 0x00404060 /* Semaphore channel 10 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11 0x00404064 /* Semaphore channel 11 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12 0x00404068 /* Semaphore channel 12 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13 0x0040406c /* Semaphore channel 13 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14 0x00404070 /* Semaphore channel 14 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15 0x00404074 /* Semaphore channel 15 */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0 0x00404078 /* General watchdog timer 0 */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1 0x0040407c /* General watchdog timer 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0 0x00404080 /* General control register 0 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1 0x00404084 /* General control register 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2 0x00404088 /* General control register 2 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3 0x0040408c /* General control register 3 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4 0x00404090 /* General control register 4 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5 0x00404094 /* General control register 5 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0 0x00404098 /* General status register 0 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1 0x0040409c /* General status register 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2 0x004040a0 /* General status register 2 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3 0x004040bc /* General status register 3 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4 0x004040c0 /* General status register 4 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0 0x00404100 /* Pinmux control register 0 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1 0x00404104 /* Pinmux control register 1 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2 0x00404108 /* Pinmux control register 2 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3 0x0040410c /* Pinmux control register 3 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4 0x00404110 /* Pinmux control register 4 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5 0x00404114 /* Pinmux control register 5 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6 0x00404118 /* Pinmux control register 6 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7 0x0040411c /* Pinmux control register 7 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8 0x00404120 /* Pinmux control register 8 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9 0x00404124 /* Pinmux control register 9 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10 0x00404128 /* Pinmux control register 10 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11 0x0040412c /* Pinmux control register 11 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12 0x00404130 /* Pinmux control register 12 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13 0x00404134 /* Pinmux control register 13 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0 0x00404138 /* Pad pull-up/pull-down control register 0 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1 0x0040413c /* Pad pull-up/pull-down control register 1 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2 0x00404140 /* Pad pull-up/pull-down control register 2 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3 0x00404144 /* Pad pull-up/pull-down control register 3 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4 0x00404148 /* Pad pull-up/pull-down control register 4 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5 0x0040414c /* Pad pull-up/pull-down control register 5 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6 0x00404150 /* Pad pull-up/pull-down control register 6 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7 0x00404154 /* Pad pull-up/pull-down control register 7 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8 0x00404158 /* Pad pull-up/pull-down control register 8 */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0 0x0040415c /* Bypass clock unselect register 0 */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL 0x00404300 /* Reset control */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE 0x00404304 /* Reset source enable */ |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET 0x00404308 /* Software master reset */ |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION 0x0040430c /* Hardware reset extension */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR 0x00404310 /* Reset Monitor */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY 0x00404314 /* Reset history */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET 0x00404318 /* Software init 0 set */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR 0x0040431c /* Software init 0 clear */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS 0x00404320 /* Software init 0 status */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR 0x00404324 /* Security software init 0 monitor */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET 0x00404330 /* Software init 1 set */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR 0x00404334 /* Software init 1 clear */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS 0x00404338 /* Software init 1 status */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR 0x0040433c /* Security software init 1 monitor */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */ |
| #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH 0x00404364 /* Scratch register */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL 0x00404368 /* Spare control bits reserved for future use */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL 0x00404380 /* Test port control */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK 0x00404384 /* Testport peek register */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE 0x00404388 /* Testport poke register */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK 0x0040438c /* Testport peek register */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE 0x00404390 /* Testport poke register */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN 0x00404394 /* EJTAG input bus enables */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL 0x00404398 /* EJTAG output select */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL 0x004043a0 /* VTRAP Control */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS 0x004043a4 /* VTRAP Status */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0 0x004043a8 /* UART Router select 0 */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1 0x004043ac /* UART Router select 1 */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG 0x00404400 /* Serial Slave Port configuration register */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV 0x00404420 /* SERS Revision Register */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG 0x00404424 /* SERS Configuration Register */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL 0x00404514 /* Block select for RO testmode */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION 0x00404518 /* Test configuration */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2 0x0040451c /* OTP option test register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2 0x00404520 /* OTP option status register */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6 0x00404528 /* General control register 6 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7 0x0040452c /* General control register 7 */ |
| |
| /*************************************************************************** |
| *CHIP_FAMILY_ID - Chip family ID |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT 0x73640000 |
| |
| /*************************************************************************** |
| *PRODUCT_ID - Product Revision ID |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT 0x73640000 |
| |
| /*************************************************************************** |
| *BSP_FEATURE_TABLE_ADDR - BSP feature table address |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *STRAP_VALUE_0 - Strapping values |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:07] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK 0xffffff80 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [06:02] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK 0x0000007c |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT 0x00000018 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *STRAP_VALUE_1 - Strapping values |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:05] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK 0xffffffe0 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias_enc [04:03] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_enc_MASK 0x00000018 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_enc_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_enc_DEFAULT 0x00000002 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_mhl_powerup [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_mhl_powerup_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_mhl_powerup_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_mhl_powerup_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_mhl_flash_boot [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_mhl_flash_boot_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_mhl_flash_boot_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_mhl_flash_boot_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *BOND_STATUS - Bond option value register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */ |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT 0 |
| |
| /*************************************************************************** |
| *OTP_OPTION_TEST_0 - OTP option test register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_moca_disable [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_reserved_2 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_2_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_2_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_2_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_output_disable [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_4kx2k_disable [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_4kx2k_disable_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_4kx2k_disable_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_4kx2k_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_reserved_3 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_3_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_3_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_reserved_6 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_6_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_6_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_6_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdmi_rx_disable [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rv9_disable [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rv9_disable_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rv9_disable_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rv9_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved0 [20:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_MASK 0x001fe000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hvd0_disable [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd0_disable_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd0_disable_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd0_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved1 [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved1_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved1_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK 0x00000060 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 0x00000003 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OTP_OPTION_TEST_1 - OTP option test register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_capsense_disable [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_capsense_disable_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_capsense_disable_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_capsense_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_moca2_disable [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca2_disable_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca2_disable_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca2_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_directv_disable [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_directv_disable_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_directv_disable_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_directv_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_15 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_14 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_13 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_reserved_9 [25:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_9_MASK 0x03800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_9_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_9_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_ldpc_disable [22:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_ldpc_disable_MASK 0x00600000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_ldpc_disable_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_ldpc_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_reserved_4 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_4_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_4_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_4_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_tfec_disable [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tfec_disable_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tfec_disable_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tfec_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_audio_1_disable [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_1_disable_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_1_disable_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_1_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_audio_0_disable [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_0_disable_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_0_disable_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_0_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_tuner_disable [10:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tuner_disable_MASK 0x00000700 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tuner_disable_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tuner_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_hdcp22_disable [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdcp22_disable_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdcp22_disable_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdcp22_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_hevc_10_bit_disable [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hevc_10_bit_disable_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hevc_10_bit_disable_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hevc_10_bit_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rfm_disable [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_reserved_5 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_5_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_5_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_5_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb3_func_disable [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_func_disable_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_func_disable_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_func_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb_p1_disable [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb_p1_disable_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb_p1_disable_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb_p1_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb_p0_disable [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb_p0_disable_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb_p0_disable_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb_p0_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_reserved_1 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_1_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_1_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OTP_OPTION_STATUS_0 - OTP option status register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_moca_disable [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_reserved_2 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_reserved_2_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_reserved_2_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_output_disable [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_4kx2k_disable [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_4kx2k_disable_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_4kx2k_disable_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_reserved_3 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_reserved_3_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_reserved_3_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_reserved_6 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_reserved_6_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_reserved_6_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdmi_rx_disable [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_rx_disable_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_rx_disable_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rv9_disable [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rv9_disable_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rv9_disable_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved0 [20:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_MASK 0x001fe000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hvd0_disable [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hvd0_disable_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hvd0_disable_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved1 [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved1_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved1_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0 |
| |
| /*************************************************************************** |
| *OTP_OPTION_STATUS_1 - OTP option status register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_capsense_disable [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_capsense_disable_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_capsense_disable_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_moca2_disable [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca2_disable_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca2_disable_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_directv_disable [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_directv_disable_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_directv_disable_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_15 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_14 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_13 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_reserved_9 [25:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_9_MASK 0x03800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_9_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_ldpc_disable [22:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_ldpc_disable_MASK 0x00600000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_ldpc_disable_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_reserved_4 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_4_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_4_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_tfec_disable [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_tfec_disable_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_tfec_disable_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_audio_1_disable [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_audio_1_disable_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_audio_1_disable_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_audio_0_disable [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_audio_0_disable_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_audio_0_disable_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_tuner_disable [10:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_tuner_disable_MASK 0x00000700 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_tuner_disable_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_hdcp22_disable [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hdcp22_disable_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hdcp22_disable_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_hevc_10_bit_disable [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hevc_10_bit_disable_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hevc_10_bit_disable_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rfm_disable [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rfm_disable_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rfm_disable_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_reserved_5 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_5_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_5_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb3_func_disable [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb3_func_disable_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb3_func_disable_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb_p1_disable [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb_p1_disable_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb_p1_disable_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb_p0_disable [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb_p0_disable_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb_p0_disable_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_reserved_1 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_1_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_1_SHIFT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_0 - Semaphore channel 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_1 - Semaphore channel 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_2 - Semaphore channel 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_3 - Semaphore channel 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_4 - Semaphore channel 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_5 - Semaphore channel 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_6 - Semaphore channel 6 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_7 - Semaphore channel 7 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_8 - Semaphore channel 8 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_9 - Semaphore channel 9 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_10 - Semaphore channel 10 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_11 - Semaphore channel 11 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_12 - Semaphore channel 12 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_13 - Semaphore channel 13 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_14 - Semaphore channel 14 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_15 - Semaphore channel 15 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GEN_WATCHDOG_0 - General watchdog timer 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GEN_WATCHDOG_1 - General watchdog timer 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_0 - General control register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: bert_pinmux_ctrl [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_bert_pinmux_ctrl_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_bert_pinmux_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_bert_pinmux_ctrl_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio0_alt_pin_sel [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio0_alt_pin_sel_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio0_alt_pin_sel_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio0_alt_pin_sel_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ana_detect_sdio_1_pd [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ana_detect_sdio_0_pd [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio_1_pad_modehv_override [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio_0_pad_modehv_override [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: rgmii_swap [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_rgmii_swap_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_rgmii_swap_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_rgmii_swap_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_1 - General control register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK 0xfffffff0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_2 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: fsk_test_dac_edge_sel [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_edge_sel_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_edge_sel_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_edge_sel_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: fsk_test_dac_en [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_en_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_en_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_en_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_2 - General control register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_3 - General control register 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_4 - General control register 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_5 - General control register 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_0 - General status register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: sat_wbafe_pll_lock [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_sat_wbafe_pll_lock_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_sat_wbafe_pll_lock_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: ebi_pad_config [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_ebi_pad_config_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_ebi_pad_config_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_1 - General status register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: sdio_1_pad_vddo [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_1_pad_vddo_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_1_pad_vddo_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: sdio_0_pad_vddo [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_0_pad_vddo_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_0_pad_vddo_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_2 - General status register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:20] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK 0xfff00000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_19 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_18 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_17_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan_16 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_16_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_16_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_16_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan_15 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_15_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_15_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_15_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan_14 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_14_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_14_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_14_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_12_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_12_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan_10 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_10_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_10_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_10_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_6 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_amp_en [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_amp_en_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_amp_en_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_amp_en_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_sel_gmii [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_gmii_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_gmii_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_gmii_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_modehv [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_modehv_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_modehv_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_modehv_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_sel [02:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_MASK 0x00000007 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DEFAULT 0x00000007 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:24] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK 0xff000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_023 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_023_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_023_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_023_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_022 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_022_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_022_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_022_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_021 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_021_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_021_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_021_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_020 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_020_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_020_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_020_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_019 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_019_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_019_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_019_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_018 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_018_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_018_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_018_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_017 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_017_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_017_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_017_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_016 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_016_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_016_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_016_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_015 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_015_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_015_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_015_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_014 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_014_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_014_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_014_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_013 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_013_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_013_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_013_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_012 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_012_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_012_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_012_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_011 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_011_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_011_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_011_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_010 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_010_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_010_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_010_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_009 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_009_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_009_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_009_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_008 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_008_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_008_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_008_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_007 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_007_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_007_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_007_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_006 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_006_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_006_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_006_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_005 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_005_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_005_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_005_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_004 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_004_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_004_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_004_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_003 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_003_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_003_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_003_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_002 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_002_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_002_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_002_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_001 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_001_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_001_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_001_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_000 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_000_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_000_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_000_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: emmc_pad_slew [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: emmc_pad_sel [26:24] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_MASK 0x07000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: bspi_pad_src [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: bspi_pad_sel [22:20] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_MASK 0x00700000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_4_pad_src [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_src_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_src_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_src_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_4_pad_sel [18:16] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_MASK 0x00070000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_3_pad_src [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_3_pad_sel [14:12] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_MASK 0x00007000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_2_pad_src [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_src_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_src_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_src_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_2_pad_sel [10:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_MASK 0x00000700 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_1_pad_src [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_1_pad_sel [06:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_MASK 0x00000070 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_0_pad_src [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_0_pad_sel [02:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_MASK 0x00000007 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_16MA 7 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: egphy_test_pin_mux_sel [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_hys_en [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_oeb [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_do [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_src [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_sel [02:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_MASK 0x00000007 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_16MA 7 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_3 - General status register 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_3 :: cpu_system_counter [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_cpu_system_counter_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_cpu_system_counter_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_4 - General status register 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_4 :: cpu_system_counter [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_cpu_system_counter_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_cpu_system_counter_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_0 - Pinmux control register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_ebi_dsb [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_dsb_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_dsb_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_dsb_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_dsb_ONOFF_EBI_DSB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_dsb_SD_CARD1_LED 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_dsb_TSPI_S1_MOSI 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_ebi_tsb [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_tsb_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_tsb_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_tsb_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_tsb_ONOFF_EBI_TSB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_tsb_SD_CARD1_PRES 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_tsb_TSPI_S1_MISO 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_ebi_rdb [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_rdb_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_rdb_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_rdb_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_rdb_ONOFF_EBI_RDB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_rdb_SD_CARD1_CLK_IN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_rdb_TSPI_S1_SCK 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_ebi_we0b [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_we0b_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_we0b_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_we0b_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_we0b_ONOFF_EBI_WE0B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_we0b_SD_CARD1_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_we0b_TSPI_S0_SS0B 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_ebi_nand_rbb [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_nand_rbb_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_nand_rbb_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_nand_rbb_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_nand_rbb_ONOFF_EBI_NAND_RBB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_nand_rbb_SD_CARD1_CMD 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_nand_rbb_TSPI_S0_MOSI 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_ebi_cs2b [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_cs2b_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_cs2b_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_cs2b_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_cs2b_ONOFF_EBI_CS2B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_cs2b_TSPI_S0_MISO 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_ebi_cs1b [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_cs1b_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_cs1b_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_cs1b_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_cs1b_ONOFF_EBI_CS1B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_cs1b_TSPI_S0_SCK 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_aud0_spdif [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_aud0_spdif_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_aud0_spdif_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_aud0_spdif_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_aud0_spdif_ONOFF_AUD0_SPDIF 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_aud0_spdif_TP_OUT_26 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_1 - Pinmux control register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_ebi_data_7 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_7_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_7_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_7_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_7_ONOFF_EBI_DATA_7 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_7_TSPI_S3_MOSI 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_ebi_data_6 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_6_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_6_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_6_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_6_ONOFF_EBI_DATA_6 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_6_TSPI_S3_MISO 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_ebi_data_5 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_5_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_5_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_5_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_5_ONOFF_EBI_DATA_5 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_5_TSPI_S3_SCK 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_ebi_data_4 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_4_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_4_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_4_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_4_ONOFF_EBI_DATA_4 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_4_TSPI_S2_SS0B 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_ebi_data_3 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_3_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_3_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_3_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_3_ONOFF_EBI_DATA_3 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_3_SD_CARD1_DAT3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_3_TSPI_S2_MOSI 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_ebi_data_2 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_2_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_2_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_2_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_2_ONOFF_EBI_DATA_2 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_2_SD_CARD1_DAT2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_2_TSPI_S2_MISO 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_ebi_data_1 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_1_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_1_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_1_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_1_ONOFF_EBI_DATA_1 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_1_SD_CARD1_DAT1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_1_TSPI_S2_SCK 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_ebi_data_0 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_0_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_0_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_0_ONOFF_EBI_DATA_0 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_0_SD_CARD1_DAT0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_0_TSPI_S1_SS0B 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_2 - Pinmux control register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_gpio_000 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_gpio_000_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_gpio_000_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_gpio_000_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_gpio_000_ONOFF_GPIO_000 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_gpio_000_CHIP2CI_MDO_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_gpio_000_EXT_IRQB_4 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_gpio_000_RMXP_DATA0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_gpio_000_RMX_DATA0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_gpio_000_DFE_MPEG_DOUT0 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_gpio_000_TP_OUT_09 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_gpio_000_PM_GPIO_000 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_ir_out [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ir_out_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ir_out_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ir_out_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ir_out_ONOFF_IR_OUT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ir_out_TP_OUT_25 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_sgpio_01 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_01_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_01_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_01_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_01_ONOFF_SGPIO_01 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_01_MOCA_BSC_SDA 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_01_BSC_M3_SDA 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_sgpio_00 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_00_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_00_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_00_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_00_ONOFF_SGPIO_00 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_00_MOCA_BSC_SCL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_00_BSC_M3_SCL 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_emmc_clk [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_emmc_clk_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_emmc_clk_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_emmc_clk_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_emmc_clk_ONOFF_EMMC_CLK 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_emmc_clk_PM_EMMC_CLK 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_emmc_cmd [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_emmc_cmd_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_emmc_cmd_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_emmc_cmd_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_emmc_cmd_ONOFF_EMMC_CMD 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_emmc_cmd_PM_EMMC_CMD 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_ebi_nand_dqs [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_nand_dqs_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_nand_dqs_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_nand_dqs_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_nand_dqs_ONOFF_EBI_NAND_DQS 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_nand_dqs_SD_CARD1_PWR0 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_ebi_nand_wpb [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_nand_wpb_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_nand_wpb_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_nand_wpb_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_nand_wpb_ONOFF_EBI_NAND_WPB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_nand_wpb_SD_CARD1_WPROT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_nand_wpb_TSPI_S3_SS0B 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_3 - Pinmux control register 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_gpio_008 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_008_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_008_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_008_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_008_ONOFF_GPIO_008 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_008_CHIP2CI_MOSTRT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_008_RMXP_SYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_008_RMX_SYNC0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_008_DFE_MPEG_SYNC 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_008_MTSIF1_RX_DATA_2_ALT 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_008_TP_IN_08 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_008_PM_GPIO_008 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_gpio_007 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_ONOFF_GPIO_007 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_CHIP2CI_MDO_7 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_USB1_PWRFLT_SEC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_RMXP_DATA7 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_RMX_PAUSE0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_DFE_MPEG_DOUT7 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_MTSIF1_RX_DATA_1_ALT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_TP_IN_07 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_PM_GPIO_007 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_gpio_006 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_006_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_006_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_006_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_006_ONOFF_GPIO_006 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_006_CHIP2CI_MDO_6 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_006_USB1_PWRON_SEC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_006_RMXP_DATA6 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_006_DFE_MPEG_DOUT6 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_006_MTSIF1_RX_DATA_0_ALT 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_006_TP_IN_06 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_006_PM_GPIO_006 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_gpio_005 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_ONOFF_GPIO_005 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_CHIP2CI_MDO_5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_USB0_PWRFLT_SEC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_RMXP_DATA5 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_RMX_CLK1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_DFE_MPEG_DOUT5 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_SDS_BERT_CLK_ALT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_TP_IN_05 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_PM_GPIO_005 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_gpio_004 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_004_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_004_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_004_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_004_ONOFF_GPIO_004 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_004_CHIP2CI_MDO_4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_004_USB0_PWRON_SEC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_004_RMXP_DATA4 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_004_RMX_VALID1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_004_DFE_MPEG_DOUT4 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_004_TP_OUT_13 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_004_PM_GPIO_004 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_gpio_003 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_003_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_003_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_003_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_003_ONOFF_GPIO_003 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_003_CHIP2CI_MDO_3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_003_EXT_IRQB_7 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_003_RMXP_DATA3 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_003_RMX_SYNC1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_003_DFE_MPEG_DOUT3 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_003_TP_OUT_12 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_003_PM_GPIO_003 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_gpio_002 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_002_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_002_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_002_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_002_ONOFF_GPIO_002 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_002_CHIP2CI_MDO_2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_002_EXT_IRQB_6 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_002_RMXP_DATA2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_002_RMX_PAUSE1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_002_DFE_MPEG_DOUT2 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_002_TP_OUT_11 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_002_PM_GPIO_002 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_gpio_001 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_ONOFF_GPIO_001 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_CHIP2CI_MDO_1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_EXT_IRQB_5 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_RMXP_DATA1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_RMX_DATA1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_DFE_MPEG_DOUT1 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_SDS_BERT_DATA_ALT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_TP_OUT_10 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_PM_GPIO_001 8 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_4 - Pinmux control register 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_016 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_016_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_016_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_016_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_016_ONOFF_GPIO_016 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_016_CI2CHIP_MDI_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_016_PPKT_DATA0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_016_PKT0_DATA 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_016_DFE_GPIO_0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_016_TP_IN_16 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_016_PM_GPIO_016 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_015 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_015_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_015_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_015_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_015_ONOFF_GPIO_015 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_015_CI2CHIP_MICLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_015_PPKT_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_015_MTSIF1_RX_SYNC_ALT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_015_TP_IN_15 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_015_PM_GPIO_015 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_014 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_014_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_014_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_014_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_014_ONOFF_GPIO_014 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_014_CI2CHIP_MCLKI 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_014_PPKT_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_014_PKT0_CLK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_014_MTSIF1_RX_CLK_ALT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_014_TP_IN_14 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_014_PM_GPIO_014 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_013 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_013_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_013_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_013_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_013_ONOFF_GPIO_013 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_013_CI2CHIP_MIVAL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_013_PPKT_VALID 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_013_PKT0_VALID 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_013_MTSIF1_RX_DATA_7_ALT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_013_TP_IN_13 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_013_PM_GPIO_013 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_012 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_012_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_012_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_012_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_012_ONOFF_GPIO_012 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_012_CI2CHIP_MISTRT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_012_PPKT_SYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_012_PKT0_SYNC 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_012_DFE_MPEG_SER_MODE 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_012_MTSIF1_RX_DATA_6_ALT 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_012_TP_IN_12 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_012_PM_GPIO_012 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_011 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_011_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_011_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_011_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_011_ONOFF_GPIO_011 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_011_CHIP2CI_MOCLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_011_EXT_USB_HUB_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_011_RMXP_CLK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_011_DFE_MPEG_CLK 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_011_MTSIF1_RX_DATA_5_ALT 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_011_TP_IN_11 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_011_PM_GPIO_011 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_010 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_010_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_010_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_010_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_010_ONOFF_GPIO_010 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_010_CHIP2CI_MCLKO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_010_RMXP_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_010_RMX_CLK0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_010_DFE_MPEG_ERR 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_010_MTSIF1_RX_DATA_4_ALT 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_010_TP_IN_10 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_010_PM_GPIO_010 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_009 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_009_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_009_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_009_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_009_ONOFF_GPIO_009 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_009_CHIP2CI_MOVAL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_009_RMXP_VALID 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_009_RMX_VALID0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_009_DFE_MPEG_DATA_EN 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_009_MTSIF1_RX_DATA_3_ALT 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_009_TP_IN_09 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_009_PM_GPIO_009 7 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_5 - Pinmux control register 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_024 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_024_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_024_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_024_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_024_ONOFF_GPIO_024 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_024_EBI_ADDR_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_024_RMXP_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_024_CHIP2POD_MCLKO 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_024_TP_IN_24 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_024_PM_GPIO_024 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_023 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_023_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_023_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_023_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_023_ONOFF_GPIO_023 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_023_CI2CHIP_MDI_7 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_023_PPKT_DATA7 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_023_PKT1_VALID 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_023_DFE_GPIO_7 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_023_TP_IN_23 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_023_PM_GPIO_023 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_022 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_022_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_022_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_022_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_022_ONOFF_GPIO_022 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_022_CI2CHIP_MDI_6 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_022_PPKT_DATA6 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_022_PKT1_CLK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_022_DFE_GPIO_6 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_022_TP_IN_22 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_022_PM_GPIO_022 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_021 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_021_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_021_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_021_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_021_ONOFF_GPIO_021 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_021_CI2CHIP_MDI_5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_021_PPKT_DATA5 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_021_PKT1_SYNC 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_021_DFE_GPIO_5 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_021_TP_IN_21 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_021_PM_GPIO_021 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_020 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_020_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_020_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_020_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_020_ONOFF_GPIO_020 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_020_CI2CHIP_MDI_4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_020_PPKT_DATA4 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_020_PKT0_ERROR 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_020_PKT3_SYNC 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_020_DFE_GPIO_4 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_020_TP_IN_20 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_020_PM_GPIO_020 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_019 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_019_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_019_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_019_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_019_ONOFF_GPIO_019 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_019_CI2CHIP_MDI_3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_019_PPKT_DATA3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_019_PKT1_ERROR 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_019_PKT3_DATA 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_019_DFE_GPIO_3 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_019_TP_IN_19 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_019_PM_GPIO_019 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_018 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_018_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_018_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_018_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_018_ONOFF_GPIO_018 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_018_CI2CHIP_MDI_2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_018_PPKT_DATA2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_018_PKT3_CLK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_018_DFE_GPIO_2 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_018_TP_IN_18 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_018_PM_GPIO_018 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_017 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_017_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_017_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_017_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_017_ONOFF_GPIO_017 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_017_CI2CHIP_MDI_1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_017_PPKT_DATA1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_017_PKT1_DATA 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_017_DFE_GPIO_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_017_TP_IN_17 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_017_PM_GPIO_017 6 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_6 - Pinmux control register 6 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_032 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_032_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_032_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_032_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_032_ONOFF_GPIO_032 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_032_EBI_ADDR_8 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_032_SC1_IO 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_032_MTSIF1_RX_DATA_3 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_032_AUD_FS_CLK0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_032_PM_GPIO_032 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_031 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_031_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_031_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_031_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_031_ONOFF_GPIO_031 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_031_EBI_ADDR_7 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_031_SC1_RST 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_031_MTSIF1_RX_DATA_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_031_UART_CTS_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_031_PM_GPIO_031 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_030 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_030_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_030_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_030_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_030_ONOFF_GPIO_030 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_030_EBI_ADDR_6 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_030_SC1_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_030_MTSIF1_RX_DATA_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_030_UART_TXD_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_030_PM_GPIO_030 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_029 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_029_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_029_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_029_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_029_ONOFF_GPIO_029 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_029_EBI_ADDR_5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_029_SC1_VCC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_029_MTSIF1_RX_DATA_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_029_UART_RTS_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_029_PM_GPIO_029 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_028 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_028_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_028_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_028_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_028_ONOFF_GPIO_028 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_028_EBI_ADDR_4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_028_CHIP2POD_SCTL0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_028_MTSIF1_ATS_RESET_ALT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_028_TP_IN_28 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_028_PM_GPIO_028 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_027 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_027_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_027_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_027_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_027_ONOFF_GPIO_027 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_027_EBI_ADDR_3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_027_CHIP2POD_SDO0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_027_MTSIF1_ATS_INC_ALT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_027_TP_IN_27 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_027_PM_GPIO_027 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_026 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_026_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_026_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_026_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_026_ONOFF_GPIO_026 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_026_EBI_ADDR_2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_026_POD2CHIP_SDI0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_026_TP_IN_26 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_026_PM_GPIO_026 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_025 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_025_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_025_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_025_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_025_ONOFF_GPIO_025 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_025_EBI_ADDR_1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_025_CHIP2POD_SCLK0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_025_TP_IN_25 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_025_PM_GPIO_025 4 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_7 - Pinmux control register 7 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: onoff_gpio_040 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_040_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_040_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_040_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_040_ONOFF_GPIO_040 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_040_EBI_WAITB 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_040_TSIO_VCTRL 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_040_MTSIF1_ATS_RESET 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_040_PM_GPIO_040 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: onoff_gpio_039 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_039_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_039_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_039_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_039_ONOFF_GPIO_039 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_039_EBI_RWB 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_039_I2S_LR0_IN 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_039_MTSIF1_ATS_INC 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_039_PM_GPIO_039 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: onoff_gpio_038 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_038_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_038_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_038_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_038_ONOFF_GPIO_038 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_038_EBI_ADDR_14 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_038_I2S_CLK0_IN 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_038_MTSIF1_RX_SYNC 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_038_PM_GPIO_038 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: onoff_gpio_037 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_037_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_037_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_037_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_037_ONOFF_GPIO_037 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_037_EBI_ADDR_13 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_037_I2S_DATA0_IN 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_037_MTSIF1_RX_CLK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_037_PM_GPIO_037 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: onoff_gpio_036 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_036_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_036_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_036_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_036_ONOFF_GPIO_036 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_036_EBI_ADDR_12 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_036_SC1_VPP 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_036_MTSIF1_RX_DATA_7 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_036_I2S_LR0_OUT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_036_PM_GPIO_036 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: onoff_gpio_035 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_035_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_035_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_035_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_035_ONOFF_GPIO_035 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_035_EBI_ADDR_11 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_035_SC1_AUX2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_035_MTSIF1_RX_DATA_6 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_035_I2S_DATA0_OUT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_035_PM_GPIO_035 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: onoff_gpio_034 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_034_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_034_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_034_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_034_ONOFF_GPIO_034 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_034_EBI_ADDR_10 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_034_SC1_AUX1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_034_MTSIF1_RX_DATA_5 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_034_I2S_CLK0_OUT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_034_PM_GPIO_034 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: onoff_gpio_033 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_033_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_033_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_033_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_033_ONOFF_GPIO_033 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_033_EBI_ADDR_9 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_033_SC1_PRES 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_033_MTSIF1_RX_DATA_4 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_033_UART_RXD_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_033_PM_GPIO_033 5 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_8 - Pinmux control register 8 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: onoff_gpio_048 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_048_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_048_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_048_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_048_ONOFF_GPIO_048 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_048_EBI_DATA13 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_048_PM_GPIO_048 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: onoff_gpio_047 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_047_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_047_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_047_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_047_ONOFF_GPIO_047 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_047_EBI_DATA12 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_047_PM_GPIO_047 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: onoff_gpio_046 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_046_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_046_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_046_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_046_ONOFF_GPIO_046 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_046_EBI_DATA11 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_046_PM_GPIO_046 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: onoff_gpio_045 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_045_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_045_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_045_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_045_ONOFF_GPIO_045 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_045_EBI_DATA10 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_045_PM_GPIO_045 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: onoff_gpio_044 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_044_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_044_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_044_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_044_ONOFF_GPIO_044 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_044_EBI_DATA9 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_044_PM_GPIO_044 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: onoff_gpio_043 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_043_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_043_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_043_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_043_ONOFF_GPIO_043 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_043_EBI_DATA8 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_043_PM_GPIO_043 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: onoff_gpio_042 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_042_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_042_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_042_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_042_ONOFF_GPIO_042 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_042_EBI_WE1B 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_042_PM_GPIO_042 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: onoff_rsvd_gpio_041 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_rsvd_gpio_041_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_rsvd_gpio_041_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_rsvd_gpio_041_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_rsvd_gpio_041_ONOFF_RSVD_GPIO_041 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_rsvd_gpio_041_PM_GPIO_041 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_9 - Pinmux control register 9 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: onoff_gpio_087 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_087_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_087_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_087_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_087_ONOFF_GPIO_087 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_087_SC0_AUX1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_087_PKT3_CLK_ALT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_087_I2S_CLK0_OUT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_087_I2S_CLK0_IN 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_087_CPU_TRACE_DATA13 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_087_TP_IN_03 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: onoff_gpio_086 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_086_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_086_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_086_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_086_ONOFF_GPIO_086 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_086_SC0_VCC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_086_PKT2_VALID 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_086_SPI_M_MOSI 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_086_UART_RXD_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_086_CPU_TRACE_DATA8 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_086_ALT_TP_IN_01 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_086_PM_GPIO_086 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: onoff_gpio_085 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_085_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_085_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_085_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_085_ONOFF_GPIO_085 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_085_SC0_PRES 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_085_PKT2_ERROR 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_085_SPI_M_SS1B 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_085_AUD_FS_CLK0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_085_CPU_TRACE_DATA12 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_085_TP_IN_02 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: onoff_gpio_084 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_084_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_084_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_084_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_084_ONOFF_GPIO_084 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_084_SC0_RST 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_084_PKT2_SYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_084_SPI_M_SS0B 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_084_UART_CTS_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_084_CPU_TRACE_DATA10 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_084_TP_IN_01 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: onoff_gpio_083 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_083_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_083_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_083_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_083_ONOFF_GPIO_083 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_083_SC0_CLK_OUT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_083_PKT2_DATA 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_083_SPI_M_SCK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_083_UART_TXD_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_083_CPU_TRACE_DATA9 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_083_ALT_TP_OUT_01 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: onoff_gpio_082 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_082_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_082_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_082_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_082_ONOFF_GPIO_082 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_082_SC0_IO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_082_PKT2_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_082_SPI_M_MISO 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_082_UART_RTS_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_082_CPU_TRACE_DATA11 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_082_TP_IN_00 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: onoff_gpio_050 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_050_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_050_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_050_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_050_ONOFF_GPIO_050 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_050_EBI_DATA15 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_050_PM_GPIO_050 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: onoff_gpio_049 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_049_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_049_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_049_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_049_ONOFF_GPIO_049 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_049_EBI_DATA14 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_049_PM_GPIO_049 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_10 - Pinmux control register 10 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: onoff_gpio_099 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_099_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_099_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_099_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_099_ONOFF_GPIO_099 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_099_MII_RXDV_RGMII_RXCTL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_099_VO_656_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_099_MTSIF0_RX_DATA_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_099_SD_CARD0_CMD 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_099_CPU_TRACE_DATA0 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_099_TP_OUT_16 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_099_PM_GPIO_099 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: onoff_gpio_098 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_ONOFF_GPIO_098 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_RGMII_RX_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_VO_656_0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_EXT_SC_CLK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_MTSIF0_RX_CLK 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_SD_CARD0_CLK_IN 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_CPU_TRACE_CLK 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_TP_OUT_15 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_PM_GPIO_098 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: onoff_rsvd_gpio_097 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_097_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_097_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_097_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_097_ONOFF_RSVD_GPIO_097 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_097_SC1_VPP 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_097_PM_GPIO_097 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: onoff_rsvd_gpio_096 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_096_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_096_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_096_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_096_ONOFF_RSVD_GPIO_096 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_096_SC1_AUX2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_096_PM_GPIO_096 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: onoff_rsvd_gpio_095 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_095_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_095_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_095_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_095_ONOFF_RSVD_GPIO_095 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_095_SC1_AUX1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_095_PM_GPIO_095 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: onoff_rsvd_gpio_094 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_094_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_094_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_094_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_094_ONOFF_RSVD_GPIO_094 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_094_SC1_VCC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_094_PM_GPIO_094 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: onoff_gpio_089 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_089_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_089_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_089_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_089_ONOFF_GPIO_089 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_089_SC0_VPP 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_089_RGMII_RX_OK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_089_PKT3_SYNC_ALT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_089_I2S_LR0_OUT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_089_I2S_LR0_IN 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_089_CPU_TRACE_DATA15 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_089_TP_IN_31 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: onoff_gpio_088 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_088_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_088_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_088_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_088_ONOFF_GPIO_088 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_088_SC0_AUX2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_088_RGMII_START_STOP 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_088_PKT3_DATA_ALT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_088_I2S_DATA0_OUT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_088_I2S_DATA0_IN 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_088_CPU_TRACE_DATA14 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_088_TP_IN_04 7 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_11 - Pinmux control register 11 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: onoff_gpio_107 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_107_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_107_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_107_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_107_ONOFF_GPIO_107 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_107_RGMII_TXD_02 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_107_TTX_REQ 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_107_UART_CTS_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_107_MTSIF0_RX_DATA_7 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_107_USB1_PWRON_SEC_ALT 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_107_TP_OUT_24 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_107_PM_GPIO_107 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: onoff_gpio_106 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_106_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_106_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_106_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_106_ONOFF_GPIO_106 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_106_RGMII_TXD_03 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_106_VO_656_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_106_UART_RTS_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_106_USB0_PWRFLT_SEC_ALT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_106_CPU_TRACE_DATA7 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_106_TP_OUT_23 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_106_PM_GPIO_106 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: onoff_gpio_105 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_ONOFF_GPIO_105 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_MII_TXEN_RGMII_TXCTL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_VO_656_7 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_UART_RTS_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_MTSIF0_RX_DATA_4 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_USB0_PWRON_SEC_ALT 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_CPU_TRACE_DATA6 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_TP_OUT_22 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_PM_GPIO_105 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: onoff_gpio_104 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_ONOFF_GPIO_104 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_RGMII_TX_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_VO_656_6 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_UART_CTS_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_MTSIF0_RX_DATA_3 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_SD_CARD0_DAT3 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_CPU_TRACE_DATA5 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_TP_OUT_21 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_PM_GPIO_104 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: onoff_gpio_103 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_ONOFF_GPIO_103 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_RGMII_RXD_00 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_VO_656_5 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_UART_CTS_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_MTSIF0_RX_SYNC 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_SD_CARD0_CLK 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_CPU_TRACE_DATA1 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_TP_OUT_20 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_PM_GPIO_103 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: onoff_gpio_102 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_ONOFF_GPIO_102 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_RGMII_RXD_01 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_VO_656_4 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_UART_RTS_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_MTSIF0_RX_DATA_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_SD_CARD0_DAT0 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_CPU_TRACE_DATA2 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_TP_OUT_19 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_PM_GPIO_102 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: onoff_gpio_101 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_101_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_101_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_101_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_101_ONOFF_GPIO_101 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_101_RGMII_RXD_02 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_101_VO_656_3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_101_SD_CARD0_DAT1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_101_CPU_TRACE_DATA3 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_101_TP_OUT_18 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_101_PM_GPIO_101 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: onoff_gpio_100 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_100_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_100_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_100_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_100_ONOFF_GPIO_100 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_100_RGMII_RXD_03 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_100_VO_656_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_100_MTSIF0_RX_DATA_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_100_SD_CARD0_DAT2 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_100_CPU_TRACE_DATA4 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_100_TP_OUT_17 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_100_PM_GPIO_100 7 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_12 - Pinmux control register 12 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: onoff_gpio_115 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_ONOFF_GPIO_115 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_MII_COL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_SPI_M_SS1B 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_MTSIF0_ATS_RESET 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_RMX_PAUSE0_ALT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_SDS_BERT_DATA 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_PKT2_VALID_ALT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_TP_OUT_28 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_PM_GPIO_115 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: onoff_gpio_114 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_ONOFF_GPIO_114 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_MII_CRS 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_SPI_M_MISO 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_MTSIF0_ATS_INC 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_RMX_VALID0_ALT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_SDS_BERT_CLK 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_PKT2_ERROR_ALT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_UART_RXD_2 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_ALT_TP_IN_02 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_PM_GPIO_114 9 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: onoff_gpio_113 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_ONOFF_GPIO_113 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_MII_TX_ERR 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_SPI_M_SS0B 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_I2S_DATA0_OUT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_RMX_DATA0_ALT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_SD_CARD0_PWR0 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_PKT2_DATA_ALT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_UART_RTS_2 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_TP_OUT_27 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_PM_GPIO_113 9 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: onoff_gpio_112 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_ONOFF_GPIO_112 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_MII_RX_ERR 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_SPI_M_MOSI 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_I2S_CLK0_OUT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_RMX_CLK0_ALT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_SD_CARD0_WPROT 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_PKT2_CLK_ALT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_UART_TXD_2 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_ALT_TP_OUT_02 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_PM_GPIO_112 9 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: onoff_gpio_111 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_111_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_111_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_111_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_111_ONOFF_GPIO_111 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_111_MII_MDC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_111_SPI_S_SS0B 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_111_MTSIF0_ATS_RESET 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_111_SD_CARD0_LED 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_111_VEC_VSYNC 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_111_PM_GPIO_111 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: onoff_gpio_110 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_110_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_110_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_110_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_110_ONOFF_GPIO_110 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_110_MII_MDIO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_110_SPI_S_MISO 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_110_MTSIF0_ATS_INC 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_110_SD_CARD0_PRES 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_110_VEC_HSYNC 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_110_PM_GPIO_110 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: onoff_gpio_109 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_109_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_109_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_109_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_109_ONOFF_GPIO_109 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_109_RGMII_TXD_00 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_109_UART_RXD_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_109_MTSIF0_RX_DATA_5 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_109_ALT_TP_IN_03 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_109_PM_GPIO_109 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: onoff_gpio_108 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_108_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_108_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_108_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_108_ONOFF_GPIO_108 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_108_RGMII_TXD_01 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_108_TTX_DATA 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_108_UART_TXD_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_108_MTSIF0_RX_DATA_6 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_108_USB1_PWRFLT_SEC_ALT 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_108_ALT_TP_OUT_03 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_108_PM_GPIO_108 7 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_13 - Pinmux control register 13 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: reserved0 [31:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_reserved0_MASK 0xffff0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_reserved0_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: onoff_gpio_124 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_124_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_124_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_124_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_124_ONOFF_GPIO_124 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_124_UART_RTS_1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_124_PM_GPIO_124 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: onoff_gpio_118 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_118_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_118_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_118_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_118_ONOFF_GPIO_118 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_118_UART_TXD_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_118_TEST_THP 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_118_ALT_TP_OUT_00 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_118_PM_GPIO_118 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: onoff_gpio_117 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_117_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_117_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_117_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_117_ONOFF_GPIO_117 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_117_UART_RXD_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_117_ALT_TP_IN_00 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_117_PM_GPIO_117 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: onoff_gpio_116 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_ONOFF_GPIO_116 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_MII_IRQ 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_SPI_M_SCK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_I2S_LR0_OUT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_RMX_SYNC0_ALT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_SD_CARD0_VOLT 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_PKT2_SYNC_ALT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_UART_CTS_2 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_TP_OUT_29 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_PM_GPIO_116 9 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_ebi_data_1_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_1_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_1_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_1_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_1_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_1_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_1_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_ebi_data_0_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_0_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_0_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_0_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_0_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_0_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_0_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_ebi_dsb_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_dsb_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_dsb_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_dsb_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_dsb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_dsb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_dsb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_ebi_tsb_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_tsb_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_tsb_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_tsb_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_tsb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_tsb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_tsb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_ebi_rdb_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_rdb_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_rdb_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_rdb_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_rdb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_rdb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_rdb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_ebi_we0b_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_we0b_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_we0b_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_we0b_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_we0b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_we0b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_we0b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_ebi_nand_rbb_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_nand_rbb_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_nand_rbb_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_nand_rbb_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_nand_rbb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_nand_rbb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_nand_rbb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_ebi_cs2b_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs2b_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs2b_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs2b_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs2b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs2b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs2b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_ebi_cs1b_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs1b_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs1b_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs1b_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs1b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs1b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs1b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_ebi_cs0b_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs0b_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs0b_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs0b_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs0b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs0b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs0b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [09:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK 0x000003ff |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_sf_wpb_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_wpb_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_wpb_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_wpb_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_wpb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_wpb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_wpb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_sf_holdb_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_holdb_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_holdb_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_holdb_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_holdb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_holdb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_holdb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_sf_mosi_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_mosi_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_mosi_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_mosi_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_mosi_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_mosi_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_mosi_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_sf_miso_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_miso_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_miso_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_miso_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_miso_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_miso_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_miso_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_sf_sck_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_sck_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_sck_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_sck_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_sck_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_sck_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_sck_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_emmc_clk_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_clk_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_clk_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_clk_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_clk_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_clk_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_clk_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_emmc_cmd_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_cmd_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_cmd_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_cmd_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_cmd_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_cmd_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_cmd_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_nand_dqs_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_dqs_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_dqs_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_dqs_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_dqs_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_dqs_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_dqs_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_nand_wpb_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_wpb_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_wpb_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_wpb_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_wpb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_wpb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_wpb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_data_7_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_7_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_7_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_7_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_7_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_7_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_7_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_data_6_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_6_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_6_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_6_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_6_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_6_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_6_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_data_5_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_5_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_5_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_5_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_5_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_5_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_5_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_data_4_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_4_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_4_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_4_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_4_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_4_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_4_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_data_3_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_3_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_3_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_3_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_3_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_3_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_3_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_data_2_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_2_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_2_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_2_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_2_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_2_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_2_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: onoff_gpio_003_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_003_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_003_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_003_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_003_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_003_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_003_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: onoff_gpio_002_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_002_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_002_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_002_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_002_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_002_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_002_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: onoff_gpio_001_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_001_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_001_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_001_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_001_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_001_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_001_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: onoff_gpio_000_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_000_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_000_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_000_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_000_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_000_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_000_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [21:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK 0x003fffff |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_018_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_018_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_018_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_018_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_018_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_018_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_018_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_017_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_017_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_017_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_017_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_017_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_017_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_017_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_016_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_016_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_016_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_016_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_016_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_016_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_016_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_015_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_015_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_015_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_015_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_015_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_015_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_015_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_014_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_014_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_014_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_014_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_014_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_014_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_014_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_013_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_013_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_013_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_013_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_013_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_013_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_013_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_012_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_012_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_012_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_012_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_012_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_012_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_012_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_011_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_011_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_011_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_011_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_011_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_011_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_011_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_010_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_010_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_010_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_010_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_010_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_010_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_010_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_009_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_009_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_009_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_009_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_009_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_009_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_009_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_008_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_008_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_008_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_008_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_008_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_008_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_008_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_007_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_007_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_007_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_007_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_007_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_007_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_007_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_006_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_006_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_006_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_006_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_006_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_006_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_006_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_005_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_005_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_005_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_005_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_005_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_005_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_005_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_004_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_004_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_004_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_004_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_004_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_004_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_004_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_033_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_033_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_033_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_033_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_033_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_033_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_033_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_032_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_032_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_032_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_032_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_032_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_032_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_032_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_031_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_031_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_031_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_031_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_031_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_031_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_031_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_030_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_030_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_030_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_030_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_030_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_030_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_030_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_029_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_029_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_029_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_029_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_029_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_029_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_029_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_028_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_028_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_028_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_028_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_028_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_028_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_028_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_027_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_027_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_027_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_027_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_027_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_027_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_027_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_026_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_026_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_026_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_026_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_026_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_026_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_026_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_025_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_025_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_025_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_025_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_025_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_025_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_025_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_024_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_024_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_024_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_024_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_024_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_024_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_024_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_023_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_023_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_023_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_023_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_023_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_023_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_023_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_022_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_022_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_022_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_022_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_022_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_022_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_022_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_021_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_021_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_021_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_021_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_021_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_021_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_021_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_020_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_020_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_020_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_020_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_020_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_020_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_020_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_019_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_019_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_019_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_019_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_019_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_019_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_019_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_048_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_048_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_048_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_048_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_048_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_048_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_048_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_047_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_047_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_047_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_047_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_047_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_047_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_047_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_046_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_046_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_046_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_046_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_046_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_046_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_046_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_045_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_045_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_045_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_045_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_045_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_045_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_045_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_044_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_044_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_044_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_044_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_044_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_044_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_044_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_043_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_043_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_043_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_043_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_043_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_043_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_043_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_042_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_042_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_042_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_042_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_042_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_042_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_042_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: reserved0 [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_040_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_040_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_040_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_040_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_040_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_040_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_040_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_039_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_039_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_039_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_039_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_039_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_039_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_039_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_038_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_038_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_038_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_038_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_038_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_038_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_038_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_037_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_037_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_037_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_037_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_037_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_037_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_037_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_036_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_036_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_036_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_036_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_036_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_036_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_036_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_035_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_035_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_035_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_035_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_035_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_035_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_035_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_034_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_034_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_034_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_034_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_034_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_034_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_034_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: onoff_gpio_098_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_098_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_098_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_098_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_098_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_098_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_098_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: reserved0 [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved0_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved0_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: onoff_rsvd_gpio_096_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_096_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_096_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_096_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_096_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_096_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_096_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: onoff_rsvd_gpio_095_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_095_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_095_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_095_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_095_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_095_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_095_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: onoff_rsvd_gpio_094_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_094_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_094_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_094_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_094_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_094_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_094_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: reserved1 [19:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved1_MASK 0x000fc000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved1_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: onoff_gpio_086_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_086_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_086_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_086_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_086_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_086_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_086_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: reserved2 [11:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved2_MASK 0x00000ff0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved2_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: onoff_gpio_050_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_050_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_050_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_050_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_050_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_050_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_050_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: onoff_gpio_049_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_049_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_049_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_049_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_049_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_049_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_049_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_113_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_113_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_113_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_113_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_113_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_113_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_113_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_112_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_112_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_112_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_112_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_112_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_112_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_112_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_111_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_111_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_111_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_111_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_111_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_111_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_111_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_110_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_110_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_110_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_110_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_110_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_110_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_110_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_109_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_109_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_109_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_109_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_109_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_109_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_109_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_108_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_108_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_108_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_108_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_108_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_108_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_108_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_107_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_107_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_107_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_107_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_107_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_107_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_107_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_106_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_106_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_106_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_106_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_106_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_106_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_106_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_105_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_105_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_105_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_105_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_105_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_105_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_105_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_104_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_104_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_104_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_104_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_104_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_104_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_104_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_103_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_103_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_103_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_103_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_103_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_103_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_103_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_102_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_102_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_102_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_102_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_102_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_102_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_102_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_101_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_101_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_101_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_101_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_101_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_101_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_101_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_100_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_100_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_100_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_100_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_100_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_100_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_100_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_099_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_099_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_099_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_099_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_099_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_099_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_099_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved0 [31:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_MASK 0xfff00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved1 [17:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_MASK 0x0003fc00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: onoff_gpio_118_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_118_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_118_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_118_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_118_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_118_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_118_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: onoff_gpio_117_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_117_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_117_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_117_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_117_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_117_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_117_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: onoff_gpio_116_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_116_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_116_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_116_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_116_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_116_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_116_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: onoff_gpio_115_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_115_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_115_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_115_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_115_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_115_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_115_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: onoff_gpio_114_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_114_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_114_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_114_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_114_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_114_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_114_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_ir_in0 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_ir_in0_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_ir_in0_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_ir_in0_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_fp_4sec_resetb [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_fp_4sec_resetb_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_fp_4sec_resetb_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_fp_4sec_resetb_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_onoff_gpio_108 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_gpio_108_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_gpio_108_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_gpio_108_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_onoff_clk_out1 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_clk_out1_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_clk_out1_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_clk_out1_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_onoff_clk_out0 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_clk_out0_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_clk_out0_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_clk_out0_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_onoff_emmc_clk [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_emmc_clk_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_emmc_clk_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_emmc_clk_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_onoff_emmc_cmd [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_emmc_cmd_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_emmc_cmd_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_emmc_cmd_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_onoff_usb0_pwron [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_usb0_pwron_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_usb0_pwron_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_usb0_pwron_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RESET_CTRL - Reset control |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK 0xfffffffe |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RESET_SOURCE_ENABLE - Reset source enable |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK 0xfffffc00 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SW_MASTER_RESET - Software master reset |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK 0xfffffffe |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *HW_RESET_EXTENSION - Hardware reset extension |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */ |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RESET_MONITOR - Reset Monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0 |
| |
| /*************************************************************************** |
| *RESET_HISTORY - Reset history |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:21] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK 0xffe00000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: mpm_reset [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_mpm_reset_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_mpm_reset_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: gen_watchdog_1_reset [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_gen_watchdog_1_reset_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_gen_watchdog_1_reset_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_gen_watchdog_1_reset_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_0_reset [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_0_reset_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_0_reset_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_1_reset [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_1_reset_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_1_reset_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_1_reset [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_1_reset_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_1_reset_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: scpu_ejtag_reset [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_1_hot_boot_reset [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_0_hot_boot_reset [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT 0 |
| |
| /*************************************************************************** |
| *SW_INIT_0_SET - Software init 0 set |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_29 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_29_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_29_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_29_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_hr_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SW_INIT_0_CLEAR - Software init 0 clear |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_29 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_29_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_29_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_29_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_hr_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SW_INIT_0_STATUS - Software init 0 status |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_29 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_29_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_29_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_29_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_hr_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_29 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_29_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_29_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_29 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_29_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_29_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_29 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_29_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_29_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *SW_INIT_1_SET - Software init 1 set |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:26] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK 0xfc000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: demod_xpt_sw_init [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_demod_xpt_sw_init_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_demod_xpt_sw_init_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_demod_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: t2_rcvr_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_t2_rcvr_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_t2_rcvr_sw_init_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_t2_rcvr_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: t2_bicm_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_t2_bicm_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_t2_bicm_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_t2_bicm_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: ufe_top_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ufe_top_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ufe_top_sw_init_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ufe_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sdio1_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sdio0_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: mpm_top_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_mpm_top_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_mpm_top_sw_init_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_mpm_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: rf4ce_top_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_rf4ce_top_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_rf4ce_top_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_rf4ce_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: avs_top_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: hdmi_aon_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_hdmi_aon_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_hdmi_aon_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_hdmi_aon_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: dfe_core_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_dfe_core_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_dfe_core_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_dfe_core_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: ds_top_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ds_top_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ds_top_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ds_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: stb_chan_top_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_stb_chan_top_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_stb_chan_top_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_stb_chan_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: aif_wb_stat_top0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_wb_stat_top0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_wb_stat_top0_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_wb_stat_top0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: aif_mdac_cal_top_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_mdac_cal_top_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_mdac_cal_top_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_mdac_cal_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds_afec0_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec0_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec0_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds1_top_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_top_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: fsk_top_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_fsk_top_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_fsk_top_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_fsk_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: leap_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_leap_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_leap_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_leap_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: vip_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vip_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vip_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vip_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: gphy_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gphy_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gphy_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gphy_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: v3d_top_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SW_INIT_1_CLEAR - Software init 1 clear |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:26] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK 0xfc000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: demod_xpt_sw_init [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_demod_xpt_sw_init_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_demod_xpt_sw_init_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_demod_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: t2_rcvr_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_t2_rcvr_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_t2_rcvr_sw_init_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_t2_rcvr_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: t2_bicm_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_t2_bicm_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_t2_bicm_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_t2_bicm_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: ufe_top_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ufe_top_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ufe_top_sw_init_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ufe_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sdio1_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sdio0_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: mpm_top_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_mpm_top_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_mpm_top_sw_init_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_mpm_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: rf4ce_top_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_rf4ce_top_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_rf4ce_top_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_rf4ce_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: avs_top_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: hdmi_aon_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_hdmi_aon_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_hdmi_aon_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_hdmi_aon_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: dfe_core_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_dfe_core_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_dfe_core_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_dfe_core_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: ds_top_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ds_top_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ds_top_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ds_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: stb_chan_top_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_stb_chan_top_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_stb_chan_top_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_stb_chan_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: aif_wb_stat_top0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_wb_stat_top0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_wb_stat_top0_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_wb_stat_top0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: aif_mdac_cal_top_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_mdac_cal_top_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_mdac_cal_top_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_mdac_cal_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds_afec0_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec0_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec0_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds1_top_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_top_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: fsk_top_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_fsk_top_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_fsk_top_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_fsk_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: leap_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_leap_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_leap_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_leap_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: vip_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vip_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vip_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vip_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: gphy_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gphy_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gphy_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gphy_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: v3d_top_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SW_INIT_1_STATUS - Software init 1 status |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:26] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK 0xfc000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: demod_xpt_sw_init [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_demod_xpt_sw_init_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_demod_xpt_sw_init_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_demod_xpt_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: t2_rcvr_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_t2_rcvr_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_t2_rcvr_sw_init_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_t2_rcvr_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: t2_bicm_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_t2_bicm_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_t2_bicm_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_t2_bicm_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: ufe_top_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ufe_top_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ufe_top_sw_init_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ufe_top_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sdio1_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sdio0_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: mpm_top_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_mpm_top_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_mpm_top_sw_init_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_mpm_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: rf4ce_top_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_rf4ce_top_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_rf4ce_top_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_rf4ce_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: avs_top_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: hdmi_aon_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_hdmi_aon_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_hdmi_aon_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_hdmi_aon_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: dfe_core_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_dfe_core_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_dfe_core_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_dfe_core_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: ds_top_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ds_top_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ds_top_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ds_top_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: stb_chan_top_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_stb_chan_top_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_stb_chan_top_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_stb_chan_top_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: aif_wb_stat_top0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_wb_stat_top0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_wb_stat_top0_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_wb_stat_top0_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: aif_mdac_cal_top_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_mdac_cal_top_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_mdac_cal_top_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_mdac_cal_top_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds_afec0_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec0_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec0_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec0_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds1_top_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_top_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: fsk_top_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_fsk_top_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_fsk_top_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_fsk_top_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: leap_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_leap_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_leap_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_leap_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: vip_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vip_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vip_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vip_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: gphy_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gphy_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gphy_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gphy_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: v3d_top_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:26] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK 0xfc000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: demod_xpt_sw_init [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_demod_xpt_sw_init_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_demod_xpt_sw_init_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: t2_rcvr_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_t2_rcvr_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_t2_rcvr_sw_init_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: t2_bicm_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_t2_bicm_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_t2_bicm_sw_init_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: ufe_top_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ufe_top_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ufe_top_sw_init_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sdio1_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sdio0_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: mpm_top_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_mpm_top_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_mpm_top_sw_init_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: rf4ce_top_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_rf4ce_top_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_rf4ce_top_sw_init_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: avs_top_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: hdmi_aon_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_hdmi_aon_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_hdmi_aon_sw_init_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: dfe_core_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_dfe_core_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_dfe_core_sw_init_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: ds_top_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ds_top_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ds_top_sw_init_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: stb_chan_top_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_stb_chan_top_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_stb_chan_top_sw_init_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: aif_wb_stat_top0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: aif_mdac_cal_top_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds_afec0_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds_afec0_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds_afec0_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds1_top_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top_sw_init_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_top_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: fsk_top_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_fsk_top_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_fsk_top_sw_init_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: leap_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_leap_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_leap_sw_init_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: vip_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vip_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vip_sw_init_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: gphy_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_gphy_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_gphy_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: v3d_top_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:26] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xfc000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: demod_xpt_sw_init [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_demod_xpt_sw_init_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_demod_xpt_sw_init_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: t2_rcvr_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_t2_rcvr_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_t2_rcvr_sw_init_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: t2_bicm_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_t2_bicm_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_t2_bicm_sw_init_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: ufe_top_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ufe_top_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ufe_top_sw_init_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sdio1_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sdio0_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: mpm_top_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_mpm_top_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_mpm_top_sw_init_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: rf4ce_top_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_rf4ce_top_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_rf4ce_top_sw_init_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: avs_top_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: hdmi_aon_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_hdmi_aon_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_hdmi_aon_sw_init_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: dfe_core_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_dfe_core_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_dfe_core_sw_init_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: ds_top_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ds_top_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ds_top_sw_init_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: stb_chan_top_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_stb_chan_top_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_stb_chan_top_sw_init_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: aif_wb_stat_top0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: aif_mdac_cal_top_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds_afec0_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds_afec0_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds_afec0_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds1_top_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top_sw_init_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_top_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: fsk_top_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_fsk_top_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_fsk_top_sw_init_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: leap_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_leap_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_leap_sw_init_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: vip_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vip_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vip_sw_init_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: gphy_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_gphy_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_gphy_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: v3d_top_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:26] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK 0xfc000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: demod_xpt_sw_init [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_demod_xpt_sw_init_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_demod_xpt_sw_init_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: t2_rcvr_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_t2_rcvr_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_t2_rcvr_sw_init_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: t2_bicm_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_t2_bicm_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_t2_bicm_sw_init_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: ufe_top_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ufe_top_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ufe_top_sw_init_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sdio1_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sdio0_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: mpm_top_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_mpm_top_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_mpm_top_sw_init_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: rf4ce_top_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_rf4ce_top_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_rf4ce_top_sw_init_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: avs_top_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: hdmi_aon_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_hdmi_aon_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_hdmi_aon_sw_init_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: dfe_core_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_dfe_core_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_dfe_core_sw_init_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: ds_top_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ds_top_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ds_top_sw_init_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: stb_chan_top_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_stb_chan_top_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_stb_chan_top_sw_init_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: aif_wb_stat_top0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: aif_mdac_cal_top_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds_afec0_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds_afec0_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds_afec0_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds1_top_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top_sw_init_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_top_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: fsk_top_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_fsk_top_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_fsk_top_sw_init_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: leap_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_leap_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_leap_sw_init_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: vip_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vip_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vip_sw_init_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: gphy_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_gphy_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_gphy_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: v3d_top_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_29 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_29_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_29_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_29_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_hr_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:26] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xfc000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: demod_xpt_sw_init [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_demod_xpt_sw_init_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_demod_xpt_sw_init_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_demod_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: t2_rcvr_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_t2_rcvr_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_t2_rcvr_sw_init_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_t2_rcvr_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: t2_bicm_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_t2_bicm_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_t2_bicm_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_t2_bicm_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: ufe_top_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ufe_top_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ufe_top_sw_init_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ufe_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sdio1_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sdio0_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: mpm_top_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_mpm_top_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_mpm_top_sw_init_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_mpm_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: rf4ce_top_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_rf4ce_top_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_rf4ce_top_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_rf4ce_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: avs_top_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: hdmi_aon_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_hdmi_aon_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_hdmi_aon_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_hdmi_aon_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: dfe_core_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_dfe_core_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_dfe_core_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_dfe_core_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: ds_top_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ds_top_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ds_top_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ds_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: stb_chan_top_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_stb_chan_top_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_stb_chan_top_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_stb_chan_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: aif_wb_stat_top0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: aif_mdac_cal_top_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds_afec0_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec0_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec0_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds1_top_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_top_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: fsk_top_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_fsk_top_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_fsk_top_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_fsk_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: leap_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_leap_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_leap_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_leap_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: vip_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vip_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vip_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vip_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: gphy_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gphy_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gphy_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gphy_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: v3d_top_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_29 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_29_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_29_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_29_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_hr_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:26] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xfc000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: demod_xpt_sw_init [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_demod_xpt_sw_init_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_demod_xpt_sw_init_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_demod_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: t2_rcvr_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_t2_rcvr_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_t2_rcvr_sw_init_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_t2_rcvr_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: t2_bicm_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_t2_bicm_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_t2_bicm_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_t2_bicm_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: ufe_top_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ufe_top_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ufe_top_sw_init_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ufe_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sdio1_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sdio0_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: mpm_top_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_mpm_top_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_mpm_top_sw_init_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_mpm_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: rf4ce_top_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_rf4ce_top_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_rf4ce_top_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_rf4ce_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: avs_top_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: hdmi_aon_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_hdmi_aon_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_hdmi_aon_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_hdmi_aon_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: dfe_core_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_dfe_core_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_dfe_core_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_dfe_core_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: ds_top_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ds_top_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ds_top_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ds_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: stb_chan_top_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_stb_chan_top_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_stb_chan_top_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_stb_chan_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: aif_wb_stat_top0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: aif_mdac_cal_top_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds_afec0_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec0_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec0_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds1_top_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_top_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: fsk_top_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_fsk_top_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_fsk_top_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_fsk_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: leap_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_leap_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_leap_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_leap_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: vip_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vip_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vip_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vip_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: gphy_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gphy_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gphy_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gphy_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: v3d_top_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UNCLEARED_SCRATCH - Scratch register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SPARE_CTRL - Spare control bits reserved for future use |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TEST_PORT_CTRL - Test port control |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_09 9 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_ICID_TP_OUT 14 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK 0x0ffffc00 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK 0x00000180 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK 0x0000007f |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 0x0000007f |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DS_TOP 1 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_UFE_TOP 2 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_T2_BICM 3 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_T2_RCVR 4 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MPM_TOP 9 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RF4CE_TOP 10 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DFE_CORE 11 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIF_MDAC_CAL_TOP 12 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIF_WB_SAT_TOP 13 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_STB_CHAN_TOP 15 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS 16 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK 17 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON 18 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF 19 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVS 20 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP 21 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC 22 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO 23 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HVD0 25 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA0 28 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT 30 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0 31 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET1 34 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0 38 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MOCA 40 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_V3D_TOP 41 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RFM 42 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_FSK_TOP 43 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_R 44 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_T 45 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_R 46 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_T 47 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS_AFEC 60 |
| |
| /*************************************************************************** |
| *TEST_PORT_OUT_PEEK - Testport peek register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_PORT_OUT_POKE - Testport poke register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TEST_PORT_IN_PEEK - Testport peek register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_PORT_IN_POKE - Testport poke register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EJTAG_INPUT_EN - EJTAG input bus enables |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:10] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK 0xfffffc00 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [09:00] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK 0x000003ff |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_CPU_ONE_HOT 2 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA0_CPU_ONE_HOT 4 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA1_CPU_ONE_HOT 8 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_AVS_CPU_ONE_HOT 16 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_LEAP_CPU_ONE_HOT 32 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_RF4CE_CPU_ONE_HOT 64 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MPM_CPU_ONE_HOT 128 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SCPU_CPU_ONE_HOT 256 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 512 |
| |
| /*************************************************************************** |
| *EJTAG_OUTPUT_SEL - EJTAG output select |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:04] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK 0xfffffff0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_CPU 1 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA0_CPU 2 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA1_CPU 3 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_AVS_CPU 4 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_LEAP_CPU 5 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_RF4CE_CPU 6 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MPM_CPU 7 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SCPU_CPU 8 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 9 |
| |
| /*************************************************************************** |
| *VTRAP_CTRL - VTRAP Control |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:23] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK 0xff800000 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_1_threshold [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_1_threshold [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_0_threshold [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_1_threshold [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_0_threshold [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [17:05] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x0003ffe0 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_1_status_clear [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_0_status_clear [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_1_status_clear [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_0_status_clear [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_1_status_clear [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VTRAP_STATUS - VTRAP Status |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:05] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK 0xffffffe0 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_1_status [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_0_status [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_1_status [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_0_status [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_1_status [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UART_ROUTER_SEL_0 - UART Router select 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: reserved0 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_reserved0_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_reserved0_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_5_cpu_sel [29:25] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_MASK 0x3e000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SID 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_AVS_TOP 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_LEAP 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_RF4CE_TOP 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SCPU 8 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_4_cpu_sel [24:20] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_MASK 0x01f00000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SID 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_AVS_TOP 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_LEAP 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_RF4CE_TOP 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SCPU 8 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_3_cpu_sel [19:15] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_MASK 0x000f8000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SID 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_AVS_TOP 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_LEAP 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_RF4CE_TOP 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SCPU 8 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_2_cpu_sel [14:10] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_MASK 0x00007c00 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SID 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_AVS_TOP 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_LEAP 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_RF4CE_TOP 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SCPU 8 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_1_cpu_sel [09:05] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_MASK 0x000003e0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SID 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_AVS_TOP 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_LEAP 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_RF4CE_TOP 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SCPU 8 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_0_cpu_sel [04:00] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_MASK 0x0000001f |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SID 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_AVS_TOP 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_LEAP 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_RF4CE_TOP 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SCPU 8 |
| |
| /*************************************************************************** |
| *UART_ROUTER_SEL_1 - UART Router select 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: reserved0 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_reserved0_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_reserved0_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_11_cpu_sel [29:25] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_MASK 0x3e000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SID 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_AVS_TOP 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_LEAP 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_RF4CE_TOP 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SCPU 8 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_10_cpu_sel [24:20] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_MASK 0x01f00000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SID 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_AVS_TOP 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_LEAP 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_RF4CE_TOP 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SCPU 8 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_9_cpu_sel [19:15] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_MASK 0x000f8000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SID 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_AVS_TOP 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_LEAP 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_RF4CE_TOP 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SCPU 8 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_8_cpu_sel [14:10] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_MASK 0x00007c00 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SID 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_AVS_TOP 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_LEAP 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_RF4CE_TOP 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SCPU 8 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_7_cpu_sel [09:05] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_MASK 0x000003e0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SID 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_AVS_TOP 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_LEAP 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_RF4CE_TOP 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SCPU 8 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_6_cpu_sel [04:00] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_MASK 0x0000001f |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SID 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_AVS_TOP 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_LEAP 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_RF4CE_TOP 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SCPU 8 |
| |
| /*************************************************************************** |
| *SSP_CONFIG - Serial Slave Port configuration register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK 0xfffff800 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK 0x00000780 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT 0x00000004 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK 0x00000078 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SERS_REV - SERS Revision Register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK 0xffff0000 |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK 0x0000ff00 |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SERS_CFG - SERS Configuration Register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK 0xe0000000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode 1 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT 0x00000000 |
| |
| /* union - case mapped_buffer_mode [26:08] */ |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0x00000000 |
| |
| /* union - case cmd_fifo_mode [26:08] */ |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK 0x07c00000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK 0x003e0000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 0x0000001f |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 0x00000010 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK 0x000000fe |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SERS_CMD_BUF_%i - Host Serial Write Command Buffer |
| ***************************************************************************/ |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE 0x00404428 |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END 7 |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE 32 |
| |
| /*************************************************************************** |
| *SERS_CMD_BUF_%i - Host Serial Write Command Buffer |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT 0 |
| |
| |
| /*************************************************************************** |
| *SERS_STAT_BUF_%i - Host Serial Read Status Buffer |
| ***************************************************************************/ |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE 0x00404448 |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END 1 |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE 32 |
| |
| /*************************************************************************** |
| *SERS_STAT_BUF_%i - Host Serial Read Status Buffer |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT 0 |
| |
| |
| /*************************************************************************** |
| *RO_TEST_BLOCK_SEL - Block select for RO testmode |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:18] */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK 0xfffc0000 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [17:14] */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0003c000 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_CMOS 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_CMOS 1 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_CMOS 2 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_NMOS 3 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_NMOS 4 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_NMOS 5 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_PMOS 6 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_PMOS 7 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_PMOS 8 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_CMOS 9 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_NMOS 10 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_PMOS 11 |
| |
| /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_en [13:02] */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_MASK 0x00003ffc |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_DISABLE_RO 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_CMOS_ONE_HOT 1 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_CMOS_ONE_HOT 2 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_CMOS_ONE_HOT 4 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_NMOS_ONE_HOT 8 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_NMOS_ONE_HOT 16 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_NMOS_ONE_HOT 32 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_PMOS_ONE_HOT 64 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_PMOS_ONE_HOT 128 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_PMOS_ONE_HOT 256 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_CMOS_ONE_HOT 512 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_NMOS_ONE_HOT 1024 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_PMOS_ONE_HOT 2048 |
| |
| /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3 |
| |
| /*************************************************************************** |
| *TEST_CONFIGURATION - Test configuration |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK 0xfffffff0 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OTP_OPTION_TEST_2 - OTP option test register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_16 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_16_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_16_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_16_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_15 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_15_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_15_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_15_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_14 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_14_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_14_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_14_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_13 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_13_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_13_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_12 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_12_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_12_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_12_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_11 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_11_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_11_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_10 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_10_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_10_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_10_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_9 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_9_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_9_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_9_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_8 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_8_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_8_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_8_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_7 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_7_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_7_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_7_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_6 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_6_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_6_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_6_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_5 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_5_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_5_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_5_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_4 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_4_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_4_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_3 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_3_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_3_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_2 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_2_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_2_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_2_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_1 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_1_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_1_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_1_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_0 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_0_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_0_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_0_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_reserved_8 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_8_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_8_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_8_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_audio_2_disable [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_audio_2_disable_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_audio_2_disable_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_audio_2_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_mhl_mpm_flash_disable [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_mpm_flash_disable_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_mpm_flash_disable_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_mpm_flash_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_mhl_mpm_disable [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_mpm_disable_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_mpm_disable_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_mpm_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_mhl_disable [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_disable_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_disable_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_gphy_disable [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_gphy_disable_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_gphy_disable_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_gphy_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_hevc_disable [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_hevc_disable_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_hevc_disable_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_hevc_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_dvbt2_disable [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbt2_disable_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbt2_disable_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbt2_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_dvbt_disable [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbt_disable_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbt_disable_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbt_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_isdbt_disable [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_isdbt_disable_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_isdbt_disable_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_isdbt_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_dfe_disable [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dfe_disable_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dfe_disable_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dfe_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_dvbc2_disable [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbc2_disable_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbc2_disable_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbc2_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_dvbc_disable [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbc_disable_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbc_disable_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbc_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_sds_channel_disable [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_sds_channel_disable_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_sds_channel_disable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_sds_channel_disable_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OTP_OPTION_STATUS_2 - OTP option status register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_16 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_16_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_16_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_16_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_15 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_15_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_15_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_15_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_14 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_14_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_14_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_14_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_13 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_13_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_13_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_12 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_12_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_12_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_12_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_11 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_11_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_11_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_10 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_10_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_10_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_10_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_9 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_9_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_9_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_9_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_8 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_8_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_8_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_8_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_7 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_7_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_7_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_7_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_6 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_6_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_6_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_6_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_5 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_5_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_5_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_5_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_4 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_4_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_4_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_3 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_3_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_3_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_2 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_2_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_2_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_2_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_1 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_1_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_1_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_1_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_0 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_0_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_0_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_0_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_reserved_8 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_reserved_8_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_reserved_8_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_audio_2_disable [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_audio_2_disable_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_audio_2_disable_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_mhl_mpm_flash_disable [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_mhl_mpm_flash_disable_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_mhl_mpm_flash_disable_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_mhl_mpm_disable [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_mhl_mpm_disable_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_mhl_mpm_disable_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_mhl_disable [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_mhl_disable_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_mhl_disable_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_gphy_disable [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_gphy_disable_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_gphy_disable_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_hevc_disable [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_hevc_disable_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_hevc_disable_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_dvbt2_disable [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_dvbt2_disable_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_dvbt2_disable_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_dvbt_disable [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_dvbt_disable_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_dvbt_disable_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_isdbt_disable [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_isdbt_disable_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_isdbt_disable_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_dfe_disable [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_dfe_disable_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_dfe_disable_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_dvbc2_disable [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_dvbc2_disable_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_dvbc2_disable_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_dvbc_disable [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_dvbc_disable_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_dvbc_disable_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_sds_channel_disable [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_sds_channel_disable_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_sds_channel_disable_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_6 - General control register 6 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_6 :: reserved0 [31:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_reserved0_MASK 0xfffffffe |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_reserved0_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_6 :: demod_xpt_tb_disable [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_demod_xpt_tb_disable_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_demod_xpt_tb_disable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_demod_xpt_tb_disable_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_7 - General control register 7 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_7 :: demod_xpt_chip_signature [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7_demod_xpt_chip_signature_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7_demod_xpt_chip_signature_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7_demod_xpt_chip_signature_DEFAULT 0x00000000 |
| |
| #endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */ |
| |
| /* End of File */ |
