| config USB_DWC2 |
| tristate "DesignWare USB2 DRD Core Support" |
| depends on USB |
| help |
| Say Y or M here if your system has a Dual Role HighSpeed |
| USB controller based on the DesignWare HSOTG IP Core. |
| |
| If you choose to build this driver as dynamically linked |
| modules, the core module will be called dwc2.ko, the |
| PCI bus interface module (if you have a PCI bus system) |
| will be called dwc2_pci.ko and the platform interface module |
| (for controllers directly connected to the CPU) will be called |
| dwc2_platform.ko. |
| |
| NOTE: This driver at present only implements the Host mode |
| of the controller. The existing s3c-hsotg driver supports |
| Peripheral mode, but only for the Samsung S3C platforms. |
| There are plans to merge the s3c-hsotg driver with this |
| driver in the near future to create a dual-role driver. |
| |
| if USB_DWC2 |
| |
| config USB_DWC2_DEBUG |
| bool "Enable Debugging Messages" |
| help |
| Say Y here to enable debugging messages in the DWC2 Driver. |
| |
| config USB_DWC2_VERBOSE |
| bool "Enable Verbose Debugging Messages" |
| depends on USB_DWC2_DEBUG |
| help |
| Say Y here to enable verbose debugging messages in the DWC2 Driver. |
| WARNING: Enabling this will quickly fill your message log. |
| If in doubt, say N. |
| |
| config USB_DWC2_TRACK_MISSED_SOFS |
| bool "Enable Missed SOF Tracking" |
| help |
| Say Y here to enable logging of missed SOF events to the dmesg log. |
| WARNING: This feature is still experimental. |
| If in doubt, say N. |
| |
| config USB_DWC2_DEBUG_PERIODIC |
| bool "Enable Debugging Messages For Periodic Transfers" |
| depends on USB_DWC2_DEBUG || USB_DWC2_VERBOSE |
| default y |
| help |
| Say N here to disable (verbose) debugging messages to be |
| logged for periodic transfers. This allows better debugging of |
| non-periodic transfers, but of course the debug logs will be |
| incomplete. Note that this also disables some debug messages |
| for which the transfer type cannot be deduced. |
| endif |
