| /* |
| * Copyright (c) 2008, 2009, 2010 QLogic Corporation. All rights reserved. |
| * |
| * This software is available to you under a choice of one of two |
| * licenses. You may choose to be licensed under the terms of the GNU |
| * General Public License (GPL) Version 2, available from the file |
| * COPYING in the main directory of this source tree, or the |
| * OpenIB.org BSD license below: |
| * |
| * Redistribution and use in source and binary forms, with or |
| * without modification, are permitted provided that the following |
| * conditions are met: |
| * |
| * - Redistributions of source code must retain the above |
| * copyright notice, this list of conditions and the following |
| * disclaimer. |
| * |
| * - Redistributions in binary form must reproduce the above |
| * copyright notice, this list of conditions and the following |
| * disclaimer in the documentation and/or other materials |
| * provided with the distribution. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| * SOFTWARE. |
| */ |
| |
| /* This file is mechanically generated from RTL. Any hand-edits will be lost! */ |
| |
| #define QIB_7322_Revision_OFFS 0x0 |
| #define QIB_7322_Revision_DEF 0x0000000002010601 |
| #define QIB_7322_Revision_R_Simulator_LSB 0x3F |
| #define QIB_7322_Revision_R_Simulator_MSB 0x3F |
| #define QIB_7322_Revision_R_Simulator_RMASK 0x1 |
| #define QIB_7322_Revision_R_Emulation_LSB 0x3E |
| #define QIB_7322_Revision_R_Emulation_MSB 0x3E |
| #define QIB_7322_Revision_R_Emulation_RMASK 0x1 |
| #define QIB_7322_Revision_R_Emulation_Revcode_LSB 0x28 |
| #define QIB_7322_Revision_R_Emulation_Revcode_MSB 0x3D |
| #define QIB_7322_Revision_R_Emulation_Revcode_RMASK 0x3FFFFF |
| #define QIB_7322_Revision_BoardID_LSB 0x20 |
| #define QIB_7322_Revision_BoardID_MSB 0x27 |
| #define QIB_7322_Revision_BoardID_RMASK 0xFF |
| #define QIB_7322_Revision_R_SW_LSB 0x18 |
| #define QIB_7322_Revision_R_SW_MSB 0x1F |
| #define QIB_7322_Revision_R_SW_RMASK 0xFF |
| #define QIB_7322_Revision_R_Arch_LSB 0x10 |
| #define QIB_7322_Revision_R_Arch_MSB 0x17 |
| #define QIB_7322_Revision_R_Arch_RMASK 0xFF |
| #define QIB_7322_Revision_R_ChipRevMajor_LSB 0x8 |
| #define QIB_7322_Revision_R_ChipRevMajor_MSB 0xF |
| #define QIB_7322_Revision_R_ChipRevMajor_RMASK 0xFF |
| #define QIB_7322_Revision_R_ChipRevMinor_LSB 0x0 |
| #define QIB_7322_Revision_R_ChipRevMinor_MSB 0x7 |
| #define QIB_7322_Revision_R_ChipRevMinor_RMASK 0xFF |
| |
| #define QIB_7322_Control_OFFS 0x8 |
| #define QIB_7322_Control_DEF 0x0000000000000000 |
| #define QIB_7322_Control_PCIECplQDiagEn_LSB 0x6 |
| #define QIB_7322_Control_PCIECplQDiagEn_MSB 0x6 |
| #define QIB_7322_Control_PCIECplQDiagEn_RMASK 0x1 |
| #define QIB_7322_Control_PCIEPostQDiagEn_LSB 0x5 |
| #define QIB_7322_Control_PCIEPostQDiagEn_MSB 0x5 |
| #define QIB_7322_Control_PCIEPostQDiagEn_RMASK 0x1 |
| #define QIB_7322_Control_SDmaDescFetchPriorityEn_LSB 0x4 |
| #define QIB_7322_Control_SDmaDescFetchPriorityEn_MSB 0x4 |
| #define QIB_7322_Control_SDmaDescFetchPriorityEn_RMASK 0x1 |
| #define QIB_7322_Control_PCIERetryBufDiagEn_LSB 0x3 |
| #define QIB_7322_Control_PCIERetryBufDiagEn_MSB 0x3 |
| #define QIB_7322_Control_PCIERetryBufDiagEn_RMASK 0x1 |
| #define QIB_7322_Control_FreezeMode_LSB 0x1 |
| #define QIB_7322_Control_FreezeMode_MSB 0x1 |
| #define QIB_7322_Control_FreezeMode_RMASK 0x1 |
| #define QIB_7322_Control_SyncReset_LSB 0x0 |
| #define QIB_7322_Control_SyncReset_MSB 0x0 |
| #define QIB_7322_Control_SyncReset_RMASK 0x1 |
| |
| #define QIB_7322_PageAlign_OFFS 0x10 |
| #define QIB_7322_PageAlign_DEF 0x0000000000001000 |
| |
| #define QIB_7322_ContextCnt_OFFS 0x18 |
| #define QIB_7322_ContextCnt_DEF 0x0000000000000012 |
| |
| #define QIB_7322_Scratch_OFFS 0x20 |
| #define QIB_7322_Scratch_DEF 0x0000000000000000 |
| |
| #define QIB_7322_CntrRegBase_OFFS 0x28 |
| #define QIB_7322_CntrRegBase_DEF 0x0000000000011000 |
| |
| #define QIB_7322_SendRegBase_OFFS 0x30 |
| #define QIB_7322_SendRegBase_DEF 0x0000000000003000 |
| |
| #define QIB_7322_UserRegBase_OFFS 0x38 |
| #define QIB_7322_UserRegBase_DEF 0x0000000000200000 |
| |
| #define QIB_7322_IntMask_OFFS 0x68 |
| #define QIB_7322_IntMask_DEF 0x0000000000000000 |
| #define QIB_7322_IntMask_SDmaIntMask_1_LSB 0x3F |
| #define QIB_7322_IntMask_SDmaIntMask_1_MSB 0x3F |
| #define QIB_7322_IntMask_SDmaIntMask_1_RMASK 0x1 |
| #define QIB_7322_IntMask_SDmaIntMask_0_LSB 0x3E |
| #define QIB_7322_IntMask_SDmaIntMask_0_MSB 0x3E |
| #define QIB_7322_IntMask_SDmaIntMask_0_RMASK 0x1 |
| #define QIB_7322_IntMask_SDmaProgressIntMask_1_LSB 0x3D |
| #define QIB_7322_IntMask_SDmaProgressIntMask_1_MSB 0x3D |
| #define QIB_7322_IntMask_SDmaProgressIntMask_1_RMASK 0x1 |
| #define QIB_7322_IntMask_SDmaProgressIntMask_0_LSB 0x3C |
| #define QIB_7322_IntMask_SDmaProgressIntMask_0_MSB 0x3C |
| #define QIB_7322_IntMask_SDmaProgressIntMask_0_RMASK 0x1 |
| #define QIB_7322_IntMask_SDmaIdleIntMask_1_LSB 0x3B |
| #define QIB_7322_IntMask_SDmaIdleIntMask_1_MSB 0x3B |
| #define QIB_7322_IntMask_SDmaIdleIntMask_1_RMASK 0x1 |
| #define QIB_7322_IntMask_SDmaIdleIntMask_0_LSB 0x3A |
| #define QIB_7322_IntMask_SDmaIdleIntMask_0_MSB 0x3A |
| #define QIB_7322_IntMask_SDmaIdleIntMask_0_RMASK 0x1 |
| #define QIB_7322_IntMask_SDmaCleanupDoneMask_1_LSB 0x39 |
| #define QIB_7322_IntMask_SDmaCleanupDoneMask_1_MSB 0x39 |
| #define QIB_7322_IntMask_SDmaCleanupDoneMask_1_RMASK 0x1 |
| #define QIB_7322_IntMask_SDmaCleanupDoneMask_0_LSB 0x38 |
| #define QIB_7322_IntMask_SDmaCleanupDoneMask_0_MSB 0x38 |
| #define QIB_7322_IntMask_SDmaCleanupDoneMask_0_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvUrg17IntMask_LSB 0x31 |
| #define QIB_7322_IntMask_RcvUrg17IntMask_MSB 0x31 |
| #define QIB_7322_IntMask_RcvUrg17IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvUrg16IntMask_LSB 0x30 |
| #define QIB_7322_IntMask_RcvUrg16IntMask_MSB 0x30 |
| #define QIB_7322_IntMask_RcvUrg16IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvUrg15IntMask_LSB 0x2F |
| #define QIB_7322_IntMask_RcvUrg15IntMask_MSB 0x2F |
| #define QIB_7322_IntMask_RcvUrg15IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvUrg14IntMask_LSB 0x2E |
| #define QIB_7322_IntMask_RcvUrg14IntMask_MSB 0x2E |
| #define QIB_7322_IntMask_RcvUrg14IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvUrg13IntMask_LSB 0x2D |
| #define QIB_7322_IntMask_RcvUrg13IntMask_MSB 0x2D |
| #define QIB_7322_IntMask_RcvUrg13IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvUrg12IntMask_LSB 0x2C |
| #define QIB_7322_IntMask_RcvUrg12IntMask_MSB 0x2C |
| #define QIB_7322_IntMask_RcvUrg12IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvUrg11IntMask_LSB 0x2B |
| #define QIB_7322_IntMask_RcvUrg11IntMask_MSB 0x2B |
| #define QIB_7322_IntMask_RcvUrg11IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvUrg10IntMask_LSB 0x2A |
| #define QIB_7322_IntMask_RcvUrg10IntMask_MSB 0x2A |
| #define QIB_7322_IntMask_RcvUrg10IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvUrg9IntMask_LSB 0x29 |
| #define QIB_7322_IntMask_RcvUrg9IntMask_MSB 0x29 |
| #define QIB_7322_IntMask_RcvUrg9IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvUrg8IntMask_LSB 0x28 |
| #define QIB_7322_IntMask_RcvUrg8IntMask_MSB 0x28 |
| #define QIB_7322_IntMask_RcvUrg8IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvUrg7IntMask_LSB 0x27 |
| #define QIB_7322_IntMask_RcvUrg7IntMask_MSB 0x27 |
| #define QIB_7322_IntMask_RcvUrg7IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvUrg6IntMask_LSB 0x26 |
| #define QIB_7322_IntMask_RcvUrg6IntMask_MSB 0x26 |
| #define QIB_7322_IntMask_RcvUrg6IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvUrg5IntMask_LSB 0x25 |
| #define QIB_7322_IntMask_RcvUrg5IntMask_MSB 0x25 |
| #define QIB_7322_IntMask_RcvUrg5IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvUrg4IntMask_LSB 0x24 |
| #define QIB_7322_IntMask_RcvUrg4IntMask_MSB 0x24 |
| #define QIB_7322_IntMask_RcvUrg4IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvUrg3IntMask_LSB 0x23 |
| #define QIB_7322_IntMask_RcvUrg3IntMask_MSB 0x23 |
| #define QIB_7322_IntMask_RcvUrg3IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvUrg2IntMask_LSB 0x22 |
| #define QIB_7322_IntMask_RcvUrg2IntMask_MSB 0x22 |
| #define QIB_7322_IntMask_RcvUrg2IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvUrg1IntMask_LSB 0x21 |
| #define QIB_7322_IntMask_RcvUrg1IntMask_MSB 0x21 |
| #define QIB_7322_IntMask_RcvUrg1IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvUrg0IntMask_LSB 0x20 |
| #define QIB_7322_IntMask_RcvUrg0IntMask_MSB 0x20 |
| #define QIB_7322_IntMask_RcvUrg0IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_ErrIntMask_1_LSB 0x1F |
| #define QIB_7322_IntMask_ErrIntMask_1_MSB 0x1F |
| #define QIB_7322_IntMask_ErrIntMask_1_RMASK 0x1 |
| #define QIB_7322_IntMask_ErrIntMask_0_LSB 0x1E |
| #define QIB_7322_IntMask_ErrIntMask_0_MSB 0x1E |
| #define QIB_7322_IntMask_ErrIntMask_0_RMASK 0x1 |
| #define QIB_7322_IntMask_ErrIntMask_LSB 0x1D |
| #define QIB_7322_IntMask_ErrIntMask_MSB 0x1D |
| #define QIB_7322_IntMask_ErrIntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_AssertGPIOIntMask_LSB 0x1C |
| #define QIB_7322_IntMask_AssertGPIOIntMask_MSB 0x1C |
| #define QIB_7322_IntMask_AssertGPIOIntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_SendDoneIntMask_1_LSB 0x19 |
| #define QIB_7322_IntMask_SendDoneIntMask_1_MSB 0x19 |
| #define QIB_7322_IntMask_SendDoneIntMask_1_RMASK 0x1 |
| #define QIB_7322_IntMask_SendDoneIntMask_0_LSB 0x18 |
| #define QIB_7322_IntMask_SendDoneIntMask_0_MSB 0x18 |
| #define QIB_7322_IntMask_SendDoneIntMask_0_RMASK 0x1 |
| #define QIB_7322_IntMask_SendBufAvailIntMask_LSB 0x17 |
| #define QIB_7322_IntMask_SendBufAvailIntMask_MSB 0x17 |
| #define QIB_7322_IntMask_SendBufAvailIntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvAvail17IntMask_LSB 0x11 |
| #define QIB_7322_IntMask_RcvAvail17IntMask_MSB 0x11 |
| #define QIB_7322_IntMask_RcvAvail17IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvAvail16IntMask_LSB 0x10 |
| #define QIB_7322_IntMask_RcvAvail16IntMask_MSB 0x10 |
| #define QIB_7322_IntMask_RcvAvail16IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvAvail15IntMask_LSB 0xF |
| #define QIB_7322_IntMask_RcvAvail15IntMask_MSB 0xF |
| #define QIB_7322_IntMask_RcvAvail15IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvAvail14IntMask_LSB 0xE |
| #define QIB_7322_IntMask_RcvAvail14IntMask_MSB 0xE |
| #define QIB_7322_IntMask_RcvAvail14IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvAvail13IntMask_LSB 0xD |
| #define QIB_7322_IntMask_RcvAvail13IntMask_MSB 0xD |
| #define QIB_7322_IntMask_RcvAvail13IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvAvail12IntMask_LSB 0xC |
| #define QIB_7322_IntMask_RcvAvail12IntMask_MSB 0xC |
| #define QIB_7322_IntMask_RcvAvail12IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvAvail11IntMask_LSB 0xB |
| #define QIB_7322_IntMask_RcvAvail11IntMask_MSB 0xB |
| #define QIB_7322_IntMask_RcvAvail11IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvAvail10IntMask_LSB 0xA |
| #define QIB_7322_IntMask_RcvAvail10IntMask_MSB 0xA |
| #define QIB_7322_IntMask_RcvAvail10IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvAvail9IntMask_LSB 0x9 |
| #define QIB_7322_IntMask_RcvAvail9IntMask_MSB 0x9 |
| #define QIB_7322_IntMask_RcvAvail9IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvAvail8IntMask_LSB 0x8 |
| #define QIB_7322_IntMask_RcvAvail8IntMask_MSB 0x8 |
| #define QIB_7322_IntMask_RcvAvail8IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvAvail7IntMask_LSB 0x7 |
| #define QIB_7322_IntMask_RcvAvail7IntMask_MSB 0x7 |
| #define QIB_7322_IntMask_RcvAvail7IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvAvail6IntMask_LSB 0x6 |
| #define QIB_7322_IntMask_RcvAvail6IntMask_MSB 0x6 |
| #define QIB_7322_IntMask_RcvAvail6IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvAvail5IntMask_LSB 0x5 |
| #define QIB_7322_IntMask_RcvAvail5IntMask_MSB 0x5 |
| #define QIB_7322_IntMask_RcvAvail5IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvAvail4IntMask_LSB 0x4 |
| #define QIB_7322_IntMask_RcvAvail4IntMask_MSB 0x4 |
| #define QIB_7322_IntMask_RcvAvail4IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvAvail3IntMask_LSB 0x3 |
| #define QIB_7322_IntMask_RcvAvail3IntMask_MSB 0x3 |
| #define QIB_7322_IntMask_RcvAvail3IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvAvail2IntMask_LSB 0x2 |
| #define QIB_7322_IntMask_RcvAvail2IntMask_MSB 0x2 |
| #define QIB_7322_IntMask_RcvAvail2IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvAvail1IntMask_LSB 0x1 |
| #define QIB_7322_IntMask_RcvAvail1IntMask_MSB 0x1 |
| #define QIB_7322_IntMask_RcvAvail1IntMask_RMASK 0x1 |
| #define QIB_7322_IntMask_RcvAvail0IntMask_LSB 0x0 |
| #define QIB_7322_IntMask_RcvAvail0IntMask_MSB 0x0 |
| #define QIB_7322_IntMask_RcvAvail0IntMask_RMASK 0x1 |
| |
| #define QIB_7322_IntStatus_OFFS 0x70 |
| #define QIB_7322_IntStatus_DEF 0x0000000000000000 |
| #define QIB_7322_IntStatus_SDmaInt_1_LSB 0x3F |
| #define QIB_7322_IntStatus_SDmaInt_1_MSB 0x3F |
| #define QIB_7322_IntStatus_SDmaInt_1_RMASK 0x1 |
| #define QIB_7322_IntStatus_SDmaInt_0_LSB 0x3E |
| #define QIB_7322_IntStatus_SDmaInt_0_MSB 0x3E |
| #define QIB_7322_IntStatus_SDmaInt_0_RMASK 0x1 |
| #define QIB_7322_IntStatus_SDmaProgressInt_1_LSB 0x3D |
| #define QIB_7322_IntStatus_SDmaProgressInt_1_MSB 0x3D |
| #define QIB_7322_IntStatus_SDmaProgressInt_1_RMASK 0x1 |
| #define QIB_7322_IntStatus_SDmaProgressInt_0_LSB 0x3C |
| #define QIB_7322_IntStatus_SDmaProgressInt_0_MSB 0x3C |
| #define QIB_7322_IntStatus_SDmaProgressInt_0_RMASK 0x1 |
| #define QIB_7322_IntStatus_SDmaIdleInt_1_LSB 0x3B |
| #define QIB_7322_IntStatus_SDmaIdleInt_1_MSB 0x3B |
| #define QIB_7322_IntStatus_SDmaIdleInt_1_RMASK 0x1 |
| #define QIB_7322_IntStatus_SDmaIdleInt_0_LSB 0x3A |
| #define QIB_7322_IntStatus_SDmaIdleInt_0_MSB 0x3A |
| #define QIB_7322_IntStatus_SDmaIdleInt_0_RMASK 0x1 |
| #define QIB_7322_IntStatus_SDmaCleanupDone_1_LSB 0x39 |
| #define QIB_7322_IntStatus_SDmaCleanupDone_1_MSB 0x39 |
| #define QIB_7322_IntStatus_SDmaCleanupDone_1_RMASK 0x1 |
| #define QIB_7322_IntStatus_SDmaCleanupDone_0_LSB 0x38 |
| #define QIB_7322_IntStatus_SDmaCleanupDone_0_MSB 0x38 |
| #define QIB_7322_IntStatus_SDmaCleanupDone_0_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvUrg17_LSB 0x31 |
| #define QIB_7322_IntStatus_RcvUrg17_MSB 0x31 |
| #define QIB_7322_IntStatus_RcvUrg17_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvUrg16_LSB 0x30 |
| #define QIB_7322_IntStatus_RcvUrg16_MSB 0x30 |
| #define QIB_7322_IntStatus_RcvUrg16_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvUrg15_LSB 0x2F |
| #define QIB_7322_IntStatus_RcvUrg15_MSB 0x2F |
| #define QIB_7322_IntStatus_RcvUrg15_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvUrg14_LSB 0x2E |
| #define QIB_7322_IntStatus_RcvUrg14_MSB 0x2E |
| #define QIB_7322_IntStatus_RcvUrg14_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvUrg13_LSB 0x2D |
| #define QIB_7322_IntStatus_RcvUrg13_MSB 0x2D |
| #define QIB_7322_IntStatus_RcvUrg13_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvUrg12_LSB 0x2C |
| #define QIB_7322_IntStatus_RcvUrg12_MSB 0x2C |
| #define QIB_7322_IntStatus_RcvUrg12_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvUrg11_LSB 0x2B |
| #define QIB_7322_IntStatus_RcvUrg11_MSB 0x2B |
| #define QIB_7322_IntStatus_RcvUrg11_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvUrg10_LSB 0x2A |
| #define QIB_7322_IntStatus_RcvUrg10_MSB 0x2A |
| #define QIB_7322_IntStatus_RcvUrg10_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvUrg9_LSB 0x29 |
| #define QIB_7322_IntStatus_RcvUrg9_MSB 0x29 |
| #define QIB_7322_IntStatus_RcvUrg9_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvUrg8_LSB 0x28 |
| #define QIB_7322_IntStatus_RcvUrg8_MSB 0x28 |
| #define QIB_7322_IntStatus_RcvUrg8_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvUrg7_LSB 0x27 |
| #define QIB_7322_IntStatus_RcvUrg7_MSB 0x27 |
| #define QIB_7322_IntStatus_RcvUrg7_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvUrg6_LSB 0x26 |
| #define QIB_7322_IntStatus_RcvUrg6_MSB 0x26 |
| #define QIB_7322_IntStatus_RcvUrg6_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvUrg5_LSB 0x25 |
| #define QIB_7322_IntStatus_RcvUrg5_MSB 0x25 |
| #define QIB_7322_IntStatus_RcvUrg5_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvUrg4_LSB 0x24 |
| #define QIB_7322_IntStatus_RcvUrg4_MSB 0x24 |
| #define QIB_7322_IntStatus_RcvUrg4_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvUrg3_LSB 0x23 |
| #define QIB_7322_IntStatus_RcvUrg3_MSB 0x23 |
| #define QIB_7322_IntStatus_RcvUrg3_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvUrg2_LSB 0x22 |
| #define QIB_7322_IntStatus_RcvUrg2_MSB 0x22 |
| #define QIB_7322_IntStatus_RcvUrg2_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvUrg1_LSB 0x21 |
| #define QIB_7322_IntStatus_RcvUrg1_MSB 0x21 |
| #define QIB_7322_IntStatus_RcvUrg1_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvUrg0_LSB 0x20 |
| #define QIB_7322_IntStatus_RcvUrg0_MSB 0x20 |
| #define QIB_7322_IntStatus_RcvUrg0_RMASK 0x1 |
| #define QIB_7322_IntStatus_Err_1_LSB 0x1F |
| #define QIB_7322_IntStatus_Err_1_MSB 0x1F |
| #define QIB_7322_IntStatus_Err_1_RMASK 0x1 |
| #define QIB_7322_IntStatus_Err_0_LSB 0x1E |
| #define QIB_7322_IntStatus_Err_0_MSB 0x1E |
| #define QIB_7322_IntStatus_Err_0_RMASK 0x1 |
| #define QIB_7322_IntStatus_Err_LSB 0x1D |
| #define QIB_7322_IntStatus_Err_MSB 0x1D |
| #define QIB_7322_IntStatus_Err_RMASK 0x1 |
| #define QIB_7322_IntStatus_AssertGPIO_LSB 0x1C |
| #define QIB_7322_IntStatus_AssertGPIO_MSB 0x1C |
| #define QIB_7322_IntStatus_AssertGPIO_RMASK 0x1 |
| #define QIB_7322_IntStatus_SendDone_1_LSB 0x19 |
| #define QIB_7322_IntStatus_SendDone_1_MSB 0x19 |
| #define QIB_7322_IntStatus_SendDone_1_RMASK 0x1 |
| #define QIB_7322_IntStatus_SendDone_0_LSB 0x18 |
| #define QIB_7322_IntStatus_SendDone_0_MSB 0x18 |
| #define QIB_7322_IntStatus_SendDone_0_RMASK 0x1 |
| #define QIB_7322_IntStatus_SendBufAvail_LSB 0x17 |
| #define QIB_7322_IntStatus_SendBufAvail_MSB 0x17 |
| #define QIB_7322_IntStatus_SendBufAvail_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvAvail17_LSB 0x11 |
| #define QIB_7322_IntStatus_RcvAvail17_MSB 0x11 |
| #define QIB_7322_IntStatus_RcvAvail17_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvAvail16_LSB 0x10 |
| #define QIB_7322_IntStatus_RcvAvail16_MSB 0x10 |
| #define QIB_7322_IntStatus_RcvAvail16_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvAvail15_LSB 0xF |
| #define QIB_7322_IntStatus_RcvAvail15_MSB 0xF |
| #define QIB_7322_IntStatus_RcvAvail15_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvAvail14_LSB 0xE |
| #define QIB_7322_IntStatus_RcvAvail14_MSB 0xE |
| #define QIB_7322_IntStatus_RcvAvail14_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvAvail13_LSB 0xD |
| #define QIB_7322_IntStatus_RcvAvail13_MSB 0xD |
| #define QIB_7322_IntStatus_RcvAvail13_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvAvail12_LSB 0xC |
| #define QIB_7322_IntStatus_RcvAvail12_MSB 0xC |
| #define QIB_7322_IntStatus_RcvAvail12_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvAvail11_LSB 0xB |
| #define QIB_7322_IntStatus_RcvAvail11_MSB 0xB |
| #define QIB_7322_IntStatus_RcvAvail11_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvAvail10_LSB 0xA |
| #define QIB_7322_IntStatus_RcvAvail10_MSB 0xA |
| #define QIB_7322_IntStatus_RcvAvail10_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvAvail9_LSB 0x9 |
| #define QIB_7322_IntStatus_RcvAvail9_MSB 0x9 |
| #define QIB_7322_IntStatus_RcvAvail9_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvAvail8_LSB 0x8 |
| #define QIB_7322_IntStatus_RcvAvail8_MSB 0x8 |
| #define QIB_7322_IntStatus_RcvAvail8_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvAvail7_LSB 0x7 |
| #define QIB_7322_IntStatus_RcvAvail7_MSB 0x7 |
| #define QIB_7322_IntStatus_RcvAvail7_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvAvail6_LSB 0x6 |
| #define QIB_7322_IntStatus_RcvAvail6_MSB 0x6 |
| #define QIB_7322_IntStatus_RcvAvail6_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvAvail5_LSB 0x5 |
| #define QIB_7322_IntStatus_RcvAvail5_MSB 0x5 |
| #define QIB_7322_IntStatus_RcvAvail5_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvAvail4_LSB 0x4 |
| #define QIB_7322_IntStatus_RcvAvail4_MSB 0x4 |
| #define QIB_7322_IntStatus_RcvAvail4_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvAvail3_LSB 0x3 |
| #define QIB_7322_IntStatus_RcvAvail3_MSB 0x3 |
| #define QIB_7322_IntStatus_RcvAvail3_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvAvail2_LSB 0x2 |
| #define QIB_7322_IntStatus_RcvAvail2_MSB 0x2 |
| #define QIB_7322_IntStatus_RcvAvail2_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvAvail1_LSB 0x1 |
| #define QIB_7322_IntStatus_RcvAvail1_MSB 0x1 |
| #define QIB_7322_IntStatus_RcvAvail1_RMASK 0x1 |
| #define QIB_7322_IntStatus_RcvAvail0_LSB 0x0 |
| #define QIB_7322_IntStatus_RcvAvail0_MSB 0x0 |
| #define QIB_7322_IntStatus_RcvAvail0_RMASK 0x1 |
| |
| #define QIB_7322_IntClear_OFFS 0x78 |
| #define QIB_7322_IntClear_DEF 0x0000000000000000 |
| #define QIB_7322_IntClear_SDmaIntClear_1_LSB 0x3F |
| #define QIB_7322_IntClear_SDmaIntClear_1_MSB 0x3F |
| #define QIB_7322_IntClear_SDmaIntClear_1_RMASK 0x1 |
| #define QIB_7322_IntClear_SDmaIntClear_0_LSB 0x3E |
| #define QIB_7322_IntClear_SDmaIntClear_0_MSB 0x3E |
| #define QIB_7322_IntClear_SDmaIntClear_0_RMASK 0x1 |
| #define QIB_7322_IntClear_SDmaProgressIntClear_1_LSB 0x3D |
| #define QIB_7322_IntClear_SDmaProgressIntClear_1_MSB 0x3D |
| #define QIB_7322_IntClear_SDmaProgressIntClear_1_RMASK 0x1 |
| #define QIB_7322_IntClear_SDmaProgressIntClear_0_LSB 0x3C |
| #define QIB_7322_IntClear_SDmaProgressIntClear_0_MSB 0x3C |
| #define QIB_7322_IntClear_SDmaProgressIntClear_0_RMASK 0x1 |
| #define QIB_7322_IntClear_SDmaIdleIntClear_1_LSB 0x3B |
| #define QIB_7322_IntClear_SDmaIdleIntClear_1_MSB 0x3B |
| #define QIB_7322_IntClear_SDmaIdleIntClear_1_RMASK 0x1 |
| #define QIB_7322_IntClear_SDmaIdleIntClear_0_LSB 0x3A |
| #define QIB_7322_IntClear_SDmaIdleIntClear_0_MSB 0x3A |
| #define QIB_7322_IntClear_SDmaIdleIntClear_0_RMASK 0x1 |
| #define QIB_7322_IntClear_SDmaCleanupDoneClear_1_LSB 0x39 |
| #define QIB_7322_IntClear_SDmaCleanupDoneClear_1_MSB 0x39 |
| #define QIB_7322_IntClear_SDmaCleanupDoneClear_1_RMASK 0x1 |
| #define QIB_7322_IntClear_SDmaCleanupDoneClear_0_LSB 0x38 |
| #define QIB_7322_IntClear_SDmaCleanupDoneClear_0_MSB 0x38 |
| #define QIB_7322_IntClear_SDmaCleanupDoneClear_0_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvUrg17IntClear_LSB 0x31 |
| #define QIB_7322_IntClear_RcvUrg17IntClear_MSB 0x31 |
| #define QIB_7322_IntClear_RcvUrg17IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvUrg16IntClear_LSB 0x30 |
| #define QIB_7322_IntClear_RcvUrg16IntClear_MSB 0x30 |
| #define QIB_7322_IntClear_RcvUrg16IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvUrg15IntClear_LSB 0x2F |
| #define QIB_7322_IntClear_RcvUrg15IntClear_MSB 0x2F |
| #define QIB_7322_IntClear_RcvUrg15IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvUrg14IntClear_LSB 0x2E |
| #define QIB_7322_IntClear_RcvUrg14IntClear_MSB 0x2E |
| #define QIB_7322_IntClear_RcvUrg14IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvUrg13IntClear_LSB 0x2D |
| #define QIB_7322_IntClear_RcvUrg13IntClear_MSB 0x2D |
| #define QIB_7322_IntClear_RcvUrg13IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvUrg12IntClear_LSB 0x2C |
| #define QIB_7322_IntClear_RcvUrg12IntClear_MSB 0x2C |
| #define QIB_7322_IntClear_RcvUrg12IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvUrg11IntClear_LSB 0x2B |
| #define QIB_7322_IntClear_RcvUrg11IntClear_MSB 0x2B |
| #define QIB_7322_IntClear_RcvUrg11IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvUrg10IntClear_LSB 0x2A |
| #define QIB_7322_IntClear_RcvUrg10IntClear_MSB 0x2A |
| #define QIB_7322_IntClear_RcvUrg10IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvUrg9IntClear_LSB 0x29 |
| #define QIB_7322_IntClear_RcvUrg9IntClear_MSB 0x29 |
| #define QIB_7322_IntClear_RcvUrg9IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvUrg8IntClear_LSB 0x28 |
| #define QIB_7322_IntClear_RcvUrg8IntClear_MSB 0x28 |
| #define QIB_7322_IntClear_RcvUrg8IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvUrg7IntClear_LSB 0x27 |
| #define QIB_7322_IntClear_RcvUrg7IntClear_MSB 0x27 |
| #define QIB_7322_IntClear_RcvUrg7IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvUrg6IntClear_LSB 0x26 |
| #define QIB_7322_IntClear_RcvUrg6IntClear_MSB 0x26 |
| #define QIB_7322_IntClear_RcvUrg6IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvUrg5IntClear_LSB 0x25 |
| #define QIB_7322_IntClear_RcvUrg5IntClear_MSB 0x25 |
| #define QIB_7322_IntClear_RcvUrg5IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvUrg4IntClear_LSB 0x24 |
| #define QIB_7322_IntClear_RcvUrg4IntClear_MSB 0x24 |
| #define QIB_7322_IntClear_RcvUrg4IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvUrg3IntClear_LSB 0x23 |
| #define QIB_7322_IntClear_RcvUrg3IntClear_MSB 0x23 |
| #define QIB_7322_IntClear_RcvUrg3IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvUrg2IntClear_LSB 0x22 |
| #define QIB_7322_IntClear_RcvUrg2IntClear_MSB 0x22 |
| #define QIB_7322_IntClear_RcvUrg2IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvUrg1IntClear_LSB 0x21 |
| #define QIB_7322_IntClear_RcvUrg1IntClear_MSB 0x21 |
| #define QIB_7322_IntClear_RcvUrg1IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvUrg0IntClear_LSB 0x20 |
| #define QIB_7322_IntClear_RcvUrg0IntClear_MSB 0x20 |
| #define QIB_7322_IntClear_RcvUrg0IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_ErrIntClear_1_LSB 0x1F |
| #define QIB_7322_IntClear_ErrIntClear_1_MSB 0x1F |
| #define QIB_7322_IntClear_ErrIntClear_1_RMASK 0x1 |
| #define QIB_7322_IntClear_ErrIntClear_0_LSB 0x1E |
| #define QIB_7322_IntClear_ErrIntClear_0_MSB 0x1E |
| #define QIB_7322_IntClear_ErrIntClear_0_RMASK 0x1 |
| #define QIB_7322_IntClear_ErrIntClear_LSB 0x1D |
| #define QIB_7322_IntClear_ErrIntClear_MSB 0x1D |
| #define QIB_7322_IntClear_ErrIntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_AssertGPIOIntClear_LSB 0x1C |
| #define QIB_7322_IntClear_AssertGPIOIntClear_MSB 0x1C |
| #define QIB_7322_IntClear_AssertGPIOIntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_SendDoneIntClear_1_LSB 0x19 |
| #define QIB_7322_IntClear_SendDoneIntClear_1_MSB 0x19 |
| #define QIB_7322_IntClear_SendDoneIntClear_1_RMASK 0x1 |
| #define QIB_7322_IntClear_SendDoneIntClear_0_LSB 0x18 |
| #define QIB_7322_IntClear_SendDoneIntClear_0_MSB 0x18 |
| #define QIB_7322_IntClear_SendDoneIntClear_0_RMASK 0x1 |
| #define QIB_7322_IntClear_SendBufAvailIntClear_LSB 0x17 |
| #define QIB_7322_IntClear_SendBufAvailIntClear_MSB 0x17 |
| #define QIB_7322_IntClear_SendBufAvailIntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvAvail17IntClear_LSB 0x11 |
| #define QIB_7322_IntClear_RcvAvail17IntClear_MSB 0x11 |
| #define QIB_7322_IntClear_RcvAvail17IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvAvail16IntClear_LSB 0x10 |
| #define QIB_7322_IntClear_RcvAvail16IntClear_MSB 0x10 |
| #define QIB_7322_IntClear_RcvAvail16IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvAvail15IntClear_LSB 0xF |
| #define QIB_7322_IntClear_RcvAvail15IntClear_MSB 0xF |
| #define QIB_7322_IntClear_RcvAvail15IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvAvail14IntClear_LSB 0xE |
| #define QIB_7322_IntClear_RcvAvail14IntClear_MSB 0xE |
| #define QIB_7322_IntClear_RcvAvail14IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvAvail13IntClear_LSB 0xD |
| #define QIB_7322_IntClear_RcvAvail13IntClear_MSB 0xD |
| #define QIB_7322_IntClear_RcvAvail13IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvAvail12IntClear_LSB 0xC |
| #define QIB_7322_IntClear_RcvAvail12IntClear_MSB 0xC |
| #define QIB_7322_IntClear_RcvAvail12IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvAvail11IntClear_LSB 0xB |
| #define QIB_7322_IntClear_RcvAvail11IntClear_MSB 0xB |
| #define QIB_7322_IntClear_RcvAvail11IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvAvail10IntClear_LSB 0xA |
| #define QIB_7322_IntClear_RcvAvail10IntClear_MSB 0xA |
| #define QIB_7322_IntClear_RcvAvail10IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvAvail9IntClear_LSB 0x9 |
| #define QIB_7322_IntClear_RcvAvail9IntClear_MSB 0x9 |
| #define QIB_7322_IntClear_RcvAvail9IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvAvail8IntClear_LSB 0x8 |
| #define QIB_7322_IntClear_RcvAvail8IntClear_MSB 0x8 |
| #define QIB_7322_IntClear_RcvAvail8IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvAvail7IntClear_LSB 0x7 |
| #define QIB_7322_IntClear_RcvAvail7IntClear_MSB 0x7 |
| #define QIB_7322_IntClear_RcvAvail7IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvAvail6IntClear_LSB 0x6 |
| #define QIB_7322_IntClear_RcvAvail6IntClear_MSB 0x6 |
| #define QIB_7322_IntClear_RcvAvail6IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvAvail5IntClear_LSB 0x5 |
| #define QIB_7322_IntClear_RcvAvail5IntClear_MSB 0x5 |
| #define QIB_7322_IntClear_RcvAvail5IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvAvail4IntClear_LSB 0x4 |
| #define QIB_7322_IntClear_RcvAvail4IntClear_MSB 0x4 |
| #define QIB_7322_IntClear_RcvAvail4IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvAvail3IntClear_LSB 0x3 |
| #define QIB_7322_IntClear_RcvAvail3IntClear_MSB 0x3 |
| #define QIB_7322_IntClear_RcvAvail3IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvAvail2IntClear_LSB 0x2 |
| #define QIB_7322_IntClear_RcvAvail2IntClear_MSB 0x2 |
| #define QIB_7322_IntClear_RcvAvail2IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvAvail1IntClear_LSB 0x1 |
| #define QIB_7322_IntClear_RcvAvail1IntClear_MSB 0x1 |
| #define QIB_7322_IntClear_RcvAvail1IntClear_RMASK 0x1 |
| #define QIB_7322_IntClear_RcvAvail0IntClear_LSB 0x0 |
| #define QIB_7322_IntClear_RcvAvail0IntClear_MSB 0x0 |
| #define QIB_7322_IntClear_RcvAvail0IntClear_RMASK 0x1 |
| |
| #define QIB_7322_ErrMask_OFFS 0x80 |
| #define QIB_7322_ErrMask_DEF 0x0000000000000000 |
| #define QIB_7322_ErrMask_ResetNegatedMask_LSB 0x3F |
| #define QIB_7322_ErrMask_ResetNegatedMask_MSB 0x3F |
| #define QIB_7322_ErrMask_ResetNegatedMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_HardwareErrMask_LSB 0x3E |
| #define QIB_7322_ErrMask_HardwareErrMask_MSB 0x3E |
| #define QIB_7322_ErrMask_HardwareErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_InvalidAddrErrMask_LSB 0x3D |
| #define QIB_7322_ErrMask_InvalidAddrErrMask_MSB 0x3D |
| #define QIB_7322_ErrMask_InvalidAddrErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_SDmaVL15ErrMask_LSB 0x38 |
| #define QIB_7322_ErrMask_SDmaVL15ErrMask_MSB 0x38 |
| #define QIB_7322_ErrMask_SDmaVL15ErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_SBufVL15MisUseErrMask_LSB 0x37 |
| #define QIB_7322_ErrMask_SBufVL15MisUseErrMask_MSB 0x37 |
| #define QIB_7322_ErrMask_SBufVL15MisUseErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_InvalidEEPCmdMask_LSB 0x35 |
| #define QIB_7322_ErrMask_InvalidEEPCmdMask_MSB 0x35 |
| #define QIB_7322_ErrMask_InvalidEEPCmdMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_RcvContextShareErrMask_LSB 0x34 |
| #define QIB_7322_ErrMask_RcvContextShareErrMask_MSB 0x34 |
| #define QIB_7322_ErrMask_RcvContextShareErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_SendVLMismatchErrMask_LSB 0x24 |
| #define QIB_7322_ErrMask_SendVLMismatchErrMask_MSB 0x24 |
| #define QIB_7322_ErrMask_SendVLMismatchErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_SendArmLaunchErrMask_LSB 0x23 |
| #define QIB_7322_ErrMask_SendArmLaunchErrMask_MSB 0x23 |
| #define QIB_7322_ErrMask_SendArmLaunchErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_SendSpecialTriggerErrMask_LSB 0x1B |
| #define QIB_7322_ErrMask_SendSpecialTriggerErrMask_MSB 0x1B |
| #define QIB_7322_ErrMask_SendSpecialTriggerErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_SDmaWrongPortErrMask_LSB 0x1A |
| #define QIB_7322_ErrMask_SDmaWrongPortErrMask_MSB 0x1A |
| #define QIB_7322_ErrMask_SDmaWrongPortErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_SDmaBufMaskDuplicateErrMask_LSB 0x19 |
| #define QIB_7322_ErrMask_SDmaBufMaskDuplicateErrMask_MSB 0x19 |
| #define QIB_7322_ErrMask_SDmaBufMaskDuplicateErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_RcvHdrFullErrMask_LSB 0xD |
| #define QIB_7322_ErrMask_RcvHdrFullErrMask_MSB 0xD |
| #define QIB_7322_ErrMask_RcvHdrFullErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_RcvEgrFullErrMask_LSB 0xC |
| #define QIB_7322_ErrMask_RcvEgrFullErrMask_MSB 0xC |
| #define QIB_7322_ErrMask_RcvEgrFullErrMask_RMASK 0x1 |
| |
| #define QIB_7322_ErrStatus_OFFS 0x88 |
| #define QIB_7322_ErrStatus_DEF 0x0000000000000000 |
| #define QIB_7322_ErrStatus_ResetNegated_LSB 0x3F |
| #define QIB_7322_ErrStatus_ResetNegated_MSB 0x3F |
| #define QIB_7322_ErrStatus_ResetNegated_RMASK 0x1 |
| #define QIB_7322_ErrStatus_HardwareErr_LSB 0x3E |
| #define QIB_7322_ErrStatus_HardwareErr_MSB 0x3E |
| #define QIB_7322_ErrStatus_HardwareErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_InvalidAddrErr_LSB 0x3D |
| #define QIB_7322_ErrStatus_InvalidAddrErr_MSB 0x3D |
| #define QIB_7322_ErrStatus_InvalidAddrErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_SDmaVL15Err_LSB 0x38 |
| #define QIB_7322_ErrStatus_SDmaVL15Err_MSB 0x38 |
| #define QIB_7322_ErrStatus_SDmaVL15Err_RMASK 0x1 |
| #define QIB_7322_ErrStatus_SBufVL15MisUseErr_LSB 0x37 |
| #define QIB_7322_ErrStatus_SBufVL15MisUseErr_MSB 0x37 |
| #define QIB_7322_ErrStatus_SBufVL15MisUseErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_InvalidEEPCmdErr_LSB 0x35 |
| #define QIB_7322_ErrStatus_InvalidEEPCmdErr_MSB 0x35 |
| #define QIB_7322_ErrStatus_InvalidEEPCmdErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_RcvContextShareErr_LSB 0x34 |
| #define QIB_7322_ErrStatus_RcvContextShareErr_MSB 0x34 |
| #define QIB_7322_ErrStatus_RcvContextShareErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_SendVLMismatchErr_LSB 0x24 |
| #define QIB_7322_ErrStatus_SendVLMismatchErr_MSB 0x24 |
| #define QIB_7322_ErrStatus_SendVLMismatchErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_SendArmLaunchErr_LSB 0x23 |
| #define QIB_7322_ErrStatus_SendArmLaunchErr_MSB 0x23 |
| #define QIB_7322_ErrStatus_SendArmLaunchErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_SendSpecialTriggerErr_LSB 0x1B |
| #define QIB_7322_ErrStatus_SendSpecialTriggerErr_MSB 0x1B |
| #define QIB_7322_ErrStatus_SendSpecialTriggerErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_SDmaWrongPortErr_LSB 0x1A |
| #define QIB_7322_ErrStatus_SDmaWrongPortErr_MSB 0x1A |
| #define QIB_7322_ErrStatus_SDmaWrongPortErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_SDmaBufMaskDuplicateErr_LSB 0x19 |
| #define QIB_7322_ErrStatus_SDmaBufMaskDuplicateErr_MSB 0x19 |
| #define QIB_7322_ErrStatus_SDmaBufMaskDuplicateErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_RcvHdrFullErr_LSB 0xD |
| #define QIB_7322_ErrStatus_RcvHdrFullErr_MSB 0xD |
| #define QIB_7322_ErrStatus_RcvHdrFullErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_RcvEgrFullErr_LSB 0xC |
| #define QIB_7322_ErrStatus_RcvEgrFullErr_MSB 0xC |
| #define QIB_7322_ErrStatus_RcvEgrFullErr_RMASK 0x1 |
| |
| #define QIB_7322_ErrClear_OFFS 0x90 |
| #define QIB_7322_ErrClear_DEF 0x0000000000000000 |
| #define QIB_7322_ErrClear_ResetNegatedClear_LSB 0x3F |
| #define QIB_7322_ErrClear_ResetNegatedClear_MSB 0x3F |
| #define QIB_7322_ErrClear_ResetNegatedClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_HardwareErrClear_LSB 0x3E |
| #define QIB_7322_ErrClear_HardwareErrClear_MSB 0x3E |
| #define QIB_7322_ErrClear_HardwareErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_InvalidAddrErrClear_LSB 0x3D |
| #define QIB_7322_ErrClear_InvalidAddrErrClear_MSB 0x3D |
| #define QIB_7322_ErrClear_InvalidAddrErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_SDmaVL15ErrClear_LSB 0x38 |
| #define QIB_7322_ErrClear_SDmaVL15ErrClear_MSB 0x38 |
| #define QIB_7322_ErrClear_SDmaVL15ErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_SBufVL15MisUseErrClear_LSB 0x37 |
| #define QIB_7322_ErrClear_SBufVL15MisUseErrClear_MSB 0x37 |
| #define QIB_7322_ErrClear_SBufVL15MisUseErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_InvalidEEPCmdErrClear_LSB 0x35 |
| #define QIB_7322_ErrClear_InvalidEEPCmdErrClear_MSB 0x35 |
| #define QIB_7322_ErrClear_InvalidEEPCmdErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_RcvContextShareErrClear_LSB 0x34 |
| #define QIB_7322_ErrClear_RcvContextShareErrClear_MSB 0x34 |
| #define QIB_7322_ErrClear_RcvContextShareErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_SendVLMismatchErrMask_LSB 0x24 |
| #define QIB_7322_ErrClear_SendVLMismatchErrMask_MSB 0x24 |
| #define QIB_7322_ErrClear_SendVLMismatchErrMask_RMASK 0x1 |
| #define QIB_7322_ErrClear_SendArmLaunchErrClear_LSB 0x23 |
| #define QIB_7322_ErrClear_SendArmLaunchErrClear_MSB 0x23 |
| #define QIB_7322_ErrClear_SendArmLaunchErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_SendSpecialTriggerErrClear_LSB 0x1B |
| #define QIB_7322_ErrClear_SendSpecialTriggerErrClear_MSB 0x1B |
| #define QIB_7322_ErrClear_SendSpecialTriggerErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_SDmaWrongPortErrClear_LSB 0x1A |
| #define QIB_7322_ErrClear_SDmaWrongPortErrClear_MSB 0x1A |
| #define QIB_7322_ErrClear_SDmaWrongPortErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_SDmaBufMaskDuplicateErrClear_LSB 0x19 |
| #define QIB_7322_ErrClear_SDmaBufMaskDuplicateErrClear_MSB 0x19 |
| #define QIB_7322_ErrClear_SDmaBufMaskDuplicateErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_RcvHdrFullErrClear_LSB 0xD |
| #define QIB_7322_ErrClear_RcvHdrFullErrClear_MSB 0xD |
| #define QIB_7322_ErrClear_RcvHdrFullErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_RcvEgrFullErrClear_LSB 0xC |
| #define QIB_7322_ErrClear_RcvEgrFullErrClear_MSB 0xC |
| #define QIB_7322_ErrClear_RcvEgrFullErrClear_RMASK 0x1 |
| |
| #define QIB_7322_HwErrMask_OFFS 0x98 |
| #define QIB_7322_HwErrMask_DEF 0x0000000000000000 |
| #define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_1_LSB 0x3F |
| #define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_1_MSB 0x3F |
| #define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_1_RMASK 0x1 |
| #define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_0_LSB 0x3E |
| #define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_0_MSB 0x3E |
| #define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_0_RMASK 0x1 |
| #define QIB_7322_HwErrMask_PCIESerdesPClkNotDetectMask_LSB 0x37 |
| #define QIB_7322_HwErrMask_PCIESerdesPClkNotDetectMask_MSB 0x37 |
| #define QIB_7322_HwErrMask_PCIESerdesPClkNotDetectMask_RMASK 0x1 |
| #define QIB_7322_HwErrMask_PowerOnBISTFailedMask_LSB 0x36 |
| #define QIB_7322_HwErrMask_PowerOnBISTFailedMask_MSB 0x36 |
| #define QIB_7322_HwErrMask_PowerOnBISTFailedMask_RMASK 0x1 |
| #define QIB_7322_HwErrMask_TempsenseTholdReachedMask_LSB 0x35 |
| #define QIB_7322_HwErrMask_TempsenseTholdReachedMask_MSB 0x35 |
| #define QIB_7322_HwErrMask_TempsenseTholdReachedMask_RMASK 0x1 |
| #define QIB_7322_HwErrMask_MemoryErrMask_LSB 0x30 |
| #define QIB_7322_HwErrMask_MemoryErrMask_MSB 0x30 |
| #define QIB_7322_HwErrMask_MemoryErrMask_RMASK 0x1 |
| #define QIB_7322_HwErrMask_pcie_phy_txParityErr_LSB 0x22 |
| #define QIB_7322_HwErrMask_pcie_phy_txParityErr_MSB 0x22 |
| #define QIB_7322_HwErrMask_pcie_phy_txParityErr_RMASK 0x1 |
| #define QIB_7322_HwErrMask_PCIeBusParityErrMask_LSB 0x1F |
| #define QIB_7322_HwErrMask_PCIeBusParityErrMask_MSB 0x21 |
| #define QIB_7322_HwErrMask_PCIeBusParityErrMask_RMASK 0x7 |
| #define QIB_7322_HwErrMask_PcieCplTimeoutMask_LSB 0x1E |
| #define QIB_7322_HwErrMask_PcieCplTimeoutMask_MSB 0x1E |
| #define QIB_7322_HwErrMask_PcieCplTimeoutMask_RMASK 0x1 |
| #define QIB_7322_HwErrMask_PciePoisonedTLPMask_LSB 0x1D |
| #define QIB_7322_HwErrMask_PciePoisonedTLPMask_MSB 0x1D |
| #define QIB_7322_HwErrMask_PciePoisonedTLPMask_RMASK 0x1 |
| #define QIB_7322_HwErrMask_SDmaMemReadErrMask_1_LSB 0x1C |
| #define QIB_7322_HwErrMask_SDmaMemReadErrMask_1_MSB 0x1C |
| #define QIB_7322_HwErrMask_SDmaMemReadErrMask_1_RMASK 0x1 |
| #define QIB_7322_HwErrMask_SDmaMemReadErrMask_0_LSB 0x1B |
| #define QIB_7322_HwErrMask_SDmaMemReadErrMask_0_MSB 0x1B |
| #define QIB_7322_HwErrMask_SDmaMemReadErrMask_0_RMASK 0x1 |
| #define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_1_LSB 0xF |
| #define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_1_MSB 0xF |
| #define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_1_RMASK 0x1 |
| #define QIB_7322_HwErrMask_IBCBusToSPCParityErrMask_1_LSB 0xE |
| #define QIB_7322_HwErrMask_IBCBusToSPCParityErrMask_1_MSB 0xE |
| #define QIB_7322_HwErrMask_IBCBusToSPCParityErrMask_1_RMASK 0x1 |
| #define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_0_LSB 0xD |
| #define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_0_MSB 0xD |
| #define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_0_RMASK 0x1 |
| #define QIB_7322_HwErrMask_statusValidNoEopMask_LSB 0xC |
| #define QIB_7322_HwErrMask_statusValidNoEopMask_MSB 0xC |
| #define QIB_7322_HwErrMask_statusValidNoEopMask_RMASK 0x1 |
| #define QIB_7322_HwErrMask_LATriggeredMask_LSB 0xB |
| #define QIB_7322_HwErrMask_LATriggeredMask_MSB 0xB |
| #define QIB_7322_HwErrMask_LATriggeredMask_RMASK 0x1 |
| |
| #define QIB_7322_HwErrStatus_OFFS 0xA0 |
| #define QIB_7322_HwErrStatus_DEF 0x0000000000000000 |
| #define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_1_LSB 0x3F |
| #define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_1_MSB 0x3F |
| #define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_1_RMASK 0x1 |
| #define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_0_LSB 0x3E |
| #define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_0_MSB 0x3E |
| #define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_0_RMASK 0x1 |
| #define QIB_7322_HwErrStatus_PCIESerdesPClkNotDetect_LSB 0x37 |
| #define QIB_7322_HwErrStatus_PCIESerdesPClkNotDetect_MSB 0x37 |
| #define QIB_7322_HwErrStatus_PCIESerdesPClkNotDetect_RMASK 0x1 |
| #define QIB_7322_HwErrStatus_PowerOnBISTFailed_LSB 0x36 |
| #define QIB_7322_HwErrStatus_PowerOnBISTFailed_MSB 0x36 |
| #define QIB_7322_HwErrStatus_PowerOnBISTFailed_RMASK 0x1 |
| #define QIB_7322_HwErrStatus_TempsenseTholdReached_LSB 0x35 |
| #define QIB_7322_HwErrStatus_TempsenseTholdReached_MSB 0x35 |
| #define QIB_7322_HwErrStatus_TempsenseTholdReached_RMASK 0x1 |
| #define QIB_7322_HwErrStatus_MemoryErr_LSB 0x30 |
| #define QIB_7322_HwErrStatus_MemoryErr_MSB 0x30 |
| #define QIB_7322_HwErrStatus_MemoryErr_RMASK 0x1 |
| #define QIB_7322_HwErrStatus_pcie_phy_txParityErr_LSB 0x22 |
| #define QIB_7322_HwErrStatus_pcie_phy_txParityErr_MSB 0x22 |
| #define QIB_7322_HwErrStatus_pcie_phy_txParityErr_RMASK 0x1 |
| #define QIB_7322_HwErrStatus_PCIeBusParity_LSB 0x1F |
| #define QIB_7322_HwErrStatus_PCIeBusParity_MSB 0x21 |
| #define QIB_7322_HwErrStatus_PCIeBusParity_RMASK 0x7 |
| #define QIB_7322_HwErrStatus_PcieCplTimeout_LSB 0x1E |
| #define QIB_7322_HwErrStatus_PcieCplTimeout_MSB 0x1E |
| #define QIB_7322_HwErrStatus_PcieCplTimeout_RMASK 0x1 |
| #define QIB_7322_HwErrStatus_PciePoisonedTLP_LSB 0x1D |
| #define QIB_7322_HwErrStatus_PciePoisonedTLP_MSB 0x1D |
| #define QIB_7322_HwErrStatus_PciePoisonedTLP_RMASK 0x1 |
| #define QIB_7322_HwErrStatus_SDmaMemReadErr_1_LSB 0x1C |
| #define QIB_7322_HwErrStatus_SDmaMemReadErr_1_MSB 0x1C |
| #define QIB_7322_HwErrStatus_SDmaMemReadErr_1_RMASK 0x1 |
| #define QIB_7322_HwErrStatus_SDmaMemReadErr_0_LSB 0x1B |
| #define QIB_7322_HwErrStatus_SDmaMemReadErr_0_MSB 0x1B |
| #define QIB_7322_HwErrStatus_SDmaMemReadErr_0_RMASK 0x1 |
| #define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_1_LSB 0xF |
| #define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_1_MSB 0xF |
| #define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_1_RMASK 0x1 |
| #define QIB_7322_HwErrStatus_IBCBusToSPCParityErr_1_LSB 0xE |
| #define QIB_7322_HwErrStatus_IBCBusToSPCParityErr_1_MSB 0xE |
| #define QIB_7322_HwErrStatus_IBCBusToSPCParityErr_1_RMASK 0x1 |
| #define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_0_LSB 0xD |
| #define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_0_MSB 0xD |
| #define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_0_RMASK 0x1 |
| #define QIB_7322_HwErrStatus_statusValidNoEop_LSB 0xC |
| #define QIB_7322_HwErrStatus_statusValidNoEop_MSB 0xC |
| #define QIB_7322_HwErrStatus_statusValidNoEop_RMASK 0x1 |
| #define QIB_7322_HwErrStatus_LATriggered_LSB 0xB |
| #define QIB_7322_HwErrStatus_LATriggered_MSB 0xB |
| #define QIB_7322_HwErrStatus_LATriggered_RMASK 0x1 |
| |
| #define QIB_7322_HwErrClear_OFFS 0xA8 |
| #define QIB_7322_HwErrClear_DEF 0x0000000000000000 |
| #define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_1_LSB 0x3F |
| #define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_1_MSB 0x3F |
| #define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_1_RMASK 0x1 |
| #define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_0_LSB 0x3E |
| #define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_0_MSB 0x3E |
| #define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_0_RMASK 0x1 |
| #define QIB_7322_HwErrClear_PCIESerdesPClkNotDetectClear_LSB 0x37 |
| #define QIB_7322_HwErrClear_PCIESerdesPClkNotDetectClear_MSB 0x37 |
| #define QIB_7322_HwErrClear_PCIESerdesPClkNotDetectClear_RMASK 0x1 |
| #define QIB_7322_HwErrClear_PowerOnBISTFailedClear_LSB 0x36 |
| #define QIB_7322_HwErrClear_PowerOnBISTFailedClear_MSB 0x36 |
| #define QIB_7322_HwErrClear_PowerOnBISTFailedClear_RMASK 0x1 |
| #define QIB_7322_HwErrClear_TempsenseTholdReachedClear_LSB 0x35 |
| #define QIB_7322_HwErrClear_TempsenseTholdReachedClear_MSB 0x35 |
| #define QIB_7322_HwErrClear_TempsenseTholdReachedClear_RMASK 0x1 |
| #define QIB_7322_HwErrClear_MemoryErrClear_LSB 0x30 |
| #define QIB_7322_HwErrClear_MemoryErrClear_MSB 0x30 |
| #define QIB_7322_HwErrClear_MemoryErrClear_RMASK 0x1 |
| #define QIB_7322_HwErrClear_pcie_phy_txParityErr_LSB 0x22 |
| #define QIB_7322_HwErrClear_pcie_phy_txParityErr_MSB 0x22 |
| #define QIB_7322_HwErrClear_pcie_phy_txParityErr_RMASK 0x1 |
| #define QIB_7322_HwErrClear_PCIeBusParityClear_LSB 0x1F |
| #define QIB_7322_HwErrClear_PCIeBusParityClear_MSB 0x21 |
| #define QIB_7322_HwErrClear_PCIeBusParityClear_RMASK 0x7 |
| #define QIB_7322_HwErrClear_PcieCplTimeoutClear_LSB 0x1E |
| #define QIB_7322_HwErrClear_PcieCplTimeoutClear_MSB 0x1E |
| #define QIB_7322_HwErrClear_PcieCplTimeoutClear_RMASK 0x1 |
| #define QIB_7322_HwErrClear_PciePoisonedTLPClear_LSB 0x1D |
| #define QIB_7322_HwErrClear_PciePoisonedTLPClear_MSB 0x1D |
| #define QIB_7322_HwErrClear_PciePoisonedTLPClear_RMASK 0x1 |
| #define QIB_7322_HwErrClear_SDmaMemReadErrClear_1_LSB 0x1C |
| #define QIB_7322_HwErrClear_SDmaMemReadErrClear_1_MSB 0x1C |
| #define QIB_7322_HwErrClear_SDmaMemReadErrClear_1_RMASK 0x1 |
| #define QIB_7322_HwErrClear_SDmaMemReadErrClear_0_LSB 0x1B |
| #define QIB_7322_HwErrClear_SDmaMemReadErrClear_0_MSB 0x1B |
| #define QIB_7322_HwErrClear_SDmaMemReadErrClear_0_RMASK 0x1 |
| #define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_1_LSB 0xF |
| #define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_1_MSB 0xF |
| #define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_1_RMASK 0x1 |
| #define QIB_7322_HwErrClear_IBCBusToSPCParityErrClear_1_LSB 0xE |
| #define QIB_7322_HwErrClear_IBCBusToSPCParityErrClear_1_MSB 0xE |
| #define QIB_7322_HwErrClear_IBCBusToSPCParityErrClear_1_RMASK 0x1 |
| #define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_0_LSB 0xD |
| #define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_0_MSB 0xD |
| #define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_0_RMASK 0x1 |
| #define QIB_7322_HwErrClear_statusValidNoEopClear_LSB 0xC |
| #define QIB_7322_HwErrClear_statusValidNoEopClear_MSB 0xC |
| #define QIB_7322_HwErrClear_statusValidNoEopClear_RMASK 0x1 |
| #define QIB_7322_HwErrClear_LATriggeredClear_LSB 0xB |
| #define QIB_7322_HwErrClear_LATriggeredClear_MSB 0xB |
| #define QIB_7322_HwErrClear_LATriggeredClear_RMASK 0x1 |
| |
| #define QIB_7322_HwDiagCtrl_OFFS 0xB0 |
| #define QIB_7322_HwDiagCtrl_DEF 0x0000000000000000 |
| #define QIB_7322_HwDiagCtrl_Diagnostic_LSB 0x3F |
| #define QIB_7322_HwDiagCtrl_Diagnostic_MSB 0x3F |
| #define QIB_7322_HwDiagCtrl_Diagnostic_RMASK 0x1 |
| #define QIB_7322_HwDiagCtrl_CounterWrEnable_LSB 0x3D |
| #define QIB_7322_HwDiagCtrl_CounterWrEnable_MSB 0x3D |
| #define QIB_7322_HwDiagCtrl_CounterWrEnable_RMASK 0x1 |
| #define QIB_7322_HwDiagCtrl_CounterDisable_LSB 0x3C |
| #define QIB_7322_HwDiagCtrl_CounterDisable_MSB 0x3C |
| #define QIB_7322_HwDiagCtrl_CounterDisable_RMASK 0x1 |
| #define QIB_7322_HwDiagCtrl_forcePCIeBusParity_LSB 0x1F |
| #define QIB_7322_HwDiagCtrl_forcePCIeBusParity_MSB 0x22 |
| #define QIB_7322_HwDiagCtrl_forcePCIeBusParity_RMASK 0xF |
| #define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_1_LSB 0xF |
| #define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_1_MSB 0xF |
| #define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_1_RMASK 0x1 |
| #define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_1_LSB 0xE |
| #define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_1_MSB 0xE |
| #define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_1_RMASK 0x1 |
| #define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_0_LSB 0xD |
| #define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_0_MSB 0xD |
| #define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_0_RMASK 0x1 |
| #define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_0_LSB 0xC |
| #define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_0_MSB 0xC |
| #define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_0_RMASK 0x1 |
| |
| #define QIB_7322_EXTStatus_OFFS 0xC0 |
| #define QIB_7322_EXTStatus_DEF 0x000000000000X000 |
| #define QIB_7322_EXTStatus_GPIOIn_LSB 0x30 |
| #define QIB_7322_EXTStatus_GPIOIn_MSB 0x3F |
| #define QIB_7322_EXTStatus_GPIOIn_RMASK 0xFFFF |
| #define QIB_7322_EXTStatus_MemBISTDisabled_LSB 0xF |
| #define QIB_7322_EXTStatus_MemBISTDisabled_MSB 0xF |
| #define QIB_7322_EXTStatus_MemBISTDisabled_RMASK 0x1 |
| #define QIB_7322_EXTStatus_MemBISTEndTest_LSB 0xE |
| #define QIB_7322_EXTStatus_MemBISTEndTest_MSB 0xE |
| #define QIB_7322_EXTStatus_MemBISTEndTest_RMASK 0x1 |
| |
| #define QIB_7322_EXTCtrl_OFFS 0xC8 |
| #define QIB_7322_EXTCtrl_DEF 0x0000000000000000 |
| #define QIB_7322_EXTCtrl_GPIOOe_LSB 0x30 |
| #define QIB_7322_EXTCtrl_GPIOOe_MSB 0x3F |
| #define QIB_7322_EXTCtrl_GPIOOe_RMASK 0xFFFF |
| #define QIB_7322_EXTCtrl_GPIOInvert_LSB 0x20 |
| #define QIB_7322_EXTCtrl_GPIOInvert_MSB 0x2F |
| #define QIB_7322_EXTCtrl_GPIOInvert_RMASK 0xFFFF |
| #define QIB_7322_EXTCtrl_LEDPort1GreenOn_LSB 0x3 |
| #define QIB_7322_EXTCtrl_LEDPort1GreenOn_MSB 0x3 |
| #define QIB_7322_EXTCtrl_LEDPort1GreenOn_RMASK 0x1 |
| #define QIB_7322_EXTCtrl_LEDPort1YellowOn_LSB 0x2 |
| #define QIB_7322_EXTCtrl_LEDPort1YellowOn_MSB 0x2 |
| #define QIB_7322_EXTCtrl_LEDPort1YellowOn_RMASK 0x1 |
| #define QIB_7322_EXTCtrl_LEDPort0GreenOn_LSB 0x1 |
| #define QIB_7322_EXTCtrl_LEDPort0GreenOn_MSB 0x1 |
| #define QIB_7322_EXTCtrl_LEDPort0GreenOn_RMASK 0x1 |
| #define QIB_7322_EXTCtrl_LEDPort0YellowOn_LSB 0x0 |
| #define QIB_7322_EXTCtrl_LEDPort0YellowOn_MSB 0x0 |
| #define QIB_7322_EXTCtrl_LEDPort0YellowOn_RMASK 0x1 |
| |
| #define QIB_7322_GPIOOut_OFFS 0xE0 |
| #define QIB_7322_GPIOOut_DEF 0x0000000000000000 |
| |
| #define QIB_7322_GPIOMask_OFFS 0xE8 |
| #define QIB_7322_GPIOMask_DEF 0x0000000000000000 |
| |
| #define QIB_7322_GPIOStatus_OFFS 0xF0 |
| #define QIB_7322_GPIOStatus_DEF 0x0000000000000000 |
| |
| #define QIB_7322_GPIOClear_OFFS 0xF8 |
| #define QIB_7322_GPIOClear_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RcvCtrl_OFFS 0x100 |
| #define QIB_7322_RcvCtrl_DEF 0x0000000000000000 |
| #define QIB_7322_RcvCtrl_TidReDirect_LSB 0x30 |
| #define QIB_7322_RcvCtrl_TidReDirect_MSB 0x3F |
| #define QIB_7322_RcvCtrl_TidReDirect_RMASK 0xFFFF |
| #define QIB_7322_RcvCtrl_TailUpd_LSB 0x2F |
| #define QIB_7322_RcvCtrl_TailUpd_MSB 0x2F |
| #define QIB_7322_RcvCtrl_TailUpd_RMASK 0x1 |
| #define QIB_7322_RcvCtrl_XrcTypeCode_LSB 0x2C |
| #define QIB_7322_RcvCtrl_XrcTypeCode_MSB 0x2E |
| #define QIB_7322_RcvCtrl_XrcTypeCode_RMASK 0x7 |
| #define QIB_7322_RcvCtrl_TidFlowEnable_LSB 0x2B |
| #define QIB_7322_RcvCtrl_TidFlowEnable_MSB 0x2B |
| #define QIB_7322_RcvCtrl_TidFlowEnable_RMASK 0x1 |
| #define QIB_7322_RcvCtrl_ContextCfg_LSB 0x29 |
| #define QIB_7322_RcvCtrl_ContextCfg_MSB 0x2A |
| #define QIB_7322_RcvCtrl_ContextCfg_RMASK 0x3 |
| #define QIB_7322_RcvCtrl_IntrAvail_LSB 0x14 |
| #define QIB_7322_RcvCtrl_IntrAvail_MSB 0x25 |
| #define QIB_7322_RcvCtrl_IntrAvail_RMASK 0x3FFFF |
| #define QIB_7322_RcvCtrl_dontDropRHQFull_LSB 0x0 |
| #define QIB_7322_RcvCtrl_dontDropRHQFull_MSB 0x11 |
| #define QIB_7322_RcvCtrl_dontDropRHQFull_RMASK 0x3FFFF |
| |
| #define QIB_7322_RcvHdrSize_OFFS 0x110 |
| #define QIB_7322_RcvHdrSize_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RcvHdrCnt_OFFS 0x118 |
| #define QIB_7322_RcvHdrCnt_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RcvHdrEntSize_OFFS 0x120 |
| #define QIB_7322_RcvHdrEntSize_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RcvTIDBase_OFFS 0x128 |
| #define QIB_7322_RcvTIDBase_DEF 0x0000000000050000 |
| |
| #define QIB_7322_RcvTIDCnt_OFFS 0x130 |
| #define QIB_7322_RcvTIDCnt_DEF 0x0000000000000200 |
| |
| #define QIB_7322_RcvEgrBase_OFFS 0x138 |
| #define QIB_7322_RcvEgrBase_DEF 0x0000000000014000 |
| |
| #define QIB_7322_RcvEgrCnt_OFFS 0x140 |
| #define QIB_7322_RcvEgrCnt_DEF 0x0000000000001000 |
| |
| #define QIB_7322_RcvBufBase_OFFS 0x148 |
| #define QIB_7322_RcvBufBase_DEF 0x0000000000080000 |
| |
| #define QIB_7322_RcvBufSize_OFFS 0x150 |
| #define QIB_7322_RcvBufSize_DEF 0x0000000000005000 |
| |
| #define QIB_7322_RxIntMemBase_OFFS 0x158 |
| #define QIB_7322_RxIntMemBase_DEF 0x0000000000077000 |
| |
| #define QIB_7322_RxIntMemSize_OFFS 0x160 |
| #define QIB_7322_RxIntMemSize_DEF 0x0000000000007000 |
| |
| #define QIB_7322_feature_mask_OFFS 0x190 |
| #define QIB_7322_feature_mask_DEF 0x00000000000000XX |
| |
| #define QIB_7322_active_feature_mask_OFFS 0x198 |
| #define QIB_7322_active_feature_mask_DEF 0x00000000000000XX |
| #define QIB_7322_active_feature_mask_Port1_QDR_Enabled_LSB 0x5 |
| #define QIB_7322_active_feature_mask_Port1_QDR_Enabled_MSB 0x5 |
| #define QIB_7322_active_feature_mask_Port1_QDR_Enabled_RMASK 0x1 |
| #define QIB_7322_active_feature_mask_Port1_DDR_Enabled_LSB 0x4 |
| #define QIB_7322_active_feature_mask_Port1_DDR_Enabled_MSB 0x4 |
| #define QIB_7322_active_feature_mask_Port1_DDR_Enabled_RMASK 0x1 |
| #define QIB_7322_active_feature_mask_Port1_SDR_Enabled_LSB 0x3 |
| #define QIB_7322_active_feature_mask_Port1_SDR_Enabled_MSB 0x3 |
| #define QIB_7322_active_feature_mask_Port1_SDR_Enabled_RMASK 0x1 |
| #define QIB_7322_active_feature_mask_Port0_QDR_Enabled_LSB 0x2 |
| #define QIB_7322_active_feature_mask_Port0_QDR_Enabled_MSB 0x2 |
| #define QIB_7322_active_feature_mask_Port0_QDR_Enabled_RMASK 0x1 |
| #define QIB_7322_active_feature_mask_Port0_DDR_Enabled_LSB 0x1 |
| #define QIB_7322_active_feature_mask_Port0_DDR_Enabled_MSB 0x1 |
| #define QIB_7322_active_feature_mask_Port0_DDR_Enabled_RMASK 0x1 |
| #define QIB_7322_active_feature_mask_Port0_SDR_Enabled_LSB 0x0 |
| #define QIB_7322_active_feature_mask_Port0_SDR_Enabled_MSB 0x0 |
| #define QIB_7322_active_feature_mask_Port0_SDR_Enabled_RMASK 0x1 |
| |
| #define QIB_7322_SendCtrl_OFFS 0x1C0 |
| #define QIB_7322_SendCtrl_DEF 0x0000000000000000 |
| #define QIB_7322_SendCtrl_Disarm_LSB 0x1F |
| #define QIB_7322_SendCtrl_Disarm_MSB 0x1F |
| #define QIB_7322_SendCtrl_Disarm_RMASK 0x1 |
| #define QIB_7322_SendCtrl_SendBufAvailPad64Byte_LSB 0x1D |
| #define QIB_7322_SendCtrl_SendBufAvailPad64Byte_MSB 0x1D |
| #define QIB_7322_SendCtrl_SendBufAvailPad64Byte_RMASK 0x1 |
| #define QIB_7322_SendCtrl_AvailUpdThld_LSB 0x18 |
| #define QIB_7322_SendCtrl_AvailUpdThld_MSB 0x1C |
| #define QIB_7322_SendCtrl_AvailUpdThld_RMASK 0x1F |
| #define QIB_7322_SendCtrl_DisarmSendBuf_LSB 0x10 |
| #define QIB_7322_SendCtrl_DisarmSendBuf_MSB 0x17 |
| #define QIB_7322_SendCtrl_DisarmSendBuf_RMASK 0xFF |
| #define QIB_7322_SendCtrl_SpecialTriggerEn_LSB 0x4 |
| #define QIB_7322_SendCtrl_SpecialTriggerEn_MSB 0x4 |
| #define QIB_7322_SendCtrl_SpecialTriggerEn_RMASK 0x1 |
| #define QIB_7322_SendCtrl_SendBufAvailUpd_LSB 0x2 |
| #define QIB_7322_SendCtrl_SendBufAvailUpd_MSB 0x2 |
| #define QIB_7322_SendCtrl_SendBufAvailUpd_RMASK 0x1 |
| #define QIB_7322_SendCtrl_SendIntBufAvail_LSB 0x1 |
| #define QIB_7322_SendCtrl_SendIntBufAvail_MSB 0x1 |
| #define QIB_7322_SendCtrl_SendIntBufAvail_RMASK 0x1 |
| |
| #define QIB_7322_SendBufBase_OFFS 0x1C8 |
| #define QIB_7322_SendBufBase_DEF 0x0018000000100000 |
| #define QIB_7322_SendBufBase_BaseAddr_LargePIO_LSB 0x20 |
| #define QIB_7322_SendBufBase_BaseAddr_LargePIO_MSB 0x34 |
| #define QIB_7322_SendBufBase_BaseAddr_LargePIO_RMASK 0x1FFFFF |
| #define QIB_7322_SendBufBase_BaseAddr_SmallPIO_LSB 0x0 |
| #define QIB_7322_SendBufBase_BaseAddr_SmallPIO_MSB 0x14 |
| #define QIB_7322_SendBufBase_BaseAddr_SmallPIO_RMASK 0x1FFFFF |
| |
| #define QIB_7322_SendBufSize_OFFS 0x1D0 |
| #define QIB_7322_SendBufSize_DEF 0x0000108000000880 |
| #define QIB_7322_SendBufSize_Size_LargePIO_LSB 0x20 |
| #define QIB_7322_SendBufSize_Size_LargePIO_MSB 0x2C |
| #define QIB_7322_SendBufSize_Size_LargePIO_RMASK 0x1FFF |
| #define QIB_7322_SendBufSize_Size_SmallPIO_LSB 0x0 |
| #define QIB_7322_SendBufSize_Size_SmallPIO_MSB 0xB |
| #define QIB_7322_SendBufSize_Size_SmallPIO_RMASK 0xFFF |
| |
| #define QIB_7322_SendBufCnt_OFFS 0x1D8 |
| #define QIB_7322_SendBufCnt_DEF 0x0000002000000080 |
| #define QIB_7322_SendBufCnt_Num_LargeBuffers_LSB 0x20 |
| #define QIB_7322_SendBufCnt_Num_LargeBuffers_MSB 0x25 |
| #define QIB_7322_SendBufCnt_Num_LargeBuffers_RMASK 0x3F |
| #define QIB_7322_SendBufCnt_Num_SmallBuffers_LSB 0x0 |
| #define QIB_7322_SendBufCnt_Num_SmallBuffers_MSB 0x8 |
| #define QIB_7322_SendBufCnt_Num_SmallBuffers_RMASK 0x1FF |
| |
| #define QIB_7322_SendBufAvailAddr_OFFS 0x1E0 |
| #define QIB_7322_SendBufAvailAddr_DEF 0x0000000000000000 |
| #define QIB_7322_SendBufAvailAddr_SendBufAvailAddr_LSB 0x6 |
| #define QIB_7322_SendBufAvailAddr_SendBufAvailAddr_MSB 0x27 |
| #define QIB_7322_SendBufAvailAddr_SendBufAvailAddr_RMASK 0x3FFFFFFFF |
| |
| #define QIB_7322_SendBufErr0_OFFS 0x240 |
| #define QIB_7322_SendBufErr0_DEF 0x0000000000000000 |
| #define QIB_7322_SendBufErr0_SendBufErr_63_0_LSB 0x0 |
| #define QIB_7322_SendBufErr0_SendBufErr_63_0_MSB 0x3F |
| #define QIB_7322_SendBufErr0_SendBufErr_63_0_RMASK 0x0 |
| |
| #define QIB_7322_AvailUpdCount_OFFS 0x268 |
| #define QIB_7322_AvailUpdCount_DEF 0x0000000000000000 |
| #define QIB_7322_AvailUpdCount_AvailUpdCount_LSB 0x0 |
| #define QIB_7322_AvailUpdCount_AvailUpdCount_MSB 0x4 |
| #define QIB_7322_AvailUpdCount_AvailUpdCount_RMASK 0x1F |
| |
| #define QIB_7322_RcvHdrAddr0_OFFS 0x280 |
| #define QIB_7322_RcvHdrAddr0_DEF 0x0000000000000000 |
| #define QIB_7322_RcvHdrAddr0_RcvHdrAddr_LSB 0x2 |
| #define QIB_7322_RcvHdrAddr0_RcvHdrAddr_MSB 0x27 |
| #define QIB_7322_RcvHdrAddr0_RcvHdrAddr_RMASK 0x3FFFFFFFFF |
| |
| #define QIB_7322_RcvHdrTailAddr0_OFFS 0x340 |
| #define QIB_7322_RcvHdrTailAddr0_DEF 0x0000000000000000 |
| #define QIB_7322_RcvHdrTailAddr0_RcvHdrTailAddr_LSB 0x2 |
| #define QIB_7322_RcvHdrTailAddr0_RcvHdrTailAddr_MSB 0x27 |
| #define QIB_7322_RcvHdrTailAddr0_RcvHdrTailAddr_RMASK 0x3FFFFFFFFF |
| |
| #define QIB_7322_ahb_access_ctrl_OFFS 0x460 |
| #define QIB_7322_ahb_access_ctrl_DEF 0x0000000000000000 |
| #define QIB_7322_ahb_access_ctrl_sw_sel_ahb_trgt_LSB 0x1 |
| #define QIB_7322_ahb_access_ctrl_sw_sel_ahb_trgt_MSB 0x2 |
| #define QIB_7322_ahb_access_ctrl_sw_sel_ahb_trgt_RMASK 0x3 |
| #define QIB_7322_ahb_access_ctrl_sw_ahb_sel_LSB 0x0 |
| #define QIB_7322_ahb_access_ctrl_sw_ahb_sel_MSB 0x0 |
| #define QIB_7322_ahb_access_ctrl_sw_ahb_sel_RMASK 0x1 |
| |
| #define QIB_7322_ahb_transaction_reg_OFFS 0x468 |
| #define QIB_7322_ahb_transaction_reg_DEF 0x0000000080000000 |
| #define QIB_7322_ahb_transaction_reg_ahb_data_LSB 0x20 |
| #define QIB_7322_ahb_transaction_reg_ahb_data_MSB 0x3F |
| #define QIB_7322_ahb_transaction_reg_ahb_data_RMASK 0xFFFFFFFF |
| #define QIB_7322_ahb_transaction_reg_ahb_rdy_LSB 0x1F |
| #define QIB_7322_ahb_transaction_reg_ahb_rdy_MSB 0x1F |
| #define QIB_7322_ahb_transaction_reg_ahb_rdy_RMASK 0x1 |
| #define QIB_7322_ahb_transaction_reg_ahb_req_err_LSB 0x1E |
| #define QIB_7322_ahb_transaction_reg_ahb_req_err_MSB 0x1E |
| #define QIB_7322_ahb_transaction_reg_ahb_req_err_RMASK 0x1 |
| #define QIB_7322_ahb_transaction_reg_write_not_read_LSB 0x1B |
| #define QIB_7322_ahb_transaction_reg_write_not_read_MSB 0x1B |
| #define QIB_7322_ahb_transaction_reg_write_not_read_RMASK 0x1 |
| #define QIB_7322_ahb_transaction_reg_ahb_address_LSB 0x10 |
| #define QIB_7322_ahb_transaction_reg_ahb_address_MSB 0x1A |
| #define QIB_7322_ahb_transaction_reg_ahb_address_RMASK 0x7FF |
| |
| #define QIB_7322_SPC_JTAG_ACCESS_REG_OFFS 0x470 |
| #define QIB_7322_SPC_JTAG_ACCESS_REG_DEF 0x0000000000000001 |
| #define QIB_7322_SPC_JTAG_ACCESS_REG_SPC_JTAG_ACCESS_EN_LSB 0xA |
| #define QIB_7322_SPC_JTAG_ACCESS_REG_SPC_JTAG_ACCESS_EN_MSB 0xA |
| #define QIB_7322_SPC_JTAG_ACCESS_REG_SPC_JTAG_ACCESS_EN_RMASK 0x1 |
| #define QIB_7322_SPC_JTAG_ACCESS_REG_bist_en_LSB 0x5 |
| #define QIB_7322_SPC_JTAG_ACCESS_REG_bist_en_MSB 0x9 |
| #define QIB_7322_SPC_JTAG_ACCESS_REG_bist_en_RMASK 0x1F |
| #define QIB_7322_SPC_JTAG_ACCESS_REG_opcode_LSB 0x3 |
| #define QIB_7322_SPC_JTAG_ACCESS_REG_opcode_MSB 0x4 |
| #define QIB_7322_SPC_JTAG_ACCESS_REG_opcode_RMASK 0x3 |
| #define QIB_7322_SPC_JTAG_ACCESS_REG_tdi_LSB 0x2 |
| #define QIB_7322_SPC_JTAG_ACCESS_REG_tdi_MSB 0x2 |
| #define QIB_7322_SPC_JTAG_ACCESS_REG_tdi_RMASK 0x1 |
| #define QIB_7322_SPC_JTAG_ACCESS_REG_tdo_LSB 0x1 |
| #define QIB_7322_SPC_JTAG_ACCESS_REG_tdo_MSB 0x1 |
| #define QIB_7322_SPC_JTAG_ACCESS_REG_tdo_RMASK 0x1 |
| #define QIB_7322_SPC_JTAG_ACCESS_REG_rdy_LSB 0x0 |
| #define QIB_7322_SPC_JTAG_ACCESS_REG_rdy_MSB 0x0 |
| #define QIB_7322_SPC_JTAG_ACCESS_REG_rdy_RMASK 0x1 |
| |
| #define QIB_7322_SendCheckMask0_OFFS 0x4C0 |
| #define QIB_7322_SendCheckMask0_DEF 0x0000000000000000 |
| #define QIB_7322_SendCheckMask0_SendCheckMask_63_32_LSB 0x0 |
| #define QIB_7322_SendCheckMask0_SendCheckMask_63_32_MSB 0x3F |
| #define QIB_7322_SendCheckMask0_SendCheckMask_63_32_RMASK 0x0 |
| |
| #define QIB_7322_SendGRHCheckMask0_OFFS 0x4E0 |
| #define QIB_7322_SendGRHCheckMask0_DEF 0x0000000000000000 |
| #define QIB_7322_SendGRHCheckMask0_SendGRHCheckMask_63_32_LSB 0x0 |
| #define QIB_7322_SendGRHCheckMask0_SendGRHCheckMask_63_32_MSB 0x3F |
| #define QIB_7322_SendGRHCheckMask0_SendGRHCheckMask_63_32_RMASK 0x0 |
| |
| #define QIB_7322_SendIBPacketMask0_OFFS 0x500 |
| #define QIB_7322_SendIBPacketMask0_DEF 0x0000000000000000 |
| #define QIB_7322_SendIBPacketMask0_SendIBPacketMask_63_32_LSB 0x0 |
| #define QIB_7322_SendIBPacketMask0_SendIBPacketMask_63_32_MSB 0x3F |
| #define QIB_7322_SendIBPacketMask0_SendIBPacketMask_63_32_RMASK 0x0 |
| |
| #define QIB_7322_IntRedirect0_OFFS 0x540 |
| #define QIB_7322_IntRedirect0_DEF 0x0000000000000000 |
| #define QIB_7322_IntRedirect0_vec11_LSB 0x37 |
| #define QIB_7322_IntRedirect0_vec11_MSB 0x3B |
| #define QIB_7322_IntRedirect0_vec11_RMASK 0x1F |
| #define QIB_7322_IntRedirect0_vec10_LSB 0x32 |
| #define QIB_7322_IntRedirect0_vec10_MSB 0x36 |
| #define QIB_7322_IntRedirect0_vec10_RMASK 0x1F |
| #define QIB_7322_IntRedirect0_vec9_LSB 0x2D |
| #define QIB_7322_IntRedirect0_vec9_MSB 0x31 |
| #define QIB_7322_IntRedirect0_vec9_RMASK 0x1F |
| #define QIB_7322_IntRedirect0_vec8_LSB 0x28 |
| #define QIB_7322_IntRedirect0_vec8_MSB 0x2C |
| #define QIB_7322_IntRedirect0_vec8_RMASK 0x1F |
| #define QIB_7322_IntRedirect0_vec7_LSB 0x23 |
| #define QIB_7322_IntRedirect0_vec7_MSB 0x27 |
| #define QIB_7322_IntRedirect0_vec7_RMASK 0x1F |
| #define QIB_7322_IntRedirect0_vec6_LSB 0x1E |
| #define QIB_7322_IntRedirect0_vec6_MSB 0x22 |
| #define QIB_7322_IntRedirect0_vec6_RMASK 0x1F |
| #define QIB_7322_IntRedirect0_vec5_LSB 0x19 |
| #define QIB_7322_IntRedirect0_vec5_MSB 0x1D |
| #define QIB_7322_IntRedirect0_vec5_RMASK 0x1F |
| #define QIB_7322_IntRedirect0_vec4_LSB 0x14 |
| #define QIB_7322_IntRedirect0_vec4_MSB 0x18 |
| #define QIB_7322_IntRedirect0_vec4_RMASK 0x1F |
| #define QIB_7322_IntRedirect0_vec3_LSB 0xF |
| #define QIB_7322_IntRedirect0_vec3_MSB 0x13 |
| #define QIB_7322_IntRedirect0_vec3_RMASK 0x1F |
| #define QIB_7322_IntRedirect0_vec2_LSB 0xA |
| #define QIB_7322_IntRedirect0_vec2_MSB 0xE |
| #define QIB_7322_IntRedirect0_vec2_RMASK 0x1F |
| #define QIB_7322_IntRedirect0_vec1_LSB 0x5 |
| #define QIB_7322_IntRedirect0_vec1_MSB 0x9 |
| #define QIB_7322_IntRedirect0_vec1_RMASK 0x1F |
| #define QIB_7322_IntRedirect0_vec0_LSB 0x0 |
| #define QIB_7322_IntRedirect0_vec0_MSB 0x4 |
| #define QIB_7322_IntRedirect0_vec0_RMASK 0x1F |
| |
| #define QIB_7322_Int_Granted_OFFS 0x570 |
| #define QIB_7322_Int_Granted_DEF 0x0000000000000000 |
| |
| #define QIB_7322_vec_clr_without_int_OFFS 0x578 |
| #define QIB_7322_vec_clr_without_int_DEF 0x0000000000000000 |
| |
| #define QIB_7322_DCACtrlA_OFFS 0x580 |
| #define QIB_7322_DCACtrlA_DEF 0x0000000000000000 |
| #define QIB_7322_DCACtrlA_SendDMAHead1DCAEnable_LSB 0x4 |
| #define QIB_7322_DCACtrlA_SendDMAHead1DCAEnable_MSB 0x4 |
| #define QIB_7322_DCACtrlA_SendDMAHead1DCAEnable_RMASK 0x1 |
| #define QIB_7322_DCACtrlA_SendDMAHead0DCAEnable_LSB 0x3 |
| #define QIB_7322_DCACtrlA_SendDMAHead0DCAEnable_MSB 0x3 |
| #define QIB_7322_DCACtrlA_SendDMAHead0DCAEnable_RMASK 0x1 |
| #define QIB_7322_DCACtrlA_RcvTailUpdDCAEnable_LSB 0x2 |
| #define QIB_7322_DCACtrlA_RcvTailUpdDCAEnable_MSB 0x2 |
| #define QIB_7322_DCACtrlA_RcvTailUpdDCAEnable_RMASK 0x1 |
| #define QIB_7322_DCACtrlA_EagerDCAEnable_LSB 0x1 |
| #define QIB_7322_DCACtrlA_EagerDCAEnable_MSB 0x1 |
| #define QIB_7322_DCACtrlA_EagerDCAEnable_RMASK 0x1 |
| #define QIB_7322_DCACtrlA_RcvHdrqDCAEnable_LSB 0x0 |
| #define QIB_7322_DCACtrlA_RcvHdrqDCAEnable_MSB 0x0 |
| #define QIB_7322_DCACtrlA_RcvHdrqDCAEnable_RMASK 0x1 |
| |
| #define QIB_7322_DCACtrlB_OFFS 0x588 |
| #define QIB_7322_DCACtrlB_DEF 0x0000000000000000 |
| #define QIB_7322_DCACtrlB_RcvHdrq3DCAXfrCnt_LSB 0x36 |
| #define QIB_7322_DCACtrlB_RcvHdrq3DCAXfrCnt_MSB 0x3B |
| #define QIB_7322_DCACtrlB_RcvHdrq3DCAXfrCnt_RMASK 0x3F |
| #define QIB_7322_DCACtrlB_RcvHdrq3DCAOPH_LSB 0x2E |
| #define QIB_7322_DCACtrlB_RcvHdrq3DCAOPH_MSB 0x35 |
| #define QIB_7322_DCACtrlB_RcvHdrq3DCAOPH_RMASK 0xFF |
| #define QIB_7322_DCACtrlB_RcvHdrq2DCAXfrCnt_LSB 0x28 |
| #define QIB_7322_DCACtrlB_RcvHdrq2DCAXfrCnt_MSB 0x2D |
| #define QIB_7322_DCACtrlB_RcvHdrq2DCAXfrCnt_RMASK 0x3F |
| #define QIB_7322_DCACtrlB_RcvHdrq2DCAOPH_LSB 0x20 |
| #define QIB_7322_DCACtrlB_RcvHdrq2DCAOPH_MSB 0x27 |
| #define QIB_7322_DCACtrlB_RcvHdrq2DCAOPH_RMASK 0xFF |
| #define QIB_7322_DCACtrlB_RcvHdrq1DCAXfrCnt_LSB 0x16 |
| #define QIB_7322_DCACtrlB_RcvHdrq1DCAXfrCnt_MSB 0x1B |
| #define QIB_7322_DCACtrlB_RcvHdrq1DCAXfrCnt_RMASK 0x3F |
| #define QIB_7322_DCACtrlB_RcvHdrq1DCAOPH_LSB 0xE |
| #define QIB_7322_DCACtrlB_RcvHdrq1DCAOPH_MSB 0x15 |
| #define QIB_7322_DCACtrlB_RcvHdrq1DCAOPH_RMASK 0xFF |
| #define QIB_7322_DCACtrlB_RcvHdrq0DCAXfrCnt_LSB 0x8 |
| #define QIB_7322_DCACtrlB_RcvHdrq0DCAXfrCnt_MSB 0xD |
| #define QIB_7322_DCACtrlB_RcvHdrq0DCAXfrCnt_RMASK 0x3F |
| #define QIB_7322_DCACtrlB_RcvHdrq0DCAOPH_LSB 0x0 |
| #define QIB_7322_DCACtrlB_RcvHdrq0DCAOPH_MSB 0x7 |
| #define QIB_7322_DCACtrlB_RcvHdrq0DCAOPH_RMASK 0xFF |
| |
| #define QIB_7322_DCACtrlC_OFFS 0x590 |
| #define QIB_7322_DCACtrlC_DEF 0x0000000000000000 |
| #define QIB_7322_DCACtrlC_RcvHdrq7DCAXfrCnt_LSB 0x36 |
| #define QIB_7322_DCACtrlC_RcvHdrq7DCAXfrCnt_MSB 0x3B |
| #define QIB_7322_DCACtrlC_RcvHdrq7DCAXfrCnt_RMASK 0x3F |
| #define QIB_7322_DCACtrlC_RcvHdrq7DCAOPH_LSB 0x2E |
| #define QIB_7322_DCACtrlC_RcvHdrq7DCAOPH_MSB 0x35 |
| #define QIB_7322_DCACtrlC_RcvHdrq7DCAOPH_RMASK 0xFF |
| #define QIB_7322_DCACtrlC_RcvHdrq6DCAXfrCnt_LSB 0x28 |
| #define QIB_7322_DCACtrlC_RcvHdrq6DCAXfrCnt_MSB 0x2D |
| #define QIB_7322_DCACtrlC_RcvHdrq6DCAXfrCnt_RMASK 0x3F |
| #define QIB_7322_DCACtrlC_RcvHdrq6DCAOPH_LSB 0x20 |
| #define QIB_7322_DCACtrlC_RcvHdrq6DCAOPH_MSB 0x27 |
| #define QIB_7322_DCACtrlC_RcvHdrq6DCAOPH_RMASK 0xFF |
| #define QIB_7322_DCACtrlC_RcvHdrq5DCAXfrCnt_LSB 0x16 |
| #define QIB_7322_DCACtrlC_RcvHdrq5DCAXfrCnt_MSB 0x1B |
| #define QIB_7322_DCACtrlC_RcvHdrq5DCAXfrCnt_RMASK 0x3F |
| #define QIB_7322_DCACtrlC_RcvHdrq5DCAOPH_LSB 0xE |
| #define QIB_7322_DCACtrlC_RcvHdrq5DCAOPH_MSB 0x15 |
| #define QIB_7322_DCACtrlC_RcvHdrq5DCAOPH_RMASK 0xFF |
| #define QIB_7322_DCACtrlC_RcvHdrq4DCAXfrCnt_LSB 0x8 |
| #define QIB_7322_DCACtrlC_RcvHdrq4DCAXfrCnt_MSB 0xD |
| #define QIB_7322_DCACtrlC_RcvHdrq4DCAXfrCnt_RMASK 0x3F |
| #define QIB_7322_DCACtrlC_RcvHdrq4DCAOPH_LSB 0x0 |
| #define QIB_7322_DCACtrlC_RcvHdrq4DCAOPH_MSB 0x7 |
| #define QIB_7322_DCACtrlC_RcvHdrq4DCAOPH_RMASK 0xFF |
| |
| #define QIB_7322_DCACtrlD_OFFS 0x598 |
| #define QIB_7322_DCACtrlD_DEF 0x0000000000000000 |
| #define QIB_7322_DCACtrlD_RcvHdrq11DCAXfrCnt_LSB 0x36 |
| #define QIB_7322_DCACtrlD_RcvHdrq11DCAXfrCnt_MSB 0x3B |
| #define QIB_7322_DCACtrlD_RcvHdrq11DCAXfrCnt_RMASK 0x3F |
| #define QIB_7322_DCACtrlD_RcvHdrq11DCAOPH_LSB 0x2E |
| #define QIB_7322_DCACtrlD_RcvHdrq11DCAOPH_MSB 0x35 |
| #define QIB_7322_DCACtrlD_RcvHdrq11DCAOPH_RMASK 0xFF |
| #define QIB_7322_DCACtrlD_RcvHdrq10DCAXfrCnt_LSB 0x28 |
| #define QIB_7322_DCACtrlD_RcvHdrq10DCAXfrCnt_MSB 0x2D |
| #define QIB_7322_DCACtrlD_RcvHdrq10DCAXfrCnt_RMASK 0x3F |
| #define QIB_7322_DCACtrlD_RcvHdrq10DCAOPH_LSB 0x20 |
| #define QIB_7322_DCACtrlD_RcvHdrq10DCAOPH_MSB 0x27 |
| #define QIB_7322_DCACtrlD_RcvHdrq10DCAOPH_RMASK 0xFF |
| #define QIB_7322_DCACtrlD_RcvHdrq9DCAXfrCnt_LSB 0x16 |
| #define QIB_7322_DCACtrlD_RcvHdrq9DCAXfrCnt_MSB 0x1B |
| #define QIB_7322_DCACtrlD_RcvHdrq9DCAXfrCnt_RMASK 0x3F |
| #define QIB_7322_DCACtrlD_RcvHdrq9DCAOPH_LSB 0xE |
| #define QIB_7322_DCACtrlD_RcvHdrq9DCAOPH_MSB 0x15 |
| #define QIB_7322_DCACtrlD_RcvHdrq9DCAOPH_RMASK 0xFF |
| #define QIB_7322_DCACtrlD_RcvHdrq8DCAXfrCnt_LSB 0x8 |
| #define QIB_7322_DCACtrlD_RcvHdrq8DCAXfrCnt_MSB 0xD |
| #define QIB_7322_DCACtrlD_RcvHdrq8DCAXfrCnt_RMASK 0x3F |
| #define QIB_7322_DCACtrlD_RcvHdrq8DCAOPH_LSB 0x0 |
| #define QIB_7322_DCACtrlD_RcvHdrq8DCAOPH_MSB 0x7 |
| #define QIB_7322_DCACtrlD_RcvHdrq8DCAOPH_RMASK 0xFF |
| |
| #define QIB_7322_DCACtrlE_OFFS 0x5A0 |
| #define QIB_7322_DCACtrlE_DEF 0x0000000000000000 |
| #define QIB_7322_DCACtrlE_RcvHdrq15DCAXfrCnt_LSB 0x36 |
| #define QIB_7322_DCACtrlE_RcvHdrq15DCAXfrCnt_MSB 0x3B |
| #define QIB_7322_DCACtrlE_RcvHdrq15DCAXfrCnt_RMASK 0x3F |
| #define QIB_7322_DCACtrlE_RcvHdrq15DCAOPH_LSB 0x2E |
| #define QIB_7322_DCACtrlE_RcvHdrq15DCAOPH_MSB 0x35 |
| #define QIB_7322_DCACtrlE_RcvHdrq15DCAOPH_RMASK 0xFF |
| #define QIB_7322_DCACtrlE_RcvHdrq14DCAXfrCnt_LSB 0x28 |
| #define QIB_7322_DCACtrlE_RcvHdrq14DCAXfrCnt_MSB 0x2D |
| #define QIB_7322_DCACtrlE_RcvHdrq14DCAXfrCnt_RMASK 0x3F |
| #define QIB_7322_DCACtrlE_RcvHdrq14DCAOPH_LSB 0x20 |
| #define QIB_7322_DCACtrlE_RcvHdrq14DCAOPH_MSB 0x27 |
| #define QIB_7322_DCACtrlE_RcvHdrq14DCAOPH_RMASK 0xFF |
| #define QIB_7322_DCACtrlE_RcvHdrq13DCAXfrCnt_LSB 0x16 |
| #define QIB_7322_DCACtrlE_RcvHdrq13DCAXfrCnt_MSB 0x1B |
| #define QIB_7322_DCACtrlE_RcvHdrq13DCAXfrCnt_RMASK 0x3F |
| #define QIB_7322_DCACtrlE_RcvHdrq13DCAOPH_LSB 0xE |
| #define QIB_7322_DCACtrlE_RcvHdrq13DCAOPH_MSB 0x15 |
| #define QIB_7322_DCACtrlE_RcvHdrq13DCAOPH_RMASK 0xFF |
| #define QIB_7322_DCACtrlE_RcvHdrq12DCAXfrCnt_LSB 0x8 |
| #define QIB_7322_DCACtrlE_RcvHdrq12DCAXfrCnt_MSB 0xD |
| #define QIB_7322_DCACtrlE_RcvHdrq12DCAXfrCnt_RMASK 0x3F |
| #define QIB_7322_DCACtrlE_RcvHdrq12DCAOPH_LSB 0x0 |
| #define QIB_7322_DCACtrlE_RcvHdrq12DCAOPH_MSB 0x7 |
| #define QIB_7322_DCACtrlE_RcvHdrq12DCAOPH_RMASK 0xFF |
| |
| #define QIB_7322_DCACtrlF_OFFS 0x5A8 |
| #define QIB_7322_DCACtrlF_DEF 0x0000000000000000 |
| #define QIB_7322_DCACtrlF_SendDma1DCAOPH_LSB 0x28 |
| #define QIB_7322_DCACtrlF_SendDma1DCAOPH_MSB 0x2F |
| #define QIB_7322_DCACtrlF_SendDma1DCAOPH_RMASK 0xFF |
| #define QIB_7322_DCACtrlF_SendDma0DCAOPH_LSB 0x20 |
| #define QIB_7322_DCACtrlF_SendDma0DCAOPH_MSB 0x27 |
| #define QIB_7322_DCACtrlF_SendDma0DCAOPH_RMASK 0xFF |
| #define QIB_7322_DCACtrlF_RcvHdrq17DCAXfrCnt_LSB 0x16 |
| #define QIB_7322_DCACtrlF_RcvHdrq17DCAXfrCnt_MSB 0x1B |
| #define QIB_7322_DCACtrlF_RcvHdrq17DCAXfrCnt_RMASK 0x3F |
| #define QIB_7322_DCACtrlF_RcvHdrq17DCAOPH_LSB 0xE |
| #define QIB_7322_DCACtrlF_RcvHdrq17DCAOPH_MSB 0x15 |
| #define QIB_7322_DCACtrlF_RcvHdrq17DCAOPH_RMASK 0xFF |
| #define QIB_7322_DCACtrlF_RcvHdrq16DCAXfrCnt_LSB 0x8 |
| #define QIB_7322_DCACtrlF_RcvHdrq16DCAXfrCnt_MSB 0xD |
| #define QIB_7322_DCACtrlF_RcvHdrq16DCAXfrCnt_RMASK 0x3F |
| #define QIB_7322_DCACtrlF_RcvHdrq16DCAOPH_LSB 0x0 |
| #define QIB_7322_DCACtrlF_RcvHdrq16DCAOPH_MSB 0x7 |
| #define QIB_7322_DCACtrlF_RcvHdrq16DCAOPH_RMASK 0xFF |
| |
| #define QIB_7322_RcvAvailTimeOut0_OFFS 0xC00 |
| #define QIB_7322_RcvAvailTimeOut0_DEF 0x0000000000000000 |
| #define QIB_7322_RcvAvailTimeOut0_RcvAvailTOCount_LSB 0x10 |
| #define QIB_7322_RcvAvailTimeOut0_RcvAvailTOCount_MSB 0x1F |
| #define QIB_7322_RcvAvailTimeOut0_RcvAvailTOCount_RMASK 0xFFFF |
| #define QIB_7322_RcvAvailTimeOut0_RcvAvailTOReload_LSB 0x0 |
| #define QIB_7322_RcvAvailTimeOut0_RcvAvailTOReload_MSB 0xF |
| #define QIB_7322_RcvAvailTimeOut0_RcvAvailTOReload_RMASK 0xFFFF |
| |
| #define QIB_7322_CntrRegBase_0_OFFS 0x1028 |
| #define QIB_7322_CntrRegBase_0_DEF 0x0000000000012000 |
| |
| #define QIB_7322_ErrMask_0_OFFS 0x1080 |
| #define QIB_7322_ErrMask_0_DEF 0x0000000000000000 |
| #define QIB_7322_ErrMask_0_IBStatusChangedMask_LSB 0x3A |
| #define QIB_7322_ErrMask_0_IBStatusChangedMask_MSB 0x3A |
| #define QIB_7322_ErrMask_0_IBStatusChangedMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_SHeadersErrMask_LSB 0x39 |
| #define QIB_7322_ErrMask_0_SHeadersErrMask_MSB 0x39 |
| #define QIB_7322_ErrMask_0_SHeadersErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_VL15BufMisuseErrMask_LSB 0x36 |
| #define QIB_7322_ErrMask_0_VL15BufMisuseErrMask_MSB 0x36 |
| #define QIB_7322_ErrMask_0_VL15BufMisuseErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_SDmaHaltErrMask_LSB 0x31 |
| #define QIB_7322_ErrMask_0_SDmaHaltErrMask_MSB 0x31 |
| #define QIB_7322_ErrMask_0_SDmaHaltErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_SDmaDescAddrMisalignErrMask_LSB 0x30 |
| #define QIB_7322_ErrMask_0_SDmaDescAddrMisalignErrMask_MSB 0x30 |
| #define QIB_7322_ErrMask_0_SDmaDescAddrMisalignErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_SDmaUnexpDataErrMask_LSB 0x2F |
| #define QIB_7322_ErrMask_0_SDmaUnexpDataErrMask_MSB 0x2F |
| #define QIB_7322_ErrMask_0_SDmaUnexpDataErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_SDmaMissingDwErrMask_LSB 0x2E |
| #define QIB_7322_ErrMask_0_SDmaMissingDwErrMask_MSB 0x2E |
| #define QIB_7322_ErrMask_0_SDmaMissingDwErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_SDmaDwEnErrMask_LSB 0x2D |
| #define QIB_7322_ErrMask_0_SDmaDwEnErrMask_MSB 0x2D |
| #define QIB_7322_ErrMask_0_SDmaDwEnErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_SDmaRpyTagErrMask_LSB 0x2C |
| #define QIB_7322_ErrMask_0_SDmaRpyTagErrMask_MSB 0x2C |
| #define QIB_7322_ErrMask_0_SDmaRpyTagErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_SDma1stDescErrMask_LSB 0x2B |
| #define QIB_7322_ErrMask_0_SDma1stDescErrMask_MSB 0x2B |
| #define QIB_7322_ErrMask_0_SDma1stDescErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_SDmaBaseErrMask_LSB 0x2A |
| #define QIB_7322_ErrMask_0_SDmaBaseErrMask_MSB 0x2A |
| #define QIB_7322_ErrMask_0_SDmaBaseErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_SDmaTailOutOfBoundErrMask_LSB 0x29 |
| #define QIB_7322_ErrMask_0_SDmaTailOutOfBoundErrMask_MSB 0x29 |
| #define QIB_7322_ErrMask_0_SDmaTailOutOfBoundErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_SDmaOutOfBoundErrMask_LSB 0x28 |
| #define QIB_7322_ErrMask_0_SDmaOutOfBoundErrMask_MSB 0x28 |
| #define QIB_7322_ErrMask_0_SDmaOutOfBoundErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_SDmaGenMismatchErrMask_LSB 0x27 |
| #define QIB_7322_ErrMask_0_SDmaGenMismatchErrMask_MSB 0x27 |
| #define QIB_7322_ErrMask_0_SDmaGenMismatchErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_SendBufMisuseErrMask_LSB 0x26 |
| #define QIB_7322_ErrMask_0_SendBufMisuseErrMask_MSB 0x26 |
| #define QIB_7322_ErrMask_0_SendBufMisuseErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_SendUnsupportedVLErrMask_LSB 0x25 |
| #define QIB_7322_ErrMask_0_SendUnsupportedVLErrMask_MSB 0x25 |
| #define QIB_7322_ErrMask_0_SendUnsupportedVLErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_SendUnexpectedPktNumErrMask_LSB 0x24 |
| #define QIB_7322_ErrMask_0_SendUnexpectedPktNumErrMask_MSB 0x24 |
| #define QIB_7322_ErrMask_0_SendUnexpectedPktNumErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_SendDroppedDataPktErrMask_LSB 0x22 |
| #define QIB_7322_ErrMask_0_SendDroppedDataPktErrMask_MSB 0x22 |
| #define QIB_7322_ErrMask_0_SendDroppedDataPktErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_SendDroppedSmpPktErrMask_LSB 0x21 |
| #define QIB_7322_ErrMask_0_SendDroppedSmpPktErrMask_MSB 0x21 |
| #define QIB_7322_ErrMask_0_SendDroppedSmpPktErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_SendPktLenErrMask_LSB 0x20 |
| #define QIB_7322_ErrMask_0_SendPktLenErrMask_MSB 0x20 |
| #define QIB_7322_ErrMask_0_SendPktLenErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_SendUnderRunErrMask_LSB 0x1F |
| #define QIB_7322_ErrMask_0_SendUnderRunErrMask_MSB 0x1F |
| #define QIB_7322_ErrMask_0_SendUnderRunErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_SendMaxPktLenErrMask_LSB 0x1E |
| #define QIB_7322_ErrMask_0_SendMaxPktLenErrMask_MSB 0x1E |
| #define QIB_7322_ErrMask_0_SendMaxPktLenErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_SendMinPktLenErrMask_LSB 0x1D |
| #define QIB_7322_ErrMask_0_SendMinPktLenErrMask_MSB 0x1D |
| #define QIB_7322_ErrMask_0_SendMinPktLenErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_RcvIBLostLinkErrMask_LSB 0x11 |
| #define QIB_7322_ErrMask_0_RcvIBLostLinkErrMask_MSB 0x11 |
| #define QIB_7322_ErrMask_0_RcvIBLostLinkErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_RcvHdrErrMask_LSB 0x10 |
| #define QIB_7322_ErrMask_0_RcvHdrErrMask_MSB 0x10 |
| #define QIB_7322_ErrMask_0_RcvHdrErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_RcvHdrLenErrMask_LSB 0xF |
| #define QIB_7322_ErrMask_0_RcvHdrLenErrMask_MSB 0xF |
| #define QIB_7322_ErrMask_0_RcvHdrLenErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_RcvBadTidErrMask_LSB 0xE |
| #define QIB_7322_ErrMask_0_RcvBadTidErrMask_MSB 0xE |
| #define QIB_7322_ErrMask_0_RcvBadTidErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_RcvBadVersionErrMask_LSB 0xB |
| #define QIB_7322_ErrMask_0_RcvBadVersionErrMask_MSB 0xB |
| #define QIB_7322_ErrMask_0_RcvBadVersionErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_RcvIBFlowErrMask_LSB 0xA |
| #define QIB_7322_ErrMask_0_RcvIBFlowErrMask_MSB 0xA |
| #define QIB_7322_ErrMask_0_RcvIBFlowErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_RcvEBPErrMask_LSB 0x9 |
| #define QIB_7322_ErrMask_0_RcvEBPErrMask_MSB 0x9 |
| #define QIB_7322_ErrMask_0_RcvEBPErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_RcvUnsupportedVLErrMask_LSB 0x8 |
| #define QIB_7322_ErrMask_0_RcvUnsupportedVLErrMask_MSB 0x8 |
| #define QIB_7322_ErrMask_0_RcvUnsupportedVLErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_RcvUnexpectedCharErrMask_LSB 0x7 |
| #define QIB_7322_ErrMask_0_RcvUnexpectedCharErrMask_MSB 0x7 |
| #define QIB_7322_ErrMask_0_RcvUnexpectedCharErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_RcvShortPktLenErrMask_LSB 0x6 |
| #define QIB_7322_ErrMask_0_RcvShortPktLenErrMask_MSB 0x6 |
| #define QIB_7322_ErrMask_0_RcvShortPktLenErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_RcvLongPktLenErrMask_LSB 0x5 |
| #define QIB_7322_ErrMask_0_RcvLongPktLenErrMask_MSB 0x5 |
| #define QIB_7322_ErrMask_0_RcvLongPktLenErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_RcvMaxPktLenErrMask_LSB 0x4 |
| #define QIB_7322_ErrMask_0_RcvMaxPktLenErrMask_MSB 0x4 |
| #define QIB_7322_ErrMask_0_RcvMaxPktLenErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_RcvMinPktLenErrMask_LSB 0x3 |
| #define QIB_7322_ErrMask_0_RcvMinPktLenErrMask_MSB 0x3 |
| #define QIB_7322_ErrMask_0_RcvMinPktLenErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_RcvICRCErrMask_LSB 0x2 |
| #define QIB_7322_ErrMask_0_RcvICRCErrMask_MSB 0x2 |
| #define QIB_7322_ErrMask_0_RcvICRCErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_RcvVCRCErrMask_LSB 0x1 |
| #define QIB_7322_ErrMask_0_RcvVCRCErrMask_MSB 0x1 |
| #define QIB_7322_ErrMask_0_RcvVCRCErrMask_RMASK 0x1 |
| #define QIB_7322_ErrMask_0_RcvFormatErrMask_LSB 0x0 |
| #define QIB_7322_ErrMask_0_RcvFormatErrMask_MSB 0x0 |
| #define QIB_7322_ErrMask_0_RcvFormatErrMask_RMASK 0x1 |
| |
| #define QIB_7322_ErrStatus_0_OFFS 0x1088 |
| #define QIB_7322_ErrStatus_0_DEF 0x0000000000000000 |
| #define QIB_7322_ErrStatus_0_IBStatusChanged_LSB 0x3A |
| #define QIB_7322_ErrStatus_0_IBStatusChanged_MSB 0x3A |
| #define QIB_7322_ErrStatus_0_IBStatusChanged_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_SHeadersErr_LSB 0x39 |
| #define QIB_7322_ErrStatus_0_SHeadersErr_MSB 0x39 |
| #define QIB_7322_ErrStatus_0_SHeadersErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_VL15BufMisuseErr_LSB 0x36 |
| #define QIB_7322_ErrStatus_0_VL15BufMisuseErr_MSB 0x36 |
| #define QIB_7322_ErrStatus_0_VL15BufMisuseErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_SDmaHaltErr_LSB 0x31 |
| #define QIB_7322_ErrStatus_0_SDmaHaltErr_MSB 0x31 |
| #define QIB_7322_ErrStatus_0_SDmaHaltErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_SDmaDescAddrMisalignErr_LSB 0x30 |
| #define QIB_7322_ErrStatus_0_SDmaDescAddrMisalignErr_MSB 0x30 |
| #define QIB_7322_ErrStatus_0_SDmaDescAddrMisalignErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_SDmaUnexpDataErr_LSB 0x2F |
| #define QIB_7322_ErrStatus_0_SDmaUnexpDataErr_MSB 0x2F |
| #define QIB_7322_ErrStatus_0_SDmaUnexpDataErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_SDmaMissingDwErr_LSB 0x2E |
| #define QIB_7322_ErrStatus_0_SDmaMissingDwErr_MSB 0x2E |
| #define QIB_7322_ErrStatus_0_SDmaMissingDwErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_SDmaDwEnErr_LSB 0x2D |
| #define QIB_7322_ErrStatus_0_SDmaDwEnErr_MSB 0x2D |
| #define QIB_7322_ErrStatus_0_SDmaDwEnErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_SDmaRpyTagErr_LSB 0x2C |
| #define QIB_7322_ErrStatus_0_SDmaRpyTagErr_MSB 0x2C |
| #define QIB_7322_ErrStatus_0_SDmaRpyTagErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_SDma1stDescErr_LSB 0x2B |
| #define QIB_7322_ErrStatus_0_SDma1stDescErr_MSB 0x2B |
| #define QIB_7322_ErrStatus_0_SDma1stDescErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_SDmaBaseErr_LSB 0x2A |
| #define QIB_7322_ErrStatus_0_SDmaBaseErr_MSB 0x2A |
| #define QIB_7322_ErrStatus_0_SDmaBaseErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_SDmaTailOutOfBoundErr_LSB 0x29 |
| #define QIB_7322_ErrStatus_0_SDmaTailOutOfBoundErr_MSB 0x29 |
| #define QIB_7322_ErrStatus_0_SDmaTailOutOfBoundErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_SDmaOutOfBoundErr_LSB 0x28 |
| #define QIB_7322_ErrStatus_0_SDmaOutOfBoundErr_MSB 0x28 |
| #define QIB_7322_ErrStatus_0_SDmaOutOfBoundErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_SDmaGenMismatchErr_LSB 0x27 |
| #define QIB_7322_ErrStatus_0_SDmaGenMismatchErr_MSB 0x27 |
| #define QIB_7322_ErrStatus_0_SDmaGenMismatchErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_SendBufMisuseErr_LSB 0x26 |
| #define QIB_7322_ErrStatus_0_SendBufMisuseErr_MSB 0x26 |
| #define QIB_7322_ErrStatus_0_SendBufMisuseErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_SendUnsupportedVLErr_LSB 0x25 |
| #define QIB_7322_ErrStatus_0_SendUnsupportedVLErr_MSB 0x25 |
| #define QIB_7322_ErrStatus_0_SendUnsupportedVLErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_SendUnexpectedPktNumErr_LSB 0x24 |
| #define QIB_7322_ErrStatus_0_SendUnexpectedPktNumErr_MSB 0x24 |
| #define QIB_7322_ErrStatus_0_SendUnexpectedPktNumErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_SendDroppedDataPktErr_LSB 0x22 |
| #define QIB_7322_ErrStatus_0_SendDroppedDataPktErr_MSB 0x22 |
| #define QIB_7322_ErrStatus_0_SendDroppedDataPktErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_SendDroppedSmpPktErr_LSB 0x21 |
| #define QIB_7322_ErrStatus_0_SendDroppedSmpPktErr_MSB 0x21 |
| #define QIB_7322_ErrStatus_0_SendDroppedSmpPktErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_SendPktLenErr_LSB 0x20 |
| #define QIB_7322_ErrStatus_0_SendPktLenErr_MSB 0x20 |
| #define QIB_7322_ErrStatus_0_SendPktLenErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_SendUnderRunErr_LSB 0x1F |
| #define QIB_7322_ErrStatus_0_SendUnderRunErr_MSB 0x1F |
| #define QIB_7322_ErrStatus_0_SendUnderRunErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_SendMaxPktLenErr_LSB 0x1E |
| #define QIB_7322_ErrStatus_0_SendMaxPktLenErr_MSB 0x1E |
| #define QIB_7322_ErrStatus_0_SendMaxPktLenErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_SendMinPktLenErr_LSB 0x1D |
| #define QIB_7322_ErrStatus_0_SendMinPktLenErr_MSB 0x1D |
| #define QIB_7322_ErrStatus_0_SendMinPktLenErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_RcvIBLostLinkErr_LSB 0x11 |
| #define QIB_7322_ErrStatus_0_RcvIBLostLinkErr_MSB 0x11 |
| #define QIB_7322_ErrStatus_0_RcvIBLostLinkErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_RcvHdrErr_LSB 0x10 |
| #define QIB_7322_ErrStatus_0_RcvHdrErr_MSB 0x10 |
| #define QIB_7322_ErrStatus_0_RcvHdrErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_RcvHdrLenErr_LSB 0xF |
| #define QIB_7322_ErrStatus_0_RcvHdrLenErr_MSB 0xF |
| #define QIB_7322_ErrStatus_0_RcvHdrLenErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_RcvBadTidErr_LSB 0xE |
| #define QIB_7322_ErrStatus_0_RcvBadTidErr_MSB 0xE |
| #define QIB_7322_ErrStatus_0_RcvBadTidErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_RcvBadVersionErr_LSB 0xB |
| #define QIB_7322_ErrStatus_0_RcvBadVersionErr_MSB 0xB |
| #define QIB_7322_ErrStatus_0_RcvBadVersionErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_RcvIBFlowErr_LSB 0xA |
| #define QIB_7322_ErrStatus_0_RcvIBFlowErr_MSB 0xA |
| #define QIB_7322_ErrStatus_0_RcvIBFlowErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_RcvEBPErr_LSB 0x9 |
| #define QIB_7322_ErrStatus_0_RcvEBPErr_MSB 0x9 |
| #define QIB_7322_ErrStatus_0_RcvEBPErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_RcvUnsupportedVLErr_LSB 0x8 |
| #define QIB_7322_ErrStatus_0_RcvUnsupportedVLErr_MSB 0x8 |
| #define QIB_7322_ErrStatus_0_RcvUnsupportedVLErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_RcvUnexpectedCharErr_LSB 0x7 |
| #define QIB_7322_ErrStatus_0_RcvUnexpectedCharErr_MSB 0x7 |
| #define QIB_7322_ErrStatus_0_RcvUnexpectedCharErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_RcvShortPktLenErr_LSB 0x6 |
| #define QIB_7322_ErrStatus_0_RcvShortPktLenErr_MSB 0x6 |
| #define QIB_7322_ErrStatus_0_RcvShortPktLenErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_RcvLongPktLenErr_LSB 0x5 |
| #define QIB_7322_ErrStatus_0_RcvLongPktLenErr_MSB 0x5 |
| #define QIB_7322_ErrStatus_0_RcvLongPktLenErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_RcvMaxPktLenErr_LSB 0x4 |
| #define QIB_7322_ErrStatus_0_RcvMaxPktLenErr_MSB 0x4 |
| #define QIB_7322_ErrStatus_0_RcvMaxPktLenErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_RcvMinPktLenErr_LSB 0x3 |
| #define QIB_7322_ErrStatus_0_RcvMinPktLenErr_MSB 0x3 |
| #define QIB_7322_ErrStatus_0_RcvMinPktLenErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_RcvICRCErr_LSB 0x2 |
| #define QIB_7322_ErrStatus_0_RcvICRCErr_MSB 0x2 |
| #define QIB_7322_ErrStatus_0_RcvICRCErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_RcvVCRCErr_LSB 0x1 |
| #define QIB_7322_ErrStatus_0_RcvVCRCErr_MSB 0x1 |
| #define QIB_7322_ErrStatus_0_RcvVCRCErr_RMASK 0x1 |
| #define QIB_7322_ErrStatus_0_RcvFormatErr_LSB 0x0 |
| #define QIB_7322_ErrStatus_0_RcvFormatErr_MSB 0x0 |
| #define QIB_7322_ErrStatus_0_RcvFormatErr_RMASK 0x1 |
| |
| #define QIB_7322_ErrClear_0_OFFS 0x1090 |
| #define QIB_7322_ErrClear_0_DEF 0x0000000000000000 |
| #define QIB_7322_ErrClear_0_IBStatusChangedClear_LSB 0x3A |
| #define QIB_7322_ErrClear_0_IBStatusChangedClear_MSB 0x3A |
| #define QIB_7322_ErrClear_0_IBStatusChangedClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_SHeadersErrClear_LSB 0x39 |
| #define QIB_7322_ErrClear_0_SHeadersErrClear_MSB 0x39 |
| #define QIB_7322_ErrClear_0_SHeadersErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_VL15BufMisuseErrClear_LSB 0x36 |
| #define QIB_7322_ErrClear_0_VL15BufMisuseErrClear_MSB 0x36 |
| #define QIB_7322_ErrClear_0_VL15BufMisuseErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_SDmaHaltErrClear_LSB 0x31 |
| #define QIB_7322_ErrClear_0_SDmaHaltErrClear_MSB 0x31 |
| #define QIB_7322_ErrClear_0_SDmaHaltErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_SDmaDescAddrMisalignErrClear_LSB 0x30 |
| #define QIB_7322_ErrClear_0_SDmaDescAddrMisalignErrClear_MSB 0x30 |
| #define QIB_7322_ErrClear_0_SDmaDescAddrMisalignErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_SDmaUnexpDataErrClear_LSB 0x2F |
| #define QIB_7322_ErrClear_0_SDmaUnexpDataErrClear_MSB 0x2F |
| #define QIB_7322_ErrClear_0_SDmaUnexpDataErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_SDmaMissingDwErrClear_LSB 0x2E |
| #define QIB_7322_ErrClear_0_SDmaMissingDwErrClear_MSB 0x2E |
| #define QIB_7322_ErrClear_0_SDmaMissingDwErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_SDmaDwEnErrClear_LSB 0x2D |
| #define QIB_7322_ErrClear_0_SDmaDwEnErrClear_MSB 0x2D |
| #define QIB_7322_ErrClear_0_SDmaDwEnErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_SDmaRpyTagErrClear_LSB 0x2C |
| #define QIB_7322_ErrClear_0_SDmaRpyTagErrClear_MSB 0x2C |
| #define QIB_7322_ErrClear_0_SDmaRpyTagErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_SDma1stDescErrClear_LSB 0x2B |
| #define QIB_7322_ErrClear_0_SDma1stDescErrClear_MSB 0x2B |
| #define QIB_7322_ErrClear_0_SDma1stDescErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_SDmaBaseErrClear_LSB 0x2A |
| #define QIB_7322_ErrClear_0_SDmaBaseErrClear_MSB 0x2A |
| #define QIB_7322_ErrClear_0_SDmaBaseErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_SDmaTailOutOfBoundErrClear_LSB 0x29 |
| #define QIB_7322_ErrClear_0_SDmaTailOutOfBoundErrClear_MSB 0x29 |
| #define QIB_7322_ErrClear_0_SDmaTailOutOfBoundErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_SDmaOutOfBoundErrClear_LSB 0x28 |
| #define QIB_7322_ErrClear_0_SDmaOutOfBoundErrClear_MSB 0x28 |
| #define QIB_7322_ErrClear_0_SDmaOutOfBoundErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_SDmaGenMismatchErrClear_LSB 0x27 |
| #define QIB_7322_ErrClear_0_SDmaGenMismatchErrClear_MSB 0x27 |
| #define QIB_7322_ErrClear_0_SDmaGenMismatchErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_SendBufMisuseErrClear_LSB 0x26 |
| #define QIB_7322_ErrClear_0_SendBufMisuseErrClear_MSB 0x26 |
| #define QIB_7322_ErrClear_0_SendBufMisuseErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_SendUnsupportedVLErrClear_LSB 0x25 |
| #define QIB_7322_ErrClear_0_SendUnsupportedVLErrClear_MSB 0x25 |
| #define QIB_7322_ErrClear_0_SendUnsupportedVLErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_SendUnexpectedPktNumErrClear_LSB 0x24 |
| #define QIB_7322_ErrClear_0_SendUnexpectedPktNumErrClear_MSB 0x24 |
| #define QIB_7322_ErrClear_0_SendUnexpectedPktNumErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_SendDroppedDataPktErrClear_LSB 0x22 |
| #define QIB_7322_ErrClear_0_SendDroppedDataPktErrClear_MSB 0x22 |
| #define QIB_7322_ErrClear_0_SendDroppedDataPktErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_SendDroppedSmpPktErrClear_LSB 0x21 |
| #define QIB_7322_ErrClear_0_SendDroppedSmpPktErrClear_MSB 0x21 |
| #define QIB_7322_ErrClear_0_SendDroppedSmpPktErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_SendPktLenErrClear_LSB 0x20 |
| #define QIB_7322_ErrClear_0_SendPktLenErrClear_MSB 0x20 |
| #define QIB_7322_ErrClear_0_SendPktLenErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_SendUnderRunErrClear_LSB 0x1F |
| #define QIB_7322_ErrClear_0_SendUnderRunErrClear_MSB 0x1F |
| #define QIB_7322_ErrClear_0_SendUnderRunErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_SendMaxPktLenErrClear_LSB 0x1E |
| #define QIB_7322_ErrClear_0_SendMaxPktLenErrClear_MSB 0x1E |
| #define QIB_7322_ErrClear_0_SendMaxPktLenErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_SendMinPktLenErrClear_LSB 0x1D |
| #define QIB_7322_ErrClear_0_SendMinPktLenErrClear_MSB 0x1D |
| #define QIB_7322_ErrClear_0_SendMinPktLenErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_RcvIBLostLinkErrClear_LSB 0x11 |
| #define QIB_7322_ErrClear_0_RcvIBLostLinkErrClear_MSB 0x11 |
| #define QIB_7322_ErrClear_0_RcvIBLostLinkErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_RcvHdrErrClear_LSB 0x10 |
| #define QIB_7322_ErrClear_0_RcvHdrErrClear_MSB 0x10 |
| #define QIB_7322_ErrClear_0_RcvHdrErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_RcvHdrLenErrClear_LSB 0xF |
| #define QIB_7322_ErrClear_0_RcvHdrLenErrClear_MSB 0xF |
| #define QIB_7322_ErrClear_0_RcvHdrLenErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_RcvBadTidErrClear_LSB 0xE |
| #define QIB_7322_ErrClear_0_RcvBadTidErrClear_MSB 0xE |
| #define QIB_7322_ErrClear_0_RcvBadTidErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_RcvBadVersionErrClear_LSB 0xB |
| #define QIB_7322_ErrClear_0_RcvBadVersionErrClear_MSB 0xB |
| #define QIB_7322_ErrClear_0_RcvBadVersionErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_RcvIBFlowErrClear_LSB 0xA |
| #define QIB_7322_ErrClear_0_RcvIBFlowErrClear_MSB 0xA |
| #define QIB_7322_ErrClear_0_RcvIBFlowErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_RcvEBPErrClear_LSB 0x9 |
| #define QIB_7322_ErrClear_0_RcvEBPErrClear_MSB 0x9 |
| #define QIB_7322_ErrClear_0_RcvEBPErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_RcvUnsupportedVLErrClear_LSB 0x8 |
| #define QIB_7322_ErrClear_0_RcvUnsupportedVLErrClear_MSB 0x8 |
| #define QIB_7322_ErrClear_0_RcvUnsupportedVLErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_RcvUnexpectedCharErrClear_LSB 0x7 |
| #define QIB_7322_ErrClear_0_RcvUnexpectedCharErrClear_MSB 0x7 |
| #define QIB_7322_ErrClear_0_RcvUnexpectedCharErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_RcvShortPktLenErrClear_LSB 0x6 |
| #define QIB_7322_ErrClear_0_RcvShortPktLenErrClear_MSB 0x6 |
| #define QIB_7322_ErrClear_0_RcvShortPktLenErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_RcvLongPktLenErrClear_LSB 0x5 |
| #define QIB_7322_ErrClear_0_RcvLongPktLenErrClear_MSB 0x5 |
| #define QIB_7322_ErrClear_0_RcvLongPktLenErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_RcvMaxPktLenErrClear_LSB 0x4 |
| #define QIB_7322_ErrClear_0_RcvMaxPktLenErrClear_MSB 0x4 |
| #define QIB_7322_ErrClear_0_RcvMaxPktLenErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_RcvMinPktLenErrClear_LSB 0x3 |
| #define QIB_7322_ErrClear_0_RcvMinPktLenErrClear_MSB 0x3 |
| #define QIB_7322_ErrClear_0_RcvMinPktLenErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_RcvICRCErrClear_LSB 0x2 |
| #define QIB_7322_ErrClear_0_RcvICRCErrClear_MSB 0x2 |
| #define QIB_7322_ErrClear_0_RcvICRCErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_RcvVCRCErrClear_LSB 0x1 |
| #define QIB_7322_ErrClear_0_RcvVCRCErrClear_MSB 0x1 |
| #define QIB_7322_ErrClear_0_RcvVCRCErrClear_RMASK 0x1 |
| #define QIB_7322_ErrClear_0_RcvFormatErrClear_LSB 0x0 |
| #define QIB_7322_ErrClear_0_RcvFormatErrClear_MSB 0x0 |
| #define QIB_7322_ErrClear_0_RcvFormatErrClear_RMASK 0x1 |
| |
| #define QIB_7322_TXEStatus_0_OFFS 0x10B8 |
| #define QIB_7322_TXEStatus_0_DEF 0x0000000XC00080FF |
| #define QIB_7322_TXEStatus_0_TXE_IBC_Idle_LSB 0x1F |
| #define QIB_7322_TXEStatus_0_TXE_IBC_Idle_MSB 0x1F |
| #define QIB_7322_TXEStatus_0_TXE_IBC_Idle_RMASK 0x1 |
| #define QIB_7322_TXEStatus_0_RmFifoEmpty_LSB 0x1E |
| #define QIB_7322_TXEStatus_0_RmFifoEmpty_MSB 0x1E |
| #define QIB_7322_TXEStatus_0_RmFifoEmpty_RMASK 0x1 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL15_LSB 0xF |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL15_MSB 0xF |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL15_RMASK 0x1 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL7_LSB 0x7 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL7_MSB 0x7 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL7_RMASK 0x1 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL6_LSB 0x6 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL6_MSB 0x6 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL6_RMASK 0x1 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL5_LSB 0x5 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL5_MSB 0x5 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL5_RMASK 0x1 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL4_LSB 0x4 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL4_MSB 0x4 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL4_RMASK 0x1 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL3_LSB 0x3 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL3_MSB 0x3 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL3_RMASK 0x1 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL2_LSB 0x2 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL2_MSB 0x2 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL2_RMASK 0x1 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL1_LSB 0x1 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL1_MSB 0x1 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL1_RMASK 0x1 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL0_LSB 0x0 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL0_MSB 0x0 |
| #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL0_RMASK 0x1 |
| |
| #define QIB_7322_RcvCtrl_0_OFFS 0x1100 |
| #define QIB_7322_RcvCtrl_0_DEF 0x0000000000000000 |
| #define QIB_7322_RcvCtrl_0_RcvResetCredit_LSB 0x2A |
| #define QIB_7322_RcvCtrl_0_RcvResetCredit_MSB 0x2A |
| #define QIB_7322_RcvCtrl_0_RcvResetCredit_RMASK 0x1 |
| #define QIB_7322_RcvCtrl_0_RcvPartitionKeyDisable_LSB 0x29 |
| #define QIB_7322_RcvCtrl_0_RcvPartitionKeyDisable_MSB 0x29 |
| #define QIB_7322_RcvCtrl_0_RcvPartitionKeyDisable_RMASK 0x1 |
| #define QIB_7322_RcvCtrl_0_RcvQPMapEnable_LSB 0x28 |
| #define QIB_7322_RcvCtrl_0_RcvQPMapEnable_MSB 0x28 |
| #define QIB_7322_RcvCtrl_0_RcvQPMapEnable_RMASK 0x1 |
| #define QIB_7322_RcvCtrl_0_RcvIBPortEnable_LSB 0x27 |
| #define QIB_7322_RcvCtrl_0_RcvIBPortEnable_MSB 0x27 |
| #define QIB_7322_RcvCtrl_0_RcvIBPortEnable_RMASK 0x1 |
| #define QIB_7322_RcvCtrl_0_ContextEnableUser_LSB 0x2 |
| #define QIB_7322_RcvCtrl_0_ContextEnableUser_MSB 0x11 |
| #define QIB_7322_RcvCtrl_0_ContextEnableUser_RMASK 0xFFFF |
| #define QIB_7322_RcvCtrl_0_ContextEnableKernel_LSB 0x0 |
| #define QIB_7322_RcvCtrl_0_ContextEnableKernel_MSB 0x0 |
| #define QIB_7322_RcvCtrl_0_ContextEnableKernel_RMASK 0x1 |
| |
| #define QIB_7322_RcvBTHQP_0_OFFS 0x1108 |
| #define QIB_7322_RcvBTHQP_0_DEF 0x0000000000000000 |
| #define QIB_7322_RcvBTHQP_0_RcvBTHQP_LSB 0x0 |
| #define QIB_7322_RcvBTHQP_0_RcvBTHQP_MSB 0x17 |
| #define QIB_7322_RcvBTHQP_0_RcvBTHQP_RMASK 0xFFFFFF |
| |
| #define QIB_7322_RcvQPMapTableA_0_OFFS 0x1110 |
| #define QIB_7322_RcvQPMapTableA_0_DEF 0x0000000000000000 |
| #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext5_LSB 0x19 |
| #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext5_MSB 0x1D |
| #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext5_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext4_LSB 0x14 |
| #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext4_MSB 0x18 |
| #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext4_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext3_LSB 0xF |
| #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext3_MSB 0x13 |
| #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext3_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext2_LSB 0xA |
| #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext2_MSB 0xE |
| #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext2_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext1_LSB 0x5 |
| #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext1_MSB 0x9 |
| #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext1_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext0_LSB 0x0 |
| #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext0_MSB 0x4 |
| #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext0_RMASK 0x1F |
| |
| #define QIB_7322_RcvQPMapTableB_0_OFFS 0x1118 |
| #define QIB_7322_RcvQPMapTableB_0_DEF 0x0000000000000000 |
| #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext11_LSB 0x19 |
| #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext11_MSB 0x1D |
| #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext11_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext10_LSB 0x14 |
| #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext10_MSB 0x18 |
| #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext10_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext9_LSB 0xF |
| #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext9_MSB 0x13 |
| #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext9_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext8_LSB 0xA |
| #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext8_MSB 0xE |
| #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext8_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext7_LSB 0x5 |
| #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext7_MSB 0x9 |
| #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext7_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext6_LSB 0x0 |
| #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext6_MSB 0x4 |
| #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext6_RMASK 0x1F |
| |
| #define QIB_7322_RcvQPMapTableC_0_OFFS 0x1120 |
| #define QIB_7322_RcvQPMapTableC_0_DEF 0x0000000000000000 |
| #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext17_LSB 0x19 |
| #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext17_MSB 0x1D |
| #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext17_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext16_LSB 0x14 |
| #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext16_MSB 0x18 |
| #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext16_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext15_LSB 0xF |
| #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext15_MSB 0x13 |
| #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext15_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext14_LSB 0xA |
| #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext14_MSB 0xE |
| #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext14_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext13_LSB 0x5 |
| #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext13_MSB 0x9 |
| #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext13_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext12_LSB 0x0 |
| #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext12_MSB 0x4 |
| #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext12_RMASK 0x1F |
| |
| #define QIB_7322_RcvQPMapTableD_0_OFFS 0x1128 |
| #define QIB_7322_RcvQPMapTableD_0_DEF 0x0000000000000000 |
| #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext23_LSB 0x19 |
| #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext23_MSB 0x1D |
| #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext23_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext22_LSB 0x14 |
| #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext22_MSB 0x18 |
| #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext22_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext21_LSB 0xF |
| #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext21_MSB 0x13 |
| #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext21_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext20_LSB 0xA |
| #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext20_MSB 0xE |
| #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext20_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext19_LSB 0x5 |
| #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext19_MSB 0x9 |
| #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext19_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext18_LSB 0x0 |
| #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext18_MSB 0x4 |
| #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext18_RMASK 0x1F |
| |
| #define QIB_7322_RcvQPMapTableE_0_OFFS 0x1130 |
| #define QIB_7322_RcvQPMapTableE_0_DEF 0x0000000000000000 |
| #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext29_LSB 0x19 |
| #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext29_MSB 0x1D |
| #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext29_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext28_LSB 0x14 |
| #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext28_MSB 0x18 |
| #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext28_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext27_LSB 0xF |
| #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext27_MSB 0x13 |
| #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext27_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext26_LSB 0xA |
| #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext26_MSB 0xE |
| #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext26_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext25_LSB 0x5 |
| #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext25_MSB 0x9 |
| #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext25_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext24_LSB 0x0 |
| #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext24_MSB 0x4 |
| #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext24_RMASK 0x1F |
| |
| #define QIB_7322_RcvQPMapTableF_0_OFFS 0x1138 |
| #define QIB_7322_RcvQPMapTableF_0_DEF 0x0000000000000000 |
| #define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext31_LSB 0x5 |
| #define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext31_MSB 0x9 |
| #define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext31_RMASK 0x1F |
| #define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext30_LSB 0x0 |
| #define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext30_MSB 0x4 |
| #define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext30_RMASK 0x1F |
| |
| #define QIB_7322_PSStat_0_OFFS 0x1140 |
| #define QIB_7322_PSStat_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_PSStart_0_OFFS 0x1148 |
| #define QIB_7322_PSStart_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_PSInterval_0_OFFS 0x1150 |
| #define QIB_7322_PSInterval_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RcvStatus_0_OFFS 0x1160 |
| #define QIB_7322_RcvStatus_0_DEF 0x0000000000000000 |
| #define QIB_7322_RcvStatus_0_DmaeqBlockingContext_LSB 0x1 |
| #define QIB_7322_RcvStatus_0_DmaeqBlockingContext_MSB 0x5 |
| #define QIB_7322_RcvStatus_0_DmaeqBlockingContext_RMASK 0x1F |
| #define QIB_7322_RcvStatus_0_RxPktInProgress_LSB 0x0 |
| #define QIB_7322_RcvStatus_0_RxPktInProgress_MSB 0x0 |
| #define QIB_7322_RcvStatus_0_RxPktInProgress_RMASK 0x1 |
| |
| #define QIB_7322_RcvPartitionKey_0_OFFS 0x1168 |
| #define QIB_7322_RcvPartitionKey_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RcvQPMulticastContext_0_OFFS 0x1170 |
| #define QIB_7322_RcvQPMulticastContext_0_DEF 0x0000000000000000 |
| #define QIB_7322_RcvQPMulticastContext_0_RcvQpMcContext_LSB 0x0 |
| #define QIB_7322_RcvQPMulticastContext_0_RcvQpMcContext_MSB 0x4 |
| #define QIB_7322_RcvQPMulticastContext_0_RcvQpMcContext_RMASK 0x1F |
| |
| #define QIB_7322_RcvPktLEDCnt_0_OFFS 0x1178 |
| #define QIB_7322_RcvPktLEDCnt_0_DEF 0x0000000000000000 |
| #define QIB_7322_RcvPktLEDCnt_0_ONperiod_LSB 0x20 |
| #define QIB_7322_RcvPktLEDCnt_0_ONperiod_MSB 0x3F |
| #define QIB_7322_RcvPktLEDCnt_0_ONperiod_RMASK 0xFFFFFFFF |
| #define QIB_7322_RcvPktLEDCnt_0_OFFperiod_LSB 0x0 |
| #define QIB_7322_RcvPktLEDCnt_0_OFFperiod_MSB 0x1F |
| #define QIB_7322_RcvPktLEDCnt_0_OFFperiod_RMASK 0xFFFFFFFF |
| |
| #define QIB_7322_SendDmaIdleCnt_0_OFFS 0x1180 |
| #define QIB_7322_SendDmaIdleCnt_0_DEF 0x0000000000000000 |
| #define QIB_7322_SendDmaIdleCnt_0_SendDmaIdleCnt_LSB 0x0 |
| #define QIB_7322_SendDmaIdleCnt_0_SendDmaIdleCnt_MSB 0xF |
| #define QIB_7322_SendDmaIdleCnt_0_SendDmaIdleCnt_RMASK 0xFFFF |
| |
| #define QIB_7322_SendDmaReloadCnt_0_OFFS 0x1188 |
| #define QIB_7322_SendDmaReloadCnt_0_DEF 0x0000000000000000 |
| #define QIB_7322_SendDmaReloadCnt_0_SendDmaReloadCnt_LSB 0x0 |
| #define QIB_7322_SendDmaReloadCnt_0_SendDmaReloadCnt_MSB 0xF |
| #define QIB_7322_SendDmaReloadCnt_0_SendDmaReloadCnt_RMASK 0xFFFF |
| |
| #define QIB_7322_SendDmaDescCnt_0_OFFS 0x1190 |
| #define QIB_7322_SendDmaDescCnt_0_DEF 0x0000000000000000 |
| #define QIB_7322_SendDmaDescCnt_0_SendDmaDescCnt_LSB 0x0 |
| #define QIB_7322_SendDmaDescCnt_0_SendDmaDescCnt_MSB 0xF |
| #define QIB_7322_SendDmaDescCnt_0_SendDmaDescCnt_RMASK 0xFFFF |
| |
| #define QIB_7322_SendCtrl_0_OFFS 0x11C0 |
| #define QIB_7322_SendCtrl_0_DEF 0x0000000000000000 |
| #define QIB_7322_SendCtrl_0_IBVLArbiterEn_LSB 0xF |
| #define QIB_7322_SendCtrl_0_IBVLArbiterEn_MSB 0xF |
| #define QIB_7322_SendCtrl_0_IBVLArbiterEn_RMASK 0x1 |
| #define QIB_7322_SendCtrl_0_TxeDrainRmFifo_LSB 0xE |
| #define QIB_7322_SendCtrl_0_TxeDrainRmFifo_MSB 0xE |
| #define QIB_7322_SendCtrl_0_TxeDrainRmFifo_RMASK 0x1 |
| #define QIB_7322_SendCtrl_0_TxeDrainLaFifo_LSB 0xD |
| #define QIB_7322_SendCtrl_0_TxeDrainLaFifo_MSB 0xD |
| #define QIB_7322_SendCtrl_0_TxeDrainLaFifo_RMASK 0x1 |
| #define QIB_7322_SendCtrl_0_SDmaHalt_LSB 0xC |
| #define QIB_7322_SendCtrl_0_SDmaHalt_MSB 0xC |
| #define QIB_7322_SendCtrl_0_SDmaHalt_RMASK 0x1 |
| #define QIB_7322_SendCtrl_0_SDmaEnable_LSB 0xB |
| #define QIB_7322_SendCtrl_0_SDmaEnable_MSB 0xB |
| #define QIB_7322_SendCtrl_0_SDmaEnable_RMASK 0x1 |
| #define QIB_7322_SendCtrl_0_SDmaSingleDescriptor_LSB 0xA |
| #define QIB_7322_SendCtrl_0_SDmaSingleDescriptor_MSB 0xA |
| #define QIB_7322_SendCtrl_0_SDmaSingleDescriptor_RMASK 0x1 |
| #define QIB_7322_SendCtrl_0_SDmaIntEnable_LSB 0x9 |
| #define QIB_7322_SendCtrl_0_SDmaIntEnable_MSB 0x9 |
| #define QIB_7322_SendCtrl_0_SDmaIntEnable_RMASK 0x1 |
| #define QIB_7322_SendCtrl_0_SDmaCleanup_LSB 0x8 |
| #define QIB_7322_SendCtrl_0_SDmaCleanup_MSB 0x8 |
| #define QIB_7322_SendCtrl_0_SDmaCleanup_RMASK 0x1 |
| #define QIB_7322_SendCtrl_0_ForceCreditUpToDate_LSB 0x7 |
| #define QIB_7322_SendCtrl_0_ForceCreditUpToDate_MSB 0x7 |
| #define QIB_7322_SendCtrl_0_ForceCreditUpToDate_RMASK 0x1 |
| #define QIB_7322_SendCtrl_0_SendEnable_LSB 0x3 |
| #define QIB_7322_SendCtrl_0_SendEnable_MSB 0x3 |
| #define QIB_7322_SendCtrl_0_SendEnable_RMASK 0x1 |
| #define QIB_7322_SendCtrl_0_TxeBypassIbc_LSB 0x1 |
| #define QIB_7322_SendCtrl_0_TxeBypassIbc_MSB 0x1 |
| #define QIB_7322_SendCtrl_0_TxeBypassIbc_RMASK 0x1 |
| #define QIB_7322_SendCtrl_0_TxeAbortIbc_LSB 0x0 |
| #define QIB_7322_SendCtrl_0_TxeAbortIbc_MSB 0x0 |
| #define QIB_7322_SendCtrl_0_TxeAbortIbc_RMASK 0x1 |
| |
| #define QIB_7322_SendDmaBase_0_OFFS 0x11F8 |
| #define QIB_7322_SendDmaBase_0_DEF 0x0000000000000000 |
| #define QIB_7322_SendDmaBase_0_SendDmaBase_LSB 0x0 |
| #define QIB_7322_SendDmaBase_0_SendDmaBase_MSB 0x2F |
| #define QIB_7322_SendDmaBase_0_SendDmaBase_RMASK 0xFFFFFFFFFFFF |
| |
| #define QIB_7322_SendDmaLenGen_0_OFFS 0x1200 |
| #define QIB_7322_SendDmaLenGen_0_DEF 0x0000000000000000 |
| #define QIB_7322_SendDmaLenGen_0_Generation_LSB 0x10 |
| #define QIB_7322_SendDmaLenGen_0_Generation_MSB 0x12 |
| #define QIB_7322_SendDmaLenGen_0_Generation_RMASK 0x7 |
| #define QIB_7322_SendDmaLenGen_0_Length_LSB 0x0 |
| #define QIB_7322_SendDmaLenGen_0_Length_MSB 0xF |
| #define QIB_7322_SendDmaLenGen_0_Length_RMASK 0xFFFF |
| |
| #define QIB_7322_SendDmaTail_0_OFFS 0x1208 |
| #define QIB_7322_SendDmaTail_0_DEF 0x0000000000000000 |
| #define QIB_7322_SendDmaTail_0_SendDmaTail_LSB 0x0 |
| #define QIB_7322_SendDmaTail_0_SendDmaTail_MSB 0xF |
| #define QIB_7322_SendDmaTail_0_SendDmaTail_RMASK 0xFFFF |
| |
| #define QIB_7322_SendDmaHead_0_OFFS 0x1210 |
| #define QIB_7322_SendDmaHead_0_DEF 0x0000000000000000 |
| #define QIB_7322_SendDmaHead_0_InternalSendDmaHead_LSB 0x20 |
| #define QIB_7322_SendDmaHead_0_InternalSendDmaHead_MSB 0x2F |
| #define QIB_7322_SendDmaHead_0_InternalSendDmaHead_RMASK 0xFFFF |
| #define QIB_7322_SendDmaHead_0_SendDmaHead_LSB 0x0 |
| #define QIB_7322_SendDmaHead_0_SendDmaHead_MSB 0xF |
| #define QIB_7322_SendDmaHead_0_SendDmaHead_RMASK 0xFFFF |
| |
| #define QIB_7322_SendDmaHeadAddr_0_OFFS 0x1218 |
| #define QIB_7322_SendDmaHeadAddr_0_DEF 0x0000000000000000 |
| #define QIB_7322_SendDmaHeadAddr_0_SendDmaHeadAddr_LSB 0x0 |
| #define QIB_7322_SendDmaHeadAddr_0_SendDmaHeadAddr_MSB 0x2F |
| #define QIB_7322_SendDmaHeadAddr_0_SendDmaHeadAddr_RMASK 0xFFFFFFFFFFFF |
| |
| #define QIB_7322_SendDmaBufMask0_0_OFFS 0x1220 |
| #define QIB_7322_SendDmaBufMask0_0_DEF 0x0000000000000000 |
| #define QIB_7322_SendDmaBufMask0_0_BufMask_63_0_LSB 0x0 |
| #define QIB_7322_SendDmaBufMask0_0_BufMask_63_0_MSB 0x3F |
| #define QIB_7322_SendDmaBufMask0_0_BufMask_63_0_RMASK 0x0 |
| |
| #define QIB_7322_SendDmaStatus_0_OFFS 0x1238 |
| #define QIB_7322_SendDmaStatus_0_DEF 0x0000000042000000 |
| #define QIB_7322_SendDmaStatus_0_ScoreBoardDrainInProg_LSB 0x3F |
| #define QIB_7322_SendDmaStatus_0_ScoreBoardDrainInProg_MSB 0x3F |
| #define QIB_7322_SendDmaStatus_0_ScoreBoardDrainInProg_RMASK 0x1 |
| #define QIB_7322_SendDmaStatus_0_HaltInProg_LSB 0x3E |
| #define QIB_7322_SendDmaStatus_0_HaltInProg_MSB 0x3E |
| #define QIB_7322_SendDmaStatus_0_HaltInProg_RMASK 0x1 |
| #define QIB_7322_SendDmaStatus_0_InternalSDmaHalt_LSB 0x3D |
| #define QIB_7322_SendDmaStatus_0_InternalSDmaHalt_MSB 0x3D |
| #define QIB_7322_SendDmaStatus_0_InternalSDmaHalt_RMASK 0x1 |
| #define QIB_7322_SendDmaStatus_0_ScbDescIndex_13_0_LSB 0x2F |
| #define QIB_7322_SendDmaStatus_0_ScbDescIndex_13_0_MSB 0x3C |
| #define QIB_7322_SendDmaStatus_0_ScbDescIndex_13_0_RMASK 0x3FFF |
| #define QIB_7322_SendDmaStatus_0_RpyLowAddr_6_0_LSB 0x28 |
| #define QIB_7322_SendDmaStatus_0_RpyLowAddr_6_0_MSB 0x2E |
| #define QIB_7322_SendDmaStatus_0_RpyLowAddr_6_0_RMASK 0x7F |
| #define QIB_7322_SendDmaStatus_0_RpyTag_7_0_LSB 0x20 |
| #define QIB_7322_SendDmaStatus_0_RpyTag_7_0_MSB 0x27 |
| #define QIB_7322_SendDmaStatus_0_RpyTag_7_0_RMASK 0xFF |
| #define QIB_7322_SendDmaStatus_0_ScbFull_LSB 0x1F |
| #define QIB_7322_SendDmaStatus_0_ScbFull_MSB 0x1F |
| #define QIB_7322_SendDmaStatus_0_ScbFull_RMASK 0x1 |
| #define QIB_7322_SendDmaStatus_0_ScbEmpty_LSB 0x1E |
| #define QIB_7322_SendDmaStatus_0_ScbEmpty_MSB 0x1E |
| #define QIB_7322_SendDmaStatus_0_ScbEmpty_RMASK 0x1 |
| #define QIB_7322_SendDmaStatus_0_ScbEntryValid_LSB 0x1D |
| #define QIB_7322_SendDmaStatus_0_ScbEntryValid_MSB 0x1D |
| #define QIB_7322_SendDmaStatus_0_ScbEntryValid_RMASK 0x1 |
| #define QIB_7322_SendDmaStatus_0_ScbFetchDescFlag_LSB 0x1C |
| #define QIB_7322_SendDmaStatus_0_ScbFetchDescFlag_MSB 0x1C |
| #define QIB_7322_SendDmaStatus_0_ScbFetchDescFlag_RMASK 0x1 |
| #define QIB_7322_SendDmaStatus_0_SplFifoReadyToGo_LSB 0x1B |
| #define QIB_7322_SendDmaStatus_0_SplFifoReadyToGo_MSB 0x1B |
| #define QIB_7322_SendDmaStatus_0_SplFifoReadyToGo_RMASK 0x1 |
| #define QIB_7322_SendDmaStatus_0_SplFifoDisarmed_LSB 0x1A |
| #define QIB_7322_SendDmaStatus_0_SplFifoDisarmed_MSB 0x1A |
| #define QIB_7322_SendDmaStatus_0_SplFifoDisarmed_RMASK 0x1 |
| #define QIB_7322_SendDmaStatus_0_SplFifoEmpty_LSB 0x19 |
| #define QIB_7322_SendDmaStatus_0_SplFifoEmpty_MSB 0x19 |
| #define QIB_7322_SendDmaStatus_0_SplFifoEmpty_RMASK 0x1 |
| #define QIB_7322_SendDmaStatus_0_SplFifoFull_LSB 0x18 |
| #define QIB_7322_SendDmaStatus_0_SplFifoFull_MSB 0x18 |
| #define QIB_7322_SendDmaStatus_0_SplFifoFull_RMASK 0x1 |
| #define QIB_7322_SendDmaStatus_0_SplFifoBufNum_LSB 0x10 |
| #define QIB_7322_SendDmaStatus_0_SplFifoBufNum_MSB 0x17 |
| #define QIB_7322_SendDmaStatus_0_SplFifoBufNum_RMASK 0xFF |
| #define QIB_7322_SendDmaStatus_0_SplFifoDescIndex_LSB 0x0 |
| #define QIB_7322_SendDmaStatus_0_SplFifoDescIndex_MSB 0xF |
| #define QIB_7322_SendDmaStatus_0_SplFifoDescIndex_RMASK 0xFFFF |
| |
| #define QIB_7322_SendDmaPriorityThld_0_OFFS 0x1258 |
| #define QIB_7322_SendDmaPriorityThld_0_DEF 0x0000000000000000 |
| #define QIB_7322_SendDmaPriorityThld_0_PriorityThreshold_LSB 0x0 |
| #define QIB_7322_SendDmaPriorityThld_0_PriorityThreshold_MSB 0x3 |
| #define QIB_7322_SendDmaPriorityThld_0_PriorityThreshold_RMASK 0xF |
| |
| #define QIB_7322_SendHdrErrSymptom_0_OFFS 0x1260 |
| #define QIB_7322_SendHdrErrSymptom_0_DEF 0x0000000000000000 |
| #define QIB_7322_SendHdrErrSymptom_0_NonKeyPacket_LSB 0x6 |
| #define QIB_7322_SendHdrErrSymptom_0_NonKeyPacket_MSB 0x6 |
| #define QIB_7322_SendHdrErrSymptom_0_NonKeyPacket_RMASK 0x1 |
| #define QIB_7322_SendHdrErrSymptom_0_GRHFail_LSB 0x5 |
| #define QIB_7322_SendHdrErrSymptom_0_GRHFail_MSB 0x5 |
| #define QIB_7322_SendHdrErrSymptom_0_GRHFail_RMASK 0x1 |
| #define QIB_7322_SendHdrErrSymptom_0_PkeyFail_LSB 0x4 |
| #define QIB_7322_SendHdrErrSymptom_0_PkeyFail_MSB 0x4 |
| #define QIB_7322_SendHdrErrSymptom_0_PkeyFail_RMASK 0x1 |
| #define QIB_7322_SendHdrErrSymptom_0_QPFail_LSB 0x3 |
| #define QIB_7322_SendHdrErrSymptom_0_QPFail_MSB 0x3 |
| #define QIB_7322_SendHdrErrSymptom_0_QPFail_RMASK 0x1 |
| #define QIB_7322_SendHdrErrSymptom_0_SLIDFail_LSB 0x2 |
| #define QIB_7322_SendHdrErrSymptom_0_SLIDFail_MSB 0x2 |
| #define QIB_7322_SendHdrErrSymptom_0_SLIDFail_RMASK 0x1 |
| #define QIB_7322_SendHdrErrSymptom_0_RawIPV6_LSB 0x1 |
| #define QIB_7322_SendHdrErrSymptom_0_RawIPV6_MSB 0x1 |
| #define QIB_7322_SendHdrErrSymptom_0_RawIPV6_RMASK 0x1 |
| #define QIB_7322_SendHdrErrSymptom_0_PacketTooSmall_LSB 0x0 |
| #define QIB_7322_SendHdrErrSymptom_0_PacketTooSmall_MSB 0x0 |
| #define QIB_7322_SendHdrErrSymptom_0_PacketTooSmall_RMASK 0x1 |
| |
| #define QIB_7322_RxCreditVL0_0_OFFS 0x1280 |
| #define QIB_7322_RxCreditVL0_0_DEF 0x0000000000000000 |
| #define QIB_7322_RxCreditVL0_0_RxBufrConsumedVL_LSB 0x10 |
| #define QIB_7322_RxCreditVL0_0_RxBufrConsumedVL_MSB 0x1B |
| #define QIB_7322_RxCreditVL0_0_RxBufrConsumedVL_RMASK 0xFFF |
| #define QIB_7322_RxCreditVL0_0_RxMaxCreditVL_LSB 0x0 |
| #define QIB_7322_RxCreditVL0_0_RxMaxCreditVL_MSB 0xB |
| #define QIB_7322_RxCreditVL0_0_RxMaxCreditVL_RMASK 0xFFF |
| |
| #define QIB_7322_SendDmaBufUsed0_0_OFFS 0x1480 |
| #define QIB_7322_SendDmaBufUsed0_0_DEF 0x0000000000000000 |
| #define QIB_7322_SendDmaBufUsed0_0_BufUsed_63_0_LSB 0x0 |
| #define QIB_7322_SendDmaBufUsed0_0_BufUsed_63_0_MSB 0x3F |
| #define QIB_7322_SendDmaBufUsed0_0_BufUsed_63_0_RMASK 0x0 |
| |
| #define QIB_7322_SendCheckControl_0_OFFS 0x14A8 |
| #define QIB_7322_SendCheckControl_0_DEF 0x0000000000000000 |
| #define QIB_7322_SendCheckControl_0_PKey_En_LSB 0x4 |
| #define QIB_7322_SendCheckControl_0_PKey_En_MSB 0x4 |
| #define QIB_7322_SendCheckControl_0_PKey_En_RMASK 0x1 |
| #define QIB_7322_SendCheckControl_0_BTHQP_En_LSB 0x3 |
| #define QIB_7322_SendCheckControl_0_BTHQP_En_MSB 0x3 |
| #define QIB_7322_SendCheckControl_0_BTHQP_En_RMASK 0x1 |
| #define QIB_7322_SendCheckControl_0_SLID_En_LSB 0x2 |
| #define QIB_7322_SendCheckControl_0_SLID_En_MSB 0x2 |
| #define QIB_7322_SendCheckControl_0_SLID_En_RMASK 0x1 |
| #define QIB_7322_SendCheckControl_0_RawIPV6_En_LSB 0x1 |
| #define QIB_7322_SendCheckControl_0_RawIPV6_En_MSB 0x1 |
| #define QIB_7322_SendCheckControl_0_RawIPV6_En_RMASK 0x1 |
| #define QIB_7322_SendCheckControl_0_PacketTooSmall_En_LSB 0x0 |
| #define QIB_7322_SendCheckControl_0_PacketTooSmall_En_MSB 0x0 |
| #define QIB_7322_SendCheckControl_0_PacketTooSmall_En_RMASK 0x1 |
| |
| #define QIB_7322_SendIBSLIDMask_0_OFFS 0x14B0 |
| #define QIB_7322_SendIBSLIDMask_0_DEF 0x0000000000000000 |
| #define QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_LSB 0x0 |
| #define QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_MSB 0xF |
| #define QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK 0xFFFF |
| |
| #define QIB_7322_SendIBSLIDAssign_0_OFFS 0x14B8 |
| #define QIB_7322_SendIBSLIDAssign_0_DEF 0x0000000000000000 |
| #define QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_LSB 0x0 |
| #define QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_MSB 0xF |
| #define QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK 0xFFFF |
| |
| #define QIB_7322_IBCStatusA_0_OFFS 0x1540 |
| #define QIB_7322_IBCStatusA_0_DEF 0x0000000000000X02 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL7_LSB 0x27 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL7_MSB 0x27 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL7_RMASK 0x1 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL6_LSB 0x26 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL6_MSB 0x26 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL6_RMASK 0x1 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL5_LSB 0x25 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL5_MSB 0x25 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL5_RMASK 0x1 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL4_LSB 0x24 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL4_MSB 0x24 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL4_RMASK 0x1 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL3_LSB 0x23 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL3_MSB 0x23 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL3_RMASK 0x1 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL2_LSB 0x22 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL2_MSB 0x22 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL2_RMASK 0x1 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL1_LSB 0x21 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL1_MSB 0x21 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL1_RMASK 0x1 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL0_LSB 0x20 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL0_MSB 0x20 |
| #define QIB_7322_IBCStatusA_0_TxCreditOk_VL0_RMASK 0x1 |
| #define QIB_7322_IBCStatusA_0_TxReady_LSB 0x1E |
| #define QIB_7322_IBCStatusA_0_TxReady_MSB 0x1E |
| #define QIB_7322_IBCStatusA_0_TxReady_RMASK 0x1 |
| #define QIB_7322_IBCStatusA_0_LinkSpeedQDR_LSB 0x1D |
| #define QIB_7322_IBCStatusA_0_LinkSpeedQDR_MSB 0x1D |
| #define QIB_7322_IBCStatusA_0_LinkSpeedQDR_RMASK 0x1 |
| #define QIB_7322_IBCStatusA_0_ScrambleCapRemote_LSB 0xF |
| #define QIB_7322_IBCStatusA_0_ScrambleCapRemote_MSB 0xF |
| #define QIB_7322_IBCStatusA_0_ScrambleCapRemote_RMASK 0x1 |
| #define QIB_7322_IBCStatusA_0_ScrambleEn_LSB 0xE |
| #define QIB_7322_IBCStatusA_0_ScrambleEn_MSB 0xE |
| #define QIB_7322_IBCStatusA_0_ScrambleEn_RMASK 0x1 |
| #define QIB_7322_IBCStatusA_0_IBTxLaneReversed_LSB 0xD |
| #define QIB_7322_IBCStatusA_0_IBTxLaneReversed_MSB 0xD |
| #define QIB_7322_IBCStatusA_0_IBTxLaneReversed_RMASK 0x1 |
| #define QIB_7322_IBCStatusA_0_IBRxLaneReversed_LSB 0xC |
| #define QIB_7322_IBCStatusA_0_IBRxLaneReversed_MSB 0xC |
| #define QIB_7322_IBCStatusA_0_IBRxLaneReversed_RMASK 0x1 |
| #define QIB_7322_IBCStatusA_0_DDS_RXEQ_FAIL_LSB 0xA |
| #define QIB_7322_IBCStatusA_0_DDS_RXEQ_FAIL_MSB 0xA |
| #define QIB_7322_IBCStatusA_0_DDS_RXEQ_FAIL_RMASK 0x1 |
| #define QIB_7322_IBCStatusA_0_LinkWidthActive_LSB 0x9 |
| #define QIB_7322_IBCStatusA_0_LinkWidthActive_MSB 0x9 |
| #define QIB_7322_IBCStatusA_0_LinkWidthActive_RMASK 0x1 |
| #define QIB_7322_IBCStatusA_0_LinkSpeedActive_LSB 0x8 |
| #define QIB_7322_IBCStatusA_0_LinkSpeedActive_MSB 0x8 |
| #define QIB_7322_IBCStatusA_0_LinkSpeedActive_RMASK 0x1 |
| #define QIB_7322_IBCStatusA_0_LinkState_LSB 0x5 |
| #define QIB_7322_IBCStatusA_0_LinkState_MSB 0x7 |
| #define QIB_7322_IBCStatusA_0_LinkState_RMASK 0x7 |
| #define QIB_7322_IBCStatusA_0_LinkTrainingState_LSB 0x0 |
| #define QIB_7322_IBCStatusA_0_LinkTrainingState_MSB 0x4 |
| #define QIB_7322_IBCStatusA_0_LinkTrainingState_RMASK 0x1F |
| |
| #define QIB_7322_IBCStatusB_0_OFFS 0x1548 |
| #define QIB_7322_IBCStatusB_0_DEF 0x00000000XXXXXXXX |
| #define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_debug_LSB 0x27 |
| #define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_debug_MSB 0x27 |
| #define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_debug_RMASK 0x1 |
| #define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_reached_threshold_LSB 0x26 |
| #define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_reached_threshold_MSB 0x26 |
| #define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_reached_threshold_RMASK 0x1 |
| #define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_started_LSB 0x25 |
| #define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_started_MSB 0x25 |
| #define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_started_RMASK 0x1 |
| #define QIB_7322_IBCStatusB_0_heartbeat_timed_out_LSB 0x24 |
| #define QIB_7322_IBCStatusB_0_heartbeat_timed_out_MSB 0x24 |
| #define QIB_7322_IBCStatusB_0_heartbeat_timed_out_RMASK 0x1 |
| #define QIB_7322_IBCStatusB_0_heartbeat_crosstalk_LSB 0x20 |
| #define QIB_7322_IBCStatusB_0_heartbeat_crosstalk_MSB 0x23 |
| #define QIB_7322_IBCStatusB_0_heartbeat_crosstalk_RMASK 0xF |
| #define QIB_7322_IBCStatusB_0_RxEqLocalDevice_LSB 0x1E |
| #define QIB_7322_IBCStatusB_0_RxEqLocalDevice_MSB 0x1F |
| #define QIB_7322_IBCStatusB_0_RxEqLocalDevice_RMASK 0x3 |
| #define QIB_7322_IBCStatusB_0_ReqDDSLocalFromRmt_LSB 0x1A |
| #define QIB_7322_IBCStatusB_0_ReqDDSLocalFromRmt_MSB 0x1D |
| #define QIB_7322_IBCStatusB_0_ReqDDSLocalFromRmt_RMASK 0xF |
| #define QIB_7322_IBCStatusB_0_LinkRoundTripLatency_LSB 0x0 |
| #define QIB_7322_IBCStatusB_0_LinkRoundTripLatency_MSB 0x19 |
| #define QIB_7322_IBCStatusB_0_LinkRoundTripLatency_RMASK 0x3FFFFFF |
| |
| #define QIB_7322_IBCCtrlA_0_OFFS 0x1560 |
| #define QIB_7322_IBCCtrlA_0_DEF 0x0000000000000000 |
| #define QIB_7322_IBCCtrlA_0_Loopback_LSB 0x3F |
| #define QIB_7322_IBCCtrlA_0_Loopback_MSB 0x3F |
| #define QIB_7322_IBCCtrlA_0_Loopback_RMASK 0x1 |
| #define QIB_7322_IBCCtrlA_0_LinkDownDefaultState_LSB 0x3E |
| #define QIB_7322_IBCCtrlA_0_LinkDownDefaultState_MSB 0x3E |
| #define QIB_7322_IBCCtrlA_0_LinkDownDefaultState_RMASK 0x1 |
| #define QIB_7322_IBCCtrlA_0_IBLinkEn_LSB 0x3D |
| #define QIB_7322_IBCCtrlA_0_IBLinkEn_MSB 0x3D |
| #define QIB_7322_IBCCtrlA_0_IBLinkEn_RMASK 0x1 |
| #define QIB_7322_IBCCtrlA_0_IBStatIntReductionEn_LSB 0x3C |
| #define QIB_7322_IBCCtrlA_0_IBStatIntReductionEn_MSB 0x3C |
| #define QIB_7322_IBCCtrlA_0_IBStatIntReductionEn_RMASK 0x1 |
| #define QIB_7322_IBCCtrlA_0_NumVLane_LSB 0x30 |
| #define QIB_7322_IBCCtrlA_0_NumVLane_MSB 0x32 |
| #define QIB_7322_IBCCtrlA_0_NumVLane_RMASK 0x7 |
| #define QIB_7322_IBCCtrlA_0_OverrunThreshold_LSB 0x24 |
| #define QIB_7322_IBCCtrlA_0_OverrunThreshold_MSB 0x27 |
| #define QIB_7322_IBCCtrlA_0_OverrunThreshold_RMASK 0xF |
| #define QIB_7322_IBCCtrlA_0_PhyerrThreshold_LSB 0x20 |
| #define QIB_7322_IBCCtrlA_0_PhyerrThreshold_MSB 0x23 |
| #define QIB_7322_IBCCtrlA_0_PhyerrThreshold_RMASK 0xF |
| #define QIB_7322_IBCCtrlA_0_MaxPktLen_LSB 0x15 |
| #define QIB_7322_IBCCtrlA_0_MaxPktLen_MSB 0x1F |
| #define QIB_7322_IBCCtrlA_0_MaxPktLen_RMASK 0x7FF |
| #define QIB_7322_IBCCtrlA_0_LinkCmd_LSB 0x13 |
| #define QIB_7322_IBCCtrlA_0_LinkCmd_MSB 0x14 |
| #define QIB_7322_IBCCtrlA_0_LinkCmd_RMASK 0x3 |
| #define QIB_7322_IBCCtrlA_0_LinkInitCmd_LSB 0x10 |
| #define QIB_7322_IBCCtrlA_0_LinkInitCmd_MSB 0x12 |
| #define QIB_7322_IBCCtrlA_0_LinkInitCmd_RMASK 0x7 |
| #define QIB_7322_IBCCtrlA_0_FlowCtrlWaterMark_LSB 0x8 |
| #define QIB_7322_IBCCtrlA_0_FlowCtrlWaterMark_MSB 0xF |
| #define QIB_7322_IBCCtrlA_0_FlowCtrlWaterMark_RMASK 0xFF |
| #define QIB_7322_IBCCtrlA_0_FlowCtrlPeriod_LSB 0x0 |
| #define QIB_7322_IBCCtrlA_0_FlowCtrlPeriod_MSB 0x7 |
| #define QIB_7322_IBCCtrlA_0_FlowCtrlPeriod_RMASK 0xFF |
| |
| #define QIB_7322_IBCCtrlB_0_OFFS 0x1568 |
| #define QIB_7322_IBCCtrlB_0_DEF 0x00000000000305FF |
| #define QIB_7322_IBCCtrlB_0_IB_DLID_MASK_LSB 0x30 |
| #define QIB_7322_IBCCtrlB_0_IB_DLID_MASK_MSB 0x3F |
| #define QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK 0xFFFF |
| #define QIB_7322_IBCCtrlB_0_IB_DLID_LSB 0x20 |
| #define QIB_7322_IBCCtrlB_0_IB_DLID_MSB 0x2F |
| #define QIB_7322_IBCCtrlB_0_IB_DLID_RMASK 0xFFFF |
| #define QIB_7322_IBCCtrlB_0_IB_ENABLE_FILT_DPKT_LSB 0x1B |
| #define QIB_7322_IBCCtrlB_0_IB_ENABLE_FILT_DPKT_MSB 0x1B |
| #define QIB_7322_IBCCtrlB_0_IB_ENABLE_FILT_DPKT_RMASK 0x1 |
| #define QIB_7322_IBCCtrlB_0_HRTBT_REQ_LSB 0x1A |
| #define QIB_7322_IBCCtrlB_0_HRTBT_REQ_MSB 0x1A |
| #define QIB_7322_IBCCtrlB_0_HRTBT_REQ_RMASK 0x1 |
| #define QIB_7322_IBCCtrlB_0_HRTBT_PORT_LSB 0x12 |
| #define QIB_7322_IBCCtrlB_0_HRTBT_PORT_MSB 0x19 |
| #define QIB_7322_IBCCtrlB_0_HRTBT_PORT_RMASK 0xFF |
| #define QIB_7322_IBCCtrlB_0_HRTBT_AUTO_LSB 0x11 |
| #define QIB_7322_IBCCtrlB_0_HRTBT_AUTO_MSB 0x11 |
| #define QIB_7322_IBCCtrlB_0_HRTBT_AUTO_RMASK 0x1 |
| #define QIB_7322_IBCCtrlB_0_HRTBT_ENB_LSB 0x10 |
| #define QIB_7322_IBCCtrlB_0_HRTBT_ENB_MSB 0x10 |
| #define QIB_7322_IBCCtrlB_0_HRTBT_ENB_RMASK 0x1 |
| #define QIB_7322_IBCCtrlB_0_SD_DDS_LSB 0xC |
| #define QIB_7322_IBCCtrlB_0_SD_DDS_MSB 0xF |
| #define QIB_7322_IBCCtrlB_0_SD_DDS_RMASK 0xF |
| #define QIB_7322_IBCCtrlB_0_SD_DDSV_LSB 0xB |
| #define QIB_7322_IBCCtrlB_0_SD_DDSV_MSB 0xB |
| #define QIB_7322_IBCCtrlB_0_SD_DDSV_RMASK 0x1 |
| #define QIB_7322_IBCCtrlB_0_SD_ADD_ENB_LSB 0xA |
| #define QIB_7322_IBCCtrlB_0_SD_ADD_ENB_MSB 0xA |
| #define QIB_7322_IBCCtrlB_0_SD_ADD_ENB_RMASK 0x1 |
| #define QIB_7322_IBCCtrlB_0_SD_RX_EQUAL_ENABLE_LSB 0x9 |
| #define QIB_7322_IBCCtrlB_0_SD_RX_EQUAL_ENABLE_MSB 0x9 |
| #define QIB_7322_IBCCtrlB_0_SD_RX_EQUAL_ENABLE_RMASK 0x1 |
| #define QIB_7322_IBCCtrlB_0_IB_LANE_REV_SUPPORTED_LSB 0x8 |
| #define QIB_7322_IBCCtrlB_0_IB_LANE_REV_SUPPORTED_MSB 0x8 |
| #define QIB_7322_IBCCtrlB_0_IB_LANE_REV_SUPPORTED_RMASK 0x1 |
| #define QIB_7322_IBCCtrlB_0_IB_POLARITY_REV_SUPP_LSB 0x7 |
| #define QIB_7322_IBCCtrlB_0_IB_POLARITY_REV_SUPP_MSB 0x7 |
| #define QIB_7322_IBCCtrlB_0_IB_POLARITY_REV_SUPP_RMASK 0x1 |
| #define QIB_7322_IBCCtrlB_0_IB_NUM_CHANNELS_LSB 0x5 |
| #define QIB_7322_IBCCtrlB_0_IB_NUM_CHANNELS_MSB 0x6 |
| #define QIB_7322_IBCCtrlB_0_IB_NUM_CHANNELS_RMASK 0x3 |
| #define QIB_7322_IBCCtrlB_0_SD_SPEED_QDR_LSB 0x4 |
| #define QIB_7322_IBCCtrlB_0_SD_SPEED_QDR_MSB 0x4 |
| #define QIB_7322_IBCCtrlB_0_SD_SPEED_QDR_RMASK 0x1 |
| #define QIB_7322_IBCCtrlB_0_SD_SPEED_DDR_LSB 0x3 |
| #define QIB_7322_IBCCtrlB_0_SD_SPEED_DDR_MSB 0x3 |
| #define QIB_7322_IBCCtrlB_0_SD_SPEED_DDR_RMASK 0x1 |
| #define QIB_7322_IBCCtrlB_0_SD_SPEED_SDR_LSB 0x2 |
| #define QIB_7322_IBCCtrlB_0_SD_SPEED_SDR_MSB 0x2 |
| #define QIB_7322_IBCCtrlB_0_SD_SPEED_SDR_RMASK 0x1 |
| #define QIB_7322_IBCCtrlB_0_SD_SPEED_LSB 0x1 |
| #define QIB_7322_IBCCtrlB_0_SD_SPEED_MSB 0x1 |
| #define QIB_7322_IBCCtrlB_0_SD_SPEED_RMASK 0x1 |
| #define QIB_7322_IBCCtrlB_0_IB_ENHANCED_MODE_LSB 0x0 |
| #define QIB_7322_IBCCtrlB_0_IB_ENHANCED_MODE_MSB 0x0 |
| #define QIB_7322_IBCCtrlB_0_IB_ENHANCED_MODE_RMASK 0x1 |
| |
| #define QIB_7322_IBCCtrlC_0_OFFS 0x1570 |
| #define QIB_7322_IBCCtrlC_0_DEF 0x0000000000000301 |
| #define QIB_7322_IBCCtrlC_0_IB_BACK_PORCH_LSB 0x5 |
| #define QIB_7322_IBCCtrlC_0_IB_BACK_PORCH_MSB 0x9 |
| #define QIB_7322_IBCCtrlC_0_IB_BACK_PORCH_RMASK 0x1F |
| #define QIB_7322_IBCCtrlC_0_IB_FRONT_PORCH_LSB 0x0 |
| #define QIB_7322_IBCCtrlC_0_IB_FRONT_PORCH_MSB 0x4 |
| #define QIB_7322_IBCCtrlC_0_IB_FRONT_PORCH_RMASK 0x1F |
| |
| #define QIB_7322_HRTBT_GUID_0_OFFS 0x1588 |
| #define QIB_7322_HRTBT_GUID_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_IB_SDTEST_IF_TX_0_OFFS 0x1590 |
| #define QIB_7322_IB_SDTEST_IF_TX_0_DEF 0x0000000000000000 |
| #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_RX_CFG_LSB 0x30 |
| #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_RX_CFG_MSB 0x3F |
| #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_RX_CFG_RMASK 0xFFFF |
| #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_TX_CFG_LSB 0x20 |
| #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_TX_CFG_MSB 0x2F |
| #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_TX_CFG_RMASK 0xFFFF |
| #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_SPEED_LSB 0xD |
| #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_SPEED_MSB 0xF |
| #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_SPEED_RMASK 0x7 |
| #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_OPCODE_LSB 0xB |
| #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_OPCODE_MSB 0xC |
| #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_OPCODE_RMASK 0x3 |
| #define QIB_7322_IB_SDTEST_IF_TX_0_CREDIT_CHANGE_LSB 0x4 |
| #define QIB_7322_IB_SDTEST_IF_TX_0_CREDIT_CHANGE_MSB 0x4 |
| #define QIB_7322_IB_SDTEST_IF_TX_0_CREDIT_CHANGE_RMASK 0x1 |
| #define QIB_7322_IB_SDTEST_IF_TX_0_VL_CAP_LSB 0x2 |
| #define QIB_7322_IB_SDTEST_IF_TX_0_VL_CAP_MSB 0x3 |
| #define QIB_7322_IB_SDTEST_IF_TX_0_VL_CAP_RMASK 0x3 |
| #define QIB_7322_IB_SDTEST_IF_TX_0_TS_3_TX_VALID_LSB 0x1 |
| #define QIB_7322_IB_SDTEST_IF_TX_0_TS_3_TX_VALID_MSB 0x1 |
| #define QIB_7322_IB_SDTEST_IF_TX_0_TS_3_TX_VALID_RMASK 0x1 |
| #define QIB_7322_IB_SDTEST_IF_TX_0_TS_T_TX_VALID_LSB 0x0 |
| #define QIB_7322_IB_SDTEST_IF_TX_0_TS_T_TX_VALID_MSB 0x0 |
| #define QIB_7322_IB_SDTEST_IF_TX_0_TS_T_TX_VALID_RMASK 0x1 |
| |
| #define QIB_7322_IB_SDTEST_IF_RX_0_OFFS 0x1598 |
| #define QIB_7322_IB_SDTEST_IF_RX_0_DEF 0x0000000000000000 |
| #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_RX_CFG_LSB 0x30 |
| #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_RX_CFG_MSB 0x3F |
| #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_RX_CFG_RMASK 0xFFFF |
| #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_TX_CFG_LSB 0x20 |
| #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_TX_CFG_MSB 0x2F |
| #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_TX_CFG_RMASK 0xFFFF |
| #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_B_LSB 0x18 |
| #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_B_MSB 0x1F |
| #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_B_RMASK 0xFF |
| #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_A_LSB 0x10 |
| #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_A_MSB 0x17 |
| #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_A_RMASK 0xFF |
| #define QIB_7322_IB_SDTEST_IF_RX_0_TS_3_RX_VALID_LSB 0x1 |
| #define QIB_7322_IB_SDTEST_IF_RX_0_TS_3_RX_VALID_MSB 0x1 |
| #define QIB_7322_IB_SDTEST_IF_RX_0_TS_3_RX_VALID_RMASK 0x1 |
| #define QIB_7322_IB_SDTEST_IF_RX_0_TS_T_RX_VALID_LSB 0x0 |
| #define QIB_7322_IB_SDTEST_IF_RX_0_TS_T_RX_VALID_MSB 0x0 |
| #define QIB_7322_IB_SDTEST_IF_RX_0_TS_T_RX_VALID_RMASK 0x1 |
| |
| #define QIB_7322_IBNCModeCtrl_0_OFFS 0x15B8 |
| #define QIB_7322_IBNCModeCtrl_0_DEF 0x0000000000000000 |
| #define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteForce_LSB 0x22 |
| #define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteForce_MSB 0x22 |
| #define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteForce_RMASK 0x1 |
| #define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteMask_LSB 0x21 |
| #define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteMask_MSB 0x21 |
| #define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteMask_RMASK 0x1 |
| #define QIB_7322_IBNCModeCtrl_0_ScrambleCapLocal_LSB 0x20 |
| #define QIB_7322_IBNCModeCtrl_0_ScrambleCapLocal_MSB 0x20 |
| #define QIB_7322_IBNCModeCtrl_0_ScrambleCapLocal_RMASK 0x1 |
| #define QIB_7322_IBNCModeCtrl_0_TSMCode_TS2_LSB 0x11 |
| #define QIB_7322_IBNCModeCtrl_0_TSMCode_TS2_MSB 0x19 |
| #define QIB_7322_IBNCModeCtrl_0_TSMCode_TS2_RMASK 0x1FF |
| #define QIB_7322_IBNCModeCtrl_0_TSMCode_TS1_LSB 0x8 |
| #define QIB_7322_IBNCModeCtrl_0_TSMCode_TS1_MSB 0x10 |
| #define QIB_7322_IBNCModeCtrl_0_TSMCode_TS1_RMASK 0x1FF |
| #define QIB_7322_IBNCModeCtrl_0_TSMEnable_ignore_TSM_on_rx_LSB 0x2 |
| #define QIB_7322_IBNCModeCtrl_0_TSMEnable_ignore_TSM_on_rx_MSB 0x2 |
| #define QIB_7322_IBNCModeCtrl_0_TSMEnable_ignore_TSM_on_rx_RMASK 0x1 |
| #define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS2_LSB 0x1 |
| #define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS2_MSB 0x1 |
| #define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS2_RMASK 0x1 |
| #define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS1_LSB 0x0 |
| #define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS1_MSB 0x0 |
| #define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS1_RMASK 0x1 |
| |
| #define QIB_7322_IBSerdesStatus_0_OFFS 0x15D0 |
| #define QIB_7322_IBSerdesStatus_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_IBPCSConfig_0_OFFS 0x15D8 |
| #define QIB_7322_IBPCSConfig_0_DEF 0x0000000000000007 |
| #define QIB_7322_IBPCSConfig_0_link_sync_mask_LSB 0x9 |
| #define QIB_7322_IBPCSConfig_0_link_sync_mask_MSB 0x12 |
| #define QIB_7322_IBPCSConfig_0_link_sync_mask_RMASK 0x3FF |
| #define QIB_7322_IBPCSConfig_0_xcv_rreset_LSB 0x2 |
| #define QIB_7322_IBPCSConfig_0_xcv_rreset_MSB 0x2 |
| #define QIB_7322_IBPCSConfig_0_xcv_rreset_RMASK 0x1 |
| #define QIB_7322_IBPCSConfig_0_xcv_treset_LSB 0x1 |
| #define QIB_7322_IBPCSConfig_0_xcv_treset_MSB 0x1 |
| #define QIB_7322_IBPCSConfig_0_xcv_treset_RMASK 0x1 |
| #define QIB_7322_IBPCSConfig_0_tx_rx_reset_LSB 0x0 |
| #define QIB_7322_IBPCSConfig_0_tx_rx_reset_MSB 0x0 |
| #define QIB_7322_IBPCSConfig_0_tx_rx_reset_RMASK 0x1 |
| |
| #define QIB_7322_IBSerdesCtrl_0_OFFS 0x15E0 |
| #define QIB_7322_IBSerdesCtrl_0_DEF 0x0000000000FFA00F |
| #define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_QDR_LSB 0x1A |
| #define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_QDR_MSB 0x1A |
| #define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_QDR_RMASK 0x1 |
| #define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_DDR_LSB 0x19 |
| #define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_DDR_MSB 0x19 |
| #define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_DDR_RMASK 0x1 |
| #define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_SDR_LSB 0x18 |
| #define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_SDR_MSB 0x18 |
| #define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_SDR_RMASK 0x1 |
| #define QIB_7322_IBSerdesCtrl_0_CHANNEL_RESET_N_LSB 0x14 |
| #define QIB_7322_IBSerdesCtrl_0_CHANNEL_RESET_N_MSB 0x17 |
| #define QIB_7322_IBSerdesCtrl_0_CHANNEL_RESET_N_RMASK 0xF |
| #define QIB_7322_IBSerdesCtrl_0_CGMODE_LSB 0x10 |
| #define QIB_7322_IBSerdesCtrl_0_CGMODE_MSB 0x13 |
| #define QIB_7322_IBSerdesCtrl_0_CGMODE_RMASK 0xF |
| #define QIB_7322_IBSerdesCtrl_0_IB_LAT_MODE_LSB 0xF |
| #define QIB_7322_IBSerdesCtrl_0_IB_LAT_MODE_MSB 0xF |
| #define QIB_7322_IBSerdesCtrl_0_IB_LAT_MODE_RMASK 0x1 |
| #define QIB_7322_IBSerdesCtrl_0_RXLOSEN_LSB 0xD |
| #define QIB_7322_IBSerdesCtrl_0_RXLOSEN_MSB 0xD |
| #define QIB_7322_IBSerdesCtrl_0_RXLOSEN_RMASK 0x1 |
| #define QIB_7322_IBSerdesCtrl_0_LPEN_LSB 0xC |
| #define QIB_7322_IBSerdesCtrl_0_LPEN_MSB 0xC |
| #define QIB_7322_IBSerdesCtrl_0_LPEN_RMASK 0x1 |
| #define QIB_7322_IBSerdesCtrl_0_PLLPD_LSB 0xB |
| #define QIB_7322_IBSerdesCtrl_0_PLLPD_MSB 0xB |
| #define QIB_7322_IBSerdesCtrl_0_PLLPD_RMASK 0x1 |
| #define QIB_7322_IBSerdesCtrl_0_TXPD_LSB 0xA |
| #define QIB_7322_IBSerdesCtrl_0_TXPD_MSB 0xA |
| #define QIB_7322_IBSerdesCtrl_0_TXPD_RMASK 0x1 |
| #define QIB_7322_IBSerdesCtrl_0_RXPD_LSB 0x9 |
| #define QIB_7322_IBSerdesCtrl_0_RXPD_MSB 0x9 |
| #define QIB_7322_IBSerdesCtrl_0_RXPD_RMASK 0x1 |
| #define QIB_7322_IBSerdesCtrl_0_TXIDLE_LSB 0x8 |
| #define QIB_7322_IBSerdesCtrl_0_TXIDLE_MSB 0x8 |
| #define QIB_7322_IBSerdesCtrl_0_TXIDLE_RMASK 0x1 |
| #define QIB_7322_IBSerdesCtrl_0_CMODE_LSB 0x0 |
| #define QIB_7322_IBSerdesCtrl_0_CMODE_MSB 0x6 |
| #define QIB_7322_IBSerdesCtrl_0_CMODE_RMASK 0x7F |
| |
| #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_OFFS 0x1600 |
| #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_DEF 0x0000000000000000 |
| #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_tx_override_deemphasis_select_LSB 0x1F |
| #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_tx_override_deemphasis_select_MSB 0x1F |
| #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_tx_override_deemphasis_select_RMASK 0x1 |
| #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_reset_tx_deemphasis_override_LSB 0x1E |
| #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_reset_tx_deemphasis_override_MSB 0x1E |
| #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_reset_tx_deemphasis_override_RMASK 0x1 |
| #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txampcntl_d2a_LSB 0xE |
| #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txampcntl_d2a_MSB 0x11 |
| #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txampcntl_d2a_RMASK 0xF |
| #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txc0_ena_LSB 0x9 |
| #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txc0_ena_MSB 0xD |
| #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txc0_ena_RMASK 0x1F |
| #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcp1_ena_LSB 0x5 |
| #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcp1_ena_MSB 0x8 |
| #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcp1_ena_RMASK 0xF |
| #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_xtra_emph0_LSB 0x3 |
| #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_xtra_emph0_MSB 0x4 |
| #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_xtra_emph0_RMASK 0x3 |
| #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_ena_LSB 0x0 |
| #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_ena_MSB 0x2 |
| #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_ena_RMASK 0x7 |
| |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_OFFS 0x1640 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_DEF 0x0000000000000000 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch3_LSB 0x27 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch3_MSB 0x27 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch3_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch2_LSB 0x26 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch2_MSB 0x26 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch2_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch1_LSB 0x25 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch1_MSB 0x25 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch1_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch0_LSB 0x24 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch0_MSB 0x24 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch0_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch3_LSB 0x23 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch3_MSB 0x23 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch3_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch2_LSB 0x22 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch2_MSB 0x22 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch2_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch1_LSB 0x21 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch1_MSB 0x21 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch1_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch0_LSB 0x20 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch0_MSB 0x20 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch0_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch3_LSB 0x18 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch3_MSB 0x1F |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch3_RMASK 0xFF |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch2_LSB 0x10 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch2_MSB 0x17 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch2_RMASK 0xFF |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch1_LSB 0x8 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch1_MSB 0xF |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch1_RMASK 0xFF |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch0_LSB 0x0 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch0_MSB 0x7 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch0_RMASK 0xFF |
| |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_OFFS 0x1648 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_DEF 0x0000000000000000 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch3_LSB 0x27 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch3_MSB 0x27 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch3_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch2_LSB 0x26 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch2_MSB 0x26 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch2_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch1_LSB 0x25 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch1_MSB 0x25 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch1_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch0_LSB 0x24 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch0_MSB 0x24 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch0_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch3_LSB 0x23 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch3_MSB 0x23 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch3_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch2_LSB 0x22 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch2_MSB 0x22 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch2_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch1_LSB 0x21 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch1_MSB 0x21 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch1_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch0_LSB 0x20 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch0_MSB 0x20 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch0_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch3_LSB 0x18 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch3_MSB 0x1F |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch3_RMASK 0xFF |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch2_LSB 0x10 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch2_MSB 0x17 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch2_RMASK 0xFF |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch1_LSB 0x8 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch1_MSB 0xF |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch1_RMASK 0xFF |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch0_LSB 0x0 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch0_MSB 0x7 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch0_RMASK 0xFF |
| |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_OFFS 0x1650 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_DEF 0x0000000000000000 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch3_LSB 0x27 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch3_MSB 0x27 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch3_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch2_LSB 0x26 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch2_MSB 0x26 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch2_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch1_LSB 0x25 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch1_MSB 0x25 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch1_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch0_LSB 0x24 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch0_MSB 0x24 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch0_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch3_LSB 0x23 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch3_MSB 0x23 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch3_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch2_LSB 0x22 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch2_MSB 0x22 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch2_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch1_LSB 0x21 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch1_MSB 0x21 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch1_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch0_LSB 0x20 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch0_MSB 0x20 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch0_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch3_LSB 0x18 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch3_MSB 0x1F |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch3_RMASK 0xFF |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch2_LSB 0x10 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch2_MSB 0x17 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch2_RMASK 0xFF |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch1_LSB 0x8 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch1_MSB 0xF |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch1_RMASK 0xFF |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch0_LSB 0x0 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch0_MSB 0x7 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch0_RMASK 0xFF |
| |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_OFFS 0x1658 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_DEF 0x0000000000000000 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch3_LSB 0x27 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch3_MSB 0x27 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch3_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch2_LSB 0x26 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch2_MSB 0x26 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch2_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch1_LSB 0x25 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch1_MSB 0x25 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch1_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch0_LSB 0x24 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch0_MSB 0x24 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch0_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch3_LSB 0x23 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch3_MSB 0x23 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch3_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch2_LSB 0x22 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch2_MSB 0x22 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch2_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch1_LSB 0x21 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch1_MSB 0x21 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch1_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch0_LSB 0x20 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch0_MSB 0x20 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch0_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch3_LSB 0x18 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch3_MSB 0x1F |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch3_RMASK 0xFF |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch2_LSB 0x10 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch2_MSB 0x17 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch2_RMASK 0xFF |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch1_LSB 0x8 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch1_MSB 0xF |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch1_RMASK 0xFF |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch0_LSB 0x0 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch0_MSB 0x7 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch0_RMASK 0xFF |
| |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_OFFS 0x1660 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_DEF 0x0000000000000000 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch3_LSB 0x27 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch3_MSB 0x27 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch3_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch2_LSB 0x26 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch2_MSB 0x26 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch2_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch1_LSB 0x25 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch1_MSB 0x25 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch1_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch0_LSB 0x24 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch0_MSB 0x24 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch0_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch3_LSB 0x23 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch3_MSB 0x23 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch3_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch2_LSB 0x22 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch2_MSB 0x22 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch2_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch1_LSB 0x21 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch1_MSB 0x21 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch1_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch0_LSB 0x20 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch0_MSB 0x20 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch0_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch3_LSB 0x18 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch3_MSB 0x1F |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch3_RMASK 0xFF |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch2_LSB 0x10 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch2_MSB 0x17 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch2_RMASK 0xFF |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch1_LSB 0x8 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch1_MSB 0xF |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch1_RMASK 0xFF |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch0_LSB 0x0 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch0_MSB 0x7 |
| #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch0_RMASK 0xFF |
| |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_OFFS 0x1668 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_DEF 0x0000000000000000 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch3_LSB 0x27 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch3_MSB 0x27 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch3_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch2_LSB 0x26 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch2_MSB 0x26 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch2_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch1_LSB 0x25 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch1_MSB 0x25 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch1_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch0_LSB 0x24 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch0_MSB 0x24 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch0_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch3_LSB 0x23 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch3_MSB 0x23 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch3_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch2_LSB 0x22 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch2_MSB 0x22 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch2_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch1_LSB 0x21 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch1_MSB 0x21 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch1_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch0_LSB 0x20 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch0_MSB 0x20 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch0_RMASK 0x1 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch3_LSB 0x18 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch3_MSB 0x1F |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch3_RMASK 0xFF |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch2_LSB 0x10 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch2_MSB 0x17 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch2_RMASK 0xFF |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch1_LSB 0x8 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch1_MSB 0xF |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch1_RMASK 0xFF |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch0_LSB 0x0 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch0_MSB 0x7 |
| #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch0_RMASK 0xFF |
| |
| #define QIB_7322_ADAPT_DISABLE_TIMER_THRESHOLD_0_OFFS 0x1670 |
| #define QIB_7322_ADAPT_DISABLE_TIMER_THRESHOLD_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_HighPriorityLimit_0_OFFS 0x1BC0 |
| #define QIB_7322_HighPriorityLimit_0_DEF 0x0000000000000000 |
| #define QIB_7322_HighPriorityLimit_0_Limit_LSB 0x0 |
| #define QIB_7322_HighPriorityLimit_0_Limit_MSB 0x7 |
| #define QIB_7322_HighPriorityLimit_0_Limit_RMASK 0xFF |
| |
| #define QIB_7322_LowPriority0_0_OFFS 0x1C00 |
| #define QIB_7322_LowPriority0_0_DEF 0x0000000000000000 |
| #define QIB_7322_LowPriority0_0_VirtualLane_LSB 0x10 |
| #define QIB_7322_LowPriority0_0_VirtualLane_MSB 0x12 |
| #define QIB_7322_LowPriority0_0_VirtualLane_RMASK 0x7 |
| #define QIB_7322_LowPriority0_0_Weight_LSB 0x0 |
| #define QIB_7322_LowPriority0_0_Weight_MSB 0x7 |
| #define QIB_7322_LowPriority0_0_Weight_RMASK 0xFF |
| |
| #define QIB_7322_HighPriority0_0_OFFS 0x1E00 |
| #define QIB_7322_HighPriority0_0_DEF 0x0000000000000000 |
| #define QIB_7322_HighPriority0_0_VirtualLane_LSB 0x10 |
| #define QIB_7322_HighPriority0_0_VirtualLane_MSB 0x12 |
| #define QIB_7322_HighPriority0_0_VirtualLane_RMASK 0x7 |
| #define QIB_7322_HighPriority0_0_Weight_LSB 0x0 |
| #define QIB_7322_HighPriority0_0_Weight_MSB 0x7 |
| #define QIB_7322_HighPriority0_0_Weight_RMASK 0xFF |
| |
| #define QIB_7322_CntrRegBase_1_OFFS 0x2028 |
| #define QIB_7322_CntrRegBase_1_DEF 0x0000000000013000 |
| |
| #define QIB_7322_RcvQPMulticastContext_1_OFFS 0x2170 |
| |
| #define QIB_7322_SendCtrl_1_OFFS 0x21C0 |
| |
| #define QIB_7322_SendBufAvail0_OFFS 0x3000 |
| #define QIB_7322_SendBufAvail0_DEF 0x0000000000000000 |
| #define QIB_7322_SendBufAvail0_SendBuf_31_0_LSB 0x0 |
| #define QIB_7322_SendBufAvail0_SendBuf_31_0_MSB 0x3F |
| #define QIB_7322_SendBufAvail0_SendBuf_31_0_RMASK 0x0 |
| |
| #define QIB_7322_MsixTable_OFFS 0x8000 |
| #define QIB_7322_MsixTable_DEF 0x0000000000000000 |
| |
| #define QIB_7322_MsixPba_OFFS 0x9000 |
| #define QIB_7322_MsixPba_DEF 0x0000000000000000 |
| |
| #define QIB_7322_LAMemory_OFFS 0xA000 |
| #define QIB_7322_LAMemory_DEF 0x0000000000000000 |
| |
| #define QIB_7322_LBIntCnt_OFFS 0x11000 |
| #define QIB_7322_LBIntCnt_DEF 0x0000000000000000 |
| |
| #define QIB_7322_LBFlowStallCnt_OFFS 0x11008 |
| #define QIB_7322_LBFlowStallCnt_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxTIDFullErrCnt_OFFS 0x110D0 |
| #define QIB_7322_RxTIDFullErrCnt_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxTIDValidErrCnt_OFFS 0x110D8 |
| #define QIB_7322_RxTIDValidErrCnt_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxP0HdrEgrOvflCnt_OFFS 0x110E8 |
| #define QIB_7322_RxP0HdrEgrOvflCnt_DEF 0x0000000000000000 |
| |
| #define QIB_7322_PcieRetryBufDiagQwordCnt_OFFS 0x111A0 |
| #define QIB_7322_PcieRetryBufDiagQwordCnt_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxTidFlowDropCnt_OFFS 0x111E0 |
| #define QIB_7322_RxTidFlowDropCnt_DEF 0x0000000000000000 |
| |
| #define QIB_7322_LBIntCnt_0_OFFS 0x12000 |
| #define QIB_7322_LBIntCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxCreditUpToDateTimeOut_0_OFFS 0x12008 |
| #define QIB_7322_TxCreditUpToDateTimeOut_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxSDmaDescCnt_0_OFFS 0x12010 |
| #define QIB_7322_TxSDmaDescCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxUnsupVLErrCnt_0_OFFS 0x12018 |
| #define QIB_7322_TxUnsupVLErrCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxDataPktCnt_0_OFFS 0x12020 |
| #define QIB_7322_TxDataPktCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxFlowPktCnt_0_OFFS 0x12028 |
| #define QIB_7322_TxFlowPktCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxDwordCnt_0_OFFS 0x12030 |
| #define QIB_7322_TxDwordCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxLenErrCnt_0_OFFS 0x12038 |
| #define QIB_7322_TxLenErrCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxMaxMinLenErrCnt_0_OFFS 0x12040 |
| #define QIB_7322_TxMaxMinLenErrCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxUnderrunCnt_0_OFFS 0x12048 |
| #define QIB_7322_TxUnderrunCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxFlowStallCnt_0_OFFS 0x12050 |
| #define QIB_7322_TxFlowStallCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxDroppedPktCnt_0_OFFS 0x12058 |
| #define QIB_7322_TxDroppedPktCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxDroppedPktCnt_0_OFFS 0x12060 |
| #define QIB_7322_RxDroppedPktCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxDataPktCnt_0_OFFS 0x12068 |
| #define QIB_7322_RxDataPktCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxFlowPktCnt_0_OFFS 0x12070 |
| #define QIB_7322_RxFlowPktCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxDwordCnt_0_OFFS 0x12078 |
| #define QIB_7322_RxDwordCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxLenErrCnt_0_OFFS 0x12080 |
| #define QIB_7322_RxLenErrCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxMaxMinLenErrCnt_0_OFFS 0x12088 |
| #define QIB_7322_RxMaxMinLenErrCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxICRCErrCnt_0_OFFS 0x12090 |
| #define QIB_7322_RxICRCErrCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxVCRCErrCnt_0_OFFS 0x12098 |
| #define QIB_7322_RxVCRCErrCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxFlowCtrlViolCnt_0_OFFS 0x120A0 |
| #define QIB_7322_RxFlowCtrlViolCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxVersionErrCnt_0_OFFS 0x120A8 |
| #define QIB_7322_RxVersionErrCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxLinkMalformCnt_0_OFFS 0x120B0 |
| #define QIB_7322_RxLinkMalformCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxEBPCnt_0_OFFS 0x120B8 |
| #define QIB_7322_RxEBPCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxLPCRCErrCnt_0_OFFS 0x120C0 |
| #define QIB_7322_RxLPCRCErrCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxBufOvflCnt_0_OFFS 0x120C8 |
| #define QIB_7322_RxBufOvflCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxLenTruncateCnt_0_OFFS 0x120D0 |
| #define QIB_7322_RxLenTruncateCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxPKeyMismatchCnt_0_OFFS 0x120E0 |
| #define QIB_7322_RxPKeyMismatchCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_IBLinkDownedCnt_0_OFFS 0x12180 |
| #define QIB_7322_IBLinkDownedCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_IBSymbolErrCnt_0_OFFS 0x12188 |
| #define QIB_7322_IBSymbolErrCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_IBStatusChangeCnt_0_OFFS 0x12190 |
| #define QIB_7322_IBStatusChangeCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_IBLinkErrRecoveryCnt_0_OFFS 0x12198 |
| #define QIB_7322_IBLinkErrRecoveryCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_ExcessBufferOvflCnt_0_OFFS 0x121A8 |
| #define QIB_7322_ExcessBufferOvflCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_LocalLinkIntegrityErrCnt_0_OFFS 0x121B0 |
| #define QIB_7322_LocalLinkIntegrityErrCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxVlErrCnt_0_OFFS 0x121B8 |
| #define QIB_7322_RxVlErrCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxDlidFltrCnt_0_OFFS 0x121C0 |
| #define QIB_7322_RxDlidFltrCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxVL15DroppedPktCnt_0_OFFS 0x121C8 |
| #define QIB_7322_RxVL15DroppedPktCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxOtherLocalPhyErrCnt_0_OFFS 0x121D0 |
| #define QIB_7322_RxOtherLocalPhyErrCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxQPInvalidContextCnt_0_OFFS 0x121D8 |
| #define QIB_7322_RxQPInvalidContextCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxHeadersErrCnt_0_OFFS 0x121F8 |
| #define QIB_7322_TxHeadersErrCnt_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_PSRcvDataCount_0_OFFS 0x12218 |
| #define QIB_7322_PSRcvDataCount_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_PSRcvPktsCount_0_OFFS 0x12220 |
| #define QIB_7322_PSRcvPktsCount_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_PSXmitDataCount_0_OFFS 0x12228 |
| #define QIB_7322_PSXmitDataCount_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_PSXmitPktsCount_0_OFFS 0x12230 |
| #define QIB_7322_PSXmitPktsCount_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_PSXmitWaitCount_0_OFFS 0x12238 |
| #define QIB_7322_PSXmitWaitCount_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_LBIntCnt_1_OFFS 0x13000 |
| #define QIB_7322_LBIntCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxCreditUpToDateTimeOut_1_OFFS 0x13008 |
| #define QIB_7322_TxCreditUpToDateTimeOut_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxSDmaDescCnt_1_OFFS 0x13010 |
| #define QIB_7322_TxSDmaDescCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxUnsupVLErrCnt_1_OFFS 0x13018 |
| #define QIB_7322_TxUnsupVLErrCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxDataPktCnt_1_OFFS 0x13020 |
| #define QIB_7322_TxDataPktCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxFlowPktCnt_1_OFFS 0x13028 |
| #define QIB_7322_TxFlowPktCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxDwordCnt_1_OFFS 0x13030 |
| #define QIB_7322_TxDwordCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxLenErrCnt_1_OFFS 0x13038 |
| #define QIB_7322_TxLenErrCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxMaxMinLenErrCnt_1_OFFS 0x13040 |
| #define QIB_7322_TxMaxMinLenErrCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxUnderrunCnt_1_OFFS 0x13048 |
| #define QIB_7322_TxUnderrunCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxFlowStallCnt_1_OFFS 0x13050 |
| #define QIB_7322_TxFlowStallCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxDroppedPktCnt_1_OFFS 0x13058 |
| #define QIB_7322_TxDroppedPktCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxDroppedPktCnt_1_OFFS 0x13060 |
| #define QIB_7322_RxDroppedPktCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxDataPktCnt_1_OFFS 0x13068 |
| #define QIB_7322_RxDataPktCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxFlowPktCnt_1_OFFS 0x13070 |
| #define QIB_7322_RxFlowPktCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxDwordCnt_1_OFFS 0x13078 |
| #define QIB_7322_RxDwordCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxLenErrCnt_1_OFFS 0x13080 |
| #define QIB_7322_RxLenErrCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxMaxMinLenErrCnt_1_OFFS 0x13088 |
| #define QIB_7322_RxMaxMinLenErrCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxICRCErrCnt_1_OFFS 0x13090 |
| #define QIB_7322_RxICRCErrCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxVCRCErrCnt_1_OFFS 0x13098 |
| #define QIB_7322_RxVCRCErrCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxFlowCtrlViolCnt_1_OFFS 0x130A0 |
| #define QIB_7322_RxFlowCtrlViolCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxVersionErrCnt_1_OFFS 0x130A8 |
| #define QIB_7322_RxVersionErrCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxLinkMalformCnt_1_OFFS 0x130B0 |
| #define QIB_7322_RxLinkMalformCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxEBPCnt_1_OFFS 0x130B8 |
| #define QIB_7322_RxEBPCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxLPCRCErrCnt_1_OFFS 0x130C0 |
| #define QIB_7322_RxLPCRCErrCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxBufOvflCnt_1_OFFS 0x130C8 |
| #define QIB_7322_RxBufOvflCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxLenTruncateCnt_1_OFFS 0x130D0 |
| #define QIB_7322_RxLenTruncateCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxPKeyMismatchCnt_1_OFFS 0x130E0 |
| #define QIB_7322_RxPKeyMismatchCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_IBLinkDownedCnt_1_OFFS 0x13180 |
| #define QIB_7322_IBLinkDownedCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_IBSymbolErrCnt_1_OFFS 0x13188 |
| #define QIB_7322_IBSymbolErrCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_IBStatusChangeCnt_1_OFFS 0x13190 |
| #define QIB_7322_IBStatusChangeCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_IBLinkErrRecoveryCnt_1_OFFS 0x13198 |
| #define QIB_7322_IBLinkErrRecoveryCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_ExcessBufferOvflCnt_1_OFFS 0x131A8 |
| #define QIB_7322_ExcessBufferOvflCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_LocalLinkIntegrityErrCnt_1_OFFS 0x131B0 |
| #define QIB_7322_LocalLinkIntegrityErrCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxVlErrCnt_1_OFFS 0x131B8 |
| #define QIB_7322_RxVlErrCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxDlidFltrCnt_1_OFFS 0x131C0 |
| #define QIB_7322_RxDlidFltrCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxVL15DroppedPktCnt_1_OFFS 0x131C8 |
| #define QIB_7322_RxVL15DroppedPktCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxOtherLocalPhyErrCnt_1_OFFS 0x131D0 |
| #define QIB_7322_RxOtherLocalPhyErrCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RxQPInvalidContextCnt_1_OFFS 0x131D8 |
| #define QIB_7322_RxQPInvalidContextCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_TxHeadersErrCnt_1_OFFS 0x131F8 |
| #define QIB_7322_TxHeadersErrCnt_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_PSRcvDataCount_1_OFFS 0x13218 |
| #define QIB_7322_PSRcvDataCount_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_PSRcvPktsCount_1_OFFS 0x13220 |
| #define QIB_7322_PSRcvPktsCount_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_PSXmitDataCount_1_OFFS 0x13228 |
| #define QIB_7322_PSXmitDataCount_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_PSXmitPktsCount_1_OFFS 0x13230 |
| #define QIB_7322_PSXmitPktsCount_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_PSXmitWaitCount_1_OFFS 0x13238 |
| #define QIB_7322_PSXmitWaitCount_1_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RcvEgrArray_OFFS 0x14000 |
| #define QIB_7322_RcvEgrArray_DEF 0x0000000000000000 |
| #define QIB_7322_RcvEgrArray_RT_BufSize_LSB 0x25 |
| #define QIB_7322_RcvEgrArray_RT_BufSize_MSB 0x27 |
| #define QIB_7322_RcvEgrArray_RT_BufSize_RMASK 0x7 |
| #define QIB_7322_RcvEgrArray_RT_Addr_LSB 0x0 |
| #define QIB_7322_RcvEgrArray_RT_Addr_MSB 0x24 |
| #define QIB_7322_RcvEgrArray_RT_Addr_RMASK 0x1FFFFFFFFF |
| |
| #define QIB_7322_RcvTIDArray0_OFFS 0x50000 |
| #define QIB_7322_RcvTIDArray0_DEF 0x0000000000000000 |
| #define QIB_7322_RcvTIDArray0_RT_BufSize_LSB 0x25 |
| #define QIB_7322_RcvTIDArray0_RT_BufSize_MSB 0x27 |
| #define QIB_7322_RcvTIDArray0_RT_BufSize_RMASK 0x7 |
| #define QIB_7322_RcvTIDArray0_RT_Addr_LSB 0x0 |
| #define QIB_7322_RcvTIDArray0_RT_Addr_MSB 0x24 |
| #define QIB_7322_RcvTIDArray0_RT_Addr_RMASK 0x1FFFFFFFFF |
| |
| #define QIB_7322_IBSD_DDS_MAP_TABLE_0_OFFS 0xD0000 |
| #define QIB_7322_IBSD_DDS_MAP_TABLE_0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RcvHdrTail0_OFFS 0x200000 |
| #define QIB_7322_RcvHdrTail0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RcvHdrHead0_OFFS 0x200008 |
| #define QIB_7322_RcvHdrHead0_DEF 0x0000000000000000 |
| #define QIB_7322_RcvHdrHead0_counter_LSB 0x20 |
| #define QIB_7322_RcvHdrHead0_counter_MSB 0x2F |
| #define QIB_7322_RcvHdrHead0_counter_RMASK 0xFFFF |
| #define QIB_7322_RcvHdrHead0_RcvHeadPointer_LSB 0x0 |
| #define QIB_7322_RcvHdrHead0_RcvHeadPointer_MSB 0x1F |
| #define QIB_7322_RcvHdrHead0_RcvHeadPointer_RMASK 0xFFFFFFFF |
| |
| #define QIB_7322_RcvEgrIndexTail0_OFFS 0x200010 |
| #define QIB_7322_RcvEgrIndexTail0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RcvEgrIndexHead0_OFFS 0x200018 |
| #define QIB_7322_RcvEgrIndexHead0_DEF 0x0000000000000000 |
| |
| #define QIB_7322_RcvTIDFlowTable0_OFFS 0x201000 |
| #define QIB_7322_RcvTIDFlowTable0_DEF 0x0000000000000000 |
| #define QIB_7322_RcvTIDFlowTable0_GenMismatch_LSB 0x1C |
| #define QIB_7322_RcvTIDFlowTable0_GenMismatch_MSB 0x1C |
| #define QIB_7322_RcvTIDFlowTable0_GenMismatch_RMASK 0x1 |
| #define QIB_7322_RcvTIDFlowTable0_SeqMismatch_LSB 0x1B |
| #define QIB_7322_RcvTIDFlowTable0_SeqMismatch_MSB 0x1B |
| #define QIB_7322_RcvTIDFlowTable0_SeqMismatch_RMASK 0x1 |
| #define QIB_7322_RcvTIDFlowTable0_KeepOnGenErr_LSB 0x16 |
| #define QIB_7322_RcvTIDFlowTable0_KeepOnGenErr_MSB 0x16 |
| #define QIB_7322_RcvTIDFlowTable0_KeepOnGenErr_RMASK 0x1 |
| #define QIB_7322_RcvTIDFlowTable0_KeepAfterSeqErr_LSB 0x15 |
| #define QIB_7322_RcvTIDFlowTable0_KeepAfterSeqErr_MSB 0x15 |
| #define QIB_7322_RcvTIDFlowTable0_KeepAfterSeqErr_RMASK 0x1 |
| #define QIB_7322_RcvTIDFlowTable0_HdrSuppEnabled_LSB 0x14 |
| #define QIB_7322_RcvTIDFlowTable0_HdrSuppEnabled_MSB 0x14 |
| #define QIB_7322_RcvTIDFlowTable0_HdrSuppEnabled_RMASK 0x1 |
| #define QIB_7322_RcvTIDFlowTable0_FlowValid_LSB 0x13 |
| #define QIB_7322_RcvTIDFlowTable0_FlowValid_MSB 0x13 |
| #define QIB_7322_RcvTIDFlowTable0_FlowValid_RMASK 0x1 |
| #define QIB_7322_RcvTIDFlowTable0_GenVal_LSB 0xB |
| #define QIB_7322_RcvTIDFlowTable0_GenVal_MSB 0x12 |
| #define QIB_7322_RcvTIDFlowTable0_GenVal_RMASK 0xFF |
| #define QIB_7322_RcvTIDFlowTable0_SeqNum_LSB 0x0 |
| #define QIB_7322_RcvTIDFlowTable0_SeqNum_MSB 0xA |
| #define QIB_7322_RcvTIDFlowTable0_SeqNum_RMASK 0x7FF |
