blob: b5843c255263df2d04c12f36e819b60bab47369f [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * probe.c - PCI detection and setup code
3 */
4
5#include <linux/kernel.h>
6#include <linux/delay.h>
7#include <linux/init.h>
8#include <linux/pci.h>
Suthikulpanit, Suravee50230712015-10-28 15:50:53 -07009#include <linux/of_device.h>
Murali Karicheride335bb42015-03-03 12:52:13 -050010#include <linux/of_pci.h>
Bjorn Helgaas589fcc22014-09-12 20:02:00 -060011#include <linux/pci_hotplug.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070012#include <linux/slab.h>
13#include <linux/module.h>
14#include <linux/cpumask.h>
Shaohua Li7d715a62008-02-25 09:46:41 +080015#include <linux/pci-aspm.h>
Taku Izumib07461a2015-09-17 10:09:37 -050016#include <linux/aer.h>
Suthikulpanit, Suravee29dbe1f2015-10-28 15:50:54 -070017#include <linux/acpi.h>
Bjorn Helgaas284f5f92012-04-30 15:21:02 -060018#include <asm-generic/pci-bridge.h>
Greg KHbc56b9e2005-04-08 14:53:31 +090019#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070020
21#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
22#define CARDBUS_RESERVE_BUSNR 3
Linus Torvalds1da177e2005-04-16 15:20:36 -070023
Stephen Hemminger0b950f02014-01-10 17:14:48 -070024static struct resource busn_resource = {
Yinghai Lu67cdc822012-05-17 18:51:12 -070025 .name = "PCI busn",
26 .start = 0,
27 .end = 255,
28 .flags = IORESOURCE_BUS,
29};
30
Linus Torvalds1da177e2005-04-16 15:20:36 -070031/* Ugh. Need to stop exporting this to modules. */
32LIST_HEAD(pci_root_buses);
33EXPORT_SYMBOL(pci_root_buses);
34
Yinghai Lu5cc62c22012-05-17 18:51:11 -070035static LIST_HEAD(pci_domain_busn_res_list);
36
37struct pci_domain_busn_res {
38 struct list_head list;
39 struct resource res;
40 int domain_nr;
41};
42
43static struct resource *get_pci_domain_busn_res(int domain_nr)
44{
45 struct pci_domain_busn_res *r;
46
47 list_for_each_entry(r, &pci_domain_busn_res_list, list)
48 if (r->domain_nr == domain_nr)
49 return &r->res;
50
51 r = kzalloc(sizeof(*r), GFP_KERNEL);
52 if (!r)
53 return NULL;
54
55 r->domain_nr = domain_nr;
56 r->res.start = 0;
57 r->res.end = 0xff;
58 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
59
60 list_add_tail(&r->list, &pci_domain_busn_res_list);
61
62 return &r->res;
63}
64
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080065static int find_anything(struct device *dev, void *data)
66{
67 return 1;
68}
Linus Torvalds1da177e2005-04-16 15:20:36 -070069
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070070/*
71 * Some device drivers need know if pci is initiated.
72 * Basically, we think pci is not initiated when there
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080073 * is no device to be found on the pci_bus_type.
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070074 */
75int no_pci_devices(void)
76{
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080077 struct device *dev;
78 int no_devices;
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070079
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080080 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
81 no_devices = (dev == NULL);
82 put_device(dev);
83 return no_devices;
84}
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070085EXPORT_SYMBOL(no_pci_devices);
86
Linus Torvalds1da177e2005-04-16 15:20:36 -070087/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070088 * PCI Bus Class
89 */
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040090static void release_pcibus_dev(struct device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -070091{
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040092 struct pci_bus *pci_bus = to_pci_bus(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -070093
Markus Elfringff0387c2014-11-10 21:02:17 -070094 put_device(pci_bus->bridge);
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -070095 pci_bus_remove_resources(pci_bus);
Benjamin Herrenschmidt98d9f302011-04-11 11:37:07 +100096 pci_release_bus_of_node(pci_bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -070097 kfree(pci_bus);
98}
99
100static struct class pcibus_class = {
101 .name = "pci_bus",
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -0400102 .dev_release = &release_pcibus_dev,
Greg Kroah-Hartman56039e62013-07-24 15:05:17 -0700103 .dev_groups = pcibus_groups,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104};
105
106static int __init pcibus_class_init(void)
107{
108 return class_register(&pcibus_class);
109}
110postcore_initcall(pcibus_class_init);
111
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400112static u64 pci_size(u64 base, u64 maxbase, u64 mask)
Yinghai Lu07eddf32006-11-29 13:53:10 -0800113{
114 u64 size = mask & maxbase; /* Find the significant bits */
115 if (!size)
116 return 0;
117
118 /* Get the lowest of them to find the decode size, and
119 from that the extent. */
120 size = (size & ~(size-1)) - 1;
121
122 /* base == maxbase can be valid only if the BAR has
123 already been programmed with all 1s. */
124 if (base == maxbase && ((base | size) & mask) != mask)
125 return 0;
126
127 return size;
128}
129
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600130static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
Yinghai Lu07eddf32006-11-29 13:53:10 -0800131{
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600132 u32 mem_type;
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600133 unsigned long flags;
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600134
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400135 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600136 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
137 flags |= IORESOURCE_IO;
138 return flags;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400139 }
140
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600141 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
142 flags |= IORESOURCE_MEM;
143 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
144 flags |= IORESOURCE_PREFETCH;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400145
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600146 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
147 switch (mem_type) {
148 case PCI_BASE_ADDRESS_MEM_TYPE_32:
149 break;
150 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600151 /* 1M mem BAR treated as 32-bit BAR */
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600152 break;
153 case PCI_BASE_ADDRESS_MEM_TYPE_64:
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600154 flags |= IORESOURCE_MEM_64;
155 break;
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600156 default:
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600157 /* mem unknown type treated as 32-bit BAR */
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600158 break;
159 }
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600160 return flags;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400161}
162
Zoltan Kiss808e34e2013-08-22 23:19:18 +0100163#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
164
Yu Zhao0b400c72008-11-22 02:40:40 +0800165/**
166 * pci_read_base - read a PCI BAR
167 * @dev: the PCI device
168 * @type: type of the BAR
169 * @res: resource buffer to be filled in
170 * @pos: BAR position in the config space
171 *
172 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400173 */
Yu Zhao0b400c72008-11-22 02:40:40 +0800174int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400175 struct resource *res, unsigned int pos)
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400176{
177 u32 l, sz, mask;
Bjorn Helgaas23b13bc2014-04-14 15:25:54 -0600178 u64 l64, sz64, mask64;
Jacob Pan253d2e52010-07-16 10:19:22 -0700179 u16 orig_cmd;
Kevin Haocf4d1cf2013-05-25 19:36:27 +0800180 struct pci_bus_region region, inverted_region;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400181
Michael S. Tsirkin1ed67432009-10-29 17:24:59 +0200182 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400183
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600184 /* No printks while decoding is disabled! */
Jacob Pan253d2e52010-07-16 10:19:22 -0700185 if (!dev->mmio_always_on) {
186 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
Zoltan Kiss808e34e2013-08-22 23:19:18 +0100187 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
188 pci_write_config_word(dev, PCI_COMMAND,
189 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
190 }
Jacob Pan253d2e52010-07-16 10:19:22 -0700191 }
192
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400193 res->name = pci_name(dev);
194
195 pci_read_config_dword(dev, pos, &l);
Michael S. Tsirkin1ed67432009-10-29 17:24:59 +0200196 pci_write_config_dword(dev, pos, l | mask);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400197 pci_read_config_dword(dev, pos, &sz);
198 pci_write_config_dword(dev, pos, l);
199
200 /*
201 * All bits set in sz means the device isn't working properly.
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600202 * If the BAR isn't implemented, all bits must be 0. If it's a
203 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
204 * 1 must be clear.
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400205 */
Myron Stowef795d862014-10-30 11:54:43 -0600206 if (sz == 0xffffffff)
207 sz = 0;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400208
209 /*
210 * I don't know how l can have all bits set. Copied from old code.
211 * Maybe it fixes a bug on some ancient platform.
212 */
213 if (l == 0xffffffff)
214 l = 0;
215
216 if (type == pci_bar_unknown) {
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600217 res->flags = decode_bar(dev, l);
218 res->flags |= IORESOURCE_SIZEALIGN;
219 if (res->flags & IORESOURCE_IO) {
Myron Stowef795d862014-10-30 11:54:43 -0600220 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
221 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
222 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400223 } else {
Myron Stowef795d862014-10-30 11:54:43 -0600224 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
225 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
226 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400227 }
228 } else {
229 res->flags |= (l & IORESOURCE_ROM_ENABLE);
Myron Stowef795d862014-10-30 11:54:43 -0600230 l64 = l & PCI_ROM_ADDRESS_MASK;
231 sz64 = sz & PCI_ROM_ADDRESS_MASK;
232 mask64 = (u32)PCI_ROM_ADDRESS_MASK;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400233 }
234
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600235 if (res->flags & IORESOURCE_MEM_64) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400236 pci_read_config_dword(dev, pos + 4, &l);
237 pci_write_config_dword(dev, pos + 4, ~0);
238 pci_read_config_dword(dev, pos + 4, &sz);
239 pci_write_config_dword(dev, pos + 4, l);
240
241 l64 |= ((u64)l << 32);
242 sz64 |= ((u64)sz << 32);
Myron Stowef795d862014-10-30 11:54:43 -0600243 mask64 |= ((u64)~0 << 32);
244 }
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400245
Myron Stowef795d862014-10-30 11:54:43 -0600246 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
247 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400248
Myron Stowef795d862014-10-30 11:54:43 -0600249 if (!sz64)
250 goto fail;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400251
Myron Stowef795d862014-10-30 11:54:43 -0600252 sz64 = pci_size(l64, sz64, mask64);
Myron Stowe7e79c5f2014-10-30 11:54:50 -0600253 if (!sz64) {
254 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
255 pos);
Myron Stowef795d862014-10-30 11:54:43 -0600256 goto fail;
Myron Stowe7e79c5f2014-10-30 11:54:50 -0600257 }
Myron Stowef795d862014-10-30 11:54:43 -0600258
259 if (res->flags & IORESOURCE_MEM_64) {
Yinghai Lu3a9ad0b2015-05-27 17:23:51 -0700260 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
261 && sz64 > 0x100000000ULL) {
Bjorn Helgaas23b13bc2014-04-14 15:25:54 -0600262 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
263 res->start = 0;
264 res->end = 0;
Myron Stowef795d862014-10-30 11:54:43 -0600265 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
266 pos, (unsigned long long)sz64);
Bjorn Helgaas23b13bc2014-04-14 15:25:54 -0600267 goto out;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600268 }
269
Yinghai Lu3a9ad0b2015-05-27 17:23:51 -0700270 if ((sizeof(pci_bus_addr_t) < 8) && l) {
Bjorn Helgaas31e9dd22014-04-29 18:37:47 -0600271 /* Above 32-bit boundary; try to reallocate */
Bjorn Helgaasc83bd902014-02-26 11:26:00 -0700272 res->flags |= IORESOURCE_UNSET;
Bjorn Helgaas72dc5602014-04-29 18:42:49 -0600273 res->start = 0;
274 res->end = sz64;
Myron Stowef795d862014-10-30 11:54:43 -0600275 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
276 pos, (unsigned long long)l64);
Bjorn Helgaas72dc5602014-04-29 18:42:49 -0600277 goto out;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400278 }
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400279 }
280
Myron Stowef795d862014-10-30 11:54:43 -0600281 region.start = l64;
282 region.end = l64 + sz64;
283
Yinghai Lufc279852013-12-09 22:54:40 -0800284 pcibios_bus_to_resource(dev->bus, res, &region);
285 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
Kevin Haocf4d1cf2013-05-25 19:36:27 +0800286
287 /*
288 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
289 * the corresponding resource address (the physical address used by
290 * the CPU. Converting that resource address back to a bus address
291 * should yield the original BAR value:
292 *
293 * resource_to_bus(bus_to_resource(A)) == A
294 *
295 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
296 * be claimed by the device.
297 */
298 if (inverted_region.start != region.start) {
Kevin Haocf4d1cf2013-05-25 19:36:27 +0800299 res->flags |= IORESOURCE_UNSET;
Kevin Haocf4d1cf2013-05-25 19:36:27 +0800300 res->start = 0;
Bjorn Helgaas26370fc2014-04-14 15:26:50 -0600301 res->end = region.end - region.start;
Myron Stowef795d862014-10-30 11:54:43 -0600302 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
303 pos, (unsigned long long)region.start);
Kevin Haocf4d1cf2013-05-25 19:36:27 +0800304 }
Kevin Hao96ddef22013-05-25 19:36:26 +0800305
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600306 goto out;
307
308
309fail:
310 res->flags = 0;
311out:
Bjorn Helgaas31e9dd22014-04-29 18:37:47 -0600312 if (res->flags)
Kevin Hao33963e302013-05-25 19:36:25 +0800313 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600314
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600315 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
Yinghai Lu07eddf32006-11-29 13:53:10 -0800316}
317
Linus Torvalds1da177e2005-04-16 15:20:36 -0700318static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
319{
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400320 unsigned int pos, reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321
Prarit Bhargavaa87f69d2016-05-11 12:27:16 -0400322 if (dev->non_compliant_bars)
323 return;
324
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400325 for (pos = 0; pos < howmany; pos++) {
326 struct resource *res = &dev->resource[pos];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700327 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400328 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329 }
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400330
Linus Torvalds1da177e2005-04-16 15:20:36 -0700331 if (rom) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400332 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333 dev->rom_base_reg = rom;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400334 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
Dan Williams92b19ff2015-08-10 23:07:06 -0400335 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400336 __pci_read_base(dev, pci_bar_mem32, res, rom);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700337 }
338}
339
Bill Pemberton15856ad2012-11-21 15:35:00 -0500340static void pci_read_bridge_io(struct pci_bus *child)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700341{
342 struct pci_dev *dev = child->self;
343 u8 io_base_lo, io_limit_lo;
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600344 unsigned long io_mask, io_granularity, base, limit;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700345 struct pci_bus_region region;
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600346 struct resource *res;
347
348 io_mask = PCI_IO_RANGE_MASK;
349 io_granularity = 0x1000;
350 if (dev->io_window_1k) {
351 /* Support 1K I/O space granularity */
352 io_mask = PCI_IO_1K_RANGE_MASK;
353 io_granularity = 0x400;
354 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700355
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356 res = child->resource[0];
357 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
358 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600359 base = (io_base_lo & io_mask) << 8;
360 limit = (io_limit_lo & io_mask) << 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361
362 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
363 u16 io_base_hi, io_limit_hi;
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600364
Linus Torvalds1da177e2005-04-16 15:20:36 -0700365 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
366 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600367 base |= ((unsigned long) io_base_hi << 16);
368 limit |= ((unsigned long) io_limit_hi << 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700369 }
370
Bjorn Helgaas5dde3832012-07-09 13:38:41 -0600371 if (base <= limit) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700372 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700373 region.start = base;
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600374 region.end = limit + io_granularity - 1;
Yinghai Lufc279852013-12-09 22:54:40 -0800375 pcibios_bus_to_resource(dev->bus, res, &region);
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600376 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700377 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700378}
379
Bill Pemberton15856ad2012-11-21 15:35:00 -0500380static void pci_read_bridge_mmio(struct pci_bus *child)
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700381{
382 struct pci_dev *dev = child->self;
383 u16 mem_base_lo, mem_limit_lo;
384 unsigned long base, limit;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700385 struct pci_bus_region region;
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700386 struct resource *res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387
388 res = child->resource[1];
389 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
390 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600391 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
392 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
Bjorn Helgaas5dde3832012-07-09 13:38:41 -0600393 if (base <= limit) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700395 region.start = base;
396 region.end = limit + 0xfffff;
Yinghai Lufc279852013-12-09 22:54:40 -0800397 pcibios_bus_to_resource(dev->bus, res, &region);
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600398 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700400}
401
Bill Pemberton15856ad2012-11-21 15:35:00 -0500402static void pci_read_bridge_mmio_pref(struct pci_bus *child)
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700403{
404 struct pci_dev *dev = child->self;
405 u16 mem_base_lo, mem_limit_lo;
Yinghai Lu7fc986d2014-11-19 14:30:32 -0700406 u64 base64, limit64;
Yinghai Lu3a9ad0b2015-05-27 17:23:51 -0700407 pci_bus_addr_t base, limit;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700408 struct pci_bus_region region;
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700409 struct resource *res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700410
411 res = child->resource[2];
412 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
413 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
Yinghai Lu7fc986d2014-11-19 14:30:32 -0700414 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
415 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700416
417 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
418 u32 mem_base_hi, mem_limit_hi;
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600419
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
421 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
422
423 /*
424 * Some bridges set the base > limit by default, and some
425 * (broken) BIOSes do not initialize them. If we find
426 * this, just assume they are not being used.
427 */
428 if (mem_base_hi <= mem_limit_hi) {
Yinghai Lu7fc986d2014-11-19 14:30:32 -0700429 base64 |= (u64) mem_base_hi << 32;
430 limit64 |= (u64) mem_limit_hi << 32;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431 }
432 }
Yinghai Lu7fc986d2014-11-19 14:30:32 -0700433
Yinghai Lu3a9ad0b2015-05-27 17:23:51 -0700434 base = (pci_bus_addr_t) base64;
435 limit = (pci_bus_addr_t) limit64;
Yinghai Lu7fc986d2014-11-19 14:30:32 -0700436
437 if (base != base64) {
438 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
439 (unsigned long long) base64);
440 return;
441 }
442
Bjorn Helgaas5dde3832012-07-09 13:38:41 -0600443 if (base <= limit) {
Yinghai Lu1f82de12009-04-23 20:48:32 -0700444 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
445 IORESOURCE_MEM | IORESOURCE_PREFETCH;
446 if (res->flags & PCI_PREF_RANGE_TYPE_64)
447 res->flags |= IORESOURCE_MEM_64;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700448 region.start = base;
449 region.end = limit + 0xfffff;
Yinghai Lufc279852013-12-09 22:54:40 -0800450 pcibios_bus_to_resource(dev->bus, res, &region);
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600451 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700452 }
453}
454
Bill Pemberton15856ad2012-11-21 15:35:00 -0500455void pci_read_bridge_bases(struct pci_bus *child)
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700456{
457 struct pci_dev *dev = child->self;
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700458 struct resource *res;
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700459 int i;
460
461 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
462 return;
463
Yinghai Lub918c622012-05-17 18:51:11 -0700464 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
465 &child->busn_res,
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700466 dev->transparent ? " (subtractive decode)" : "");
467
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700468 pci_bus_remove_resources(child);
469 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
470 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
471
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700472 pci_read_bridge_io(child);
473 pci_read_bridge_mmio(child);
474 pci_read_bridge_mmio_pref(child);
Bjorn Helgaas2adf7512010-02-23 10:24:26 -0700475
476 if (dev->transparent) {
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700477 pci_bus_for_each_resource(child->parent, res, i) {
Bjorn Helgaasd739a092014-04-14 16:10:54 -0600478 if (res && res->flags) {
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700479 pci_bus_add_resource(child, res,
480 PCI_SUBTRACTIVE_DECODE);
Bjorn Helgaas2adf7512010-02-23 10:24:26 -0700481 dev_printk(KERN_DEBUG, &dev->dev,
482 " bridge window %pR (subtractive decode)\n",
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700483 res);
484 }
Bjorn Helgaas2adf7512010-02-23 10:24:26 -0700485 }
486 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700487}
488
Catalin Marinas670ba0c2014-09-29 15:29:26 +0100489static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700490{
491 struct pci_bus *b;
492
Eric Sesterhennf5afe802006-02-28 15:34:49 +0100493 b = kzalloc(sizeof(*b), GFP_KERNEL);
Bjorn Helgaas05013482013-06-05 14:22:11 -0600494 if (!b)
495 return NULL;
496
497 INIT_LIST_HEAD(&b->node);
498 INIT_LIST_HEAD(&b->children);
499 INIT_LIST_HEAD(&b->devices);
500 INIT_LIST_HEAD(&b->slots);
501 INIT_LIST_HEAD(&b->resources);
502 b->max_bus_speed = PCI_SPEED_UNKNOWN;
503 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
Catalin Marinas670ba0c2014-09-29 15:29:26 +0100504#ifdef CONFIG_PCI_DOMAINS_GENERIC
505 if (parent)
506 b->domain_nr = parent->domain_nr;
507#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700508 return b;
509}
510
Jiang Liu70efde22013-06-07 16:16:51 -0600511static void pci_release_host_bridge_dev(struct device *dev)
512{
513 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
514
515 if (bridge->release_fn)
516 bridge->release_fn(bridge);
517
518 pci_free_resource_list(&bridge->windows);
519
520 kfree(bridge);
521}
522
Yinghai Lu7b543662012-04-02 18:31:53 -0700523static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
524{
525 struct pci_host_bridge *bridge;
526
527 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
Bjorn Helgaas05013482013-06-05 14:22:11 -0600528 if (!bridge)
529 return NULL;
Yinghai Lu7b543662012-04-02 18:31:53 -0700530
Bjorn Helgaas05013482013-06-05 14:22:11 -0600531 INIT_LIST_HEAD(&bridge->windows);
532 bridge->bus = b;
Yinghai Lu7b543662012-04-02 18:31:53 -0700533 return bridge;
534}
535
Stephen Hemminger0b950f02014-01-10 17:14:48 -0700536static const unsigned char pcix_bus_speed[] = {
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500537 PCI_SPEED_UNKNOWN, /* 0 */
538 PCI_SPEED_66MHz_PCIX, /* 1 */
539 PCI_SPEED_100MHz_PCIX, /* 2 */
540 PCI_SPEED_133MHz_PCIX, /* 3 */
541 PCI_SPEED_UNKNOWN, /* 4 */
542 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
543 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
544 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
545 PCI_SPEED_UNKNOWN, /* 8 */
546 PCI_SPEED_66MHz_PCIX_266, /* 9 */
547 PCI_SPEED_100MHz_PCIX_266, /* A */
548 PCI_SPEED_133MHz_PCIX_266, /* B */
549 PCI_SPEED_UNKNOWN, /* C */
550 PCI_SPEED_66MHz_PCIX_533, /* D */
551 PCI_SPEED_100MHz_PCIX_533, /* E */
552 PCI_SPEED_133MHz_PCIX_533 /* F */
553};
554
Jacob Keller343e51a2013-07-31 06:53:16 +0000555const unsigned char pcie_link_speed[] = {
Matthew Wilcox3749c512009-12-13 08:11:32 -0500556 PCI_SPEED_UNKNOWN, /* 0 */
557 PCIE_SPEED_2_5GT, /* 1 */
558 PCIE_SPEED_5_0GT, /* 2 */
Matthew Wilcox9dfd97f2009-12-13 08:11:35 -0500559 PCIE_SPEED_8_0GT, /* 3 */
Matthew Wilcox3749c512009-12-13 08:11:32 -0500560 PCI_SPEED_UNKNOWN, /* 4 */
561 PCI_SPEED_UNKNOWN, /* 5 */
562 PCI_SPEED_UNKNOWN, /* 6 */
563 PCI_SPEED_UNKNOWN, /* 7 */
564 PCI_SPEED_UNKNOWN, /* 8 */
565 PCI_SPEED_UNKNOWN, /* 9 */
566 PCI_SPEED_UNKNOWN, /* A */
567 PCI_SPEED_UNKNOWN, /* B */
568 PCI_SPEED_UNKNOWN, /* C */
569 PCI_SPEED_UNKNOWN, /* D */
570 PCI_SPEED_UNKNOWN, /* E */
571 PCI_SPEED_UNKNOWN /* F */
572};
573
574void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
575{
Bjorn Helgaas231afea2012-12-05 13:51:18 -0700576 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
Matthew Wilcox3749c512009-12-13 08:11:32 -0500577}
578EXPORT_SYMBOL_GPL(pcie_update_link_speed);
579
Matthew Wilcox45b4cdd52009-12-13 08:11:34 -0500580static unsigned char agp_speeds[] = {
581 AGP_UNKNOWN,
582 AGP_1X,
583 AGP_2X,
584 AGP_4X,
585 AGP_8X
586};
587
588static enum pci_bus_speed agp_speed(int agp3, int agpstat)
589{
590 int index = 0;
591
592 if (agpstat & 4)
593 index = 3;
594 else if (agpstat & 2)
595 index = 2;
596 else if (agpstat & 1)
597 index = 1;
598 else
599 goto out;
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700600
Matthew Wilcox45b4cdd52009-12-13 08:11:34 -0500601 if (agp3) {
602 index += 2;
603 if (index == 5)
604 index = 0;
605 }
606
607 out:
608 return agp_speeds[index];
609}
610
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500611static void pci_set_bus_speed(struct pci_bus *bus)
612{
613 struct pci_dev *bridge = bus->self;
614 int pos;
615
Matthew Wilcox45b4cdd52009-12-13 08:11:34 -0500616 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
617 if (!pos)
618 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
619 if (pos) {
620 u32 agpstat, agpcmd;
621
622 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
623 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
624
625 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
626 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
627 }
628
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500629 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
630 if (pos) {
631 u16 status;
632 enum pci_bus_speed max;
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500633
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700634 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
635 &status);
636
637 if (status & PCI_X_SSTATUS_533MHZ) {
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500638 max = PCI_SPEED_133MHz_PCIX_533;
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700639 } else if (status & PCI_X_SSTATUS_266MHZ) {
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500640 max = PCI_SPEED_133MHz_PCIX_266;
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700641 } else if (status & PCI_X_SSTATUS_133MHZ) {
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400642 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500643 max = PCI_SPEED_133MHz_PCIX_ECC;
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400644 else
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500645 max = PCI_SPEED_133MHz_PCIX;
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500646 } else {
647 max = PCI_SPEED_66MHz_PCIX;
648 }
649
650 bus->max_bus_speed = max;
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700651 bus->cur_bus_speed = pcix_bus_speed[
652 (status & PCI_X_SSTATUS_FREQ) >> 6];
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500653
654 return;
655 }
656
Yijing Wangfdfe1512013-09-05 15:55:29 +0800657 if (pci_is_pcie(bridge)) {
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500658 u32 linkcap;
659 u16 linksta;
660
Jiang Liu59875ae2012-07-24 17:20:06 +0800661 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
Bjorn Helgaas231afea2012-12-05 13:51:18 -0700662 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500663
Jiang Liu59875ae2012-07-24 17:20:06 +0800664 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500665 pcie_update_link_speed(bus, linksta);
666 }
667}
668
Marc Zyngier44aa0c62015-07-28 14:46:11 +0100669static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
670{
Marc Zyngierb165e2b2015-07-28 14:46:12 +0100671 struct irq_domain *d;
672
Marc Zyngier44aa0c62015-07-28 14:46:11 +0100673 /*
674 * Any firmware interface that can resolve the msi_domain
675 * should be called from here.
676 */
Marc Zyngierb165e2b2015-07-28 14:46:12 +0100677 d = pci_host_bridge_of_msi_domain(bus);
Marc Zyngier44aa0c62015-07-28 14:46:11 +0100678
Marc Zyngierb165e2b2015-07-28 14:46:12 +0100679 return d;
Marc Zyngier44aa0c62015-07-28 14:46:11 +0100680}
681
682static void pci_set_bus_msi_domain(struct pci_bus *bus)
683{
684 struct irq_domain *d;
Alex Williamson38ea72b2015-09-18 15:08:54 -0600685 struct pci_bus *b;
Marc Zyngier44aa0c62015-07-28 14:46:11 +0100686
687 /*
Alex Williamson38ea72b2015-09-18 15:08:54 -0600688 * The bus can be a root bus, a subordinate bus, or a virtual bus
689 * created by an SR-IOV device. Walk up to the first bridge device
690 * found or derive the domain from the host bridge.
Marc Zyngier44aa0c62015-07-28 14:46:11 +0100691 */
Alex Williamson38ea72b2015-09-18 15:08:54 -0600692 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
693 if (b->self)
694 d = dev_get_msi_domain(&b->self->dev);
695 }
696
697 if (!d)
698 d = pci_host_bridge_msi_domain(b);
Marc Zyngier44aa0c62015-07-28 14:46:11 +0100699
700 dev_set_msi_domain(&bus->dev, d);
701}
702
Adrian Bunkcbd4e052008-04-18 13:53:55 -0700703static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
704 struct pci_dev *bridge, int busnr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700705{
706 struct pci_bus *child;
707 int i;
Yinghai Lu4f535092013-01-21 13:20:52 -0800708 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700709
710 /*
711 * Allocate a new bus, and inherit stuff from the parent..
712 */
Catalin Marinas670ba0c2014-09-29 15:29:26 +0100713 child = pci_alloc_bus(parent);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700714 if (!child)
715 return NULL;
716
Linus Torvalds1da177e2005-04-16 15:20:36 -0700717 child->parent = parent;
718 child->ops = parent->ops;
Thierry Reding0cbdcfc2013-08-09 22:27:08 +0200719 child->msi = parent->msi;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700720 child->sysdata = parent->sysdata;
Michael S. Tsirkin6e325a62006-02-14 18:52:22 +0200721 child->bus_flags = parent->bus_flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700722
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -0400723 /* initialize some portions of the bus device, but don't register it
Yinghai Lu4f535092013-01-21 13:20:52 -0800724 * now as the parent is not properly set up yet.
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -0400725 */
726 child->dev.class = &pcibus_class;
Kay Sievers1a927132008-10-30 02:17:49 +0100727 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700728
729 /*
730 * Set up the primary, secondary and subordinate
731 * bus numbers.
732 */
Yinghai Lub918c622012-05-17 18:51:11 -0700733 child->number = child->busn_res.start = busnr;
734 child->primary = parent->busn_res.start;
735 child->busn_res.end = 0xff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700736
Yinghai Lu4f535092013-01-21 13:20:52 -0800737 if (!bridge) {
738 child->dev.parent = parent->bridge;
739 goto add_dev;
740 }
Yu Zhao3789fa82008-11-22 02:41:07 +0800741
742 child->self = bridge;
743 child->bridge = get_device(&bridge->dev);
Yinghai Lu4f535092013-01-21 13:20:52 -0800744 child->dev.parent = child->bridge;
Benjamin Herrenschmidt98d9f302011-04-11 11:37:07 +1000745 pci_set_bus_of_node(child);
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500746 pci_set_bus_speed(child);
747
Linus Torvalds1da177e2005-04-16 15:20:36 -0700748 /* Set up default resource pointers and names.. */
Yu Zhaofde09c62008-11-22 02:39:32 +0800749 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700750 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
751 child->resource[i]->name = child->name;
752 }
753 bridge->subordinate = child;
754
Yinghai Lu4f535092013-01-21 13:20:52 -0800755add_dev:
Marc Zyngier44aa0c62015-07-28 14:46:11 +0100756 pci_set_bus_msi_domain(child);
Yinghai Lu4f535092013-01-21 13:20:52 -0800757 ret = device_register(&child->dev);
758 WARN_ON(ret < 0);
759
Jiang Liu10a95742013-04-12 05:44:20 +0000760 pcibios_add_bus(child);
761
Yinghai Lu4f535092013-01-21 13:20:52 -0800762 /* Create legacy_io and legacy_mem files for this bus */
763 pci_create_legacy_files(child);
764
Linus Torvalds1da177e2005-04-16 15:20:36 -0700765 return child;
766}
767
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400768struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
769 int busnr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770{
771 struct pci_bus *child;
772
773 child = pci_alloc_child_bus(parent, dev, busnr);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700774 if (child) {
Zhang Yanmind71374d2006-06-02 12:35:43 +0800775 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700776 list_add_tail(&child->node, &parent->children);
Zhang Yanmind71374d2006-06-02 12:35:43 +0800777 up_write(&pci_bus_sem);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700778 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700779 return child;
780}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -0600781EXPORT_SYMBOL(pci_add_new_bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700782
Rajat Jainf3dbd802014-09-02 16:26:00 -0700783static void pci_enable_crs(struct pci_dev *pdev)
784{
785 u16 root_cap = 0;
786
787 /* Enable CRS Software Visibility if supported */
788 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
789 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
790 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
791 PCI_EXP_RTCTL_CRSSVE);
792}
793
Linus Torvalds1da177e2005-04-16 15:20:36 -0700794/*
795 * If it's a bridge, configure it and scan the bus behind it.
796 * For CardBus bridges, we don't scan behind as the devices will
797 * be handled by the bridge driver itself.
798 *
799 * We need to process bridges in two passes -- first we scan those
800 * already configured by the BIOS and after we are done with all of
801 * them, we proceed to assigning numbers to the remaining buses in
802 * order to avoid overlaps between old and new bus numbers.
803 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500804int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700805{
806 struct pci_bus *child;
807 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
Dominik Brodowski49887942005-12-08 16:53:12 +0100808 u32 buses, i, j = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700809 u16 bctl;
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600810 u8 primary, secondary, subordinate;
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100811 int broken = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700812
813 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600814 primary = buses & 0xFF;
815 secondary = (buses >> 8) & 0xFF;
816 subordinate = (buses >> 16) & 0xFF;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700817
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600818 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
819 secondary, subordinate, pass);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700820
Yinghai Lu71f6bd42012-01-30 12:25:24 +0100821 if (!primary && (primary != bus->number) && secondary && subordinate) {
822 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
823 primary = bus->number;
824 }
825
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100826 /* Check if setup is sensible at all */
827 if (!pass &&
Yinghai Lu1965f662012-09-10 17:19:33 -0700828 (primary != bus->number || secondary <= bus->number ||
Bjorn Helgaas12d87062014-09-19 11:08:40 -0600829 secondary > subordinate)) {
Yinghai Lu1965f662012-09-10 17:19:33 -0700830 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
831 secondary, subordinate);
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100832 broken = 1;
833 }
834
Linus Torvalds1da177e2005-04-16 15:20:36 -0700835 /* Disable MasterAbortMode during probing to avoid reporting
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700836 of bus errors (in some architectures) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700837 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
838 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
839 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
840
Rajat Jainf3dbd802014-09-02 16:26:00 -0700841 pci_enable_crs(dev);
842
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600843 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
844 !is_cardbus && !broken) {
845 unsigned int cmax;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700846 /*
847 * Bus already configured by firmware, process it in the first
848 * pass and just note the configuration.
849 */
850 if (pass)
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000851 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700852
853 /*
Andreas Noever2ed85822014-01-23 21:59:22 +0100854 * The bus might already exist for two reasons: Either we are
855 * rescanning the bus or the bus is reachable through more than
856 * one bridge. The second case can happen with the i450NX
857 * chipset.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700858 */
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600859 child = pci_find_bus(pci_domain_nr(bus), secondary);
Alex Chiang74710de2009-03-20 14:56:10 -0600860 if (!child) {
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600861 child = pci_add_new_bus(bus, dev, secondary);
Alex Chiang74710de2009-03-20 14:56:10 -0600862 if (!child)
863 goto out;
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600864 child->primary = primary;
Yinghai Lubc76b732012-05-17 18:51:13 -0700865 pci_bus_insert_busn_res(child, secondary, subordinate);
Alex Chiang74710de2009-03-20 14:56:10 -0600866 child->bridge_ctl = bctl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700867 }
868
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869 cmax = pci_scan_child_bus(child);
Andreas Noeverc95b0bd2014-01-23 21:59:27 +0100870 if (cmax > subordinate)
871 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
872 subordinate, cmax);
873 /* subordinate should equal child->busn_res.end */
874 if (subordinate > max)
875 max = subordinate;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876 } else {
877 /*
878 * We need to assign a number to this bus which we always
879 * do in the second pass.
880 */
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700881 if (!pass) {
Andreas Noever619c8c32014-01-23 21:59:23 +0100882 if (pcibios_assign_all_busses() || broken || is_cardbus)
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700883 /* Temporarily disable forwarding of the
884 configuration cycles on all bridges in
885 this bus segment to avoid possible
886 conflicts in the second pass between two
887 bridges programmed with overlapping
888 bus ranges. */
889 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
890 buses & ~0xffffff);
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000891 goto out;
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700892 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700893
894 /* Clear errors */
895 pci_write_config_word(dev, PCI_STATUS, 0xffff);
896
Bjorn Helgaas7a0b33d2014-09-19 10:56:06 -0600897 /* Prevent assigning a bus number that already exists.
898 * This can happen when a bridge is hot-plugged, so in
899 * this case we only re-scan this bus. */
Tiejun Chenb1a98b62011-06-02 11:02:50 +0800900 child = pci_find_bus(pci_domain_nr(bus), max+1);
901 if (!child) {
Andreas Noever9a4d7d82014-01-23 21:59:21 +0100902 child = pci_add_new_bus(bus, dev, max+1);
Tiejun Chenb1a98b62011-06-02 11:02:50 +0800903 if (!child)
904 goto out;
Bjorn Helgaas12d87062014-09-19 11:08:40 -0600905 pci_bus_insert_busn_res(child, max+1, 0xff);
Tiejun Chenb1a98b62011-06-02 11:02:50 +0800906 }
Andreas Noever9a4d7d82014-01-23 21:59:21 +0100907 max++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700908 buses = (buses & 0xff000000)
909 | ((unsigned int)(child->primary) << 0)
Yinghai Lub918c622012-05-17 18:51:11 -0700910 | ((unsigned int)(child->busn_res.start) << 8)
911 | ((unsigned int)(child->busn_res.end) << 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700912
913 /*
914 * yenta.c forces a secondary latency timer of 176.
915 * Copy that behaviour here.
916 */
917 if (is_cardbus) {
918 buses &= ~0xff000000;
919 buses |= CARDBUS_LATENCY_TIMER << 24;
920 }
Jesper Juhl7c867c82011-01-24 21:14:33 +0100921
Linus Torvalds1da177e2005-04-16 15:20:36 -0700922 /*
923 * We need to blast all three values with a single write.
924 */
925 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
926
927 if (!is_cardbus) {
Gary Hade11949252007-10-08 16:24:16 -0700928 child->bridge_ctl = bctl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700929 max = pci_scan_child_bus(child);
930 } else {
931 /*
932 * For CardBus bridges, we leave 4 bus numbers
933 * as cards with a PCI-to-PCI bridge can be
934 * inserted later.
935 */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400936 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
Dominik Brodowski49887942005-12-08 16:53:12 +0100937 struct pci_bus *parent = bus;
Rajesh Shahcc574502005-04-28 00:25:47 -0700938 if (pci_find_bus(pci_domain_nr(bus),
939 max+i+1))
940 break;
Dominik Brodowski49887942005-12-08 16:53:12 +0100941 while (parent->parent) {
942 if ((!pcibios_assign_all_busses()) &&
Yinghai Lub918c622012-05-17 18:51:11 -0700943 (parent->busn_res.end > max) &&
944 (parent->busn_res.end <= max+i)) {
Dominik Brodowski49887942005-12-08 16:53:12 +0100945 j = 1;
946 }
947 parent = parent->parent;
948 }
949 if (j) {
950 /*
951 * Often, there are two cardbus bridges
952 * -- try to leave one valid bus number
953 * for each one.
954 */
955 i /= 2;
956 break;
957 }
958 }
Rajesh Shahcc574502005-04-28 00:25:47 -0700959 max += i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700960 }
961 /*
962 * Set the subordinate bus number to its real value.
963 */
Yinghai Lubc76b732012-05-17 18:51:13 -0700964 pci_bus_update_busn_res_end(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700965 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
966 }
967
Gary Hadecb3576f2008-02-08 14:00:52 -0800968 sprintf(child->name,
969 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
970 pci_domain_nr(bus), child->number);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700971
Bernhard Kaindld55bef52007-07-30 20:35:13 +0200972 /* Has only triggered on CardBus, fixup is in yenta_socket */
Dominik Brodowski49887942005-12-08 16:53:12 +0100973 while (bus->parent) {
Yinghai Lub918c622012-05-17 18:51:11 -0700974 if ((child->busn_res.end > bus->busn_res.end) ||
975 (child->number > bus->busn_res.end) ||
Dominik Brodowski49887942005-12-08 16:53:12 +0100976 (child->number < bus->number) ||
Yinghai Lub918c622012-05-17 18:51:11 -0700977 (child->busn_res.end < bus->number)) {
Ryan Desfosses227f0642014-04-18 20:13:50 -0400978 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
Yinghai Lub918c622012-05-17 18:51:11 -0700979 &child->busn_res,
980 (bus->number > child->busn_res.end &&
981 bus->busn_res.end < child->number) ?
Joe Perchesa6f29a92007-11-19 17:48:29 -0800982 "wholly" : "partially",
983 bus->self->transparent ? " transparent" : "",
Bjorn Helgaas865df572009-11-04 10:32:57 -0700984 dev_name(&bus->dev),
Yinghai Lub918c622012-05-17 18:51:11 -0700985 &bus->busn_res);
Dominik Brodowski49887942005-12-08 16:53:12 +0100986 }
987 bus = bus->parent;
988 }
989
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000990out:
991 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
992
Linus Torvalds1da177e2005-04-16 15:20:36 -0700993 return max;
994}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -0600995EXPORT_SYMBOL(pci_scan_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700996
997/*
998 * Read interrupt line and base address registers.
999 * The architecture-dependent code can tweak these, of course.
1000 */
1001static void pci_read_irq(struct pci_dev *dev)
1002{
1003 unsigned char irq;
1004
1005 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
Kristen Accardiffeff782005-11-02 16:24:32 -08001006 dev->pin = irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001007 if (irq)
1008 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1009 dev->irq = irq;
1010}
1011
Benjamin Herrenschmidtbb209c82010-01-26 17:10:03 +00001012void set_pcie_port_type(struct pci_dev *pdev)
Yu Zhao480b93b2009-03-20 11:25:14 +08001013{
1014 int pos;
1015 u16 reg16;
Yijing Wangd0751b92015-05-21 15:05:02 +08001016 int type;
1017 struct pci_dev *parent;
Yu Zhao480b93b2009-03-20 11:25:14 +08001018
1019 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1020 if (!pos)
1021 return;
Kenji Kaneshige0efea002009-11-05 12:05:11 +09001022 pdev->pcie_cap = pos;
Yu Zhao480b93b2009-03-20 11:25:14 +08001023 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
Yijing Wang786e2282012-07-24 17:20:02 +08001024 pdev->pcie_flags_reg = reg16;
Jon Masonb03e7492011-07-20 15:20:54 -05001025 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
1026 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
Yijing Wangd0751b92015-05-21 15:05:02 +08001027
1028 /*
1029 * A Root Port is always the upstream end of a Link. No PCIe
1030 * component has two Links. Two Links are connected by a Switch
1031 * that has a Port on each Link and internal logic to connect the
1032 * two Ports.
1033 */
1034 type = pci_pcie_type(pdev);
1035 if (type == PCI_EXP_TYPE_ROOT_PORT)
1036 pdev->has_secondary_link = 1;
1037 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1038 type == PCI_EXP_TYPE_DOWNSTREAM) {
1039 parent = pci_upstream_bridge(pdev);
Yijing Wangb35b1df2015-08-17 18:47:58 +08001040
1041 /*
1042 * Usually there's an upstream device (Root Port or Switch
1043 * Downstream Port), but we can't assume one exists.
1044 */
1045 if (parent && !parent->has_secondary_link)
Yijing Wangd0751b92015-05-21 15:05:02 +08001046 pdev->has_secondary_link = 1;
1047 }
Yu Zhao480b93b2009-03-20 11:25:14 +08001048}
1049
Benjamin Herrenschmidtbb209c82010-01-26 17:10:03 +00001050void set_pcie_hotplug_bridge(struct pci_dev *pdev)
Eric W. Biederman28760482009-09-09 14:09:24 -07001051{
Eric W. Biederman28760482009-09-09 14:09:24 -07001052 u32 reg32;
1053
Jiang Liu59875ae2012-07-24 17:20:06 +08001054 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32);
Eric W. Biederman28760482009-09-09 14:09:24 -07001055 if (reg32 & PCI_EXP_SLTCAP_HPC)
1056 pdev->is_hotplug_bridge = 1;
1057}
1058
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001059/**
Alex Williamson78916b02014-05-05 14:20:51 -06001060 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1061 * @dev: PCI device
1062 *
1063 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1064 * when forwarding a type1 configuration request the bridge must check that
1065 * the extended register address field is zero. The bridge is not permitted
1066 * to forward the transactions and must handle it as an Unsupported Request.
1067 * Some bridges do not follow this rule and simply drop the extended register
1068 * bits, resulting in the standard config space being aliased, every 256
1069 * bytes across the entire configuration space. Test for this condition by
1070 * comparing the first dword of each potential alias to the vendor/device ID.
1071 * Known offenders:
1072 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1073 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1074 */
1075static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1076{
1077#ifdef CONFIG_PCI_QUIRKS
1078 int pos;
1079 u32 header, tmp;
1080
1081 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1082
1083 for (pos = PCI_CFG_SPACE_SIZE;
1084 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1085 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1086 || header != tmp)
1087 return false;
1088 }
1089
1090 return true;
1091#else
1092 return false;
1093#endif
1094}
1095
1096/**
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001097 * pci_cfg_space_size - get the configuration space size of the PCI device.
1098 * @dev: PCI device
1099 *
1100 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1101 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1102 * access it. Maybe we don't have a way to generate extended config space
1103 * accesses, or the device is behind a reverse Express bridge. So we try
1104 * reading the dword at 0x100 which must either be 0 or a valid extended
1105 * capability header.
1106 */
1107static int pci_cfg_space_size_ext(struct pci_dev *dev)
1108{
1109 u32 status;
1110 int pos = PCI_CFG_SPACE_SIZE;
1111
1112 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1113 goto fail;
Alex Williamson78916b02014-05-05 14:20:51 -06001114 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001115 goto fail;
1116
1117 return PCI_CFG_SPACE_EXP_SIZE;
1118
1119 fail:
1120 return PCI_CFG_SPACE_SIZE;
1121}
1122
1123int pci_cfg_space_size(struct pci_dev *dev)
1124{
1125 int pos;
1126 u32 status;
1127 u16 class;
1128
1129 class = dev->class >> 8;
1130 if (class == PCI_CLASS_BRIDGE_HOST)
1131 return pci_cfg_space_size_ext(dev);
1132
1133 if (!pci_is_pcie(dev)) {
1134 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1135 if (!pos)
1136 goto fail;
1137
1138 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1139 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1140 goto fail;
1141 }
1142
1143 return pci_cfg_space_size_ext(dev);
1144
1145 fail:
1146 return PCI_CFG_SPACE_SIZE;
1147}
1148
Bartlomiej Zolnierkiewicz01abc2a2007-04-23 23:19:36 +02001149#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
Randy Dunlap76e6a1d2006-12-29 16:47:29 -08001150
Guilherme G. Piccoli22b68392015-08-24 22:42:46 +10001151void pci_msi_setup_pci_dev(struct pci_dev *dev)
Michael S. Tsirkin18516172015-05-07 09:52:21 -05001152{
1153 /*
1154 * Disable the MSI hardware to avoid screaming interrupts
1155 * during boot. This is the power on reset default so
1156 * usually this should be a noop.
1157 */
1158 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1159 if (dev->msi_cap)
1160 pci_msi_set_enable(dev, 0);
1161
1162 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1163 if (dev->msix_cap)
1164 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1165}
1166
Linus Torvalds1da177e2005-04-16 15:20:36 -07001167/**
1168 * pci_setup_device - fill in class and map information of a device
1169 * @dev: the device structure to fill
1170 *
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001171 * Initialize the device structure with information about the device's
Linus Torvalds1da177e2005-04-16 15:20:36 -07001172 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1173 * Called at initialisation of the PCI subsystem and by CardBus services.
Yu Zhao480b93b2009-03-20 11:25:14 +08001174 * Returns 0 on success and negative if unknown type of device (not normal,
1175 * bridge or CardBus).
Linus Torvalds1da177e2005-04-16 15:20:36 -07001176 */
Yu Zhao480b93b2009-03-20 11:25:14 +08001177int pci_setup_device(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001178{
1179 u32 class;
Bjorn Helgaas8cbac3c2016-02-25 14:35:57 -06001180 u16 cmd;
Yu Zhao480b93b2009-03-20 11:25:14 +08001181 u8 hdr_type;
Gabe Blackbc577d22009-10-06 10:45:19 -05001182 int pos = 0;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001183 struct pci_bus_region region;
1184 struct resource *res;
Yu Zhao480b93b2009-03-20 11:25:14 +08001185
1186 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1187 return -EIO;
1188
1189 dev->sysdata = dev->bus->sysdata;
1190 dev->dev.parent = dev->bus->bridge;
1191 dev->dev.bus = &pci_bus_type;
1192 dev->hdr_type = hdr_type & 0x7f;
1193 dev->multifunction = !!(hdr_type & 0x80);
Yu Zhao480b93b2009-03-20 11:25:14 +08001194 dev->error_state = pci_channel_io_normal;
1195 set_pcie_port_type(dev);
1196
Yijing Wang017ffe62015-07-17 17:16:32 +08001197 pci_dev_assign_slot(dev);
Yu Zhao480b93b2009-03-20 11:25:14 +08001198 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1199 set this higher, assuming the system even supports it. */
1200 dev->dma_mask = 0xffffffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001201
Greg Kroah-Hartmaneebfcfb2008-07-02 13:24:49 -07001202 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1203 dev->bus->number, PCI_SLOT(dev->devfn),
1204 PCI_FUNC(dev->devfn));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001205
1206 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
Auke Kokb8a3a522007-06-08 15:46:30 -07001207 dev->revision = class & 0xff;
Yinghai Lu2dd8ba92012-02-19 14:50:12 -08001208 dev->class = class >> 8; /* upper 3 bytes */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001209
Yinghai Lu2dd8ba92012-02-19 14:50:12 -08001210 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1211 dev->vendor, dev->device, dev->hdr_type, dev->class);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001212
Yu Zhao853346e2009-03-21 22:05:11 +08001213 /* need to have dev->class ready */
1214 dev->cfg_size = pci_cfg_space_size(dev);
1215
Linus Torvalds1da177e2005-04-16 15:20:36 -07001216 /* "Unknown power state" */
Daniel Ritz3fe9d192005-08-17 15:32:19 -07001217 dev->current_state = PCI_UNKNOWN;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001218
Michael S. Tsirkin18516172015-05-07 09:52:21 -05001219 pci_msi_setup_pci_dev(dev);
1220
Linus Torvalds1da177e2005-04-16 15:20:36 -07001221 /* Early fixups, before probing the BARs */
1222 pci_fixup_device(pci_fixup_early, dev);
Yu Zhaof79b1b12009-05-28 00:25:05 +08001223 /* device class may be changed after fixup */
1224 class = dev->class >> 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001225
Bjorn Helgaas8cbac3c2016-02-25 14:35:57 -06001226 if (dev->non_compliant_bars) {
1227 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1228 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1229 dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1230 cmd &= ~PCI_COMMAND_IO;
1231 cmd &= ~PCI_COMMAND_MEMORY;
1232 pci_write_config_word(dev, PCI_COMMAND, cmd);
1233 }
1234 }
1235
Linus Torvalds1da177e2005-04-16 15:20:36 -07001236 switch (dev->hdr_type) { /* header type */
1237 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1238 if (class == PCI_CLASS_BRIDGE_PCI)
1239 goto bad;
1240 pci_read_irq(dev);
1241 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1242 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1243 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
Alan Cox368c73d2006-10-04 00:41:26 +01001244
1245 /*
Bjorn Helgaas075eb9e2014-03-05 14:07:03 -07001246 * Do the ugly legacy mode stuff here rather than broken chip
1247 * quirk code. Legacy mode ATA controllers have fixed
1248 * addresses. These are not always echoed in BAR0-3, and
1249 * BAR0-3 in a few cases contain junk!
Alan Cox368c73d2006-10-04 00:41:26 +01001250 */
1251 if (class == PCI_CLASS_STORAGE_IDE) {
1252 u8 progif;
1253 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1254 if ((progif & 1) == 0) {
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001255 region.start = 0x1F0;
1256 region.end = 0x1F7;
1257 res = &dev->resource[0];
1258 res->flags = LEGACY_IO_RESOURCE;
Yinghai Lufc279852013-12-09 22:54:40 -08001259 pcibios_bus_to_resource(dev->bus, res, &region);
Bjorn Helgaas075eb9e2014-03-05 14:07:03 -07001260 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1261 res);
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001262 region.start = 0x3F6;
1263 region.end = 0x3F6;
1264 res = &dev->resource[1];
1265 res->flags = LEGACY_IO_RESOURCE;
Yinghai Lufc279852013-12-09 22:54:40 -08001266 pcibios_bus_to_resource(dev->bus, res, &region);
Bjorn Helgaas075eb9e2014-03-05 14:07:03 -07001267 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1268 res);
Alan Cox368c73d2006-10-04 00:41:26 +01001269 }
1270 if ((progif & 4) == 0) {
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001271 region.start = 0x170;
1272 region.end = 0x177;
1273 res = &dev->resource[2];
1274 res->flags = LEGACY_IO_RESOURCE;
Yinghai Lufc279852013-12-09 22:54:40 -08001275 pcibios_bus_to_resource(dev->bus, res, &region);
Bjorn Helgaas075eb9e2014-03-05 14:07:03 -07001276 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1277 res);
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001278 region.start = 0x376;
1279 region.end = 0x376;
1280 res = &dev->resource[3];
1281 res->flags = LEGACY_IO_RESOURCE;
Yinghai Lufc279852013-12-09 22:54:40 -08001282 pcibios_bus_to_resource(dev->bus, res, &region);
Bjorn Helgaas075eb9e2014-03-05 14:07:03 -07001283 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1284 res);
Alan Cox368c73d2006-10-04 00:41:26 +01001285 }
1286 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001287 break;
1288
1289 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1290 if (class != PCI_CLASS_BRIDGE_PCI)
1291 goto bad;
1292 /* The PCI-to-PCI bridge spec requires that subtractive
1293 decoding (i.e. transparent) bridge must have programming
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001294 interface code of 0x01. */
Kristen Accardi3efd2732005-11-02 16:55:49 -08001295 pci_read_irq(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001296 dev->transparent = ((dev->class & 0xff) == 1);
1297 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
Eric W. Biederman28760482009-09-09 14:09:24 -07001298 set_pcie_hotplug_bridge(dev);
Gabe Blackbc577d22009-10-06 10:45:19 -05001299 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1300 if (pos) {
1301 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1302 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1303 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001304 break;
1305
1306 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1307 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1308 goto bad;
1309 pci_read_irq(dev);
1310 pci_read_bases(dev, 1, 0);
1311 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1312 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1313 break;
1314
1315 default: /* unknown header */
Ryan Desfosses227f0642014-04-18 20:13:50 -04001316 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1317 dev->hdr_type);
Yu Zhao480b93b2009-03-20 11:25:14 +08001318 return -EIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001319
1320 bad:
Ryan Desfosses227f0642014-04-18 20:13:50 -04001321 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1322 dev->class, dev->hdr_type);
Bjorn Helgaas2b4aed12015-06-19 16:20:58 -05001323 dev->class = PCI_CLASS_NOT_DEFINED << 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001324 }
1325
1326 /* We found a fine healthy device, go go go... */
1327 return 0;
1328}
1329
Bjorn Helgaas9dae3a92015-08-20 16:08:27 -05001330static void pci_configure_mps(struct pci_dev *dev)
1331{
1332 struct pci_dev *bridge = pci_upstream_bridge(dev);
Keith Busch27d868b2015-08-24 08:48:16 -05001333 int mps, p_mps, rc;
Bjorn Helgaas9dae3a92015-08-20 16:08:27 -05001334
1335 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1336 return;
1337
1338 mps = pcie_get_mps(dev);
1339 p_mps = pcie_get_mps(bridge);
1340
1341 if (mps == p_mps)
1342 return;
1343
1344 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1345 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1346 mps, pci_name(bridge), p_mps);
1347 return;
1348 }
Keith Busch27d868b2015-08-24 08:48:16 -05001349
1350 /*
1351 * Fancier MPS configuration is done later by
1352 * pcie_bus_configure_settings()
1353 */
1354 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1355 return;
1356
1357 rc = pcie_set_mps(dev, p_mps);
1358 if (rc) {
1359 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1360 p_mps);
1361 return;
1362 }
1363
1364 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
1365 p_mps, mps, 128 << dev->pcie_mpss);
Bjorn Helgaas9dae3a92015-08-20 16:08:27 -05001366}
1367
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001368static struct hpp_type0 pci_default_type0 = {
1369 .revision = 1,
1370 .cache_line_size = 8,
1371 .latency_timer = 0x40,
1372 .enable_serr = 0,
1373 .enable_perr = 0,
1374};
1375
1376static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1377{
1378 u16 pci_cmd, pci_bctl;
1379
Bjorn Helgaasc6285fc2014-08-29 18:10:19 -06001380 if (!hpp)
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001381 hpp = &pci_default_type0;
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001382
1383 if (hpp->revision > 1) {
1384 dev_warn(&dev->dev,
1385 "PCI settings rev %d not supported; using defaults\n",
1386 hpp->revision);
1387 hpp = &pci_default_type0;
1388 }
1389
1390 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1391 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1392 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1393 if (hpp->enable_serr)
1394 pci_cmd |= PCI_COMMAND_SERR;
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001395 if (hpp->enable_perr)
1396 pci_cmd |= PCI_COMMAND_PARITY;
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001397 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1398
1399 /* Program bridge control value */
1400 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1401 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1402 hpp->latency_timer);
1403 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1404 if (hpp->enable_serr)
1405 pci_bctl |= PCI_BRIDGE_CTL_SERR;
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001406 if (hpp->enable_perr)
1407 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001408 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1409 }
1410}
1411
1412static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1413{
1414 if (hpp)
1415 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1416}
1417
Johannes Thumshirnac6e42d2016-11-23 10:56:28 -06001418static bool pcie_root_rcb_set(struct pci_dev *dev)
1419{
1420 struct pci_dev *rp = pcie_find_root_port(dev);
1421 u16 lnkctl;
1422
1423 if (!rp)
1424 return false;
1425
1426 pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
1427 if (lnkctl & PCI_EXP_LNKCTL_RCB)
1428 return true;
1429
1430 return false;
1431}
1432
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001433static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1434{
1435 int pos;
1436 u32 reg32;
1437
1438 if (!hpp)
1439 return;
1440
1441 if (hpp->revision > 1) {
1442 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1443 hpp->revision);
1444 return;
1445 }
1446
Bjorn Helgaas302328c2014-09-03 13:26:29 -06001447 /*
1448 * Don't allow _HPX to change MPS or MRRS settings. We manage
1449 * those to make sure they're consistent with the rest of the
1450 * platform.
1451 */
1452 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1453 PCI_EXP_DEVCTL_READRQ;
1454 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1455 PCI_EXP_DEVCTL_READRQ);
1456
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001457 /* Initialize Device Control Register */
1458 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1459 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1460
1461 /* Initialize Link Control Register */
Johannes Thumshirnac6e42d2016-11-23 10:56:28 -06001462 if (pcie_cap_has_lnkctl(dev)) {
1463
1464 /*
1465 * If the Root Port supports Read Completion Boundary of
1466 * 128, set RCB to 128. Otherwise, clear it.
1467 */
1468 hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
1469 hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
1470 if (pcie_root_rcb_set(dev))
1471 hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
1472
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001473 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1474 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
Johannes Thumshirnac6e42d2016-11-23 10:56:28 -06001475 }
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001476
1477 /* Find Advanced Error Reporting Enhanced Capability */
1478 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1479 if (!pos)
1480 return;
1481
1482 /* Initialize Uncorrectable Error Mask Register */
1483 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32);
1484 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1485 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1486
1487 /* Initialize Uncorrectable Error Severity Register */
1488 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32);
1489 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1490 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1491
1492 /* Initialize Correctable Error Mask Register */
1493 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32);
1494 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1495 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1496
1497 /* Initialize Advanced Error Capabilities and Control Register */
1498 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
1499 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1500 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1501
1502 /*
1503 * FIXME: The following two registers are not supported yet.
1504 *
1505 * o Secondary Uncorrectable Error Severity Register
1506 * o Secondary Uncorrectable Error Mask Register
1507 */
1508}
1509
Bjorn Helgaas6cd33642014-08-27 14:29:47 -06001510static void pci_configure_device(struct pci_dev *dev)
1511{
1512 struct hotplug_params hpp;
1513 int ret;
1514
Bjorn Helgaas9dae3a92015-08-20 16:08:27 -05001515 pci_configure_mps(dev);
1516
Bjorn Helgaas6cd33642014-08-27 14:29:47 -06001517 memset(&hpp, 0, sizeof(hpp));
1518 ret = pci_get_hp_params(dev, &hpp);
1519 if (ret)
1520 return;
1521
1522 program_hpp_type2(dev, hpp.t2);
1523 program_hpp_type1(dev, hpp.t1);
1524 program_hpp_type0(dev, hpp.t0);
1525}
1526
Zhao, Yu201de562008-10-13 19:49:55 +08001527static void pci_release_capabilities(struct pci_dev *dev)
1528{
1529 pci_vpd_release(dev);
Yu Zhaod1b054d2009-03-20 11:25:11 +08001530 pci_iov_release(dev);
Yinghai Luf7968412012-02-11 00:18:30 -08001531 pci_free_cap_save_buffers(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001532}
1533
Linus Torvalds1da177e2005-04-16 15:20:36 -07001534/**
1535 * pci_release_dev - free a pci device structure when all users of it are finished.
1536 * @dev: device that's been disconnected
1537 *
1538 * Will be called only by the device core when all users of this pci device are
1539 * done.
1540 */
1541static void pci_release_dev(struct device *dev)
1542{
Rafael J. Wysocki04480092014-02-01 15:38:29 +01001543 struct pci_dev *pci_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001544
Rafael J. Wysocki04480092014-02-01 15:38:29 +01001545 pci_dev = to_pci_dev(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001546 pci_release_capabilities(pci_dev);
Benjamin Herrenschmidt98d9f302011-04-11 11:37:07 +10001547 pci_release_of_node(pci_dev);
Sebastian Ott6ae32c52013-06-04 19:18:14 +02001548 pcibios_release_device(pci_dev);
Gu Zheng8b1fce02013-05-25 21:48:31 +08001549 pci_bus_put(pci_dev->bus);
Alex Williamson782a9852014-05-20 08:53:21 -06001550 kfree(pci_dev->driver_override);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001551 kfree(pci_dev);
1552}
1553
Gu Zheng3c6e6ae2013-05-25 21:48:30 +08001554struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
Michael Ellerman65891212007-04-05 17:19:08 +10001555{
1556 struct pci_dev *dev;
1557
1558 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1559 if (!dev)
1560 return NULL;
1561
Michael Ellerman65891212007-04-05 17:19:08 +10001562 INIT_LIST_HEAD(&dev->bus_list);
Brian King88e7b162013-04-08 03:05:07 +00001563 dev->dev.type = &pci_dev_type;
Gu Zheng3c6e6ae2013-05-25 21:48:30 +08001564 dev->bus = pci_bus_get(bus);
Michael Ellerman65891212007-04-05 17:19:08 +10001565
1566 return dev;
1567}
Gu Zheng3c6e6ae2013-05-25 21:48:30 +08001568EXPORT_SYMBOL(pci_alloc_dev);
1569
Yinghai Luefdc87d2012-01-27 10:55:10 -08001570bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001571 int crs_timeout)
Yinghai Luefdc87d2012-01-27 10:55:10 -08001572{
1573 int delay = 1;
1574
1575 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1576 return false;
1577
1578 /* some broken boards return 0 or ~0 if a slot is empty: */
1579 if (*l == 0xffffffff || *l == 0x00000000 ||
1580 *l == 0x0000ffff || *l == 0xffff0000)
1581 return false;
1582
Rajat Jain89665a62014-09-08 14:19:49 -07001583 /*
1584 * Configuration Request Retry Status. Some root ports return the
1585 * actual device ID instead of the synthetic ID (0xFFFF) required
1586 * by the PCIe spec. Ignore the device ID and only check for
1587 * (vendor id == 1).
1588 */
1589 while ((*l & 0xffff) == 0x0001) {
Yinghai Luefdc87d2012-01-27 10:55:10 -08001590 if (!crs_timeout)
1591 return false;
1592
1593 msleep(delay);
1594 delay *= 2;
1595 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1596 return false;
1597 /* Card hasn't responded in 60 seconds? Must be stuck. */
1598 if (delay > crs_timeout) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04001599 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1600 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1601 PCI_FUNC(devfn));
Yinghai Luefdc87d2012-01-27 10:55:10 -08001602 return false;
1603 }
1604 }
1605
1606 return true;
1607}
1608EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1609
Linus Torvalds1da177e2005-04-16 15:20:36 -07001610/*
1611 * Read the config data for a PCI device, sanity-check it
1612 * and fill in the dev structure...
1613 */
Adrian Bunk7f7b5de2008-04-18 13:53:55 -07001614static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001615{
1616 struct pci_dev *dev;
1617 u32 l;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001618
Yinghai Luefdc87d2012-01-27 10:55:10 -08001619 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001620 return NULL;
1621
Gu Zheng8b1fce02013-05-25 21:48:31 +08001622 dev = pci_alloc_dev(bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001623 if (!dev)
1624 return NULL;
1625
Linus Torvalds1da177e2005-04-16 15:20:36 -07001626 dev->devfn = devfn;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001627 dev->vendor = l & 0xffff;
1628 dev->device = (l >> 16) & 0xffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001629
Benjamin Herrenschmidt98d9f302011-04-11 11:37:07 +10001630 pci_set_of_node(dev);
1631
Yu Zhao480b93b2009-03-20 11:25:14 +08001632 if (pci_setup_device(dev)) {
Gu Zheng8b1fce02013-05-25 21:48:31 +08001633 pci_bus_put(dev->bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001634 kfree(dev);
1635 return NULL;
1636 }
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001637
1638 return dev;
1639}
1640
Zhao, Yu201de562008-10-13 19:49:55 +08001641static void pci_init_capabilities(struct pci_dev *dev)
1642{
Sean O. Stalley938174e2015-10-29 17:35:39 -05001643 /* Enhanced Allocation */
1644 pci_ea_init(dev);
1645
Zhao, Yu201de562008-10-13 19:49:55 +08001646 /* MSI/MSI-X list */
1647 pci_msi_init_pci_dev(dev);
1648
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01001649 /* Buffers for saving PCIe and PCI-X capabilities */
1650 pci_allocate_cap_save_buffers(dev);
1651
Zhao, Yu201de562008-10-13 19:49:55 +08001652 /* Power Management */
1653 pci_pm_init(dev);
1654
1655 /* Vital Product Data */
1656 pci_vpd_pci22_init(dev);
Yu Zhao58c3a722008-10-14 14:02:53 +08001657
1658 /* Alternative Routing-ID Forwarding */
Yijing Wang31ab2472013-01-15 11:12:17 +08001659 pci_configure_ari(dev);
Yu Zhaod1b054d2009-03-20 11:25:11 +08001660
1661 /* Single Root I/O Virtualization */
1662 pci_iov_init(dev);
Allen Kayae21ee62009-10-07 10:27:17 -07001663
Bjorn Helgaasedc90fe2015-07-17 15:05:46 -05001664 /* Address Translation Services */
1665 pci_ats_init(dev);
1666
Allen Kayae21ee62009-10-07 10:27:17 -07001667 /* Enable ACS P2P upstream forwarding */
Chris Wright5d990b62009-12-04 12:15:21 -08001668 pci_enable_acs(dev);
Taku Izumib07461a2015-09-17 10:09:37 -05001669
1670 pci_cleanup_aer_error_status_regs(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001671}
1672
Marc Zyngier098259e2015-10-02 10:19:32 +01001673/*
1674 * This is the equivalent of pci_host_bridge_msi_domain that acts on
1675 * devices. Firmware interfaces that can select the MSI domain on a
1676 * per-device basis should be called from here.
1677 */
1678static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
1679{
1680 struct irq_domain *d;
1681
1682 /*
1683 * If a domain has been set through the pcibios_add_device
1684 * callback, then this is the one (platform code knows best).
1685 */
1686 d = dev_get_msi_domain(&dev->dev);
1687 if (d)
1688 return d;
1689
Marc Zyngier54fa97e2015-10-02 14:43:06 +01001690 /*
1691 * Let's see if we have a firmware interface able to provide
1692 * the domain.
1693 */
1694 d = pci_msi_get_device_domain(dev);
1695 if (d)
1696 return d;
1697
Marc Zyngier098259e2015-10-02 10:19:32 +01001698 return NULL;
1699}
1700
Marc Zyngier44aa0c62015-07-28 14:46:11 +01001701static void pci_set_msi_domain(struct pci_dev *dev)
1702{
Marc Zyngier098259e2015-10-02 10:19:32 +01001703 struct irq_domain *d;
1704
Marc Zyngier44aa0c62015-07-28 14:46:11 +01001705 /*
Marc Zyngier098259e2015-10-02 10:19:32 +01001706 * If the platform or firmware interfaces cannot supply a
1707 * device-specific MSI domain, then inherit the default domain
1708 * from the host bridge itself.
Marc Zyngier44aa0c62015-07-28 14:46:11 +01001709 */
Marc Zyngier098259e2015-10-02 10:19:32 +01001710 d = pci_dev_msi_domain(dev);
1711 if (!d)
1712 d = dev_get_msi_domain(&dev->bus->dev);
1713
1714 dev_set_msi_domain(&dev->dev, d);
Marc Zyngier44aa0c62015-07-28 14:46:11 +01001715}
1716
Suthikulpanit, Suravee50230712015-10-28 15:50:53 -07001717/**
1718 * pci_dma_configure - Setup DMA configuration
1719 * @dev: ptr to pci_dev struct of the PCI device
1720 *
1721 * Function to update PCI devices's DMA configuration using the same
Suthikulpanit, Suravee29dbe1f2015-10-28 15:50:54 -07001722 * info from the OF node or ACPI node of host bridge's parent (if any).
Suthikulpanit, Suravee50230712015-10-28 15:50:53 -07001723 */
1724static void pci_dma_configure(struct pci_dev *dev)
1725{
1726 struct device *bridge = pci_get_host_bridge_device(dev);
1727
Suravee Suthikulpanit768acd62015-11-18 16:49:52 -08001728 if (IS_ENABLED(CONFIG_OF) &&
1729 bridge->parent && bridge->parent->of_node) {
Suthikulpanit, Suravee50230712015-10-28 15:50:53 -07001730 of_dma_configure(&dev->dev, bridge->parent->of_node);
Suthikulpanit, Suravee29dbe1f2015-10-28 15:50:54 -07001731 } else if (has_acpi_companion(bridge)) {
1732 struct acpi_device *adev = to_acpi_device_node(bridge->fwnode);
1733 enum dev_dma_attr attr = acpi_get_dma_attr(adev);
1734
1735 if (attr == DEV_DMA_NOT_SUPPORTED)
1736 dev_warn(&dev->dev, "DMA not supported.\n");
1737 else
1738 arch_setup_dma_ops(&dev->dev, 0, 0, NULL,
1739 attr == DEV_DMA_COHERENT);
Suthikulpanit, Suravee50230712015-10-28 15:50:53 -07001740 }
1741
1742 pci_put_host_bridge_device(bridge);
1743}
1744
Sam Ravnborg96bde062007-03-26 21:53:30 -08001745void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001746{
Yinghai Lu4f535092013-01-21 13:20:52 -08001747 int ret;
1748
Bjorn Helgaas6cd33642014-08-27 14:29:47 -06001749 pci_configure_device(dev);
1750
Linus Torvalds1da177e2005-04-16 15:20:36 -07001751 device_initialize(&dev->dev);
1752 dev->dev.release = pci_release_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001753
Yinghai Lu7629d192013-01-21 13:20:44 -08001754 set_dev_node(&dev->dev, pcibus_to_node(bus));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001755 dev->dev.dma_mask = &dev->dma_mask;
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001756 dev->dev.dma_parms = &dev->dma_parms;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001757 dev->dev.coherent_dma_mask = 0xffffffffull;
Suthikulpanit, Suravee50230712015-10-28 15:50:53 -07001758 pci_dma_configure(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001759
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001760 pci_set_dma_max_seg_size(dev, 65536);
FUJITA Tomonori59fc67d2008-02-04 22:28:14 -08001761 pci_set_dma_seg_boundary(dev, 0xffffffff);
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001762
Linus Torvalds1da177e2005-04-16 15:20:36 -07001763 /* Fix up broken headers */
1764 pci_fixup_device(pci_fixup_header, dev);
1765
Yinghai Lu2069ecf2012-02-15 21:40:31 -08001766 /* moved out from quirk header fixup code */
1767 pci_reassigndev_resource_alignment(dev);
1768
Rafael J. Wysocki4b77b0a2009-09-09 23:49:59 +02001769 /* Clear the state_saved flag. */
1770 dev->state_saved = false;
1771
Zhao, Yu201de562008-10-13 19:49:55 +08001772 /* Initialize various capabilities */
1773 pci_init_capabilities(dev);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001774
Linus Torvalds1da177e2005-04-16 15:20:36 -07001775 /*
1776 * Add the device to our list of discovered devices
1777 * and the bus list for fixup functions, etc.
1778 */
Zhang Yanmind71374d2006-06-02 12:35:43 +08001779 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001780 list_add_tail(&dev->bus_list, &bus->devices);
Zhang Yanmind71374d2006-06-02 12:35:43 +08001781 up_write(&pci_bus_sem);
Yinghai Lu4f535092013-01-21 13:20:52 -08001782
Yinghai Lu4f535092013-01-21 13:20:52 -08001783 ret = pcibios_add_device(dev);
1784 WARN_ON(ret < 0);
1785
Marc Zyngier44aa0c62015-07-28 14:46:11 +01001786 /* Setup MSI irq domain */
1787 pci_set_msi_domain(dev);
1788
Yinghai Lu4f535092013-01-21 13:20:52 -08001789 /* Notifier could use PCI capabilities */
1790 dev->match_driver = false;
1791 ret = device_add(&dev->dev);
1792 WARN_ON(ret < 0);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001793}
1794
Bjorn Helgaas10874f52014-04-14 16:11:40 -06001795struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001796{
1797 struct pci_dev *dev;
1798
Trent Piepho90bdb312009-03-20 14:56:00 -06001799 dev = pci_get_slot(bus, devfn);
1800 if (dev) {
1801 pci_dev_put(dev);
1802 return dev;
1803 }
1804
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001805 dev = pci_scan_device(bus, devfn);
1806 if (!dev)
1807 return NULL;
1808
1809 pci_device_add(dev, bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001810
1811 return dev;
1812}
Adrian Bunkb73e9682007-11-21 15:07:11 -08001813EXPORT_SYMBOL(pci_scan_single_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001814
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001815static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001816{
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001817 int pos;
1818 u16 cap = 0;
1819 unsigned next_fn;
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07001820
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001821 if (pci_ari_enabled(bus)) {
1822 if (!dev)
1823 return 0;
1824 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1825 if (!pos)
1826 return 0;
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07001827
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001828 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1829 next_fn = PCI_ARI_CAP_NFN(cap);
1830 if (next_fn <= fn)
1831 return 0; /* protect against malformed list */
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001832
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001833 return next_fn;
1834 }
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001835
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001836 /* dev may be NULL for non-contiguous multifunction devices */
1837 if (!dev || dev->multifunction)
1838 return (fn + 1) % 8;
1839
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001840 return 0;
1841}
1842
1843static int only_one_child(struct pci_bus *bus)
1844{
1845 struct pci_dev *parent = bus->self;
Bjorn Helgaas284f5f92012-04-30 15:21:02 -06001846
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001847 if (!parent || !pci_is_pcie(parent))
1848 return 0;
Yijing Wang62f87c02012-07-24 17:20:03 +08001849 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
Bjorn Helgaas284f5f92012-04-30 15:21:02 -06001850 return 1;
Yijing Wang777e61e2015-05-21 15:05:04 +08001851 if (parent->has_secondary_link &&
Bjorn Helgaas284f5f92012-04-30 15:21:02 -06001852 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001853 return 1;
1854 return 0;
1855}
1856
Linus Torvalds1da177e2005-04-16 15:20:36 -07001857/**
1858 * pci_scan_slot - scan a PCI slot on a bus for devices.
1859 * @bus: PCI bus to scan
1860 * @devfn: slot number to scan (must have zero function.)
1861 *
1862 * Scan a PCI slot on the specified PCI bus for devices, adding
1863 * discovered devices to the @bus->devices list. New devices
Greg Kroah-Hartman8a1bc902008-02-14 14:56:56 -08001864 * will not have is_added set.
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001865 *
1866 * Returns the number of new devices found.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001867 */
Sam Ravnborg96bde062007-03-26 21:53:30 -08001868int pci_scan_slot(struct pci_bus *bus, int devfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001869{
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001870 unsigned fn, nr = 0;
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001871 struct pci_dev *dev;
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001872
1873 if (only_one_child(bus) && (devfn > 0))
1874 return 0; /* Already scanned the entire slot */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001875
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001876 dev = pci_scan_single_device(bus, devfn);
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07001877 if (!dev)
1878 return 0;
1879 if (!dev->is_added)
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001880 nr++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001881
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001882 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001883 dev = pci_scan_single_device(bus, devfn + fn);
1884 if (dev) {
1885 if (!dev->is_added)
1886 nr++;
1887 dev->multifunction = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001888 }
1889 }
Shaohua Li7d715a62008-02-25 09:46:41 +08001890
Shaohua Li149e1632008-07-23 10:32:31 +08001891 /* only one slot has pcie device */
1892 if (bus->self && nr)
Shaohua Li7d715a62008-02-25 09:46:41 +08001893 pcie_aspm_init_link_state(bus->self);
1894
Linus Torvalds1da177e2005-04-16 15:20:36 -07001895 return nr;
1896}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06001897EXPORT_SYMBOL(pci_scan_slot);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001898
Jon Masonb03e7492011-07-20 15:20:54 -05001899static int pcie_find_smpss(struct pci_dev *dev, void *data)
1900{
1901 u8 *smpss = data;
1902
1903 if (!pci_is_pcie(dev))
1904 return 0;
1905
Yijing Wangd4aa68f2013-08-22 11:24:47 +08001906 /*
1907 * We don't have a way to change MPS settings on devices that have
1908 * drivers attached. A hot-added device might support only the minimum
1909 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1910 * where devices may be hot-added, we limit the fabric MPS to 128 so
1911 * hot-added devices will work correctly.
1912 *
1913 * However, if we hot-add a device to a slot directly below a Root
1914 * Port, it's impossible for there to be other existing devices below
1915 * the port. We don't limit the MPS in this case because we can
1916 * reconfigure MPS on both the Root Port and the hot-added device,
1917 * and there are no other devices involved.
1918 *
1919 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
Jon Masonb03e7492011-07-20 15:20:54 -05001920 */
Yijing Wangd4aa68f2013-08-22 11:24:47 +08001921 if (dev->is_hotplug_bridge &&
1922 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
Jon Masonb03e7492011-07-20 15:20:54 -05001923 *smpss = 0;
1924
1925 if (*smpss > dev->pcie_mpss)
1926 *smpss = dev->pcie_mpss;
1927
1928 return 0;
1929}
1930
1931static void pcie_write_mps(struct pci_dev *dev, int mps)
1932{
Jon Mason62f392e2011-10-14 14:56:14 -05001933 int rc;
Jon Masonb03e7492011-07-20 15:20:54 -05001934
1935 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
Jon Mason62f392e2011-10-14 14:56:14 -05001936 mps = 128 << dev->pcie_mpss;
Jon Masonb03e7492011-07-20 15:20:54 -05001937
Yijing Wang62f87c02012-07-24 17:20:03 +08001938 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1939 dev->bus->self)
Jon Mason62f392e2011-10-14 14:56:14 -05001940 /* For "Performance", the assumption is made that
Jon Masonb03e7492011-07-20 15:20:54 -05001941 * downstream communication will never be larger than
1942 * the MRRS. So, the MPS only needs to be configured
1943 * for the upstream communication. This being the case,
1944 * walk from the top down and set the MPS of the child
1945 * to that of the parent bus.
Jon Mason62f392e2011-10-14 14:56:14 -05001946 *
1947 * Configure the device MPS with the smaller of the
1948 * device MPSS or the bridge MPS (which is assumed to be
1949 * properly configured at this point to the largest
1950 * allowable MPS based on its parent bus).
Jon Masonb03e7492011-07-20 15:20:54 -05001951 */
Jon Mason62f392e2011-10-14 14:56:14 -05001952 mps = min(mps, pcie_get_mps(dev->bus->self));
Jon Masonb03e7492011-07-20 15:20:54 -05001953 }
1954
1955 rc = pcie_set_mps(dev, mps);
1956 if (rc)
1957 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1958}
1959
Jon Mason62f392e2011-10-14 14:56:14 -05001960static void pcie_write_mrrs(struct pci_dev *dev)
Jon Masonb03e7492011-07-20 15:20:54 -05001961{
Jon Mason62f392e2011-10-14 14:56:14 -05001962 int rc, mrrs;
Jon Masonb03e7492011-07-20 15:20:54 -05001963
Jon Masoned2888e2011-09-08 16:41:18 -05001964 /* In the "safe" case, do not configure the MRRS. There appear to be
1965 * issues with setting MRRS to 0 on a number of devices.
1966 */
Jon Masoned2888e2011-09-08 16:41:18 -05001967 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1968 return;
Jon Masonb03e7492011-07-20 15:20:54 -05001969
Jon Masoned2888e2011-09-08 16:41:18 -05001970 /* For Max performance, the MRRS must be set to the largest supported
1971 * value. However, it cannot be configured larger than the MPS the
Jon Mason62f392e2011-10-14 14:56:14 -05001972 * device or the bus can support. This should already be properly
1973 * configured by a prior call to pcie_write_mps.
Jon Masoned2888e2011-09-08 16:41:18 -05001974 */
Jon Mason62f392e2011-10-14 14:56:14 -05001975 mrrs = pcie_get_mps(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05001976
1977 /* MRRS is a R/W register. Invalid values can be written, but a
Jon Masoned2888e2011-09-08 16:41:18 -05001978 * subsequent read will verify if the value is acceptable or not.
Jon Masonb03e7492011-07-20 15:20:54 -05001979 * If the MRRS value provided is not acceptable (e.g., too large),
1980 * shrink the value until it is acceptable to the HW.
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001981 */
Jon Masonb03e7492011-07-20 15:20:54 -05001982 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1983 rc = pcie_set_readrq(dev, mrrs);
Jon Mason62f392e2011-10-14 14:56:14 -05001984 if (!rc)
1985 break;
Jon Masonb03e7492011-07-20 15:20:54 -05001986
Jon Mason62f392e2011-10-14 14:56:14 -05001987 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
Jon Masonb03e7492011-07-20 15:20:54 -05001988 mrrs /= 2;
1989 }
Jon Mason62f392e2011-10-14 14:56:14 -05001990
1991 if (mrrs < 128)
Ryan Desfosses227f0642014-04-18 20:13:50 -04001992 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
Jon Masonb03e7492011-07-20 15:20:54 -05001993}
1994
1995static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1996{
Jon Masona513a992011-10-14 14:56:16 -05001997 int mps, orig_mps;
Jon Masonb03e7492011-07-20 15:20:54 -05001998
1999 if (!pci_is_pcie(dev))
2000 return 0;
2001
Keith Busch27d868b2015-08-24 08:48:16 -05002002 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2003 pcie_bus_config == PCIE_BUS_DEFAULT)
Yijing Wang5895af72013-08-26 16:33:06 +08002004 return 0;
Yijing Wang5895af72013-08-26 16:33:06 +08002005
Jon Masona513a992011-10-14 14:56:16 -05002006 mps = 128 << *(u8 *)data;
2007 orig_mps = pcie_get_mps(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05002008
2009 pcie_write_mps(dev, mps);
Jon Mason62f392e2011-10-14 14:56:14 -05002010 pcie_write_mrrs(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05002011
Ryan Desfosses227f0642014-04-18 20:13:50 -04002012 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2013 pcie_get_mps(dev), 128 << dev->pcie_mpss,
Jon Masona513a992011-10-14 14:56:16 -05002014 orig_mps, pcie_get_readrq(dev));
Jon Masonb03e7492011-07-20 15:20:54 -05002015
2016 return 0;
2017}
2018
Jon Masona513a992011-10-14 14:56:16 -05002019/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
Jon Masonb03e7492011-07-20 15:20:54 -05002020 * parents then children fashion. If this changes, then this code will not
2021 * work as designed.
2022 */
Bjorn Helgaasa58674f2013-08-22 11:24:44 +08002023void pcie_bus_configure_settings(struct pci_bus *bus)
Jon Masonb03e7492011-07-20 15:20:54 -05002024{
Bjorn Helgaas1e358f92014-04-29 12:51:55 -06002025 u8 smpss = 0;
Jon Masonb03e7492011-07-20 15:20:54 -05002026
Bjorn Helgaasa58674f2013-08-22 11:24:44 +08002027 if (!bus->self)
2028 return;
2029
Jon Masonb03e7492011-07-20 15:20:54 -05002030 if (!pci_is_pcie(bus->self))
2031 return;
2032
Jon Mason5f39e672011-10-03 09:50:20 -05002033 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
Jon Mason33154722013-08-26 16:33:05 +08002034 * to be aware of the MPS of the destination. To work around this,
Jon Mason5f39e672011-10-03 09:50:20 -05002035 * simply force the MPS of the entire system to the smallest possible.
2036 */
2037 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2038 smpss = 0;
2039
Jon Masonb03e7492011-07-20 15:20:54 -05002040 if (pcie_bus_config == PCIE_BUS_SAFE) {
Bjorn Helgaasa58674f2013-08-22 11:24:44 +08002041 smpss = bus->self->pcie_mpss;
Jon Mason5f39e672011-10-03 09:50:20 -05002042
Jon Masonb03e7492011-07-20 15:20:54 -05002043 pcie_find_smpss(bus->self, &smpss);
2044 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2045 }
2046
2047 pcie_bus_configure_set(bus->self, &smpss);
2048 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2049}
Jon Masondebc3b72011-08-02 00:01:18 -05002050EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
Jon Masonb03e7492011-07-20 15:20:54 -05002051
Bill Pemberton15856ad2012-11-21 15:35:00 -05002052unsigned int pci_scan_child_bus(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002053{
Yinghai Lub918c622012-05-17 18:51:11 -07002054 unsigned int devfn, pass, max = bus->busn_res.start;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002055 struct pci_dev *dev;
2056
Bjorn Helgaas0207c352009-11-04 10:32:52 -07002057 dev_dbg(&bus->dev, "scanning bus\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002058
2059 /* Go find them, Rover! */
2060 for (devfn = 0; devfn < 0x100; devfn += 8)
2061 pci_scan_slot(bus, devfn);
2062
Yu Zhaoa28724b2009-03-20 11:25:13 +08002063 /* Reserve buses for SR-IOV capability. */
2064 max += pci_iov_bus_range(bus);
2065
Linus Torvalds1da177e2005-04-16 15:20:36 -07002066 /*
2067 * After performing arch-dependent fixup of the bus, look behind
2068 * all PCI-to-PCI bridges on this bus.
2069 */
Alex Chiang74710de2009-03-20 14:56:10 -06002070 if (!bus->is_added) {
Bjorn Helgaas0207c352009-11-04 10:32:52 -07002071 dev_dbg(&bus->dev, "fixups for bus\n");
Alex Chiang74710de2009-03-20 14:56:10 -06002072 pcibios_fixup_bus(bus);
Jiang Liu981cf9e2013-04-12 05:44:16 +00002073 bus->is_added = 1;
Alex Chiang74710de2009-03-20 14:56:10 -06002074 }
2075
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04002076 for (pass = 0; pass < 2; pass++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002077 list_for_each_entry(dev, &bus->devices, bus_list) {
Yijing Wang6788a512014-05-04 12:23:38 +08002078 if (pci_is_bridge(dev))
Linus Torvalds1da177e2005-04-16 15:20:36 -07002079 max = pci_scan_bridge(bus, dev, max, pass);
2080 }
2081
2082 /*
2083 * We've scanned the bus and so we know all about what's on
2084 * the other side of any bridges that may be on this bus plus
2085 * any devices.
2086 *
2087 * Return how far we've got finding sub-buses.
2088 */
Bjorn Helgaas0207c352009-11-04 10:32:52 -07002089 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002090 return max;
2091}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06002092EXPORT_SYMBOL_GPL(pci_scan_child_bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002093
Rafael J. Wysocki6c0cc952013-01-09 22:33:37 +01002094/**
2095 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2096 * @bridge: Host bridge to set up.
2097 *
2098 * Default empty implementation. Replace with an architecture-specific setup
2099 * routine, if necessary.
2100 */
2101int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2102{
2103 return 0;
2104}
2105
Jiang Liu10a95742013-04-12 05:44:20 +00002106void __weak pcibios_add_bus(struct pci_bus *bus)
2107{
2108}
2109
2110void __weak pcibios_remove_bus(struct pci_bus *bus)
2111{
2112}
2113
Bjorn Helgaas166c6372011-10-28 16:25:45 -06002114struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2115 struct pci_ops *ops, void *sysdata, struct list_head *resources)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002116{
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07002117 int error;
Bjorn Helgaas5a21d702012-02-23 20:18:59 -07002118 struct pci_host_bridge *bridge;
Bjorn Helgaas0207c352009-11-04 10:32:52 -07002119 struct pci_bus *b, *b2;
Jiang Liu14d76b62015-02-05 13:44:44 +08002120 struct resource_entry *window, *n;
Bjorn Helgaasa9d9f522011-10-28 16:25:40 -06002121 struct resource *res;
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07002122 resource_size_t offset;
2123 char bus_addr[64];
2124 char *fmt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002125
Catalin Marinas670ba0c2014-09-29 15:29:26 +01002126 b = pci_alloc_bus(NULL);
Bjorn Helgaas5a21d702012-02-23 20:18:59 -07002127 if (!b)
Yinghai Lu7b543662012-04-02 18:31:53 -07002128 return NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002129
2130 b->sysdata = sysdata;
2131 b->ops = ops;
Yinghai Lu4f535092013-01-21 13:20:52 -08002132 b->number = b->busn_res.start = bus;
Catalin Marinas670ba0c2014-09-29 15:29:26 +01002133 pci_bus_assign_domain_nr(b, parent);
Bjorn Helgaas0207c352009-11-04 10:32:52 -07002134 b2 = pci_find_bus(pci_domain_nr(b), bus);
2135 if (b2) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002136 /* If we already got to this bus through a different bridge, ignore it */
Bjorn Helgaas0207c352009-11-04 10:32:52 -07002137 dev_dbg(&b2->dev, "bus already known\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002138 goto err_out;
2139 }
Zhang Yanmind71374d2006-06-02 12:35:43 +08002140
Yinghai Lu7b543662012-04-02 18:31:53 -07002141 bridge = pci_alloc_host_bridge(b);
2142 if (!bridge)
2143 goto err_out;
2144
2145 bridge->dev.parent = parent;
Jiang Liu70efde22013-06-07 16:16:51 -06002146 bridge->dev.release = pci_release_host_bridge_dev;
Yinghai Lu7b543662012-04-02 18:31:53 -07002147 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
Rafael J. Wysocki6c0cc952013-01-09 22:33:37 +01002148 error = pcibios_root_bridge_prepare(bridge);
Jiang Liu343df772013-06-07 01:10:08 +08002149 if (error) {
2150 kfree(bridge);
2151 goto err_out;
2152 }
Rafael J. Wysocki6c0cc952013-01-09 22:33:37 +01002153
Yinghai Lu7b543662012-04-02 18:31:53 -07002154 error = device_register(&bridge->dev);
Jiang Liu343df772013-06-07 01:10:08 +08002155 if (error) {
2156 put_device(&bridge->dev);
2157 goto err_out;
2158 }
Yinghai Lu7b543662012-04-02 18:31:53 -07002159 b->bridge = get_device(&bridge->dev);
Rafael J. Wysockia1e4d722010-02-08 19:16:33 +01002160 device_enable_async_suspend(b->bridge);
Benjamin Herrenschmidt98d9f302011-04-11 11:37:07 +10002161 pci_set_bus_of_node(b);
Marc Zyngier44aa0c62015-07-28 14:46:11 +01002162 pci_set_bus_msi_domain(b);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002163
Yinghai Lu0d358f22008-02-19 03:20:41 -08002164 if (!parent)
2165 set_dev_node(b->bridge, pcibus_to_node(b));
2166
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -04002167 b->dev.class = &pcibus_class;
2168 b->dev.parent = b->bridge;
Kay Sievers1a927132008-10-30 02:17:49 +01002169 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -04002170 error = device_register(&b->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002171 if (error)
2172 goto class_dev_reg_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002173
Jiang Liu10a95742013-04-12 05:44:20 +00002174 pcibios_add_bus(b);
2175
Linus Torvalds1da177e2005-04-16 15:20:36 -07002176 /* Create legacy_io and legacy_mem files for this bus */
2177 pci_create_legacy_files(b);
2178
Bjorn Helgaasa9d9f522011-10-28 16:25:40 -06002179 if (parent)
2180 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
2181 else
2182 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
2183
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07002184 /* Add initial resources to the bus */
Jiang Liu14d76b62015-02-05 13:44:44 +08002185 resource_list_for_each_entry_safe(window, n, resources) {
2186 list_move_tail(&window->node, &bridge->windows);
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07002187 res = window->res;
2188 offset = window->offset;
Yinghai Luf848ffb2012-05-17 18:51:12 -07002189 if (res->flags & IORESOURCE_BUS)
2190 pci_bus_insert_busn_res(b, bus, res->end);
2191 else
2192 pci_bus_add_resource(b, res, 0);
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07002193 if (offset) {
2194 if (resource_type(res) == IORESOURCE_IO)
2195 fmt = " (bus address [%#06llx-%#06llx])";
2196 else
2197 fmt = " (bus address [%#010llx-%#010llx])";
2198 snprintf(bus_addr, sizeof(bus_addr), fmt,
2199 (unsigned long long) (res->start - offset),
2200 (unsigned long long) (res->end - offset));
2201 } else
2202 bus_addr[0] = '\0';
2203 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
Bjorn Helgaasa9d9f522011-10-28 16:25:40 -06002204 }
2205
Bjorn Helgaasa5390aa2012-02-23 20:18:59 -07002206 down_write(&pci_bus_sem);
2207 list_add_tail(&b->node, &pci_root_buses);
2208 up_write(&pci_bus_sem);
2209
Linus Torvalds1da177e2005-04-16 15:20:36 -07002210 return b;
2211
Linus Torvalds1da177e2005-04-16 15:20:36 -07002212class_dev_reg_err:
Yinghai Lu7b543662012-04-02 18:31:53 -07002213 put_device(&bridge->dev);
2214 device_unregister(&bridge->dev);
Yinghai Lu7b543662012-04-02 18:31:53 -07002215err_out:
2216 kfree(b);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002217 return NULL;
2218}
Ray Juie6b29de2015-04-08 11:21:33 -07002219EXPORT_SYMBOL_GPL(pci_create_root_bus);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10002220
Yinghai Lu98a35832012-05-18 11:35:50 -06002221int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2222{
2223 struct resource *res = &b->busn_res;
2224 struct resource *parent_res, *conflict;
2225
2226 res->start = bus;
2227 res->end = bus_max;
2228 res->flags = IORESOURCE_BUS;
2229
2230 if (!pci_is_root_bus(b))
2231 parent_res = &b->parent->busn_res;
2232 else {
2233 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2234 res->flags |= IORESOURCE_PCI_FIXED;
2235 }
2236
Andreas Noeverced04d12014-01-23 21:59:24 +01002237 conflict = request_resource_conflict(parent_res, res);
Yinghai Lu98a35832012-05-18 11:35:50 -06002238
2239 if (conflict)
2240 dev_printk(KERN_DEBUG, &b->dev,
2241 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2242 res, pci_is_root_bus(b) ? "domain " : "",
2243 parent_res, conflict->name, conflict);
Yinghai Lu98a35832012-05-18 11:35:50 -06002244
2245 return conflict == NULL;
2246}
2247
2248int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2249{
2250 struct resource *res = &b->busn_res;
2251 struct resource old_res = *res;
2252 resource_size_t size;
2253 int ret;
2254
2255 if (res->start > bus_max)
2256 return -EINVAL;
2257
2258 size = bus_max - res->start + 1;
2259 ret = adjust_resource(res, res->start, size);
2260 dev_printk(KERN_DEBUG, &b->dev,
2261 "busn_res: %pR end %s updated to %02x\n",
2262 &old_res, ret ? "can not be" : "is", bus_max);
2263
2264 if (!ret && !res->parent)
2265 pci_bus_insert_busn_res(b, res->start, res->end);
2266
2267 return ret;
2268}
2269
2270void pci_bus_release_busn_res(struct pci_bus *b)
2271{
2272 struct resource *res = &b->busn_res;
2273 int ret;
2274
2275 if (!res->flags || !res->parent)
2276 return;
2277
2278 ret = release_resource(res);
2279 dev_printk(KERN_DEBUG, &b->dev,
2280 "busn_res: %pR %s released\n",
2281 res, ret ? "can not be" : "is");
2282}
2283
Lorenzo Pieralisid2a79262015-08-03 21:27:10 -05002284struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
2285 struct pci_ops *ops, void *sysdata,
2286 struct list_head *resources, struct msi_controller *msi)
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06002287{
Jiang Liu14d76b62015-02-05 13:44:44 +08002288 struct resource_entry *window;
Yinghai Lu4d99f522012-05-17 18:51:12 -07002289 bool found = false;
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06002290 struct pci_bus *b;
Yinghai Lu4d99f522012-05-17 18:51:12 -07002291 int max;
2292
Jiang Liu14d76b62015-02-05 13:44:44 +08002293 resource_list_for_each_entry(window, resources)
Yinghai Lu4d99f522012-05-17 18:51:12 -07002294 if (window->res->flags & IORESOURCE_BUS) {
2295 found = true;
2296 break;
2297 }
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06002298
2299 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2300 if (!b)
2301 return NULL;
2302
Lorenzo Pieralisid2a79262015-08-03 21:27:10 -05002303 b->msi = msi;
2304
Yinghai Lu4d99f522012-05-17 18:51:12 -07002305 if (!found) {
2306 dev_info(&b->dev,
2307 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2308 bus);
2309 pci_bus_insert_busn_res(b, bus, 255);
2310 }
2311
2312 max = pci_scan_child_bus(b);
2313
2314 if (!found)
2315 pci_bus_update_busn_res_end(b, max);
2316
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06002317 return b;
2318}
Lorenzo Pieralisid2a79262015-08-03 21:27:10 -05002319
2320struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2321 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2322{
2323 return pci_scan_root_bus_msi(parent, bus, ops, sysdata, resources,
2324 NULL);
2325}
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06002326EXPORT_SYMBOL(pci_scan_root_bus);
2327
Bill Pemberton15856ad2012-11-21 15:35:00 -05002328struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
Bjorn Helgaasde4b2f72011-10-28 16:25:55 -06002329 void *sysdata)
2330{
2331 LIST_HEAD(resources);
2332 struct pci_bus *b;
2333
2334 pci_add_resource(&resources, &ioport_resource);
2335 pci_add_resource(&resources, &iomem_resource);
Yinghai Lu857c3b62012-05-17 18:51:12 -07002336 pci_add_resource(&resources, &busn_resource);
Bjorn Helgaasde4b2f72011-10-28 16:25:55 -06002337 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2338 if (b) {
Yinghai Lu857c3b62012-05-17 18:51:12 -07002339 pci_scan_child_bus(b);
Bjorn Helgaasde4b2f72011-10-28 16:25:55 -06002340 } else {
2341 pci_free_resource_list(&resources);
2342 }
2343 return b;
2344}
2345EXPORT_SYMBOL(pci_scan_bus);
2346
Alex Chiang3ed4fd92009-03-20 14:56:25 -06002347/**
Yinghai Lu2f320522012-01-21 02:08:22 -08002348 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2349 * @bridge: PCI bridge for the bus to scan
2350 *
2351 * Scan a PCI bus and child buses for new devices, add them,
2352 * and enable them, resizing bridge mmio/io resource if necessary
2353 * and possible. The caller must ensure the child devices are already
2354 * removed for resizing to occur.
2355 *
2356 * Returns the max number of subordinate bus discovered.
2357 */
Bjorn Helgaas10874f52014-04-14 16:11:40 -06002358unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
Yinghai Lu2f320522012-01-21 02:08:22 -08002359{
2360 unsigned int max;
2361 struct pci_bus *bus = bridge->subordinate;
2362
2363 max = pci_scan_child_bus(bus);
2364
2365 pci_assign_unassigned_bridge_resources(bridge);
2366
2367 pci_bus_add_devices(bus);
2368
2369 return max;
2370}
2371
Yinghai Lua5213a32012-10-30 14:31:21 -06002372/**
2373 * pci_rescan_bus - scan a PCI bus for devices.
2374 * @bus: PCI bus to scan
2375 *
2376 * Scan a PCI bus and child buses for new devices, adds them,
2377 * and enables them.
2378 *
2379 * Returns the max number of subordinate bus discovered.
2380 */
Bjorn Helgaas10874f52014-04-14 16:11:40 -06002381unsigned int pci_rescan_bus(struct pci_bus *bus)
Yinghai Lua5213a32012-10-30 14:31:21 -06002382{
2383 unsigned int max;
2384
2385 max = pci_scan_child_bus(bus);
2386 pci_assign_unassigned_bus_resources(bus);
2387 pci_bus_add_devices(bus);
2388
2389 return max;
2390}
2391EXPORT_SYMBOL_GPL(pci_rescan_bus);
2392
Rafael J. Wysocki9d169472014-01-10 15:22:18 +01002393/*
2394 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2395 * routines should always be executed under this mutex.
2396 */
2397static DEFINE_MUTEX(pci_rescan_remove_lock);
2398
2399void pci_lock_rescan_remove(void)
2400{
2401 mutex_lock(&pci_rescan_remove_lock);
2402}
2403EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2404
2405void pci_unlock_rescan_remove(void)
2406{
2407 mutex_unlock(&pci_rescan_remove_lock);
2408}
2409EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2410
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04002411static int __init pci_sort_bf_cmp(const struct device *d_a,
2412 const struct device *d_b)
Matt Domsch6b4b78f2006-09-29 15:23:23 -05002413{
Greg Kroah-Hartman99178b02008-08-26 11:00:57 -05002414 const struct pci_dev *a = to_pci_dev(d_a);
2415 const struct pci_dev *b = to_pci_dev(d_b);
2416
Matt Domsch6b4b78f2006-09-29 15:23:23 -05002417 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2418 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2419
2420 if (a->bus->number < b->bus->number) return -1;
2421 else if (a->bus->number > b->bus->number) return 1;
2422
2423 if (a->devfn < b->devfn) return -1;
2424 else if (a->devfn > b->devfn) return 1;
2425
2426 return 0;
2427}
2428
Greg Kroah-Hartman5ff580c2008-02-14 14:56:56 -08002429void __init pci_sort_breadthfirst(void)
Matt Domsch6b4b78f2006-09-29 15:23:23 -05002430{
Greg Kroah-Hartman99178b02008-08-26 11:00:57 -05002431 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
Matt Domsch6b4b78f2006-09-29 15:23:23 -05002432}