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H. Peter Anvin7b11fb52008-01-30 13:30:07 +01001/*
2 * Defines x86 CPU feature bits
3 */
H. Peter Anvin1965aae2008-10-22 22:26:29 -07004#ifndef _ASM_X86_CPUFEATURE_H
5#define _ASM_X86_CPUFEATURE_H
H. Peter Anvin7b11fb52008-01-30 13:30:07 +01006
David Howellsabbf1592012-10-02 18:01:26 +01007#ifndef _ASM_X86_REQUIRED_FEATURES_H
H. Peter Anvin7b11fb52008-01-30 13:30:07 +01008#include <asm/required-features.h>
David Howellsabbf1592012-10-02 18:01:26 +01009#endif
H. Peter Anvin7b11fb52008-01-30 13:30:07 +010010
Dave Hansen381aa072014-09-11 14:15:13 -070011#ifndef _ASM_X86_DISABLED_FEATURES_H
12#include <asm/disabled-features.h>
13#endif
14
Wan Zongshun2167cea2015-10-30 13:11:39 +010015#define NCAPINTS 14 /* N 32-bit words worth of info */
Borislav Petkov65fc9852013-03-20 15:07:23 +010016#define NBUGINTS 1 /* N 32-bit bug flags */
H. Peter Anvin7b11fb52008-01-30 13:30:07 +010017
H. Peter Anvin7414aa42008-08-27 17:56:44 -070018/*
19 * Note: If the comment begins with a quoted string, that string is used
20 * in /proc/cpuinfo instead of the macro name. If the string is "",
21 * this feature bit is not displayed in /proc/cpuinfo at all.
22 */
H. Peter Anvin7b11fb52008-01-30 13:30:07 +010023
24/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
Fenghua Yu446fd802014-05-29 11:12:29 -070025#define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */
26#define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */
27#define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */
28#define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */
29#define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */
30#define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
31#define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */
32#define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */
33#define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */
34#define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */
35#define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */
36#define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */
37#define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */
38#define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */
39#define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */
H. Peter Anvin2798c632008-08-27 21:20:07 -070040 /* (plus FCMOVcc, FCOMI with FPU) */
Fenghua Yu446fd802014-05-29 11:12:29 -070041#define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */
42#define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */
43#define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */
44#define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */
45#define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */
46#define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */
47#define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */
48#define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
49#define X86_FEATURE_XMM ( 0*32+25) /* "sse" */
50#define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */
51#define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */
52#define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */
53#define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */
54#define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */
55#define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */
H. Peter Anvin7b11fb52008-01-30 13:30:07 +010056
57/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
58/* Don't duplicate feature flags which are redundant with Intel! */
Fenghua Yu446fd802014-05-29 11:12:29 -070059#define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */
60#define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */
61#define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */
62#define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */
63#define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */
64#define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */
65#define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */
66#define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */
67#define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */
68#define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */
H. Peter Anvin7b11fb52008-01-30 13:30:07 +010069
70/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
Fenghua Yu446fd802014-05-29 11:12:29 -070071#define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */
72#define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */
73#define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */
H. Peter Anvin7b11fb52008-01-30 13:30:07 +010074
75/* Other features, Linux-defined mapping, word 3 */
76/* This range is used for feature bits which conflict or are synthesized */
Fenghua Yu446fd802014-05-29 11:12:29 -070077#define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */
78#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */
79#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */
80#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */
H. Peter Anvin7b11fb52008-01-30 13:30:07 +010081/* cpu types for specific tunings: */
Fenghua Yu446fd802014-05-29 11:12:29 -070082#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */
83#define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */
84#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */
85#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */
86#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */
87#define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */
Borislav Petkov9b13a932014-06-18 00:06:23 +020088/* free, was #define X86_FEATURE_FXSAVE_LEAK ( 3*32+10) * "" FXSAVE leaks FOP/FIP/FOP */
Fenghua Yu446fd802014-05-29 11:12:29 -070089#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */
90#define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */
91#define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */
92#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */
93#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */
94#define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */
95#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */
96#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */
Borislav Petkov9b13a932014-06-18 00:06:23 +020097/* free, was #define X86_FEATURE_11AP ( 3*32+19) * "" Bad local APIC aka 11AP */
Fenghua Yu446fd802014-05-29 11:12:29 -070098#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
99#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */
100#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */
101#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */
102#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */
Borislav Petkov9b13a932014-06-18 00:06:23 +0200103/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */
Fenghua Yu446fd802014-05-29 11:12:29 -0700104#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */
105#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */
106#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */
107#define X86_FEATURE_EAGER_FPU ( 3*32+29) /* "eagerfpu" Non lazy FPU restore */
108#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */
H. Peter Anvin7b11fb52008-01-30 13:30:07 +0100109
110/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
Fenghua Yu446fd802014-05-29 11:12:29 -0700111#define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */
112#define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */
113#define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */
114#define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */
115#define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */
116#define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */
117#define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */
118#define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */
119#define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */
120#define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */
121#define X86_FEATURE_CID ( 4*32+10) /* Context ID */
Mathias Krauseb1c599b2015-07-24 09:15:11 +0200122#define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */
Fenghua Yu446fd802014-05-29 11:12:29 -0700123#define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */
124#define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */
125#define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */
126#define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */
127#define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */
128#define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */
129#define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */
130#define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */
131#define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */
132#define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */
133#define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */
134#define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* Tsc deadline timer */
135#define X86_FEATURE_AES ( 4*32+25) /* AES instructions */
136#define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
137#define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */
138#define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */
139#define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */
140#define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */
141#define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */
H. Peter Anvin7b11fb52008-01-30 13:30:07 +0100142
143/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
Fenghua Yu446fd802014-05-29 11:12:29 -0700144#define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */
145#define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */
146#define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
147#define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
148#define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */
149#define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */
150#define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */
151#define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */
152#define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */
153#define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */
H. Peter Anvin7b11fb52008-01-30 13:30:07 +0100154
155/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
Fenghua Yu446fd802014-05-29 11:12:29 -0700156#define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */
157#define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */
158#define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */
159#define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */
160#define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */
161#define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */
162#define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */
163#define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */
164#define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */
165#define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */
166#define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */
167#define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */
168#define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */
169#define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */
170#define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */
171#define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */
172#define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */
173#define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */
174#define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */
175#define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */
176#define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */
177#define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */
Jacob Shind6d55f02014-05-29 17:26:50 +0200178#define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */
Fenghua Yu446fd802014-05-29 11:12:29 -0700179#define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */
Huang Ruif9675672015-08-10 12:19:53 +0200180#define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */
H. Peter Anvin7b11fb52008-01-30 13:30:07 +0100181
182/*
183 * Auxiliary flags: Linux defined - For features scattered in various
H. Peter Anvinbdc802d2010-07-07 17:29:18 -0700184 * CPUID levels like 0x6, 0xA etc, word 7
H. Peter Anvin7b11fb52008-01-30 13:30:07 +0100185 */
Fenghua Yu446fd802014-05-29 11:12:29 -0700186#define X86_FEATURE_IDA ( 7*32+ 0) /* Intel Dynamic Acceleration */
187#define X86_FEATURE_ARAT ( 7*32+ 1) /* Always Running APIC Timer */
188#define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */
189#define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
Fenghua Yu446fd802014-05-29 11:12:29 -0700190#define X86_FEATURE_PLN ( 7*32+ 5) /* Intel Power Limit Notification */
191#define X86_FEATURE_PTS ( 7*32+ 6) /* Intel Package Thermal Status */
192#define X86_FEATURE_DTHERM ( 7*32+ 7) /* Digital Thermal Sensor */
193#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */
194#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
Dirk Brandewie77873882014-11-06 09:40:46 -0800195#define X86_FEATURE_HWP ( 7*32+ 10) /* "hwp" Intel HWP */
Kristen Carlson Accardia7adb912015-09-22 10:51:36 -0700196#define X86_FEATURE_HWP_NOTIFY ( 7*32+ 11) /* Intel HWP_NOTIFY */
Dirk Brandewie77873882014-11-06 09:40:46 -0800197#define X86_FEATURE_HWP_ACT_WINDOW ( 7*32+ 12) /* Intel HWP_ACT_WINDOW */
198#define X86_FEATURE_HWP_EPP ( 7*32+13) /* Intel HWP_EPP */
199#define X86_FEATURE_HWP_PKG_REQ ( 7*32+14) /* Intel HWP_PKG_REQ */
Alexander Shishkined696282015-01-14 14:18:19 +0200200#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */
H. Peter Anvin7b11fb52008-01-30 13:30:07 +0100201
H. Peter Anvinbdc802d2010-07-07 17:29:18 -0700202/* Virtualization flags: Linux defined, word 8 */
Fenghua Yu446fd802014-05-29 11:12:29 -0700203#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
204#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */
205#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */
206#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */
207#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */
208#define X86_FEATURE_NPT ( 8*32+ 5) /* AMD Nested Page Table support */
209#define X86_FEATURE_LBRV ( 8*32+ 6) /* AMD LBR Virtualization support */
210#define X86_FEATURE_SVML ( 8*32+ 7) /* "svm_lock" AMD SVM locking MSR */
211#define X86_FEATURE_NRIPS ( 8*32+ 8) /* "nrip_save" AMD SVM next_rip save */
212#define X86_FEATURE_TSCRATEMSR ( 8*32+ 9) /* "tsc_scale" AMD TSC scaling support */
213#define X86_FEATURE_VMCBCLEAN ( 8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */
214#define X86_FEATURE_FLUSHBYASID ( 8*32+11) /* AMD flush-by-ASID support */
215#define X86_FEATURE_DECODEASSISTS ( 8*32+12) /* AMD Decode Assists support */
216#define X86_FEATURE_PAUSEFILTER ( 8*32+13) /* AMD filtered pause intercept */
217#define X86_FEATURE_PFTHRESHOLD ( 8*32+14) /* AMD pause filter threshold */
Paolo Bonzinic1118b32014-09-22 13:17:48 +0200218#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */
Boris Ostrovsky91e2eea2015-11-19 16:55:45 -0500219#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */
Andre Przywaraaeb9c7d2010-09-06 15:14:20 +0200220
Sheng Yange38e05a2008-09-10 18:53:34 +0800221
H. Peter Anvinbdc802d2010-07-07 17:29:18 -0700222/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
Fenghua Yu446fd802014-05-29 11:12:29 -0700223#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/
224#define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */
225#define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */
226#define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */
227#define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */
228#define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */
229#define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */
230#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */
231#define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */
232#define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */
Peter P Waskiewicz Jrcbc82b12015-01-23 18:45:43 +0000233#define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */
Fenghua Yu446fd802014-05-29 11:12:29 -0700234#define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */
235#define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */
236#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
237#define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */
238#define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */
Ross Zwisler719d3592015-02-19 10:37:28 -0700239#define X86_FEATURE_PCOMMIT ( 9*32+22) /* PCOMMIT instruction */
Fenghua Yu446fd802014-05-29 11:12:29 -0700240#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */
Ross Zwislerd9dc64f2015-01-27 09:53:51 -0700241#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */
Fenghua Yu446fd802014-05-29 11:12:29 -0700242#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */
243#define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */
244#define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */
Tim Chen488ca7d2015-08-21 14:56:46 -0700245#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */
H. Peter Anvinbdc802d2010-07-07 17:29:18 -0700246
Fenghua Yu6229ad22014-05-29 11:12:30 -0700247/* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */
248#define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */
249#define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */
250#define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */
251#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */
252
Peter P Waskiewicz Jrcbc82b12015-01-23 18:45:43 +0000253/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */
254#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */
255
256/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */
257#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */
258
Wan Zongshun2167cea2015-10-30 13:11:39 +0100259/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */
260#define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */
261
Borislav Petkov65fc9852013-03-20 15:07:23 +0100262/*
263 * BUG word(s)
264 */
265#define X86_BUG(x) (NCAPINTS*32 + (x))
266
Borislav Petkove2604b42013-03-20 15:07:24 +0100267#define X86_BUG_F00F X86_BUG(0) /* Intel F00F */
Borislav Petkov93a829e2013-03-20 15:07:25 +0100268#define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */
Borislav Petkovc5b41a62013-03-20 15:07:26 +0100269#define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */
Borislav Petkov80a208b2014-06-24 13:25:03 +0200270#define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */
271#define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */
Borislav Petkov9b13a932014-06-18 00:06:23 +0200272#define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */
273#define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */
274#define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */
Andy Lutomirski61f01dd2015-04-26 16:47:59 -0700275#define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */
Borislav Petkove2604b42013-03-20 15:07:24 +0100276
H. Peter Anvinfa1408e2008-02-04 16:48:00 +0100277#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
278
H. Peter Anvina3c8acd2010-05-11 17:47:07 -0700279#include <asm/asm.h>
H. Peter Anvinfa1408e2008-02-04 16:48:00 +0100280#include <linux/bitops.h>
281
Josh Triplett9def39be2013-10-30 08:09:45 -0700282#ifdef CONFIG_X86_FEATURE_NAMES
H. Peter Anvinfa1408e2008-02-04 16:48:00 +0100283extern const char * const x86_cap_flags[NCAPINTS*32];
284extern const char * const x86_power_flags[32];
Josh Triplett9def39be2013-10-30 08:09:45 -0700285#define X86_CAP_FMT "%s"
286#define x86_cap_flag(flag) x86_cap_flags[flag]
287#else
288#define X86_CAP_FMT "%d:%d"
289#define x86_cap_flag(flag) ((flag) >> 5), ((flag) & 31)
290#endif
H. Peter Anvinfa1408e2008-02-04 16:48:00 +0100291
Borislav Petkov80a208b2014-06-24 13:25:03 +0200292/*
293 * In order to save room, we index into this array by doing
294 * X86_BUG_<name> - NCAPINTS*32.
295 */
296extern const char * const x86_bug_flags[NBUGINTS*32];
297
Ingo Molnar0f8d2b92008-02-26 08:34:21 +0100298#define test_cpu_cap(c, bit) \
299 test_bit(bit, (unsigned long *)((c)->x86_capability))
300
Christoph Lameter349c0042011-03-12 12:50:10 +0100301#define REQUIRED_MASK_BIT_SET(bit) \
H. Peter Anvin7b11fb52008-01-30 13:30:07 +0100302 ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \
303 (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \
304 (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \
305 (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || \
306 (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \
307 (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \
308 (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \
H. Peter Anvinbdc802d2010-07-07 17:29:18 -0700309 (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) || \
310 (((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) || \
Christoph Lameter349c0042011-03-12 12:50:10 +0100311 (((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9)) )
312
Dave Hansen381aa072014-09-11 14:15:13 -0700313#define DISABLED_MASK_BIT_SET(bit) \
314 ( (((bit)>>5)==0 && (1UL<<((bit)&31) & DISABLED_MASK0)) || \
315 (((bit)>>5)==1 && (1UL<<((bit)&31) & DISABLED_MASK1)) || \
316 (((bit)>>5)==2 && (1UL<<((bit)&31) & DISABLED_MASK2)) || \
317 (((bit)>>5)==3 && (1UL<<((bit)&31) & DISABLED_MASK3)) || \
318 (((bit)>>5)==4 && (1UL<<((bit)&31) & DISABLED_MASK4)) || \
319 (((bit)>>5)==5 && (1UL<<((bit)&31) & DISABLED_MASK5)) || \
320 (((bit)>>5)==6 && (1UL<<((bit)&31) & DISABLED_MASK6)) || \
321 (((bit)>>5)==7 && (1UL<<((bit)&31) & DISABLED_MASK7)) || \
322 (((bit)>>5)==8 && (1UL<<((bit)&31) & DISABLED_MASK8)) || \
323 (((bit)>>5)==9 && (1UL<<((bit)&31) & DISABLED_MASK9)) )
324
Christoph Lameter349c0042011-03-12 12:50:10 +0100325#define cpu_has(c, bit) \
326 (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
Ingo Molnar0f8d2b92008-02-26 08:34:21 +0100327 test_cpu_cap(c, bit))
328
Christoph Lameter349c0042011-03-12 12:50:10 +0100329#define this_cpu_has(bit) \
330 (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
331 x86_this_cpu_test_bit(bit, (unsigned long *)&cpu_info.x86_capability))
332
Dave Hansen381aa072014-09-11 14:15:13 -0700333/*
334 * This macro is for detection of features which need kernel
335 * infrastructure to be used. It may *not* directly test the CPU
336 * itself. Use the cpu_has() family if you want true runtime
337 * testing of CPU features, like in hypervisor code where you are
338 * supporting a possible guest feature where host support for it
339 * is not relevant.
340 */
341#define cpu_feature_enabled(bit) \
342 (__builtin_constant_p(bit) && DISABLED_MASK_BIT_SET(bit) ? 0 : \
343 cpu_has(&boot_cpu_data, bit))
344
H. Peter Anvin7b11fb52008-01-30 13:30:07 +0100345#define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit)
346
Jeremy Fitzhardinge53756d32008-01-30 13:30:55 +0100347#define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability))
348#define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability))
Andi Kleen7d851c82008-01-30 13:33:20 +0100349#define setup_clear_cpu_cap(bit) do { \
350 clear_cpu_cap(&boot_cpu_data, bit); \
Yinghai Lu3e0c3732009-05-09 23:47:42 -0700351 set_bit(bit, (unsigned long *)cpu_caps_cleared); \
Andi Kleen7d851c82008-01-30 13:33:20 +0100352} while (0)
Andi Kleen404ee5b2008-01-30 13:33:20 +0100353#define setup_force_cpu_cap(bit) do { \
354 set_cpu_cap(&boot_cpu_data, bit); \
Yinghai Lu3e0c3732009-05-09 23:47:42 -0700355 set_bit(bit, (unsigned long *)cpu_caps_set); \
Andi Kleen404ee5b2008-01-30 13:33:20 +0100356} while (0)
Jeremy Fitzhardinge53756d32008-01-30 13:30:55 +0100357
H. Peter Anvin7b11fb52008-01-30 13:30:07 +0100358#define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU)
H. Peter Anvin7b11fb52008-01-30 13:30:07 +0100359#define cpu_has_de boot_cpu_has(X86_FEATURE_DE)
360#define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE)
361#define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC)
H. Peter Anvin7b11fb52008-01-30 13:30:07 +0100362#define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE)
363#define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC)
364#define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP)
365#define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR)
366#define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX)
367#define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR)
368#define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM)
369#define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2)
370#define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3)
Mathias Krause66be8952011-08-04 20:19:25 +0200371#define cpu_has_ssse3 boot_cpu_has(X86_FEATURE_SSSE3)
Huang Ying54b6a1b2009-01-18 16:28:34 +1100372#define cpu_has_aes boot_cpu_has(X86_FEATURE_AES)
Mathias Krause66be8952011-08-04 20:19:25 +0200373#define cpu_has_avx boot_cpu_has(X86_FEATURE_AVX)
Jussi Kivilinna60488012013-04-13 13:46:45 +0300374#define cpu_has_avx2 boot_cpu_has(X86_FEATURE_AVX2)
H. Peter Anvin7b11fb52008-01-30 13:30:07 +0100375#define cpu_has_ht boot_cpu_has(X86_FEATURE_HT)
H. Peter Anvin7b11fb52008-01-30 13:30:07 +0100376#define cpu_has_nx boot_cpu_has(X86_FEATURE_NX)
H. Peter Anvin7b11fb52008-01-30 13:30:07 +0100377#define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE)
378#define cpu_has_xstore_enabled boot_cpu_has(X86_FEATURE_XSTORE_EN)
379#define cpu_has_xcrypt boot_cpu_has(X86_FEATURE_XCRYPT)
380#define cpu_has_xcrypt_enabled boot_cpu_has(X86_FEATURE_XCRYPT_EN)
381#define cpu_has_ace2 boot_cpu_has(X86_FEATURE_ACE2)
382#define cpu_has_ace2_enabled boot_cpu_has(X86_FEATURE_ACE2_EN)
383#define cpu_has_phe boot_cpu_has(X86_FEATURE_PHE)
384#define cpu_has_phe_enabled boot_cpu_has(X86_FEATURE_PHE_EN)
385#define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM)
386#define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN)
387#define cpu_has_ds boot_cpu_has(X86_FEATURE_DS)
388#define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS)
H. Peter Anvin840d2832014-02-27 08:31:30 -0800389#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLUSH)
H. Peter Anvin7b11fb52008-01-30 13:30:07 +0100390#define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS)
Andi Kleen019c3e72008-02-04 16:48:09 +0100391#define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES)
stephane eranian86975102008-03-07 13:05:27 -0800392#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
venkatesh.pallipadi@intel.com2e5d9c82008-03-18 17:00:14 -0700393#define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT)
H. Peter Anvinf1240c02008-08-27 18:53:07 -0700394#define cpu_has_xmm4_1 boot_cpu_has(X86_FEATURE_XMM4_1)
Austin Zhang2a618122008-08-25 11:14:51 -0400395#define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2)
Suresh Siddha32e1d0a2008-07-10 11:16:50 -0700396#define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC)
H. Peter Anvinf1240c02008-08-27 18:53:07 -0700397#define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE)
Suresh Siddha212b0212012-09-06 15:05:18 -0700398#define cpu_has_xsaveopt boot_cpu_has(X86_FEATURE_XSAVEOPT)
Fenghua Yu6229ad22014-05-29 11:12:30 -0700399#define cpu_has_xsaves boot_cpu_has(X86_FEATURE_XSAVES)
Mathias Krause66be8952011-08-04 20:19:25 +0200400#define cpu_has_osxsave boot_cpu_has(X86_FEATURE_OSXSAVE)
Alok Kataria49ab56a2008-11-01 18:34:37 -0700401#define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR)
Huang Ying0e1227d2009-10-19 11:53:06 +0900402#define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ)
Robert Richter4979d272011-02-02 17:36:12 +0100403#define cpu_has_perfctr_core boot_cpu_has(X86_FEATURE_PERFCTR_CORE)
Jacob Shine2595142013-02-06 11:26:29 -0600404#define cpu_has_perfctr_nb boot_cpu_has(X86_FEATURE_PERFCTR_NB)
Jacob Shinc43ca502013-04-19 16:34:28 -0500405#define cpu_has_perfctr_l2 boot_cpu_has(X86_FEATURE_PERFCTR_L2)
Christoph Lameter3824abd2011-06-01 12:25:47 -0500406#define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8)
407#define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16)
Suresh Siddha5d2bd702012-09-06 14:58:52 -0700408#define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU)
Andreas Herrmann193f3fc2012-10-19 10:58:13 +0200409#define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT)
Jacob Shind6d55f02014-05-29 17:26:50 +0200410#define cpu_has_bpext boot_cpu_has(X86_FEATURE_BPEXT)
H. Peter Anvin7b11fb52008-01-30 13:30:07 +0100411
Tetsuo Handa2fd81862010-08-30 09:45:40 +0900412#if __GNUC__ >= 4
Borislav Petkov5700f742013-06-09 12:07:32 +0200413extern void warn_pre_alternatives(void);
Borislav Petkov4a90a992013-06-09 12:07:33 +0200414extern bool __static_cpu_has_safe(u16 bit);
Borislav Petkov5700f742013-06-09 12:07:32 +0200415
H. Peter Anvina3c8acd2010-05-11 17:47:07 -0700416/*
417 * Static testing of CPU features. Used the same as boot_cpu_has().
418 * These are only valid after alternatives have run, but will statically
419 * patch the target code for additional performance.
H. Peter Anvina3c8acd2010-05-11 17:47:07 -0700420 */
H. Peter Anvin83a7a2a2010-06-10 00:10:43 +0000421static __always_inline __pure bool __static_cpu_has(u16 bit)
H. Peter Anvina3c8acd2010-05-11 17:47:07 -0700422{
Borislav Petkov62122fd2013-06-28 18:41:41 +0200423#ifdef CC_HAVE_ASM_GOTO
Borislav Petkov5700f742013-06-09 12:07:32 +0200424
425#ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS
Borislav Petkov62122fd2013-06-28 18:41:41 +0200426
Borislav Petkov5700f742013-06-09 12:07:32 +0200427 /*
428 * Catch too early usage of this before alternatives
429 * have run.
430 */
Ingo Molnar3f0116c2013-10-10 10:16:30 +0200431 asm_volatile_goto("1: jmp %l[t_warn]\n"
Borislav Petkov5700f742013-06-09 12:07:32 +0200432 "2:\n"
433 ".section .altinstructions,\"a\"\n"
434 " .long 1b - .\n"
435 " .long 0\n" /* no replacement */
436 " .word %P0\n" /* 1: do replace */
437 " .byte 2b - 1b\n" /* source len */
438 " .byte 0\n" /* replacement len */
Borislav Petkov43321952014-12-27 10:41:52 +0100439 " .byte 0\n" /* pad len */
Borislav Petkov5700f742013-06-09 12:07:32 +0200440 ".previous\n"
441 /* skipping size check since replacement size = 0 */
442 : : "i" (X86_FEATURE_ALWAYS) : : t_warn);
Borislav Petkov62122fd2013-06-28 18:41:41 +0200443
Borislav Petkov5700f742013-06-09 12:07:32 +0200444#endif
445
Ingo Molnar3f0116c2013-10-10 10:16:30 +0200446 asm_volatile_goto("1: jmp %l[t_no]\n"
H. Peter Anvina3c8acd2010-05-11 17:47:07 -0700447 "2:\n"
448 ".section .altinstructions,\"a\"\n"
Andy Lutomirski59e97e42011-07-13 09:24:10 -0400449 " .long 1b - .\n"
450 " .long 0\n" /* no replacement */
H. Peter Anvin83a7a2a2010-06-10 00:10:43 +0000451 " .word %P0\n" /* feature bit */
H. Peter Anvina3c8acd2010-05-11 17:47:07 -0700452 " .byte 2b - 1b\n" /* source len */
453 " .byte 0\n" /* replacement len */
Borislav Petkov43321952014-12-27 10:41:52 +0100454 " .byte 0\n" /* pad len */
H. Peter Anvina3c8acd2010-05-11 17:47:07 -0700455 ".previous\n"
H. Peter Anvin83a7a2a2010-06-10 00:10:43 +0000456 /* skipping size check since replacement size = 0 */
H. Peter Anvina3c8acd2010-05-11 17:47:07 -0700457 : : "i" (bit) : : t_no);
458 return true;
459 t_no:
460 return false;
Borislav Petkov5700f742013-06-09 12:07:32 +0200461
462#ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS
463 t_warn:
464 warn_pre_alternatives();
465 return false;
466#endif
Borislav Petkov62122fd2013-06-28 18:41:41 +0200467
468#else /* CC_HAVE_ASM_GOTO */
469
H. Peter Anvina3c8acd2010-05-11 17:47:07 -0700470 u8 flag;
471 /* Open-coded due to __stringify() in ALTERNATIVE() */
472 asm volatile("1: movb $0,%0\n"
473 "2:\n"
474 ".section .altinstructions,\"a\"\n"
Andy Lutomirski59e97e42011-07-13 09:24:10 -0400475 " .long 1b - .\n"
476 " .long 3f - .\n"
H. Peter Anvin83a7a2a2010-06-10 00:10:43 +0000477 " .word %P1\n" /* feature bit */
H. Peter Anvina3c8acd2010-05-11 17:47:07 -0700478 " .byte 2b - 1b\n" /* source len */
479 " .byte 4f - 3f\n" /* replacement len */
Borislav Petkov43321952014-12-27 10:41:52 +0100480 " .byte 0\n" /* pad len */
H. Peter Anvin83a7a2a2010-06-10 00:10:43 +0000481 ".previous\n"
482 ".section .discard,\"aw\",@progbits\n"
483 " .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */
H. Peter Anvina3c8acd2010-05-11 17:47:07 -0700484 ".previous\n"
485 ".section .altinstr_replacement,\"ax\"\n"
486 "3: movb $1,%0\n"
487 "4:\n"
488 ".previous\n"
489 : "=qm" (flag) : "i" (bit));
490 return flag;
Borislav Petkov62122fd2013-06-28 18:41:41 +0200491
492#endif /* CC_HAVE_ASM_GOTO */
H. Peter Anvina3c8acd2010-05-11 17:47:07 -0700493}
494
495#define static_cpu_has(bit) \
496( \
497 __builtin_constant_p(boot_cpu_has(bit)) ? \
498 boot_cpu_has(bit) : \
H. Peter Anvin83a7a2a2010-06-10 00:10:43 +0000499 __builtin_constant_p(bit) ? \
H. Peter Anvina3c8acd2010-05-11 17:47:07 -0700500 __static_cpu_has(bit) : \
501 boot_cpu_has(bit) \
502)
Borislav Petkov4a90a992013-06-09 12:07:33 +0200503
504static __always_inline __pure bool _static_cpu_has_safe(u16 bit)
505{
Borislav Petkov62122fd2013-06-28 18:41:41 +0200506#ifdef CC_HAVE_ASM_GOTO
Borislav Petkov48c7a252015-01-05 13:48:41 +0100507 asm_volatile_goto("1: jmp %l[t_dynamic]\n"
Borislav Petkov4a90a992013-06-09 12:07:33 +0200508 "2:\n"
Borislav Petkov43321952014-12-27 10:41:52 +0100509 ".skip -(((5f-4f) - (2b-1b)) > 0) * "
510 "((5f-4f) - (2b-1b)),0x90\n"
511 "3:\n"
Borislav Petkov4a90a992013-06-09 12:07:33 +0200512 ".section .altinstructions,\"a\"\n"
513 " .long 1b - .\n" /* src offset */
Borislav Petkov43321952014-12-27 10:41:52 +0100514 " .long 4f - .\n" /* repl offset */
Borislav Petkov4a90a992013-06-09 12:07:33 +0200515 " .word %P1\n" /* always replace */
Borislav Petkov43321952014-12-27 10:41:52 +0100516 " .byte 3b - 1b\n" /* src len */
517 " .byte 5f - 4f\n" /* repl len */
518 " .byte 3b - 2b\n" /* pad len */
Borislav Petkov4a90a992013-06-09 12:07:33 +0200519 ".previous\n"
520 ".section .altinstr_replacement,\"ax\"\n"
Borislav Petkov48c7a252015-01-05 13:48:41 +0100521 "4: jmp %l[t_no]\n"
Borislav Petkov43321952014-12-27 10:41:52 +0100522 "5:\n"
Borislav Petkov4a90a992013-06-09 12:07:33 +0200523 ".previous\n"
524 ".section .altinstructions,\"a\"\n"
525 " .long 1b - .\n" /* src offset */
526 " .long 0\n" /* no replacement */
527 " .word %P0\n" /* feature bit */
Borislav Petkov43321952014-12-27 10:41:52 +0100528 " .byte 3b - 1b\n" /* src len */
Borislav Petkov4a90a992013-06-09 12:07:33 +0200529 " .byte 0\n" /* repl len */
Borislav Petkov43321952014-12-27 10:41:52 +0100530 " .byte 0\n" /* pad len */
Borislav Petkov4a90a992013-06-09 12:07:33 +0200531 ".previous\n"
532 : : "i" (bit), "i" (X86_FEATURE_ALWAYS)
533 : : t_dynamic, t_no);
534 return true;
535 t_no:
536 return false;
537 t_dynamic:
538 return __static_cpu_has_safe(bit);
Borislav Petkov62122fd2013-06-28 18:41:41 +0200539#else
Borislav Petkov4a90a992013-06-09 12:07:33 +0200540 u8 flag;
541 /* Open-coded due to __stringify() in ALTERNATIVE() */
542 asm volatile("1: movb $2,%0\n"
543 "2:\n"
544 ".section .altinstructions,\"a\"\n"
545 " .long 1b - .\n" /* src offset */
546 " .long 3f - .\n" /* repl offset */
547 " .word %P2\n" /* always replace */
548 " .byte 2b - 1b\n" /* source len */
549 " .byte 4f - 3f\n" /* replacement len */
Borislav Petkov43321952014-12-27 10:41:52 +0100550 " .byte 0\n" /* pad len */
Borislav Petkov4a90a992013-06-09 12:07:33 +0200551 ".previous\n"
552 ".section .discard,\"aw\",@progbits\n"
553 " .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */
554 ".previous\n"
555 ".section .altinstr_replacement,\"ax\"\n"
556 "3: movb $0,%0\n"
557 "4:\n"
558 ".previous\n"
559 ".section .altinstructions,\"a\"\n"
560 " .long 1b - .\n" /* src offset */
561 " .long 5f - .\n" /* repl offset */
562 " .word %P1\n" /* feature bit */
563 " .byte 4b - 3b\n" /* src len */
564 " .byte 6f - 5f\n" /* repl len */
Borislav Petkov43321952014-12-27 10:41:52 +0100565 " .byte 0\n" /* pad len */
Borislav Petkov4a90a992013-06-09 12:07:33 +0200566 ".previous\n"
567 ".section .discard,\"aw\",@progbits\n"
568 " .byte 0xff + (6f-5f) - (4b-3b)\n" /* size check */
569 ".previous\n"
570 ".section .altinstr_replacement,\"ax\"\n"
571 "5: movb $1,%0\n"
572 "6:\n"
573 ".previous\n"
574 : "=qm" (flag)
575 : "i" (bit), "i" (X86_FEATURE_ALWAYS));
576 return (flag == 2 ? __static_cpu_has_safe(bit) : flag);
Borislav Petkov62122fd2013-06-28 18:41:41 +0200577#endif /* CC_HAVE_ASM_GOTO */
Borislav Petkov4a90a992013-06-09 12:07:33 +0200578}
579
580#define static_cpu_has_safe(bit) \
581( \
582 __builtin_constant_p(boot_cpu_has(bit)) ? \
583 boot_cpu_has(bit) : \
584 _static_cpu_has_safe(bit) \
585)
H. Peter Anvin1ba4f222010-05-27 12:02:00 -0700586#else
587/*
588 * gcc 3.x is too stupid to do the static test; fall back to dynamic.
589 */
Borislav Petkov4a90a992013-06-09 12:07:33 +0200590#define static_cpu_has(bit) boot_cpu_has(bit)
591#define static_cpu_has_safe(bit) boot_cpu_has(bit)
H. Peter Anvin1ba4f222010-05-27 12:02:00 -0700592#endif
H. Peter Anvina3c8acd2010-05-11 17:47:07 -0700593
Borislav Petkov9b13a932014-06-18 00:06:23 +0200594#define cpu_has_bug(c, bit) cpu_has(c, (bit))
595#define set_cpu_bug(c, bit) set_cpu_cap(c, (bit))
596#define clear_cpu_bug(c, bit) clear_cpu_cap(c, (bit))
Borislav Petkov65fc9852013-03-20 15:07:23 +0100597
Borislav Petkov9b13a932014-06-18 00:06:23 +0200598#define static_cpu_has_bug(bit) static_cpu_has((bit))
599#define static_cpu_has_bug_safe(bit) static_cpu_has_safe((bit))
600#define boot_cpu_has_bug(bit) cpu_has_bug(&boot_cpu_data, (bit))
Borislav Petkov65fc9852013-03-20 15:07:23 +0100601
Borislav Petkov9b13a932014-06-18 00:06:23 +0200602#define MAX_CPU_FEATURES (NCAPINTS * 32)
603#define cpu_have_feature boot_cpu_has
Ard Biesheuvel2b9c1f02014-02-08 13:34:10 +0100604
Borislav Petkov9b13a932014-06-18 00:06:23 +0200605#define CPU_FEATURE_TYPEFMT "x86,ven%04Xfam%04Xmod%04X"
606#define CPU_FEATURE_TYPEVAL boot_cpu_data.x86_vendor, boot_cpu_data.x86, \
607 boot_cpu_data.x86_model
Ard Biesheuvel2b9c1f02014-02-08 13:34:10 +0100608
H. Peter Anvinfa1408e2008-02-04 16:48:00 +0100609#endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */
H. Peter Anvin1965aae2008-10-22 22:26:29 -0700610#endif /* _ASM_X86_CPUFEATURE_H */