| /*************************************************************************** |
| * Copyright (c) 1999-2010, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Fri Jan 22 20:26:40 2010 |
| * MD5 Checksum a2d1f2163f65e87d228a0fb491cb442d |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: /magnum/basemodules/chp/7125/rdb/c0/bchp_vcxo_ctl_misc.h $ |
| * |
| * Hydra_Software_Devel/1 1/25/10 10:10p albertl |
| * SW7125-177: Initial revision. |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_VCXO_CTL_MISC_H__ |
| #define BCHP_VCXO_CTL_MISC_H__ |
| |
| /*************************************************************************** |
| *VCXO_CTL_MISC - VCXO Core Registers |
| ***************************************************************************/ |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL 0x00471000 /* VCXO 0 PLL reset, ndiv_mode, vco range, powerdown and clock enable */ |
| #define BCHP_VCXO_CTL_MISC_VC0_DIV 0x00471004 /* VCXO 0 PLL divider settings */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_CLOCK_ENA 0x00471008 /* VCXO 0 clock outputs enable for all channels */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_1 0x0047100c /* Power control for channel 1 post divider: 27MHz used as optional PCI clock */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_2 0x00471010 /* Power control for channel 2 post divider: 6.92MHz Rate Manager Clock */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_3 0x00471014 /* Power control for channel 3 post divider: 23.04MHz optional reference clock for AUDIO and SmartCard PLLs */ |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRLBUS_LO 0x00471018 /* VCXO 0 PLL PLL_CTRL bus lower 31_0 */ |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRLBUS_HI 0x0047101c /* VCXO 0 PLL PLL_CTRL bus higher 37_32 */ |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL 0x00471020 /* Audio PLL 0 reset, ndiv_mode and powerdown */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_CLOCK_ENA 0x00471024 /* Audio PLL 0 clock outputs enable for all channels */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_1 0x00471028 /* Audio PLL 0 channel 1 powerdown post divider */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_2 0x0047102c /* Audio PLL 0 channel 2 powerdown post divider */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_3 0x00471030 /* Audio PLL 0 channel 3 powerdown post divider */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL 0x00471040 /* RAP_AVD PLL reset */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1 0x00471044 /* PLL channel 1: 250 MHz raptor DSP clock, PLL source post divider powerdown, channel gate on/off and cml buffer enable */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_2 0x00471048 /* PLL channel 2: 25 MHz EPHY clock, PLL source post divider powerdown, channel gate on/off and cml buffer enable */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_4 0x0047104c /* PLL channel 4: 75 MHz SATA clock, PLL source post divider powerdown, channel gate on/off and cml buffer */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_5 0x00471050 /* PLL channel 5: 250 MHz HDMI clock, PLL source post divider powerdown, channel gate on/off and cml buffer enable */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6 0x00471054 /* PLL channel 6: 250 MHz AVD clock, PLL source post divider powerdown, channel gate on/off and cml buffer */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_DIV 0x00471058 /* AVD RAP PLL divider settings */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRL 0x00471060 /* Audio PLL 0 reset, ndiv_mode and powerdown */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_1 0x00471064 /* Channel 1 clock enable: 324MHz DOCSIS Clock */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_2 0x00471068 /* Channel 2 clock enable: 162MHz DOCSIS Clock */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_3 0x0047106c /* Channel 3 clock enable: 216MHz NCO DOCSIS Clock */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_4 0x00471070 /* Channel 4 clock enable: 100MHz DOCSIS Clock */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_5 0x00471074 /* Channel 5 clock enable: 54MHz DOCSIS Clock */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRLBUS_HI 0x00471078 /* SYS 1 PLL control bus higher word */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRLBUS_LO 0x0047107c /* SYS 1 PLL control bus lower word */ |
| #define BCHP_VCXO_CTL_MISC_LOCK 0x00471080 /* VCXO core lock status */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET 0x00471084 /* VCXO Lock Counter Reset */ |
| #define BCHP_VCXO_CTL_MISC_VC0_LOCK_CNT 0x00471088 /* VCXO 0 PLL Lock Counter */ |
| #define BCHP_VCXO_CTL_MISC_AC0_LOCK_CNT 0x0047108c /* Audio PLL 0 Lock Counter */ |
| #define BCHP_VCXO_CTL_MISC_SC_LOCK_CNT 0x00471090 /* Smart Card PLL Lock Counter */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_LOCK_CNT 0x00471094 /* Audio DSP and AVD PLL Lock Counter */ |
| #define BCHP_VCXO_CTL_MISC_MAIN_LOCK_CNT 0x00471098 /* MAIN PLL Lock Counter */ |
| #define BCHP_VCXO_CTL_MISC_MIPS_LOCK_CNT 0x0047109c /* CPU PLL Lock Counter */ |
| #define BCHP_VCXO_CTL_MISC_MOCA_LOCK_CNT 0x004710a0 /* MOCA PLL Lock Counter */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_LOCK_CNT 0x004710a4 /* DOCSIS PLL Lock Counter */ |
| #define BCHP_VCXO_CTL_MISC_TEST_CTRL 0x004710a8 /* TOP LEVEL PLLs (except MIPS and DOCSIS PLL) test select */ |
| |
| /*************************************************************************** |
| *VC0_CTRL - VCXO 0 PLL reset, ndiv_mode, vco range, powerdown and clock enable |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: VC0_CTRL :: reserved0 [31:07] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_reserved0_MASK 0xffffff80 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_reserved0_SHIFT 7 |
| |
| /* VCXO_CTL_MISC :: VC0_CTRL :: NDIV_MODE [06:04] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_NDIV_MODE_MASK 0x00000070 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_NDIV_MODE_SHIFT 4 |
| |
| /* VCXO_CTL_MISC :: VC0_CTRL :: POWERDOWN [03:03] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_POWERDOWN_MASK 0x00000008 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_POWERDOWN_SHIFT 3 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_POWERDOWN_Powerdown 1 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_POWERDOWN_Normal 0 |
| |
| /* VCXO_CTL_MISC :: VC0_CTRL :: CLOCK_ENA [02:02] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_CLOCK_ENA_MASK 0x00000004 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_CLOCK_ENA_SHIFT 2 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_CLOCK_ENA_Enable 1 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_CLOCK_ENA_Disable 0 |
| |
| /* VCXO_CTL_MISC :: VC0_CTRL :: DRESET [01:01] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_DRESET_MASK 0x00000002 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_DRESET_SHIFT 1 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_DRESET_Reset 1 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_DRESET_Normal 0 |
| |
| /* VCXO_CTL_MISC :: VC0_CTRL :: ARESET [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_ARESET_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_ARESET_SHIFT 0 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_ARESET_Reset 1 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_ARESET_Normal 0 |
| |
| /*************************************************************************** |
| *VC0_DIV - VCXO 0 PLL divider settings |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: VC0_DIV :: reserved0 [31:26] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_DIV_reserved0_MASK 0xfc000000 |
| #define BCHP_VCXO_CTL_MISC_VC0_DIV_reserved0_SHIFT 26 |
| |
| /* VCXO_CTL_MISC :: VC0_DIV :: VCORNG [25:24] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_DIV_VCORNG_MASK 0x03000000 |
| #define BCHP_VCXO_CTL_MISC_VC0_DIV_VCORNG_SHIFT 24 |
| |
| /* VCXO_CTL_MISC :: VC0_DIV :: M3DIV [23:16] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_DIV_M3DIV_MASK 0x00ff0000 |
| #define BCHP_VCXO_CTL_MISC_VC0_DIV_M3DIV_SHIFT 16 |
| |
| /* VCXO_CTL_MISC :: VC0_DIV :: M2DIV [15:08] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_DIV_M2DIV_MASK 0x0000ff00 |
| #define BCHP_VCXO_CTL_MISC_VC0_DIV_M2DIV_SHIFT 8 |
| |
| /* VCXO_CTL_MISC :: VC0_DIV :: M1DIV [07:00] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_DIV_M1DIV_MASK 0x000000ff |
| #define BCHP_VCXO_CTL_MISC_VC0_DIV_M1DIV_SHIFT 0 |
| |
| /*************************************************************************** |
| *VC0_PM_CLOCK_ENA - VCXO 0 clock outputs enable for all channels |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: VC0_PM_CLOCK_ENA :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_CLOCK_ENA_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_CLOCK_ENA_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: VC0_PM_CLOCK_ENA :: CLOCK_ENA [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_CLOCK_ENA_CLOCK_ENA_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_CLOCK_ENA_CLOCK_ENA_SHIFT 0 |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_CLOCK_ENA_CLOCK_ENA_Enable 1 |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_CLOCK_ENA_CLOCK_ENA_Disable 0 |
| |
| /*************************************************************************** |
| *VC0_PM_DIS_CHL_1 - Power control for channel 1 post divider: 27MHz used as optional PCI clock |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: VC0_PM_DIS_CHL_1 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_1_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_1_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: VC0_PM_DIS_CHL_1 :: DIS_CH [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_1_DIS_CH_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_1_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *VC0_PM_DIS_CHL_2 - Power control for channel 2 post divider: 6.92MHz Rate Manager Clock |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: VC0_PM_DIS_CHL_2 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_2_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_2_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: VC0_PM_DIS_CHL_2 :: DIS_CH [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_2_DIS_CH_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_2_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *VC0_PM_DIS_CHL_3 - Power control for channel 3 post divider: 23.04MHz optional reference clock for AUDIO and SmartCard PLLs |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: VC0_PM_DIS_CHL_3 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_3_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_3_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: VC0_PM_DIS_CHL_3 :: DIS_CH [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_3_DIS_CH_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_3_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *VC0_CTRLBUS_LO - VCXO 0 PLL PLL_CTRL bus lower 31_0 |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: VC0_CTRLBUS_LO :: CTL_BITS_31_0 [31:00] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRLBUS_LO_CTL_BITS_31_0_MASK 0xffffffff |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRLBUS_LO_CTL_BITS_31_0_SHIFT 0 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRLBUS_LO_CTL_BITS_31_0_Above_1p6GHz 942418016 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRLBUS_LO_CTL_BITS_31_0_Below_1p6GHz 536872384 |
| |
| /*************************************************************************** |
| *VC0_CTRLBUS_HI - VCXO 0 PLL PLL_CTRL bus higher 37_32 |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: VC0_CTRLBUS_HI :: reserved0 [31:06] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRLBUS_HI_reserved0_MASK 0xffffffc0 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRLBUS_HI_reserved0_SHIFT 6 |
| |
| /* VCXO_CTL_MISC :: VC0_CTRLBUS_HI :: CTL_BITS_37_32 [05:00] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRLBUS_HI_CTL_BITS_37_32_MASK 0x0000003f |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRLBUS_HI_CTL_BITS_37_32_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC0_CTRL - Audio PLL 0 reset, ndiv_mode and powerdown |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC0_CTRL :: reserved0 [31:03] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_reserved0_SHIFT 3 |
| |
| /* VCXO_CTL_MISC :: AC0_CTRL :: POWERDOWN [02:02] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_POWERDOWN_MASK 0x00000004 |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_POWERDOWN_SHIFT 2 |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_POWERDOWN_Powerdown 1 |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_POWERDOWN_Normal 0 |
| |
| /* VCXO_CTL_MISC :: AC0_CTRL :: DRESET [01:01] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_DRESET_MASK 0x00000002 |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_DRESET_SHIFT 1 |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_DRESET_Reset 1 |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_DRESET_Normal 0 |
| |
| /* VCXO_CTL_MISC :: AC0_CTRL :: ARESET [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_ARESET_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_ARESET_SHIFT 0 |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_ARESET_Reset 1 |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_ARESET_Normal 0 |
| |
| /*************************************************************************** |
| *AC0_PM_CLOCK_ENA - Audio PLL 0 clock outputs enable for all channels |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC0_PM_CLOCK_ENA :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_CLOCK_ENA_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_CLOCK_ENA_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: AC0_PM_CLOCK_ENA :: CLOCK_ENA [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_CLOCK_ENA_CLOCK_ENA_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_CLOCK_ENA_CLOCK_ENA_SHIFT 0 |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_CLOCK_ENA_CLOCK_ENA_Enable 1 |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_CLOCK_ENA_CLOCK_ENA_Disable 0 |
| |
| /*************************************************************************** |
| *AC0_PM_DIS_CHL_1 - Audio PLL 0 channel 1 powerdown post divider |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC0_PM_DIS_CHL_1 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_1_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_1_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: AC0_PM_DIS_CHL_1 :: DIS_CH [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_1_DIS_CH_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_1_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC0_PM_DIS_CHL_2 - Audio PLL 0 channel 2 powerdown post divider |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC0_PM_DIS_CHL_2 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_2_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_2_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: AC0_PM_DIS_CHL_2 :: DIS_CH [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_2_DIS_CH_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_2_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC0_PM_DIS_CHL_3 - Audio PLL 0 channel 3 powerdown post divider |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC0_PM_DIS_CHL_3 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_3_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_3_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: AC0_PM_DIS_CHL_3 :: DIS_CH [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_3_DIS_CH_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_3_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *RAP_AVD_PLL_CTRL - RAP_AVD PLL reset |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CTRL :: reserved0 [31:06] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_reserved0_MASK 0xffffffc0 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_reserved0_SHIFT 6 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CTRL :: LDO_CTRL [05:04] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_LDO_CTRL_MASK 0x00000030 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_LDO_CTRL_SHIFT 4 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CTRL :: reserved_for_eco1 [03:03] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_reserved_for_eco1_MASK 0x00000008 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_reserved_for_eco1_SHIFT 3 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CTRL :: POWERDOWN [02:02] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_POWERDOWN_MASK 0x00000004 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_POWERDOWN_SHIFT 2 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_POWERDOWN_Powerdown 1 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_POWERDOWN_Normal 0 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CTRL :: DRESET [01:01] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_DRESET_MASK 0x00000002 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_DRESET_SHIFT 1 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_DRESET_Reset 1 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_DRESET_Normal 0 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CTRL :: ARESET [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_ARESET_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_ARESET_SHIFT 0 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_ARESET_Reset 1 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_ARESET_Normal 0 |
| |
| /*************************************************************************** |
| *RAP_AVD_PLL_CHL_1 - PLL channel 1: 250 MHz raptor DSP clock, PLL source post divider powerdown, channel gate on/off and cml buffer enable |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_1 :: reserved0 [31:03] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_reserved0_MASK 0xfffffff8 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_reserved0_SHIFT 3 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_1 :: DIS_CH [02:02] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_DIS_CH_MASK 0x00000004 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_DIS_CH_SHIFT 2 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_1 :: CLOCK_ENA [01:01] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_CLOCK_ENA_MASK 0x00000002 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_CLOCK_ENA_SHIFT 1 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_CLOCK_ENA_Enable 1 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_CLOCK_ENA_Disable 0 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_1 :: EN_CMLBUF [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_EN_CMLBUF_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_EN_CMLBUF_SHIFT 0 |
| |
| /*************************************************************************** |
| *RAP_AVD_PLL_CHL_2 - PLL channel 2: 25 MHz EPHY clock, PLL source post divider powerdown, channel gate on/off and cml buffer enable |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_2 :: reserved0 [31:03] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_2_reserved0_MASK 0xfffffff8 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_2_reserved0_SHIFT 3 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_2 :: DIS_CH [02:02] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_2_DIS_CH_MASK 0x00000004 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_2_DIS_CH_SHIFT 2 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_2 :: CLOCK_ENA [01:01] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_2_CLOCK_ENA_MASK 0x00000002 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_2_CLOCK_ENA_SHIFT 1 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_2_CLOCK_ENA_Enable 1 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_2_CLOCK_ENA_Disable 0 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_2 :: EN_CMLBUF [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_2_EN_CMLBUF_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_2_EN_CMLBUF_SHIFT 0 |
| |
| /*************************************************************************** |
| *RAP_AVD_PLL_CHL_4 - PLL channel 4: 75 MHz SATA clock, PLL source post divider powerdown, channel gate on/off and cml buffer |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_4 :: reserved0 [31:03] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_4_reserved0_MASK 0xfffffff8 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_4_reserved0_SHIFT 3 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_4 :: DIS_CH [02:02] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_4_DIS_CH_MASK 0x00000004 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_4_DIS_CH_SHIFT 2 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_4 :: CLOCK_ENA [01:01] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_4_CLOCK_ENA_MASK 0x00000002 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_4_CLOCK_ENA_SHIFT 1 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_4_CLOCK_ENA_Enable 1 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_4_CLOCK_ENA_Disable 0 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_4 :: EN_CMLBUF [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_4_EN_CMLBUF_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_4_EN_CMLBUF_SHIFT 0 |
| |
| /*************************************************************************** |
| *RAP_AVD_PLL_CHL_5 - PLL channel 5: 250 MHz HDMI clock, PLL source post divider powerdown, channel gate on/off and cml buffer enable |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_5 :: reserved0 [31:03] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_5_reserved0_MASK 0xfffffff8 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_5_reserved0_SHIFT 3 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_5 :: DIS_CH [02:02] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_5_DIS_CH_MASK 0x00000004 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_5_DIS_CH_SHIFT 2 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_5 :: CLOCK_ENA [01:01] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_5_CLOCK_ENA_MASK 0x00000002 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_5_CLOCK_ENA_SHIFT 1 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_5_CLOCK_ENA_Enable 1 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_5_CLOCK_ENA_Disable 0 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_5 :: EN_CMLBUF [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_5_EN_CMLBUF_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_5_EN_CMLBUF_SHIFT 0 |
| |
| /*************************************************************************** |
| *RAP_AVD_PLL_CHL_6 - PLL channel 6: 250 MHz AVD clock, PLL source post divider powerdown, channel gate on/off and cml buffer |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_6 :: reserved0 [31:03] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_reserved0_MASK 0xfffffff8 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_reserved0_SHIFT 3 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_6 :: DIS_CH [02:02] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_DIS_CH_MASK 0x00000004 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_DIS_CH_SHIFT 2 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_6 :: CLOCK_ENA [01:01] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_CLOCK_ENA_MASK 0x00000002 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_CLOCK_ENA_SHIFT 1 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_CLOCK_ENA_Enable 1 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_CLOCK_ENA_Disable 0 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_6 :: EN_CMLBUF [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_EN_CMLBUF_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_EN_CMLBUF_SHIFT 0 |
| |
| /*************************************************************************** |
| *RAP_AVD_DIV - AVD RAP PLL divider settings |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: RAP_AVD_DIV :: reserved0 [31:25] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_DIV_reserved0_MASK 0xfe000000 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_DIV_reserved0_SHIFT 25 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_DIV :: NDIV_INT [24:16] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_DIV_NDIV_INT_MASK 0x01ff0000 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_DIV_NDIV_INT_SHIFT 16 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_DIV :: M6DIV [15:08] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_DIV_M6DIV_MASK 0x0000ff00 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_DIV_M6DIV_SHIFT 8 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_DIV :: M1DIV [07:00] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_DIV_M1DIV_MASK 0x000000ff |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_DIV_M1DIV_SHIFT 0 |
| |
| /*************************************************************************** |
| *DOCSIS_CTRL - Audio PLL 0 reset, ndiv_mode and powerdown |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: DOCSIS_CTRL :: reserved0 [31:07] */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRL_reserved0_MASK 0xffffff80 |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRL_reserved0_SHIFT 7 |
| |
| /* VCXO_CTL_MISC :: DOCSIS_CTRL :: BGAP_ADJ [06:03] */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRL_BGAP_ADJ_MASK 0x00000078 |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRL_BGAP_ADJ_SHIFT 3 |
| |
| /* VCXO_CTL_MISC :: DOCSIS_CTRL :: POWERDOWN [02:02] */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRL_POWERDOWN_MASK 0x00000004 |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRL_POWERDOWN_SHIFT 2 |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRL_POWERDOWN_Powerdown 1 |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRL_POWERDOWN_Normal 0 |
| |
| /* VCXO_CTL_MISC :: DOCSIS_CTRL :: DRESET [01:01] */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRL_DRESET_MASK 0x00000002 |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRL_DRESET_SHIFT 1 |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRL_DRESET_Reset 1 |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRL_DRESET_Normal 0 |
| |
| /* VCXO_CTL_MISC :: DOCSIS_CTRL :: ARESET [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRL_ARESET_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRL_ARESET_SHIFT 0 |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRL_ARESET_Reset 1 |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRL_ARESET_Normal 0 |
| |
| /*************************************************************************** |
| *DOCSIS_PM_DIS_CHL_1 - Channel 1 clock enable: 324MHz DOCSIS Clock |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: DOCSIS_PM_DIS_CHL_1 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_1_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_1_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: DOCSIS_PM_DIS_CHL_1 :: CLOCK_ENA [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_1_CLOCK_ENA_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_1_CLOCK_ENA_SHIFT 0 |
| |
| /*************************************************************************** |
| *DOCSIS_PM_DIS_CHL_2 - Channel 2 clock enable: 162MHz DOCSIS Clock |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: DOCSIS_PM_DIS_CHL_2 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_2_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_2_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: DOCSIS_PM_DIS_CHL_2 :: CLOCK_ENA [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_2_CLOCK_ENA_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_2_CLOCK_ENA_SHIFT 0 |
| |
| /*************************************************************************** |
| *DOCSIS_PM_DIS_CHL_3 - Channel 3 clock enable: 216MHz NCO DOCSIS Clock |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: DOCSIS_PM_DIS_CHL_3 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_3_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_3_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: DOCSIS_PM_DIS_CHL_3 :: CLOCK_ENA [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_3_CLOCK_ENA_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_3_CLOCK_ENA_SHIFT 0 |
| |
| /*************************************************************************** |
| *DOCSIS_PM_DIS_CHL_4 - Channel 4 clock enable: 100MHz DOCSIS Clock |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: DOCSIS_PM_DIS_CHL_4 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_4_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_4_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: DOCSIS_PM_DIS_CHL_4 :: CLOCK_ENA [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_4_CLOCK_ENA_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_4_CLOCK_ENA_SHIFT 0 |
| |
| /*************************************************************************** |
| *DOCSIS_PM_DIS_CHL_5 - Channel 5 clock enable: 54MHz DOCSIS Clock |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: DOCSIS_PM_DIS_CHL_5 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_5_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_5_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: DOCSIS_PM_DIS_CHL_5 :: CLOCK_ENA [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_5_CLOCK_ENA_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_PM_DIS_CHL_5_CLOCK_ENA_SHIFT 0 |
| |
| /*************************************************************************** |
| *DOCSIS_CTRLBUS_HI - SYS 1 PLL control bus higher word |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: DOCSIS_CTRLBUS_HI :: reserved0 [31:06] */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRLBUS_HI_reserved0_MASK 0xffffffc0 |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRLBUS_HI_reserved0_SHIFT 6 |
| |
| /* VCXO_CTL_MISC :: DOCSIS_CTRLBUS_HI :: CTRL_BITS_37_32 [05:00] */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRLBUS_HI_CTRL_BITS_37_32_MASK 0x0000003f |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRLBUS_HI_CTRL_BITS_37_32_SHIFT 0 |
| |
| /*************************************************************************** |
| *DOCSIS_CTRLBUS_LO - SYS 1 PLL control bus lower word |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: DOCSIS_CTRLBUS_LO :: CTRL_BITS_31_0 [31:00] */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRLBUS_LO_CTRL_BITS_31_0_MASK 0xffffffff |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_CTRLBUS_LO_CTRL_BITS_31_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *LOCK - VCXO core lock status |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: LOCK :: reserved0 [31:08] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_reserved0_MASK 0xffffff00 |
| #define BCHP_VCXO_CTL_MISC_LOCK_reserved0_SHIFT 8 |
| |
| /* VCXO_CTL_MISC :: LOCK :: DOCSIS [07:07] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_DOCSIS_MASK 0x00000080 |
| #define BCHP_VCXO_CTL_MISC_LOCK_DOCSIS_SHIFT 7 |
| |
| /* VCXO_CTL_MISC :: LOCK :: MOCA [06:06] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_MOCA_MASK 0x00000040 |
| #define BCHP_VCXO_CTL_MISC_LOCK_MOCA_SHIFT 6 |
| |
| /* VCXO_CTL_MISC :: LOCK :: MAIN [05:05] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_MAIN_MASK 0x00000020 |
| #define BCHP_VCXO_CTL_MISC_LOCK_MAIN_SHIFT 5 |
| |
| /* VCXO_CTL_MISC :: LOCK :: MIPS [04:04] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_MIPS_MASK 0x00000010 |
| #define BCHP_VCXO_CTL_MISC_LOCK_MIPS_SHIFT 4 |
| |
| /* VCXO_CTL_MISC :: LOCK :: RAP_AVD [03:03] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_RAP_AVD_MASK 0x00000008 |
| #define BCHP_VCXO_CTL_MISC_LOCK_RAP_AVD_SHIFT 3 |
| |
| /* VCXO_CTL_MISC :: LOCK :: SC [02:02] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_SC_MASK 0x00000004 |
| #define BCHP_VCXO_CTL_MISC_LOCK_SC_SHIFT 2 |
| |
| /* VCXO_CTL_MISC :: LOCK :: AC0 [01:01] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_AC0_MASK 0x00000002 |
| #define BCHP_VCXO_CTL_MISC_LOCK_AC0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: LOCK :: VC0 [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_VC0_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_LOCK_VC0_SHIFT 0 |
| |
| /*************************************************************************** |
| *LOCK_CNTR_RESET - VCXO Lock Counter Reset |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: LOCK_CNTR_RESET :: reserved0 [31:08] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_reserved0_MASK 0xffffff00 |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_reserved0_SHIFT 8 |
| |
| /* VCXO_CTL_MISC :: LOCK_CNTR_RESET :: DOCSIS [07:07] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_DOCSIS_MASK 0x00000080 |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_DOCSIS_SHIFT 7 |
| |
| /* VCXO_CTL_MISC :: LOCK_CNTR_RESET :: MOCA [06:06] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_MOCA_MASK 0x00000040 |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_MOCA_SHIFT 6 |
| |
| /* VCXO_CTL_MISC :: LOCK_CNTR_RESET :: MAIN [05:05] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_MAIN_MASK 0x00000020 |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_MAIN_SHIFT 5 |
| |
| /* VCXO_CTL_MISC :: LOCK_CNTR_RESET :: MIPS [04:04] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_MIPS_MASK 0x00000010 |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_MIPS_SHIFT 4 |
| |
| /* VCXO_CTL_MISC :: LOCK_CNTR_RESET :: RAP_AVD [03:03] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_RAP_AVD_MASK 0x00000008 |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_RAP_AVD_SHIFT 3 |
| |
| /* VCXO_CTL_MISC :: LOCK_CNTR_RESET :: SC [02:02] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_SC_MASK 0x00000004 |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_SC_SHIFT 2 |
| |
| /* VCXO_CTL_MISC :: LOCK_CNTR_RESET :: AC0 [01:01] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_AC0_MASK 0x00000002 |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_AC0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: LOCK_CNTR_RESET :: VC0 [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_VC0_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_VC0_SHIFT 0 |
| |
| /*************************************************************************** |
| *VC0_LOCK_CNT - VCXO 0 PLL Lock Counter |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: VC0_LOCK_CNT :: reserved0 [31:12] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_LOCK_CNT_reserved0_MASK 0xfffff000 |
| #define BCHP_VCXO_CTL_MISC_VC0_LOCK_CNT_reserved0_SHIFT 12 |
| |
| /* VCXO_CTL_MISC :: VC0_LOCK_CNT :: COUNT [11:00] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_LOCK_CNT_COUNT_MASK 0x00000fff |
| #define BCHP_VCXO_CTL_MISC_VC0_LOCK_CNT_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC0_LOCK_CNT - Audio PLL 0 Lock Counter |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC0_LOCK_CNT :: reserved0 [31:12] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_LOCK_CNT_reserved0_MASK 0xfffff000 |
| #define BCHP_VCXO_CTL_MISC_AC0_LOCK_CNT_reserved0_SHIFT 12 |
| |
| /* VCXO_CTL_MISC :: AC0_LOCK_CNT :: COUNT [11:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_LOCK_CNT_COUNT_MASK 0x00000fff |
| #define BCHP_VCXO_CTL_MISC_AC0_LOCK_CNT_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *SC_LOCK_CNT - Smart Card PLL Lock Counter |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: SC_LOCK_CNT :: reserved0 [31:12] */ |
| #define BCHP_VCXO_CTL_MISC_SC_LOCK_CNT_reserved0_MASK 0xfffff000 |
| #define BCHP_VCXO_CTL_MISC_SC_LOCK_CNT_reserved0_SHIFT 12 |
| |
| /* VCXO_CTL_MISC :: SC_LOCK_CNT :: COUNT [11:00] */ |
| #define BCHP_VCXO_CTL_MISC_SC_LOCK_CNT_COUNT_MASK 0x00000fff |
| #define BCHP_VCXO_CTL_MISC_SC_LOCK_CNT_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *RAP_AVD_LOCK_CNT - Audio DSP and AVD PLL Lock Counter |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: RAP_AVD_LOCK_CNT :: reserved0 [31:12] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_LOCK_CNT_reserved0_MASK 0xfffff000 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_LOCK_CNT_reserved0_SHIFT 12 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_LOCK_CNT :: COUNT [11:00] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_LOCK_CNT_COUNT_MASK 0x00000fff |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_LOCK_CNT_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *MAIN_LOCK_CNT - MAIN PLL Lock Counter |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: MAIN_LOCK_CNT :: reserved0 [31:12] */ |
| #define BCHP_VCXO_CTL_MISC_MAIN_LOCK_CNT_reserved0_MASK 0xfffff000 |
| #define BCHP_VCXO_CTL_MISC_MAIN_LOCK_CNT_reserved0_SHIFT 12 |
| |
| /* VCXO_CTL_MISC :: MAIN_LOCK_CNT :: COUNT [11:00] */ |
| #define BCHP_VCXO_CTL_MISC_MAIN_LOCK_CNT_COUNT_MASK 0x00000fff |
| #define BCHP_VCXO_CTL_MISC_MAIN_LOCK_CNT_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *MIPS_LOCK_CNT - CPU PLL Lock Counter |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: MIPS_LOCK_CNT :: reserved0 [31:12] */ |
| #define BCHP_VCXO_CTL_MISC_MIPS_LOCK_CNT_reserved0_MASK 0xfffff000 |
| #define BCHP_VCXO_CTL_MISC_MIPS_LOCK_CNT_reserved0_SHIFT 12 |
| |
| /* VCXO_CTL_MISC :: MIPS_LOCK_CNT :: COUNT [11:00] */ |
| #define BCHP_VCXO_CTL_MISC_MIPS_LOCK_CNT_COUNT_MASK 0x00000fff |
| #define BCHP_VCXO_CTL_MISC_MIPS_LOCK_CNT_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *MOCA_LOCK_CNT - MOCA PLL Lock Counter |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: MOCA_LOCK_CNT :: reserved0 [31:12] */ |
| #define BCHP_VCXO_CTL_MISC_MOCA_LOCK_CNT_reserved0_MASK 0xfffff000 |
| #define BCHP_VCXO_CTL_MISC_MOCA_LOCK_CNT_reserved0_SHIFT 12 |
| |
| /* VCXO_CTL_MISC :: MOCA_LOCK_CNT :: COUNT [11:00] */ |
| #define BCHP_VCXO_CTL_MISC_MOCA_LOCK_CNT_COUNT_MASK 0x00000fff |
| #define BCHP_VCXO_CTL_MISC_MOCA_LOCK_CNT_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *DOCSIS_LOCK_CNT - DOCSIS PLL Lock Counter |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: DOCSIS_LOCK_CNT :: reserved0 [31:12] */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_LOCK_CNT_reserved0_MASK 0xfffff000 |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_LOCK_CNT_reserved0_SHIFT 12 |
| |
| /* VCXO_CTL_MISC :: DOCSIS_LOCK_CNT :: COUNT [11:00] */ |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_LOCK_CNT_COUNT_MASK 0x00000fff |
| #define BCHP_VCXO_CTL_MISC_DOCSIS_LOCK_CNT_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_CTRL - TOP LEVEL PLLs (except MIPS and DOCSIS PLL) test select |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: TEST_CTRL :: reserved0 [31:14] */ |
| #define BCHP_VCXO_CTL_MISC_TEST_CTRL_reserved0_MASK 0xffffc000 |
| #define BCHP_VCXO_CTL_MISC_TEST_CTRL_reserved0_SHIFT 14 |
| |
| /* VCXO_CTL_MISC :: TEST_CTRL :: RAP_AVD_ENA [13:13] */ |
| #define BCHP_VCXO_CTL_MISC_TEST_CTRL_RAP_AVD_ENA_MASK 0x00002000 |
| #define BCHP_VCXO_CTL_MISC_TEST_CTRL_RAP_AVD_ENA_SHIFT 13 |
| |
| /* VCXO_CTL_MISC :: TEST_CTRL :: VC0_ENA [12:12] */ |
| #define BCHP_VCXO_CTL_MISC_TEST_CTRL_VC0_ENA_MASK 0x00001000 |
| #define BCHP_VCXO_CTL_MISC_TEST_CTRL_VC0_ENA_SHIFT 12 |
| |
| /* VCXO_CTL_MISC :: TEST_CTRL :: AC0_ENA [11:11] */ |
| #define BCHP_VCXO_CTL_MISC_TEST_CTRL_AC0_ENA_MASK 0x00000800 |
| #define BCHP_VCXO_CTL_MISC_TEST_CTRL_AC0_ENA_SHIFT 11 |
| |
| /* VCXO_CTL_MISC :: TEST_CTRL :: MAIN_ENA [10:10] */ |
| #define BCHP_VCXO_CTL_MISC_TEST_CTRL_MAIN_ENA_MASK 0x00000400 |
| #define BCHP_VCXO_CTL_MISC_TEST_CTRL_MAIN_ENA_SHIFT 10 |
| |
| /* VCXO_CTL_MISC :: TEST_CTRL :: SC_ENA [09:09] */ |
| #define BCHP_VCXO_CTL_MISC_TEST_CTRL_SC_ENA_MASK 0x00000200 |
| #define BCHP_VCXO_CTL_MISC_TEST_CTRL_SC_ENA_SHIFT 9 |
| |
| /* VCXO_CTL_MISC :: TEST_CTRL :: RAP_AVD_SEL [08:05] */ |
| #define BCHP_VCXO_CTL_MISC_TEST_CTRL_RAP_AVD_SEL_MASK 0x000001e0 |
| #define BCHP_VCXO_CTL_MISC_TEST_CTRL_RAP_AVD_SEL_SHIFT 5 |
| |
| /* VCXO_CTL_MISC :: TEST_CTRL :: MAIN_VCXO_AUDIO_SC_SEL [04:01] */ |
| #define BCHP_VCXO_CTL_MISC_TEST_CTRL_MAIN_VCXO_AUDIO_SC_SEL_MASK 0x0000001e |
| #define BCHP_VCXO_CTL_MISC_TEST_CTRL_MAIN_VCXO_AUDIO_SC_SEL_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: TEST_CTRL :: reserved_for_eco1 [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_TEST_CTRL_reserved_for_eco1_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_TEST_CTRL_reserved_for_eco1_SHIFT 0 |
| |
| #endif /* #ifndef BCHP_VCXO_CTL_MISC_H__ */ |
| |
| /* End of File */ |
