| /*************************************************************************** |
| * Copyright (c) 1999-2010, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Mon Jun 21 20:17:34 2010 |
| * MD5 Checksum ca6a65ea070ab31476b927e4308136d1 |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: /magnum/basemodules/chp/7125/rdb/c0/bchp_clkgen.h $ |
| * |
| * Hydra_Software_Devel/2 6/23/10 3:21p albertl |
| * SW7125-1: Updated to match RDB. |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_CLKGEN_H__ |
| #define BCHP_CLKGEN_H__ |
| |
| /*************************************************************************** |
| *CLKGEN - Clkgen registers |
| ***************************************************************************/ |
| #define BCHP_CLKGEN_ACC_PAD_CLK_PM_CTRL 0x00470000 /* Clock Disable Control Register for ACC Pad Clock */ |
| #define BCHP_CLKGEN_AVD_CLK_PM_CTRL 0x00470004 /* Clock Disable Control Register for AVD */ |
| #define BCHP_CLKGEN_BNM_SCB_BRIDGE_CLK_PM_CTRL 0x00470008 /* Clock Disable Control Register for BNM_SCB_BRIDGE */ |
| #define BCHP_CLKGEN_BVN_CLK_PM_CTRL 0x0047000c /* Clock Disable Control Register for BVN */ |
| #define BCHP_CLKGEN_CGM_CLK_PM_CTRL 0x00470010 /* Clock Disable Control Register for CGM */ |
| #define BCHP_CLKGEN_CLK_27_OUT_PM_CTRL 0x00470014 /* Clock Disable Control Register for CLK_27_OUT Pad clock */ |
| #define BCHP_CLKGEN_CML_BUF_CLK_PM_CTRL 0x00470018 /* Clock Disable Control Register for CML Buffers */ |
| #define BCHP_CLKGEN_CPU_CLK_PM_CTRL 0x0047001c /* Clock Disable Control Register for CPU */ |
| #define BCHP_CLKGEN_DDR23_APHY_CLK_PM_CTRL 0x00470020 /* Clock Disable Control Register for DDR23_APHY */ |
| #define BCHP_CLKGEN_DSMAC_FPM_CLK_PM_CTRL 0x00470024 /* Clock Disable Control Register for DSMAC_FPM */ |
| #define BCHP_CLKGEN_DVP_HT_CLK_PM_CTRL 0x00470028 /* Clock Disable Control Register for DVP_HT */ |
| #define BCHP_CLKGEN_GFX_CLK_PM_CTRL 0x0047002c /* Clock Disable Control Register for GFX */ |
| #define BCHP_CLKGEN_GFX_3D_OTP_CLK_PM_CTRL 0x00470030 /* Clock Disable Control Register for 3D_OTP GFX */ |
| #define BCHP_CLKGEN_HIF_CLK_PM_CTRL 0x00470034 /* Clock Disable Control Register for HIF */ |
| #define BCHP_CLKGEN_MEMC_CLK_PM_CTRL 0x00470038 /* Clock Disable Control Register for MEMC */ |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL 0x0047003c /* Clock Disable Control Register for MOCA */ |
| #define BCHP_CLKGEN_PINMUX_CLK_PM_CTRL 0x00470040 /* Clock Disable Control Register for PINMUX */ |
| #define BCHP_CLKGEN_RPTD_AIO_CLK_PM_CTRL 0x00470044 /* Clock Disable Control Register for RTPD_AIO */ |
| #define BCHP_CLKGEN_SATA_CLK_PM_CTRL 0x00470048 /* Clock Disable Control Register for SATA */ |
| #define BCHP_CLKGEN_SECTOP_CLK_PM_CTRL 0x0047004c /* Clock Disable Control Register for SECTOP */ |
| #define BCHP_CLKGEN_SECTOP_DMA_CLK_PM_CTRL 0x00470050 /* Clock Disable Control Register for SECTOP_DMA */ |
| #define BCHP_CLKGEN_SUN_CLK_PM_CTRL 0x00470054 /* Clock Disable Control Register for SUN */ |
| #define BCHP_CLKGEN_SUN_SC_CLK_PM_CTRL 0x00470058 /* Clock Disable Control Register for SUN_SC */ |
| #define BCHP_CLKGEN_TDAC0_CLK_PM_CTRL 0x0047005c /* Clock Disable Control Register for TDAC0 */ |
| #define BCHP_CLKGEN_TDAC1_CLK_PM_CTRL 0x00470060 /* Clock Disable Control Register for TDAC1 */ |
| #define BCHP_CLKGEN_USB_CLK_PM_CTRL 0x00470064 /* Clock Disable Control Register for USB */ |
| #define BCHP_CLKGEN_USMAC_TC_CLK_PM_CTRL 0x00470068 /* Clock Disable Control Register for USMAC_TC */ |
| #define BCHP_CLKGEN_VCXO_CLK_PM_CTRL 0x0047006c /* Clock Disable Control Register for VCXO */ |
| #define BCHP_CLKGEN_VEC_CLK_PM_CTRL 0x00470070 /* Clock Disable Control Register for VEC */ |
| #define BCHP_CLKGEN_XPT_CLK_PM_CTRL 0x00470074 /* Clock Disable Control Register for XPT */ |
| #define BCHP_CLKGEN_PLL_MOCA_CTRL 0x00470080 /* MOCA PLL m3div, m4div, reset */ |
| #define BCHP_CLKGEN_PLL_MOCA_CTLBUS_HI 0x00470084 /* MOCA PLL control bus higher word */ |
| #define BCHP_CLKGEN_PLL_MOCA_CTLBUS_LO 0x00470088 /* MOCA PLL control bus lower word */ |
| #define BCHP_CLKGEN_PLL_MOCA_CH3_PM_CTRL 0x00470094 /* MOCA PLL channel 3: 225 MHz MocA PHY differential clocks, PLL source post divider powerdown, channel gate on/off and cml buffer enable */ |
| #define BCHP_CLKGEN_PLL_MOCA_CH4_PM_CTRL 0x00470098 /* MOCA PLL channel 4: 225 MHz MocA CPU differential clocks, PLL source post divider powerdown, channel gate on/off and cml buffer enable */ |
| #define BCHP_CLKGEN_PLL_MOCA_CH5_PM_CTRL 0x0047009c /* MOCA PLL channel 5: 50 MHz USDS PLL reference clocks, PLL source post divider powerdown, channel gate on/off and cml buffer enable */ |
| #define BCHP_CLKGEN_PLL_MOCA_CH6_PM_CTRL 0x004700a0 /* MOCA PLL channel 6: 100 MHz MocA digital clock, PLL source post divider powerdown, channel gate on/off and cml buffer enable */ |
| #define BCHP_CLKGEN_PLL_MAIN_CTRL 0x004700b0 /* PLL_MAIN Reset Status & DLY */ |
| #define BCHP_CLKGEN_PLL_MAIN_CH3_PM_CTRL 0x004700b4 /* PLL_MAIN Powerdown 81MHz Main clock */ |
| #define BCHP_CLKGEN_PLL_MAIN_CH4_PM_CTRL 0x004700b8 /* PLL_MAIN Powerdown 48MHz USB clock */ |
| #define BCHP_CLKGEN_PLL_MAIN_CH5_PM_CTRL 0x004700bc /* PLL_MAIN Powerdown 32.4MHz Soft Modem clock */ |
| #define BCHP_CLKGEN_PLL_MAIN_CH6_PM_CTRL 0x004700c0 /* PLL_MAIN Powerdown 99p7MHz HIF/SATA clock */ |
| #define BCHP_CLKGEN_PAD_CLOCK 0x004700d0 /* PAD Clock Control Register */ |
| #define BCHP_CLKGEN_HIF_CLOCK_SEL 0x004700d4 /* Select 108/99.7 clock to HIF */ |
| #define BCHP_CLKGEN_MISC_CLOCK_SELECTS 0x004700d8 /* Misc clock selects in chip. */ |
| #define BCHP_CLKGEN_PLL_TEST_CTRL 0x004700dc /* PLL_TEST_CTRL Control Register */ |
| #define BCHP_CLKGEN_DIFFOSC_TEST_CTRL 0x004700e0 /* DIFFOSC_TEST_CTRL Control Register */ |
| #define BCHP_CLKGEN_MIPS_PLL_CTRL 0x004700e4 /* MIPS_PLL_CTRL Register */ |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL 0x004700e8 /* AC_CTRL for D2CDIFF */ |
| #define BCHP_CLKGEN_SMARTCARD_CLOCK_CTRL 0x004700ec /* SMARTCARD_CLOCK_CTRL Register */ |
| #define BCHP_CLKGEN_PLL_TIMER_SELECT 0x004700f0 /* Select the delay after reset before using PLL */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL 0x004700f4 /* Program the PLLs to be alive in standby */ |
| #define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL 0x004700f8 /* Program the 216/108 clocks to be alive in standby */ |
| #define BCHP_CLKGEN_REVISION 0x00470100 /* Chip Revision */ |
| #define BCHP_CLKGEN_SCRATCH_REG 0x00470104 /* Scratch Register */ |
| |
| /*************************************************************************** |
| *ACC_PAD_CLK_PM_CTRL - Clock Disable Control Register for ACC Pad Clock |
| ***************************************************************************/ |
| /* CLKGEN :: ACC_PAD_CLK_PM_CTRL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_ACC_PAD_CLK_PM_CTRL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_ACC_PAD_CLK_PM_CTRL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: ACC_PAD_CLK_PM_CTRL :: DIS_CLK_ACC [00:00] */ |
| #define BCHP_CLKGEN_ACC_PAD_CLK_PM_CTRL_DIS_CLK_ACC_MASK 0x00000001 |
| #define BCHP_CLKGEN_ACC_PAD_CLK_PM_CTRL_DIS_CLK_ACC_SHIFT 0 |
| |
| /*************************************************************************** |
| *AVD_CLK_PM_CTRL - Clock Disable Control Register for AVD |
| ***************************************************************************/ |
| /* CLKGEN :: AVD_CLK_PM_CTRL :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_AVD_CLK_PM_CTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_AVD_CLK_PM_CTRL_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: AVD_CLK_PM_CTRL :: DIS_CLK_250 [02:02] */ |
| #define BCHP_CLKGEN_AVD_CLK_PM_CTRL_DIS_CLK_250_MASK 0x00000004 |
| #define BCHP_CLKGEN_AVD_CLK_PM_CTRL_DIS_CLK_250_SHIFT 2 |
| |
| /* CLKGEN :: AVD_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */ |
| #define BCHP_CLKGEN_AVD_CLK_PM_CTRL_DIS_CLK_108_MASK 0x00000002 |
| #define BCHP_CLKGEN_AVD_CLK_PM_CTRL_DIS_CLK_108_SHIFT 1 |
| |
| /* CLKGEN :: AVD_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */ |
| #define BCHP_CLKGEN_AVD_CLK_PM_CTRL_DIS_CLK_216_MASK 0x00000001 |
| #define BCHP_CLKGEN_AVD_CLK_PM_CTRL_DIS_CLK_216_SHIFT 0 |
| |
| /*************************************************************************** |
| *BNM_SCB_BRIDGE_CLK_PM_CTRL - Clock Disable Control Register for BNM_SCB_BRIDGE |
| ***************************************************************************/ |
| /* CLKGEN :: BNM_SCB_BRIDGE_CLK_PM_CTRL :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_BNM_SCB_BRIDGE_CLK_PM_CTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_BNM_SCB_BRIDGE_CLK_PM_CTRL_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: BNM_SCB_BRIDGE_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */ |
| #define BCHP_CLKGEN_BNM_SCB_BRIDGE_CLK_PM_CTRL_DIS_CLK_108_MASK 0x00000002 |
| #define BCHP_CLKGEN_BNM_SCB_BRIDGE_CLK_PM_CTRL_DIS_CLK_108_SHIFT 1 |
| |
| /* CLKGEN :: BNM_SCB_BRIDGE_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */ |
| #define BCHP_CLKGEN_BNM_SCB_BRIDGE_CLK_PM_CTRL_DIS_CLK_216_MASK 0x00000001 |
| #define BCHP_CLKGEN_BNM_SCB_BRIDGE_CLK_PM_CTRL_DIS_CLK_216_SHIFT 0 |
| |
| /*************************************************************************** |
| *BVN_CLK_PM_CTRL - Clock Disable Control Register for BVN |
| ***************************************************************************/ |
| /* CLKGEN :: BVN_CLK_PM_CTRL :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_BVN_CLK_PM_CTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_BVN_CLK_PM_CTRL_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: BVN_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */ |
| #define BCHP_CLKGEN_BVN_CLK_PM_CTRL_DIS_CLK_108_MASK 0x00000002 |
| #define BCHP_CLKGEN_BVN_CLK_PM_CTRL_DIS_CLK_108_SHIFT 1 |
| |
| /* CLKGEN :: BVN_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */ |
| #define BCHP_CLKGEN_BVN_CLK_PM_CTRL_DIS_CLK_216_MASK 0x00000001 |
| #define BCHP_CLKGEN_BVN_CLK_PM_CTRL_DIS_CLK_216_SHIFT 0 |
| |
| /*************************************************************************** |
| *CGM_CLK_PM_CTRL - Clock Disable Control Register for CGM |
| ***************************************************************************/ |
| /* CLKGEN :: CGM_CLK_PM_CTRL :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_CGM_CLK_PM_CTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_CGM_CLK_PM_CTRL_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: CGM_CLK_PM_CTRL :: DIS_CLK_CPU [02:02] */ |
| #define BCHP_CLKGEN_CGM_CLK_PM_CTRL_DIS_CLK_CPU_MASK 0x00000004 |
| #define BCHP_CLKGEN_CGM_CLK_PM_CTRL_DIS_CLK_CPU_SHIFT 2 |
| |
| /* CLKGEN :: CGM_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */ |
| #define BCHP_CLKGEN_CGM_CLK_PM_CTRL_DIS_CLK_108_MASK 0x00000002 |
| #define BCHP_CLKGEN_CGM_CLK_PM_CTRL_DIS_CLK_108_SHIFT 1 |
| |
| /* CLKGEN :: CGM_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */ |
| #define BCHP_CLKGEN_CGM_CLK_PM_CTRL_DIS_CLK_216_MASK 0x00000001 |
| #define BCHP_CLKGEN_CGM_CLK_PM_CTRL_DIS_CLK_216_SHIFT 0 |
| |
| /*************************************************************************** |
| *CLK_27_OUT_PM_CTRL - Clock Disable Control Register for CLK_27_OUT Pad clock |
| ***************************************************************************/ |
| /* CLKGEN :: CLK_27_OUT_PM_CTRL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_CLK_27_OUT_PM_CTRL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_CLK_27_OUT_PM_CTRL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: CLK_27_OUT_PM_CTRL :: DIS_CLK_27_OUT [00:00] */ |
| #define BCHP_CLKGEN_CLK_27_OUT_PM_CTRL_DIS_CLK_27_OUT_MASK 0x00000001 |
| #define BCHP_CLKGEN_CLK_27_OUT_PM_CTRL_DIS_CLK_27_OUT_SHIFT 0 |
| |
| /*************************************************************************** |
| *CML_BUF_CLK_PM_CTRL - Clock Disable Control Register for CML Buffers |
| ***************************************************************************/ |
| /* CLKGEN :: CML_BUF_CLK_PM_CTRL :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_CML_BUF_CLK_PM_CTRL_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_CML_BUF_CLK_PM_CTRL_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: CML_BUF_CLK_PM_CTRL :: DIS_CLK_PM [03:00] */ |
| #define BCHP_CLKGEN_CML_BUF_CLK_PM_CTRL_DIS_CLK_PM_MASK 0x0000000f |
| #define BCHP_CLKGEN_CML_BUF_CLK_PM_CTRL_DIS_CLK_PM_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU_CLK_PM_CTRL - Clock Disable Control Register for CPU |
| ***************************************************************************/ |
| /* CLKGEN :: CPU_CLK_PM_CTRL :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_CPU_CLK_PM_CTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_CPU_CLK_PM_CTRL_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: CPU_CLK_PM_CTRL :: reserved_for_eco1 [01:01] */ |
| #define BCHP_CLKGEN_CPU_CLK_PM_CTRL_reserved_for_eco1_MASK 0x00000002 |
| #define BCHP_CLKGEN_CPU_CLK_PM_CTRL_reserved_for_eco1_SHIFT 1 |
| |
| /* CLKGEN :: CPU_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */ |
| #define BCHP_CLKGEN_CPU_CLK_PM_CTRL_DIS_CLK_216_MASK 0x00000001 |
| #define BCHP_CLKGEN_CPU_CLK_PM_CTRL_DIS_CLK_216_SHIFT 0 |
| |
| /*************************************************************************** |
| *DDR23_APHY_CLK_PM_CTRL - Clock Disable Control Register for DDR23_APHY |
| ***************************************************************************/ |
| /* CLKGEN :: DDR23_APHY_CLK_PM_CTRL :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_DDR23_APHY_CLK_PM_CTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_DDR23_APHY_CLK_PM_CTRL_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: DDR23_APHY_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */ |
| #define BCHP_CLKGEN_DDR23_APHY_CLK_PM_CTRL_DIS_CLK_108_MASK 0x00000002 |
| #define BCHP_CLKGEN_DDR23_APHY_CLK_PM_CTRL_DIS_CLK_108_SHIFT 1 |
| |
| /* CLKGEN :: DDR23_APHY_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */ |
| #define BCHP_CLKGEN_DDR23_APHY_CLK_PM_CTRL_DIS_CLK_216_MASK 0x00000001 |
| #define BCHP_CLKGEN_DDR23_APHY_CLK_PM_CTRL_DIS_CLK_216_SHIFT 0 |
| |
| /*************************************************************************** |
| *DSMAC_FPM_CLK_PM_CTRL - Clock Disable Control Register for DSMAC_FPM |
| ***************************************************************************/ |
| /* CLKGEN :: DSMAC_FPM_CLK_PM_CTRL :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_DSMAC_FPM_CLK_PM_CTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_DSMAC_FPM_CLK_PM_CTRL_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: DSMAC_FPM_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */ |
| #define BCHP_CLKGEN_DSMAC_FPM_CLK_PM_CTRL_DIS_CLK_108_MASK 0x00000002 |
| #define BCHP_CLKGEN_DSMAC_FPM_CLK_PM_CTRL_DIS_CLK_108_SHIFT 1 |
| |
| /* CLKGEN :: DSMAC_FPM_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */ |
| #define BCHP_CLKGEN_DSMAC_FPM_CLK_PM_CTRL_DIS_CLK_216_MASK 0x00000001 |
| #define BCHP_CLKGEN_DSMAC_FPM_CLK_PM_CTRL_DIS_CLK_216_SHIFT 0 |
| |
| /*************************************************************************** |
| *DVP_HT_CLK_PM_CTRL - Clock Disable Control Register for DVP_HT |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_CLK_PM_CTRL :: reserved0 [31:07] */ |
| #define BCHP_CLKGEN_DVP_HT_CLK_PM_CTRL_reserved0_MASK 0xffffff80 |
| #define BCHP_CLKGEN_DVP_HT_CLK_PM_CTRL_reserved0_SHIFT 7 |
| |
| /* CLKGEN :: DVP_HT_CLK_PM_CTRL :: DIS_CLK_27X_PM [06:06] */ |
| #define BCHP_CLKGEN_DVP_HT_CLK_PM_CTRL_DIS_CLK_27X_PM_MASK 0x00000040 |
| #define BCHP_CLKGEN_DVP_HT_CLK_PM_CTRL_DIS_CLK_27X_PM_SHIFT 6 |
| |
| /* CLKGEN :: DVP_HT_CLK_PM_CTRL :: DIS_CLK_27X_IIC [05:05] */ |
| #define BCHP_CLKGEN_DVP_HT_CLK_PM_CTRL_DIS_CLK_27X_IIC_MASK 0x00000020 |
| #define BCHP_CLKGEN_DVP_HT_CLK_PM_CTRL_DIS_CLK_27X_IIC_SHIFT 5 |
| |
| /* CLKGEN :: DVP_HT_CLK_PM_CTRL :: DIS_CLK_250_MAX [04:04] */ |
| #define BCHP_CLKGEN_DVP_HT_CLK_PM_CTRL_DIS_CLK_250_MAX_MASK 0x00000010 |
| #define BCHP_CLKGEN_DVP_HT_CLK_PM_CTRL_DIS_CLK_250_MAX_SHIFT 4 |
| |
| /* CLKGEN :: DVP_HT_CLK_PM_CTRL :: DIS_CLK_108_ALTERNATE [03:03] */ |
| #define BCHP_CLKGEN_DVP_HT_CLK_PM_CTRL_DIS_CLK_108_ALTERNATE_MASK 0x00000008 |
| #define BCHP_CLKGEN_DVP_HT_CLK_PM_CTRL_DIS_CLK_108_ALTERNATE_SHIFT 3 |
| |
| /* CLKGEN :: DVP_HT_CLK_PM_CTRL :: DIS_CLK_216_ALTERNATE [02:02] */ |
| #define BCHP_CLKGEN_DVP_HT_CLK_PM_CTRL_DIS_CLK_216_ALTERNATE_MASK 0x00000004 |
| #define BCHP_CLKGEN_DVP_HT_CLK_PM_CTRL_DIS_CLK_216_ALTERNATE_SHIFT 2 |
| |
| /* CLKGEN :: DVP_HT_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */ |
| #define BCHP_CLKGEN_DVP_HT_CLK_PM_CTRL_DIS_CLK_108_MASK 0x00000002 |
| #define BCHP_CLKGEN_DVP_HT_CLK_PM_CTRL_DIS_CLK_108_SHIFT 1 |
| |
| /* CLKGEN :: DVP_HT_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */ |
| #define BCHP_CLKGEN_DVP_HT_CLK_PM_CTRL_DIS_CLK_216_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HT_CLK_PM_CTRL_DIS_CLK_216_SHIFT 0 |
| |
| /*************************************************************************** |
| *GFX_CLK_PM_CTRL - Clock Disable Control Register for GFX |
| ***************************************************************************/ |
| /* CLKGEN :: GFX_CLK_PM_CTRL :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_GFX_CLK_PM_CTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_GFX_CLK_PM_CTRL_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: GFX_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */ |
| #define BCHP_CLKGEN_GFX_CLK_PM_CTRL_DIS_CLK_108_MASK 0x00000002 |
| #define BCHP_CLKGEN_GFX_CLK_PM_CTRL_DIS_CLK_108_SHIFT 1 |
| |
| /* CLKGEN :: GFX_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */ |
| #define BCHP_CLKGEN_GFX_CLK_PM_CTRL_DIS_CLK_216_MASK 0x00000001 |
| #define BCHP_CLKGEN_GFX_CLK_PM_CTRL_DIS_CLK_216_SHIFT 0 |
| |
| /*************************************************************************** |
| *GFX_3D_OTP_CLK_PM_CTRL - Clock Disable Control Register for 3D_OTP GFX |
| ***************************************************************************/ |
| /* CLKGEN :: GFX_3D_OTP_CLK_PM_CTRL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_GFX_3D_OTP_CLK_PM_CTRL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_GFX_3D_OTP_CLK_PM_CTRL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: GFX_3D_OTP_CLK_PM_CTRL :: DIS_CLK_216_3D_OTP [00:00] */ |
| #define BCHP_CLKGEN_GFX_3D_OTP_CLK_PM_CTRL_DIS_CLK_216_3D_OTP_MASK 0x00000001 |
| #define BCHP_CLKGEN_GFX_3D_OTP_CLK_PM_CTRL_DIS_CLK_216_3D_OTP_SHIFT 0 |
| |
| /*************************************************************************** |
| *HIF_CLK_PM_CTRL - Clock Disable Control Register for HIF |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_CLK_PM_CTRL :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_HIF_CLK_PM_CTRL_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_HIF_CLK_PM_CTRL_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: HIF_CLK_PM_CTRL :: DIS_CLK_27 [05:05] */ |
| #define BCHP_CLKGEN_HIF_CLK_PM_CTRL_DIS_CLK_27_MASK 0x00000020 |
| #define BCHP_CLKGEN_HIF_CLK_PM_CTRL_DIS_CLK_27_SHIFT 5 |
| |
| /* CLKGEN :: HIF_CLK_PM_CTRL :: DIS_CLK_54 [04:04] */ |
| #define BCHP_CLKGEN_HIF_CLK_PM_CTRL_DIS_CLK_54_MASK 0x00000010 |
| #define BCHP_CLKGEN_HIF_CLK_PM_CTRL_DIS_CLK_54_SHIFT 4 |
| |
| /* CLKGEN :: HIF_CLK_PM_CTRL :: DIS_CLK_81 [03:03] */ |
| #define BCHP_CLKGEN_HIF_CLK_PM_CTRL_DIS_CLK_81_MASK 0x00000008 |
| #define BCHP_CLKGEN_HIF_CLK_PM_CTRL_DIS_CLK_81_SHIFT 3 |
| |
| /* CLKGEN :: HIF_CLK_PM_CTRL :: DIS_CLK_99P7_108 [02:02] */ |
| #define BCHP_CLKGEN_HIF_CLK_PM_CTRL_DIS_CLK_99P7_108_MASK 0x00000004 |
| #define BCHP_CLKGEN_HIF_CLK_PM_CTRL_DIS_CLK_99P7_108_SHIFT 2 |
| |
| /* CLKGEN :: HIF_CLK_PM_CTRL :: reserved_for_eco1 [01:00] */ |
| #define BCHP_CLKGEN_HIF_CLK_PM_CTRL_reserved_for_eco1_MASK 0x00000003 |
| #define BCHP_CLKGEN_HIF_CLK_PM_CTRL_reserved_for_eco1_SHIFT 0 |
| |
| /*************************************************************************** |
| *MEMC_CLK_PM_CTRL - Clock Disable Control Register for MEMC |
| ***************************************************************************/ |
| /* CLKGEN :: MEMC_CLK_PM_CTRL :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_MEMC_CLK_PM_CTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_MEMC_CLK_PM_CTRL_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: MEMC_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */ |
| #define BCHP_CLKGEN_MEMC_CLK_PM_CTRL_DIS_CLK_108_MASK 0x00000002 |
| #define BCHP_CLKGEN_MEMC_CLK_PM_CTRL_DIS_CLK_108_SHIFT 1 |
| |
| /* CLKGEN :: MEMC_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */ |
| #define BCHP_CLKGEN_MEMC_CLK_PM_CTRL_DIS_CLK_216_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMC_CLK_PM_CTRL_DIS_CLK_216_SHIFT 0 |
| |
| /*************************************************************************** |
| *MOCA_CLK_PM_CTRL - Clock Disable Control Register for MOCA |
| ***************************************************************************/ |
| /* CLKGEN :: MOCA_CLK_PM_CTRL :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: MOCA_CLK_PM_CTRL :: DIS_CLK_250_GENET_CG [11:11] */ |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_250_GENET_CG_MASK 0x00000800 |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_250_GENET_CG_SHIFT 11 |
| |
| /* CLKGEN :: MOCA_CLK_PM_CTRL :: DIS_CLK_250_GENET_MOCA [10:10] */ |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_250_GENET_MOCA_MASK 0x00000400 |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_250_GENET_MOCA_SHIFT 10 |
| |
| /* CLKGEN :: MOCA_CLK_PM_CTRL :: DIS_CLK_UNIMAC_SYS_RX [09:09] */ |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_RX_MASK 0x00000200 |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_RX_SHIFT 9 |
| |
| /* CLKGEN :: MOCA_CLK_PM_CTRL :: DIS_CLK_UNIMAC_SYS_TX [08:08] */ |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_TX_MASK 0x00000100 |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_TX_SHIFT 8 |
| |
| /* CLKGEN :: MOCA_CLK_PM_CTRL :: reserved_for_eco1 [07:07] */ |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_reserved_for_eco1_MASK 0x00000080 |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_reserved_for_eco1_SHIFT 7 |
| |
| /* CLKGEN :: MOCA_CLK_PM_CTRL :: DIS_CLK_L2_INTR [06:06] */ |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_L2_INTR_MASK 0x00000040 |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_L2_INTR_SHIFT 6 |
| |
| /* CLKGEN :: MOCA_CLK_PM_CTRL :: DIS_CLK_HFB [05:05] */ |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_HFB_MASK 0x00000020 |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_HFB_SHIFT 5 |
| |
| /* CLKGEN :: MOCA_CLK_PM_CTRL :: DIS_CLK_GMII [04:04] */ |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_GMII_MASK 0x00000010 |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_GMII_SHIFT 4 |
| |
| /* CLKGEN :: MOCA_CLK_PM_CTRL :: reserved_for_eco2 [03:03] */ |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_reserved_for_eco2_MASK 0x00000008 |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_reserved_for_eco2_SHIFT 3 |
| |
| /* CLKGEN :: MOCA_CLK_PM_CTRL :: DIS_CLK_54 [02:02] */ |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_54_MASK 0x00000004 |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_54_SHIFT 2 |
| |
| /* CLKGEN :: MOCA_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */ |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_108_MASK 0x00000002 |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_108_SHIFT 1 |
| |
| /* CLKGEN :: MOCA_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */ |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_216_MASK 0x00000001 |
| #define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_216_SHIFT 0 |
| |
| /*************************************************************************** |
| *PINMUX_CLK_PM_CTRL - Clock Disable Control Register for PINMUX |
| ***************************************************************************/ |
| /* CLKGEN :: PINMUX_CLK_PM_CTRL :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PINMUX_CLK_PM_CTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PINMUX_CLK_PM_CTRL_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PINMUX_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */ |
| #define BCHP_CLKGEN_PINMUX_CLK_PM_CTRL_DIS_CLK_108_MASK 0x00000002 |
| #define BCHP_CLKGEN_PINMUX_CLK_PM_CTRL_DIS_CLK_108_SHIFT 1 |
| |
| /* CLKGEN :: PINMUX_CLK_PM_CTRL :: reserved1 [00:00] */ |
| #define BCHP_CLKGEN_PINMUX_CLK_PM_CTRL_reserved1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PINMUX_CLK_PM_CTRL_reserved1_SHIFT 0 |
| |
| /*************************************************************************** |
| *RPTD_AIO_CLK_PM_CTRL - Clock Disable Control Register for RTPD_AIO |
| ***************************************************************************/ |
| /* CLKGEN :: RPTD_AIO_CLK_PM_CTRL :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_RPTD_AIO_CLK_PM_CTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_RPTD_AIO_CLK_PM_CTRL_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: RPTD_AIO_CLK_PM_CTRL :: DIS_CLK_250_RPTD [02:02] */ |
| #define BCHP_CLKGEN_RPTD_AIO_CLK_PM_CTRL_DIS_CLK_250_RPTD_MASK 0x00000004 |
| #define BCHP_CLKGEN_RPTD_AIO_CLK_PM_CTRL_DIS_CLK_250_RPTD_SHIFT 2 |
| |
| /* CLKGEN :: RPTD_AIO_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */ |
| #define BCHP_CLKGEN_RPTD_AIO_CLK_PM_CTRL_DIS_CLK_108_MASK 0x00000002 |
| #define BCHP_CLKGEN_RPTD_AIO_CLK_PM_CTRL_DIS_CLK_108_SHIFT 1 |
| |
| /* CLKGEN :: RPTD_AIO_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */ |
| #define BCHP_CLKGEN_RPTD_AIO_CLK_PM_CTRL_DIS_CLK_216_MASK 0x00000001 |
| #define BCHP_CLKGEN_RPTD_AIO_CLK_PM_CTRL_DIS_CLK_216_SHIFT 0 |
| |
| /*************************************************************************** |
| *SATA_CLK_PM_CTRL - Clock Disable Control Register for SATA |
| ***************************************************************************/ |
| /* CLKGEN :: SATA_CLK_PM_CTRL :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_SATA_CLK_PM_CTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_SATA_CLK_PM_CTRL_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: SATA_CLK_PM_CTRL :: DIS_CLK_99P7 [02:02] */ |
| #define BCHP_CLKGEN_SATA_CLK_PM_CTRL_DIS_CLK_99P7_MASK 0x00000004 |
| #define BCHP_CLKGEN_SATA_CLK_PM_CTRL_DIS_CLK_99P7_SHIFT 2 |
| |
| /* CLKGEN :: SATA_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */ |
| #define BCHP_CLKGEN_SATA_CLK_PM_CTRL_DIS_CLK_108_MASK 0x00000002 |
| #define BCHP_CLKGEN_SATA_CLK_PM_CTRL_DIS_CLK_108_SHIFT 1 |
| |
| /* CLKGEN :: SATA_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */ |
| #define BCHP_CLKGEN_SATA_CLK_PM_CTRL_DIS_CLK_216_MASK 0x00000001 |
| #define BCHP_CLKGEN_SATA_CLK_PM_CTRL_DIS_CLK_216_SHIFT 0 |
| |
| /*************************************************************************** |
| *SECTOP_CLK_PM_CTRL - Clock Disable Control Register for SECTOP |
| ***************************************************************************/ |
| /* CLKGEN :: SECTOP_CLK_PM_CTRL :: reserved0 [31:00] */ |
| #define BCHP_CLKGEN_SECTOP_CLK_PM_CTRL_reserved0_MASK 0xffffffff |
| #define BCHP_CLKGEN_SECTOP_CLK_PM_CTRL_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *SECTOP_DMA_CLK_PM_CTRL - Clock Disable Control Register for SECTOP_DMA |
| ***************************************************************************/ |
| /* CLKGEN :: SECTOP_DMA_CLK_PM_CTRL :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SECTOP_DMA_CLK_PM_CTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SECTOP_DMA_CLK_PM_CTRL_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SECTOP_DMA_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */ |
| #define BCHP_CLKGEN_SECTOP_DMA_CLK_PM_CTRL_DIS_CLK_108_MASK 0x00000002 |
| #define BCHP_CLKGEN_SECTOP_DMA_CLK_PM_CTRL_DIS_CLK_108_SHIFT 1 |
| |
| /* CLKGEN :: SECTOP_DMA_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */ |
| #define BCHP_CLKGEN_SECTOP_DMA_CLK_PM_CTRL_DIS_CLK_216_MASK 0x00000001 |
| #define BCHP_CLKGEN_SECTOP_DMA_CLK_PM_CTRL_DIS_CLK_216_SHIFT 0 |
| |
| /*************************************************************************** |
| *SUN_CLK_PM_CTRL - Clock Disable Control Register for SUN |
| ***************************************************************************/ |
| /* CLKGEN :: SUN_CLK_PM_CTRL :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_SUN_CLK_PM_CTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_SUN_CLK_PM_CTRL_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: SUN_CLK_PM_CTRL :: DIS_CLK_27X_PM [02:02] */ |
| #define BCHP_CLKGEN_SUN_CLK_PM_CTRL_DIS_CLK_27X_PM_MASK 0x00000004 |
| #define BCHP_CLKGEN_SUN_CLK_PM_CTRL_DIS_CLK_27X_PM_SHIFT 2 |
| |
| /* CLKGEN :: SUN_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */ |
| #define BCHP_CLKGEN_SUN_CLK_PM_CTRL_DIS_CLK_108_MASK 0x00000002 |
| #define BCHP_CLKGEN_SUN_CLK_PM_CTRL_DIS_CLK_108_SHIFT 1 |
| |
| /* CLKGEN :: SUN_CLK_PM_CTRL :: reserved_for_eco1 [00:00] */ |
| #define BCHP_CLKGEN_SUN_CLK_PM_CTRL_reserved_for_eco1_MASK 0x00000001 |
| #define BCHP_CLKGEN_SUN_CLK_PM_CTRL_reserved_for_eco1_SHIFT 0 |
| |
| /*************************************************************************** |
| *SUN_SC_CLK_PM_CTRL - Clock Disable Control Register for SUN_SC |
| ***************************************************************************/ |
| /* CLKGEN :: SUN_SC_CLK_PM_CTRL :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SUN_SC_CLK_PM_CTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SUN_SC_CLK_PM_CTRL_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SUN_SC_CLK_PM_CTRL :: DIS_CLK_40_27X_SC1 [01:01] */ |
| #define BCHP_CLKGEN_SUN_SC_CLK_PM_CTRL_DIS_CLK_40_27X_SC1_MASK 0x00000002 |
| #define BCHP_CLKGEN_SUN_SC_CLK_PM_CTRL_DIS_CLK_40_27X_SC1_SHIFT 1 |
| |
| /* CLKGEN :: SUN_SC_CLK_PM_CTRL :: DIS_CLK_40_27X_SC0 [00:00] */ |
| #define BCHP_CLKGEN_SUN_SC_CLK_PM_CTRL_DIS_CLK_40_27X_SC0_MASK 0x00000001 |
| #define BCHP_CLKGEN_SUN_SC_CLK_PM_CTRL_DIS_CLK_40_27X_SC0_SHIFT 0 |
| |
| /*************************************************************************** |
| *TDAC0_CLK_PM_CTRL - Clock Disable Control Register for TDAC0 |
| ***************************************************************************/ |
| /* CLKGEN :: TDAC0_CLK_PM_CTRL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_TDAC0_CLK_PM_CTRL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_TDAC0_CLK_PM_CTRL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: TDAC0_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */ |
| #define BCHP_CLKGEN_TDAC0_CLK_PM_CTRL_DIS_CLK_216_MASK 0x00000001 |
| #define BCHP_CLKGEN_TDAC0_CLK_PM_CTRL_DIS_CLK_216_SHIFT 0 |
| |
| /*************************************************************************** |
| *TDAC1_CLK_PM_CTRL - Clock Disable Control Register for TDAC1 |
| ***************************************************************************/ |
| /* CLKGEN :: TDAC1_CLK_PM_CTRL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_TDAC1_CLK_PM_CTRL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_TDAC1_CLK_PM_CTRL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: TDAC1_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */ |
| #define BCHP_CLKGEN_TDAC1_CLK_PM_CTRL_DIS_CLK_216_MASK 0x00000001 |
| #define BCHP_CLKGEN_TDAC1_CLK_PM_CTRL_DIS_CLK_216_SHIFT 0 |
| |
| /*************************************************************************** |
| *USB_CLK_PM_CTRL - Clock Disable Control Register for USB |
| ***************************************************************************/ |
| /* CLKGEN :: USB_CLK_PM_CTRL :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB_CLK_PM_CTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB_CLK_PM_CTRL_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */ |
| #define BCHP_CLKGEN_USB_CLK_PM_CTRL_DIS_CLK_108_MASK 0x00000002 |
| #define BCHP_CLKGEN_USB_CLK_PM_CTRL_DIS_CLK_108_SHIFT 1 |
| |
| /* CLKGEN :: USB_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */ |
| #define BCHP_CLKGEN_USB_CLK_PM_CTRL_DIS_CLK_216_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB_CLK_PM_CTRL_DIS_CLK_216_SHIFT 0 |
| |
| /*************************************************************************** |
| *USMAC_TC_CLK_PM_CTRL - Clock Disable Control Register for USMAC_TC |
| ***************************************************************************/ |
| /* CLKGEN :: USMAC_TC_CLK_PM_CTRL :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USMAC_TC_CLK_PM_CTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USMAC_TC_CLK_PM_CTRL_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USMAC_TC_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */ |
| #define BCHP_CLKGEN_USMAC_TC_CLK_PM_CTRL_DIS_CLK_108_MASK 0x00000002 |
| #define BCHP_CLKGEN_USMAC_TC_CLK_PM_CTRL_DIS_CLK_108_SHIFT 1 |
| |
| /* CLKGEN :: USMAC_TC_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */ |
| #define BCHP_CLKGEN_USMAC_TC_CLK_PM_CTRL_DIS_CLK_216_MASK 0x00000001 |
| #define BCHP_CLKGEN_USMAC_TC_CLK_PM_CTRL_DIS_CLK_216_SHIFT 0 |
| |
| /*************************************************************************** |
| *VCXO_CLK_PM_CTRL - Clock Disable Control Register for VCXO |
| ***************************************************************************/ |
| /* CLKGEN :: VCXO_CLK_PM_CTRL :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_VCXO_CLK_PM_CTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_VCXO_CLK_PM_CTRL_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: VCXO_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */ |
| #define BCHP_CLKGEN_VCXO_CLK_PM_CTRL_DIS_CLK_108_MASK 0x00000002 |
| #define BCHP_CLKGEN_VCXO_CLK_PM_CTRL_DIS_CLK_108_SHIFT 1 |
| |
| /* CLKGEN :: VCXO_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */ |
| #define BCHP_CLKGEN_VCXO_CLK_PM_CTRL_DIS_CLK_216_MASK 0x00000001 |
| #define BCHP_CLKGEN_VCXO_CLK_PM_CTRL_DIS_CLK_216_SHIFT 0 |
| |
| /*************************************************************************** |
| *VEC_CLK_PM_CTRL - Clock Disable Control Register for VEC |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_CLK_PM_CTRL :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_VEC_CLK_PM_CTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_VEC_CLK_PM_CTRL_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: VEC_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */ |
| #define BCHP_CLKGEN_VEC_CLK_PM_CTRL_DIS_CLK_108_MASK 0x00000002 |
| #define BCHP_CLKGEN_VEC_CLK_PM_CTRL_DIS_CLK_108_SHIFT 1 |
| |
| /* CLKGEN :: VEC_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */ |
| #define BCHP_CLKGEN_VEC_CLK_PM_CTRL_DIS_CLK_216_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_CLK_PM_CTRL_DIS_CLK_216_SHIFT 0 |
| |
| /*************************************************************************** |
| *XPT_CLK_PM_CTRL - Clock Disable Control Register for XPT |
| ***************************************************************************/ |
| /* CLKGEN :: XPT_CLK_PM_CTRL :: reserved0 [31:07] */ |
| #define BCHP_CLKGEN_XPT_CLK_PM_CTRL_reserved0_MASK 0xffffff80 |
| #define BCHP_CLKGEN_XPT_CLK_PM_CTRL_reserved0_SHIFT 7 |
| |
| /* CLKGEN :: XPT_CLK_PM_CTRL :: DIS_CLK_20P25 [06:06] */ |
| #define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_20P25_MASK 0x00000040 |
| #define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_20P25_SHIFT 6 |
| |
| /* CLKGEN :: XPT_CLK_PM_CTRL :: DIS_CLK_27 [05:05] */ |
| #define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_27_MASK 0x00000020 |
| #define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_27_SHIFT 5 |
| |
| /* CLKGEN :: XPT_CLK_PM_CTRL :: DIS_CLK_40P5 [04:04] */ |
| #define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_40P5_MASK 0x00000010 |
| #define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_40P5_SHIFT 4 |
| |
| /* CLKGEN :: XPT_CLK_PM_CTRL :: DIS_CLK_54 [03:03] */ |
| #define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_54_MASK 0x00000008 |
| #define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_54_SHIFT 3 |
| |
| /* CLKGEN :: XPT_CLK_PM_CTRL :: DIS_CLK_81 [02:02] */ |
| #define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_81_MASK 0x00000004 |
| #define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_81_SHIFT 2 |
| |
| /* CLKGEN :: XPT_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */ |
| #define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_108_MASK 0x00000002 |
| #define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_108_SHIFT 1 |
| |
| /* CLKGEN :: XPT_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */ |
| #define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_216_MASK 0x00000001 |
| #define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_216_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_CTRL - MOCA PLL m3div, m4div, reset |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_CTRL :: reserved0 [31:29] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CTRL_reserved0_MASK 0xe0000000 |
| #define BCHP_CLKGEN_PLL_MOCA_CTRL_reserved0_SHIFT 29 |
| |
| /* CLKGEN :: PLL_MOCA_CTRL :: M6DIV [28:21] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CTRL_M6DIV_MASK 0x1fe00000 |
| #define BCHP_CLKGEN_PLL_MOCA_CTRL_M6DIV_SHIFT 21 |
| |
| /* CLKGEN :: PLL_MOCA_CTRL :: M4DIV [20:13] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CTRL_M4DIV_MASK 0x001fe000 |
| #define BCHP_CLKGEN_PLL_MOCA_CTRL_M4DIV_SHIFT 13 |
| |
| /* CLKGEN :: PLL_MOCA_CTRL :: M3DIV [12:05] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CTRL_M3DIV_MASK 0x00001fe0 |
| #define BCHP_CLKGEN_PLL_MOCA_CTRL_M3DIV_SHIFT 5 |
| |
| /* CLKGEN :: PLL_MOCA_CTRL :: POWERDOWN [04:04] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CTRL_POWERDOWN_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_MOCA_CTRL_POWERDOWN_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_MOCA_CTRL_POWERDOWN_Powerdown 1 |
| #define BCHP_CLKGEN_PLL_MOCA_CTRL_POWERDOWN_Normal 0 |
| |
| /* CLKGEN :: PLL_MOCA_CTRL :: LDO_CTRL [03:02] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CTRL_LDO_CTRL_MASK 0x0000000c |
| #define BCHP_CLKGEN_PLL_MOCA_CTRL_LDO_CTRL_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MOCA_CTRL :: DRESET [01:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CTRL_DRESET_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MOCA_CTRL_DRESET_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_CTRL_DRESET_Reset 1 |
| #define BCHP_CLKGEN_PLL_MOCA_CTRL_DRESET_Normal 0 |
| |
| /* CLKGEN :: PLL_MOCA_CTRL :: ARESET [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CTRL_ARESET_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_CTRL_ARESET_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_CTRL_ARESET_Reset 1 |
| #define BCHP_CLKGEN_PLL_MOCA_CTRL_ARESET_Normal 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_CTLBUS_HI - MOCA PLL control bus higher word |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_CTLBUS_HI :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CTLBUS_HI_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_PLL_MOCA_CTLBUS_HI_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: PLL_MOCA_CTLBUS_HI :: CTL_BITS_37_32 [05:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CTLBUS_HI_CTL_BITS_37_32_MASK 0x0000003f |
| #define BCHP_CLKGEN_PLL_MOCA_CTLBUS_HI_CTL_BITS_37_32_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_CTLBUS_LO - MOCA PLL control bus lower word |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_CTLBUS_LO :: CTL_BITS_31_0 [31:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CTLBUS_LO_CTL_BITS_31_0_MASK 0xffffffff |
| #define BCHP_CLKGEN_PLL_MOCA_CTLBUS_LO_CTL_BITS_31_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_CH3_PM_CTRL - MOCA PLL channel 3: 225 MHz MocA PHY differential clocks, PLL source post divider powerdown, channel gate on/off and cml buffer enable |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_CH3_PM_CTRL :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CH3_PM_CTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PLL_MOCA_CH3_PM_CTRL_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PLL_MOCA_CH3_PM_CTRL :: DIS_CH [02:02] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CH3_PM_CTRL_DIS_CH_MASK 0x00000004 |
| #define BCHP_CLKGEN_PLL_MOCA_CH3_PM_CTRL_DIS_CH_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MOCA_CH3_PM_CTRL :: CLOCK_ENAB [01:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CH3_PM_CTRL_CLOCK_ENAB_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MOCA_CH3_PM_CTRL_CLOCK_ENAB_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_CH3_PM_CTRL_CLOCK_ENAB_Enable 0 |
| #define BCHP_CLKGEN_PLL_MOCA_CH3_PM_CTRL_CLOCK_ENAB_Disable 1 |
| |
| /* CLKGEN :: PLL_MOCA_CH3_PM_CTRL :: EN_CMLBUF [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CH3_PM_CTRL_EN_CMLBUF_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_CH3_PM_CTRL_EN_CMLBUF_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_CH4_PM_CTRL - MOCA PLL channel 4: 225 MHz MocA CPU differential clocks, PLL source post divider powerdown, channel gate on/off and cml buffer enable |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_CH4_PM_CTRL :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CH4_PM_CTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PLL_MOCA_CH4_PM_CTRL_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PLL_MOCA_CH4_PM_CTRL :: DIS_CH [02:02] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CH4_PM_CTRL_DIS_CH_MASK 0x00000004 |
| #define BCHP_CLKGEN_PLL_MOCA_CH4_PM_CTRL_DIS_CH_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MOCA_CH4_PM_CTRL :: CLOCK_ENAB [01:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CH4_PM_CTRL_CLOCK_ENAB_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MOCA_CH4_PM_CTRL_CLOCK_ENAB_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_CH4_PM_CTRL_CLOCK_ENAB_Enable 0 |
| #define BCHP_CLKGEN_PLL_MOCA_CH4_PM_CTRL_CLOCK_ENAB_Disable 1 |
| |
| /* CLKGEN :: PLL_MOCA_CH4_PM_CTRL :: EN_CMLBUF [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CH4_PM_CTRL_EN_CMLBUF_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_CH4_PM_CTRL_EN_CMLBUF_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_CH5_PM_CTRL - MOCA PLL channel 5: 50 MHz USDS PLL reference clocks, PLL source post divider powerdown, channel gate on/off and cml buffer enable |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_CH5_PM_CTRL :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CH5_PM_CTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PLL_MOCA_CH5_PM_CTRL_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PLL_MOCA_CH5_PM_CTRL :: DIS_CH [02:02] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CH5_PM_CTRL_DIS_CH_MASK 0x00000004 |
| #define BCHP_CLKGEN_PLL_MOCA_CH5_PM_CTRL_DIS_CH_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MOCA_CH5_PM_CTRL :: CLOCK_ENAB [01:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CH5_PM_CTRL_CLOCK_ENAB_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MOCA_CH5_PM_CTRL_CLOCK_ENAB_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_CH5_PM_CTRL_CLOCK_ENAB_Enable 0 |
| #define BCHP_CLKGEN_PLL_MOCA_CH5_PM_CTRL_CLOCK_ENAB_Disable 1 |
| |
| /* CLKGEN :: PLL_MOCA_CH5_PM_CTRL :: EN_CMLBUF [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CH5_PM_CTRL_EN_CMLBUF_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_CH5_PM_CTRL_EN_CMLBUF_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_CH6_PM_CTRL - MOCA PLL channel 6: 100 MHz MocA digital clock, PLL source post divider powerdown, channel gate on/off and cml buffer enable |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_CH6_PM_CTRL :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CH6_PM_CTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PLL_MOCA_CH6_PM_CTRL_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PLL_MOCA_CH6_PM_CTRL :: DIS_CH [02:02] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CH6_PM_CTRL_DIS_CH_MASK 0x00000004 |
| #define BCHP_CLKGEN_PLL_MOCA_CH6_PM_CTRL_DIS_CH_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MOCA_CH6_PM_CTRL :: CLOCK_ENAB [01:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CH6_PM_CTRL_CLOCK_ENAB_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MOCA_CH6_PM_CTRL_CLOCK_ENAB_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_CH6_PM_CTRL_CLOCK_ENAB_Enable 0 |
| #define BCHP_CLKGEN_PLL_MOCA_CH6_PM_CTRL_CLOCK_ENAB_Disable 1 |
| |
| /* CLKGEN :: PLL_MOCA_CH6_PM_CTRL :: EN_CMLBUF [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_CH6_PM_CTRL_EN_CMLBUF_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_CH6_PM_CTRL_EN_CMLBUF_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MAIN_CTRL - PLL_MAIN Reset Status & DLY |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MAIN_CTRL :: reserved0 [31:07] */ |
| #define BCHP_CLKGEN_PLL_MAIN_CTRL_reserved0_MASK 0xffffff80 |
| #define BCHP_CLKGEN_PLL_MAIN_CTRL_reserved0_SHIFT 7 |
| |
| /* CLKGEN :: PLL_MAIN_CTRL :: PLL_MAIN_DLY_CH6 [06:06] */ |
| #define BCHP_CLKGEN_PLL_MAIN_CTRL_PLL_MAIN_DLY_CH6_MASK 0x00000040 |
| #define BCHP_CLKGEN_PLL_MAIN_CTRL_PLL_MAIN_DLY_CH6_SHIFT 6 |
| |
| /* CLKGEN :: PLL_MAIN_CTRL :: PLL_MAIN_DLY_CH5 [05:05] */ |
| #define BCHP_CLKGEN_PLL_MAIN_CTRL_PLL_MAIN_DLY_CH5_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_MAIN_CTRL_PLL_MAIN_DLY_CH5_SHIFT 5 |
| |
| /* CLKGEN :: PLL_MAIN_CTRL :: PLL_MAIN_DLY_CH4 [04:04] */ |
| #define BCHP_CLKGEN_PLL_MAIN_CTRL_PLL_MAIN_DLY_CH4_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_MAIN_CTRL_PLL_MAIN_DLY_CH4_SHIFT 4 |
| |
| /* CLKGEN :: PLL_MAIN_CTRL :: PLL_MAIN_DLY_CH3 [03:03] */ |
| #define BCHP_CLKGEN_PLL_MAIN_CTRL_PLL_MAIN_DLY_CH3_MASK 0x00000008 |
| #define BCHP_CLKGEN_PLL_MAIN_CTRL_PLL_MAIN_DLY_CH3_SHIFT 3 |
| |
| /* CLKGEN :: PLL_MAIN_CTRL :: PLL_MAIN_DLY_CH2 [02:02] */ |
| #define BCHP_CLKGEN_PLL_MAIN_CTRL_PLL_MAIN_DLY_CH2_MASK 0x00000004 |
| #define BCHP_CLKGEN_PLL_MAIN_CTRL_PLL_MAIN_DLY_CH2_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MAIN_CTRL :: DLY_CH1_PLLMAIN [01:01] */ |
| #define BCHP_CLKGEN_PLL_MAIN_CTRL_DLY_CH1_PLLMAIN_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MAIN_CTRL_DLY_CH1_PLLMAIN_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MAIN_CTRL :: RST_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_MAIN_CTRL_RST_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MAIN_CTRL_RST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MAIN_CH3_PM_CTRL - PLL_MAIN Powerdown 81MHz Main clock |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MAIN_CH3_PM_CTRL :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PLL_MAIN_CH3_PM_CTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PLL_MAIN_CH3_PM_CTRL_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PLL_MAIN_CH3_PM_CTRL :: DIS_CH [02:02] */ |
| #define BCHP_CLKGEN_PLL_MAIN_CH3_PM_CTRL_DIS_CH_MASK 0x00000004 |
| #define BCHP_CLKGEN_PLL_MAIN_CH3_PM_CTRL_DIS_CH_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MAIN_CH3_PM_CTRL :: reserved_for_eco1 [01:00] */ |
| #define BCHP_CLKGEN_PLL_MAIN_CH3_PM_CTRL_reserved_for_eco1_MASK 0x00000003 |
| #define BCHP_CLKGEN_PLL_MAIN_CH3_PM_CTRL_reserved_for_eco1_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MAIN_CH4_PM_CTRL - PLL_MAIN Powerdown 48MHz USB clock |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MAIN_CH4_PM_CTRL :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PLL_MAIN_CH4_PM_CTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PLL_MAIN_CH4_PM_CTRL_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PLL_MAIN_CH4_PM_CTRL :: DIS_CH [02:02] */ |
| #define BCHP_CLKGEN_PLL_MAIN_CH4_PM_CTRL_DIS_CH_MASK 0x00000004 |
| #define BCHP_CLKGEN_PLL_MAIN_CH4_PM_CTRL_DIS_CH_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MAIN_CH4_PM_CTRL :: reserved_for_eco1 [01:01] */ |
| #define BCHP_CLKGEN_PLL_MAIN_CH4_PM_CTRL_reserved_for_eco1_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MAIN_CH4_PM_CTRL_reserved_for_eco1_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MAIN_CH4_PM_CTRL :: EN_CMLBUF [00:00] */ |
| #define BCHP_CLKGEN_PLL_MAIN_CH4_PM_CTRL_EN_CMLBUF_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MAIN_CH4_PM_CTRL_EN_CMLBUF_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MAIN_CH5_PM_CTRL - PLL_MAIN Powerdown 32.4MHz Soft Modem clock |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MAIN_CH5_PM_CTRL :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PLL_MAIN_CH5_PM_CTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PLL_MAIN_CH5_PM_CTRL_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PLL_MAIN_CH5_PM_CTRL :: DIS_CH [02:02] */ |
| #define BCHP_CLKGEN_PLL_MAIN_CH5_PM_CTRL_DIS_CH_MASK 0x00000004 |
| #define BCHP_CLKGEN_PLL_MAIN_CH5_PM_CTRL_DIS_CH_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MAIN_CH5_PM_CTRL :: reserved_for_eco1 [01:00] */ |
| #define BCHP_CLKGEN_PLL_MAIN_CH5_PM_CTRL_reserved_for_eco1_MASK 0x00000003 |
| #define BCHP_CLKGEN_PLL_MAIN_CH5_PM_CTRL_reserved_for_eco1_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MAIN_CH6_PM_CTRL - PLL_MAIN Powerdown 99p7MHz HIF/SATA clock |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MAIN_CH6_PM_CTRL :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PLL_MAIN_CH6_PM_CTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PLL_MAIN_CH6_PM_CTRL_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PLL_MAIN_CH6_PM_CTRL :: DIS_CH [02:02] */ |
| #define BCHP_CLKGEN_PLL_MAIN_CH6_PM_CTRL_DIS_CH_MASK 0x00000004 |
| #define BCHP_CLKGEN_PLL_MAIN_CH6_PM_CTRL_DIS_CH_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MAIN_CH6_PM_CTRL :: reserved_for_eco1 [01:00] */ |
| #define BCHP_CLKGEN_PLL_MAIN_CH6_PM_CTRL_reserved_for_eco1_MASK 0x00000003 |
| #define BCHP_CLKGEN_PLL_MAIN_CH6_PM_CTRL_reserved_for_eco1_SHIFT 0 |
| |
| /*************************************************************************** |
| *PAD_CLOCK - PAD Clock Control Register |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CLOCK :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PAD_CLOCK_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PAD_CLOCK :: CLK_ACC_TEST_SEL [12:07] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_CLK_ACC_TEST_SEL_MASK 0x00001f80 |
| #define BCHP_CLKGEN_PAD_CLOCK_CLK_ACC_TEST_SEL_SHIFT 7 |
| |
| /* CLKGEN :: PAD_CLOCK :: CLOCK_ACC_TEST_DIVIDE_EN [06:06] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_CLOCK_ACC_TEST_DIVIDE_EN_MASK 0x00000040 |
| #define BCHP_CLKGEN_PAD_CLOCK_CLOCK_ACC_TEST_DIVIDE_EN_SHIFT 6 |
| |
| /* CLKGEN :: PAD_CLOCK :: CLOCK_ACC_TEST_MODE [05:05] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_CLOCK_ACC_TEST_MODE_MASK 0x00000020 |
| #define BCHP_CLKGEN_PAD_CLOCK_CLOCK_ACC_TEST_MODE_SHIFT 5 |
| |
| /* CLKGEN :: PAD_CLOCK :: ACC_PAD_CLOCK_SEL [04:04] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_ACC_PAD_CLOCK_SEL_MASK 0x00000010 |
| #define BCHP_CLKGEN_PAD_CLOCK_ACC_PAD_CLOCK_SEL_SHIFT 4 |
| |
| /* CLKGEN :: PAD_CLOCK :: reserved_for_eco1 [03:03] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_reserved_for_eco1_MASK 0x00000008 |
| #define BCHP_CLKGEN_PAD_CLOCK_reserved_for_eco1_SHIFT 3 |
| |
| /* CLKGEN :: PAD_CLOCK :: CLK_27_OUT_INV [02:02] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_CLK_27_OUT_INV_MASK 0x00000004 |
| #define BCHP_CLKGEN_PAD_CLOCK_CLK_27_OUT_INV_SHIFT 2 |
| |
| /* CLKGEN :: PAD_CLOCK :: CLK_27_OUT_SEL [01:00] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_CLK_27_OUT_SEL_MASK 0x00000003 |
| #define BCHP_CLKGEN_PAD_CLOCK_CLK_27_OUT_SEL_SHIFT 0 |
| |
| /*************************************************************************** |
| *HIF_CLOCK_SEL - Select 108/99.7 clock to HIF |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_CLOCK_SEL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_SEL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_HIF_CLOCK_SEL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: HIF_CLOCK_SEL :: HIF_CLOCK_SEL [00:00] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_SEL_HIF_CLOCK_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_HIF_CLOCK_SEL_HIF_CLOCK_SEL_SHIFT 0 |
| |
| /*************************************************************************** |
| *MISC_CLOCK_SELECTS - Misc clock selects in chip. |
| ***************************************************************************/ |
| /* CLKGEN :: MISC_CLOCK_SELECTS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_MISC_CLOCK_SELECTS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_MISC_CLOCK_SELECTS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: MISC_CLOCK_SELECTS :: CLOCK_SEL_ENET_CG_MOCA [01:01] */ |
| #define BCHP_CLKGEN_MISC_CLOCK_SELECTS_CLOCK_SEL_ENET_CG_MOCA_MASK 0x00000002 |
| #define BCHP_CLKGEN_MISC_CLOCK_SELECTS_CLOCK_SEL_ENET_CG_MOCA_SHIFT 1 |
| |
| /* CLKGEN :: MISC_CLOCK_SELECTS :: CLOCK_SEL_GMII_CG_MOCA [00:00] */ |
| #define BCHP_CLKGEN_MISC_CLOCK_SELECTS_CLOCK_SEL_GMII_CG_MOCA_MASK 0x00000001 |
| #define BCHP_CLKGEN_MISC_CLOCK_SELECTS_CLOCK_SEL_GMII_CG_MOCA_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_TEST_CTRL - PLL_TEST_CTRL Control Register |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_TEST_CTRL :: reserved0 [31:10] */ |
| #define BCHP_CLKGEN_PLL_TEST_CTRL_reserved0_MASK 0xfffffc00 |
| #define BCHP_CLKGEN_PLL_TEST_CTRL_reserved0_SHIFT 10 |
| |
| /* CLKGEN :: PLL_TEST_CTRL :: MOCA_ENA [09:09] */ |
| #define BCHP_CLKGEN_PLL_TEST_CTRL_MOCA_ENA_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_TEST_CTRL_MOCA_ENA_SHIFT 9 |
| |
| /* CLKGEN :: PLL_TEST_CTRL :: CPU_ENA [08:08] */ |
| #define BCHP_CLKGEN_PLL_TEST_CTRL_CPU_ENA_MASK 0x00000100 |
| #define BCHP_CLKGEN_PLL_TEST_CTRL_CPU_ENA_SHIFT 8 |
| |
| /* CLKGEN :: PLL_TEST_CTRL :: MOCA_SEL [07:05] */ |
| #define BCHP_CLKGEN_PLL_TEST_CTRL_MOCA_SEL_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_TEST_CTRL_MOCA_SEL_SHIFT 5 |
| |
| /* CLKGEN :: PLL_TEST_CTRL :: CPU_SEL [04:01] */ |
| #define BCHP_CLKGEN_PLL_TEST_CTRL_CPU_SEL_MASK 0x0000001e |
| #define BCHP_CLKGEN_PLL_TEST_CTRL_CPU_SEL_SHIFT 1 |
| |
| /* CLKGEN :: PLL_TEST_CTRL :: reserved_for_eco1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_TEST_CTRL_reserved_for_eco1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_TEST_CTRL_reserved_for_eco1_SHIFT 0 |
| |
| /*************************************************************************** |
| *DIFFOSC_TEST_CTRL - DIFFOSC_TEST_CTRL Control Register |
| ***************************************************************************/ |
| /* CLKGEN :: DIFFOSC_TEST_CTRL :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_DIFFOSC_TEST_CTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_DIFFOSC_TEST_CTRL_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: DIFFOSC_TEST_CTRL :: LIMITER_EN_DIFFOSC [01:01] */ |
| #define BCHP_CLKGEN_DIFFOSC_TEST_CTRL_LIMITER_EN_DIFFOSC_MASK 0x00000002 |
| #define BCHP_CLKGEN_DIFFOSC_TEST_CTRL_LIMITER_EN_DIFFOSC_SHIFT 1 |
| |
| /* CLKGEN :: DIFFOSC_TEST_CTRL :: TEST_EN_DIFFOSC [00:00] */ |
| #define BCHP_CLKGEN_DIFFOSC_TEST_CTRL_TEST_EN_DIFFOSC_MASK 0x00000001 |
| #define BCHP_CLKGEN_DIFFOSC_TEST_CTRL_TEST_EN_DIFFOSC_SHIFT 0 |
| |
| /*************************************************************************** |
| *MIPS_PLL_CTRL - MIPS_PLL_CTRL Register |
| ***************************************************************************/ |
| /* CLKGEN :: MIPS_PLL_CTRL :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_MIPS_PLL_CTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_MIPS_PLL_CTRL_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: MIPS_PLL_CTRL :: LDO_CTRL [01:00] */ |
| #define BCHP_CLKGEN_MIPS_PLL_CTRL_LDO_CTRL_MASK 0x00000003 |
| #define BCHP_CLKGEN_MIPS_PLL_CTRL_LDO_CTRL_SHIFT 0 |
| |
| /*************************************************************************** |
| *D2CDIFF_AC_CTRL - AC_CTRL for D2CDIFF |
| ***************************************************************************/ |
| /* CLKGEN :: D2CDIFF_AC_CTRL :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: D2CDIFF_AC_CTRL :: OSC_STATUS [13:13] */ |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_OSC_STATUS_MASK 0x00002000 |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_OSC_STATUS_SHIFT 13 |
| |
| /* CLKGEN :: D2CDIFF_AC_CTRL :: MOCA_STATUS [12:12] */ |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MOCA_STATUS_MASK 0x00001000 |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MOCA_STATUS_SHIFT 12 |
| |
| /* CLKGEN :: D2CDIFF_AC_CTRL :: RPTD_STATUS [11:11] */ |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_RPTD_STATUS_MASK 0x00000800 |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_RPTD_STATUS_SHIFT 11 |
| |
| /* CLKGEN :: D2CDIFF_AC_CTRL :: AVD_STATUS [10:10] */ |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_AVD_STATUS_MASK 0x00000400 |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_AVD_STATUS_SHIFT 10 |
| |
| /* CLKGEN :: D2CDIFF_AC_CTRL :: MIPS_STATUS [09:09] */ |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MIPS_STATUS_MASK 0x00000200 |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MIPS_STATUS_SHIFT 9 |
| |
| /* CLKGEN :: D2CDIFF_AC_CTRL :: MAIN_STATUS [08:08] */ |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MAIN_STATUS_MASK 0x00000100 |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MAIN_STATUS_SHIFT 8 |
| |
| /* CLKGEN :: D2CDIFF_AC_CTRL :: reserved_for_eco1 [07:06] */ |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_reserved_for_eco1_MASK 0x000000c0 |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_reserved_for_eco1_SHIFT 6 |
| |
| /* CLKGEN :: D2CDIFF_AC_CTRL :: OSC_XOR [05:05] */ |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_OSC_XOR_MASK 0x00000020 |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_OSC_XOR_SHIFT 5 |
| |
| /* CLKGEN :: D2CDIFF_AC_CTRL :: MOCA_XOR [04:04] */ |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MOCA_XOR_MASK 0x00000010 |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MOCA_XOR_SHIFT 4 |
| |
| /* CLKGEN :: D2CDIFF_AC_CTRL :: RPTD_XOR [03:03] */ |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_RPTD_XOR_MASK 0x00000008 |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_RPTD_XOR_SHIFT 3 |
| |
| /* CLKGEN :: D2CDIFF_AC_CTRL :: AVD_XOR [02:02] */ |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_AVD_XOR_MASK 0x00000004 |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_AVD_XOR_SHIFT 2 |
| |
| /* CLKGEN :: D2CDIFF_AC_CTRL :: MIPS_XOR [01:01] */ |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MIPS_XOR_MASK 0x00000002 |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MIPS_XOR_SHIFT 1 |
| |
| /* CLKGEN :: D2CDIFF_AC_CTRL :: MAIN_XOR [00:00] */ |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MAIN_XOR_MASK 0x00000001 |
| #define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MAIN_XOR_SHIFT 0 |
| |
| /*************************************************************************** |
| *SMARTCARD_CLOCK_CTRL - SMARTCARD_CLOCK_CTRL Register |
| ***************************************************************************/ |
| /* CLKGEN :: SMARTCARD_CLOCK_CTRL :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_SMARTCARD_CLOCK_CTRL_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_SMARTCARD_CLOCK_CTRL_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: SMARTCARD_CLOCK_CTRL :: SMARTCARD_PLL_REFERENCE_CLK_SEL [04:04] */ |
| #define BCHP_CLKGEN_SMARTCARD_CLOCK_CTRL_SMARTCARD_PLL_REFERENCE_CLK_SEL_MASK 0x00000010 |
| #define BCHP_CLKGEN_SMARTCARD_CLOCK_CTRL_SMARTCARD_PLL_REFERENCE_CLK_SEL_SHIFT 4 |
| |
| /* CLKGEN :: SMARTCARD_CLOCK_CTRL :: SMARTCARD_CLOCK_2_SOURCE_SEL [03:02] */ |
| #define BCHP_CLKGEN_SMARTCARD_CLOCK_CTRL_SMARTCARD_CLOCK_2_SOURCE_SEL_MASK 0x0000000c |
| #define BCHP_CLKGEN_SMARTCARD_CLOCK_CTRL_SMARTCARD_CLOCK_2_SOURCE_SEL_SHIFT 2 |
| |
| /* CLKGEN :: SMARTCARD_CLOCK_CTRL :: SMARTCARD_CLOCK_1_SOURCE_SEL [01:00] */ |
| #define BCHP_CLKGEN_SMARTCARD_CLOCK_CTRL_SMARTCARD_CLOCK_1_SOURCE_SEL_MASK 0x00000003 |
| #define BCHP_CLKGEN_SMARTCARD_CLOCK_CTRL_SMARTCARD_CLOCK_1_SOURCE_SEL_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_TIMER_SELECT - Select the delay after reset before using PLL |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_TIMER_SELECT :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_TIMER_SELECT_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_TIMER_SELECT_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_TIMER_SELECT :: TIMER [01:00] */ |
| #define BCHP_CLKGEN_PLL_TIMER_SELECT_TIMER_MASK 0x00000003 |
| #define BCHP_CLKGEN_PLL_TIMER_SELECT_TIMER_SHIFT 0 |
| |
| /*************************************************************************** |
| *PM_PLL_ALIVE_SEL - Program the PLLs to be alive in standby |
| ***************************************************************************/ |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: DDR_PLL [02:02] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DDR_PLL_MASK 0x00000004 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DDR_PLL_SHIFT 2 |
| |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: MIPS_PLL [01:01] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_MIPS_PLL_MASK 0x00000002 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_MIPS_PLL_SHIFT 1 |
| |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: MAIN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_MAIN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_MAIN_PLL_SHIFT 0 |
| |
| /*************************************************************************** |
| *PM_CLOCK_216_108_ALIVE_SEL - Program the 216/108 clocks to be alive in standby |
| ***************************************************************************/ |
| /* CLKGEN :: PM_CLOCK_216_108_ALIVE_SEL :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PM_CLOCK_216_108_ALIVE_SEL :: CLOCK_108_CG_XPT [01:01] */ |
| #define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_108_CG_XPT_MASK 0x00000002 |
| #define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_108_CG_XPT_SHIFT 1 |
| |
| /* CLKGEN :: PM_CLOCK_216_108_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */ |
| #define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_216_CG_XPT_MASK 0x00000001 |
| #define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT 0 |
| |
| /*************************************************************************** |
| *REVISION - Chip Revision |
| ***************************************************************************/ |
| /* CLKGEN :: REVISION :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_REVISION_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_REVISION_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: REVISION :: MAJOR [15:08] */ |
| #define BCHP_CLKGEN_REVISION_MAJOR_MASK 0x0000ff00 |
| #define BCHP_CLKGEN_REVISION_MAJOR_SHIFT 8 |
| |
| /* CLKGEN :: REVISION :: MINOR [07:00] */ |
| #define BCHP_CLKGEN_REVISION_MINOR_MASK 0x000000ff |
| #define BCHP_CLKGEN_REVISION_MINOR_SHIFT 0 |
| |
| /*************************************************************************** |
| *SCRATCH_REG - Scratch Register |
| ***************************************************************************/ |
| /* CLKGEN :: SCRATCH_REG :: VALUE [31:00] */ |
| #define BCHP_CLKGEN_SCRATCH_REG_VALUE_MASK 0xffffffff |
| #define BCHP_CLKGEN_SCRATCH_REG_VALUE_SHIFT 0 |
| |
| #endif /* #ifndef BCHP_CLKGEN_H__ */ |
| |
| /* End of File */ |
