| /*************************************************************************** |
| * Copyright (c) 1999-2012, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Tue Aug 7 03:07:16 2012 |
| * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: $ |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_CLKGEN_H__ |
| #define BCHP_CLKGEN_H__ |
| |
| /*************************************************************************** |
| *CLKGEN - clkgen registers |
| ***************************************************************************/ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL 0x00420000 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV 0x00420004 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN 0x00420008 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS 0x0042000c /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN 0x00420010 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET 0x00420014 /* Resets */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x00420018 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x0042001c /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS 0x00420020 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL 0x00420024 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV 0x00420028 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN 0x0042002c /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS 0x00420030 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN 0x00420034 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET 0x00420038 /* Resets */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x0042003c /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x00420040 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS 0x00420044 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 0x00420048 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 0x0042004c /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 0x00420050 /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 0x00420054 /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 0x00420058 /* PLL CHANNEL control CH 4 */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5 0x0042005c /* PLL CHANNEL control CH 5 */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL 0x00420060 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV 0x00420064 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN 0x00420068 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS 0x0042006c /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC 0x00420070 /* Miscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2 0x00420074 /* Miscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN 0x00420078 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET 0x0042007c /* Resets */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH 0x00420080 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW 0x00420084 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS 0x00420088 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0 0x0042008c /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1 0x00420090 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2 0x00420094 /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3 0x00420098 /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CONTROL 0x0042009c /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV 0x004200a0 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN 0x004200a4 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS 0x004200a8 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC 0x004200ac /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_PWRDN 0x004200b0 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET 0x004200b4 /* Resets */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH 0x004200b8 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW 0x004200bc /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_STATUS 0x004200c0 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x004200c4 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x004200c8 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x004200cc /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x004200d0 /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x004200d4 /* PLL CHANNEL control CH 4 */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x004200d8 /* PLL CHANNEL control CH 5 */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL 0x004200dc /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV 0x004200e0 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN 0x004200e4 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS 0x004200e8 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC 0x004200ec /* Miscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2 0x004200f0 /* Miscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN 0x004200f4 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_RESET 0x004200f8 /* Resets */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x004200fc /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x00420100 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS 0x00420104 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 0x00420108 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 0x0042010c /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 0x00420110 /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 0x00420114 /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 0x00420118 /* PLL CHANNEL control CH 4 */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL 0x0042011c /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV 0x00420120 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN 0x00420124 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS 0x00420128 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC 0x0042012c /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN 0x00420130 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET 0x00420134 /* Resets */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH 0x00420138 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW 0x0042013c /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS 0x00420140 /* Status */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 0x00420144 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 0x00420148 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 0x0042014c /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL 0x00420150 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV 0x00420154 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC 0x00420158 /* Fractional */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN 0x0042015c /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS 0x00420160 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC 0x00420164 /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN 0x00420168 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET 0x0042016c /* Resets */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH 0x00420170 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW 0x00420174 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS 0x00420178 /* Status */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE 0x0042017c /* Avd0 top clock enable */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS 0x00420180 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE 0x00420184 /* Avd0 top memory standby enable */ |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK 0x00420188 /* Avd0 top observe clock */ |
| #define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY 0x0042018c /* Avd0 top power switch memory */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE 0x00420190 /* Bcm mips top clock enable */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS 0x00420194 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE 0x00420198 /* Bcm mips top memory standby enable */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK 0x0042019c /* Bcm mips top observe clock */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY 0x004201a0 /* Bcm mips top power switch memory */ |
| #define BCHP_CLKGEN_BSPI_CLOCK_MUX_SELECT 0x004201a4 /* Mux selects for BSPI_CLOCK clocks */ |
| #define BCHP_CLKGEN_BVN_TOP_ENABLE 0x004201a8 /* Bvn top enable */ |
| #define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE 0x004201ac /* Bvn top memory standby enable */ |
| #define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY 0x004201b0 /* Bvn top power switch memory */ |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201b4 /* Cktap 108 0 cktap cpu adjustment selection */ |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201b8 /* Cktap 108 1 cktap cpu adjustment selection */ |
| #define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201bc /* Cktap 108 2 cktap cpu adjustment selection */ |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201c0 /* Cktap 216 0 cktap cpu adjustment selection */ |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK 0x004201c4 /* CKTAP CPU Adjustment System 108 Clock */ |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK 0x004201c8 /* CKTAP CPU Adjustment System 216 Clock */ |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK 0x004201cc /* CKTAP CPU Adjustment System Scb Clock */ |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201d0 /* Cktap scb 0 cktap cpu adjustment selection */ |
| #define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201d4 /* Cktap scb 1 cktap cpu adjustment selection */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE 0x004201d8 /* Disable CLKGEN's clocks */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS 0x004201dc /* Clock Disable Status */ |
| #define BCHP_CLKGEN_CLKGEN_TS_CONTROL 0x004201e0 /* Clkgen ts control */ |
| #define BCHP_CLKGEN_CLKGEN_TS_DATA 0x004201e4 /* Clkgen ts data */ |
| #define BCHP_CLKGEN_CLKGEN_TS_STATUS 0x004201e8 /* Clkgen ts status */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL 0x004201ec /* Clock Monitor Control */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT 0x004201f0 /* Clock Monitor Max Reference Count */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER 0x004201f4 /* Clock Monitor Reference Counter */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE 0x004201f8 /* Clock Monitor Reference Counter */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER 0x004201fc /* Clock Monitor View Counter */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE 0x00420200 /* Disable CORE_XPT's clocks */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS 0x00420204 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE 0x00420208 /* Core xpt clock enable */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS 0x0042020c /* Clock Enable Status */ |
| #define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE 0x00420210 /* Core xpt memory standby enable */ |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK 0x00420214 /* Core xpt observe clock */ |
| #define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY 0x00420218 /* Core xpt power switch memory */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE 0x0042021c /* Disable DVP_HT's clocks */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_STATUS 0x00420220 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE 0x00420224 /* Dvp ht clock enable */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS 0x00420228 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_DVP_HT_ENABLE 0x0042022c /* Dvp ht enable */ |
| #define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE 0x00420230 /* Dvp ht memory standby enable */ |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK 0x00420234 /* Dvp ht observe clock */ |
| #define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY 0x00420238 /* Dvp ht power switch memory */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_BYPASS 0x0042023c /* Genet top rgmii inst bypass */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE 0x00420240 /* Disable GENET_TOP_RGMII_INST's clocks */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS 0x00420244 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE 0x00420248 /* Genet top rgmii inst clock enable */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS 0x0042024c /* Clock Enable Status */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT 0x00420250 /* Genet top rgmii inst clock select */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A 0x00420254 /* Genet top rgmii inst memory standby enable a */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK 0x00420258 /* Genet top rgmii inst observe clock */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A 0x0042025c /* Genet top rgmii inst power switch memory a */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE 0x00420260 /* Disable GRAPHICS's clocks */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_STATUS 0x00420264 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE 0x00420268 /* Graphics clock enable */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_STATUS 0x0042026c /* Clock Enable Status */ |
| #define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE 0x00420270 /* Graphics memory standby enable */ |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK 0x00420274 /* Graphics observe clock */ |
| #define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY 0x00420278 /* Graphics power switch memory */ |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE 0x0042027c /* Disable HIF's clocks */ |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_STATUS 0x00420280 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE 0x00420284 /* Hif clock enable */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_STATUS 0x00420288 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE 0x0042028c /* Hif memory standby enable */ |
| #define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY 0x00420290 /* Hif power switch memory */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT 0x00420294 /* Mux selects for Internal clocks */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE 0x00420298 /* Disable LEAP_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS 0x0042029c /* Clock Disable Status */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE 0x004202a0 /* Leap top inst clock enable */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS 0x004202a4 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_DATA 0x004202a8 /* Leap top inst data */ |
| #define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE 0x004202ac /* Memsys 16 clock enable */ |
| #define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_STATUS 0x004202b0 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE 0x004202b4 /* Memsys 16 memory standby enable */ |
| #define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK 0x004202b8 /* Memsys 16 observe clock */ |
| #define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY 0x004202bc /* Memsys 16 power switch memory */ |
| #define BCHP_CLKGEN_MEMSYS_16_STATUS 0x004202c0 /* Memsys 16 status */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION 0x004202c4 /* Select observation clk */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION 0x004202c8 /* Select observation clk */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION 0x004202cc /* Select observation clk */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION 0x004202d0 /* Select observation clk */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE 0x004202d4 /* Disable PAD's clocks */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS 0x004202d8 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT 0x004202dc /* Mux selects for Pad clocks */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS 0x004202e0 /* PLL_AUDIO0 Reset Status */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS 0x004202e4 /* PLL_AUDIO1 Reset Status */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST 0x004202e8 /* PLL_AVD_MIPS Glitchless Clock Switching */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_STATUS 0x004202ec /* PLL_AVD_MIPS Glitchless Switching */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_STATUS 0x004202f0 /* PLL_AVD_MIPS Reset Status */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS 0x004202f4 /* PLL_SC Reset Status */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS 0x004202f8 /* PLL_SYS1 Reset Status */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS 0x004202fc /* PLL_VCXO Reset Status */ |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL 0x00420300 /* Select clocks that can stay alive during power management standby mode. */ |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL 0x00420304 /* Select clocks that can stay alive during power management standby mode. */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL 0x00420308 /* PLL Alive in Standby Mode */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM 0x0042030c /* Power management LDO PLL state machine */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE 0x00420310 /* Raaga dsp top clock enable */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS 0x00420314 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE 0x00420318 /* Raaga dsp top memory standby enable */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK 0x0042031c /* Raaga dsp top observe clock */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY 0x00420320 /* Raaga dsp top power switch memory */ |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE 0x00420324 /* Sectop inst clock enable */ |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS 0x00420328 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE 0x0042032c /* Sectop inst memory standby enable */ |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK 0x00420330 /* Sectop inst observe clock */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT 0x00420334 /* Mux selects for Smartcard clocks */ |
| #define BCHP_CLKGEN_SPARE 0x00420338 /* Spares */ |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK 0x0042033c /* Sys aon observe clock */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE 0x00420340 /* Disable SYS_CTRL's clocks */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS 0x00420344 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE 0x00420348 /* Sys ctrl clock enable */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_STATUS 0x0042034c /* Clock Enable Status */ |
| #define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE 0x00420350 /* Sys ctrl memory standby enable */ |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK 0x00420354 /* Sys ctrl observe clock */ |
| #define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY 0x00420358 /* Sys ctrl power switch memory */ |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_DISABLE 0x0042035c /* Disable T2_BICM_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_DISABLE_STATUS 0x00420360 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_ENABLE 0x00420364 /* T2 bicm top inst clock enable */ |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_ENABLE_STATUS 0x00420368 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_MEMORY_STANDBY_ENABLE 0x0042036c /* T2 bicm top inst memory standby enable */ |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_POWER_SWITCH_MEMORY0 0x00420370 /* T2 bicm top inst power switch memory0 */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_DISABLE 0x00420374 /* Disable T2_RCVR_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_DISABLE_STATUS 0x00420378 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_ENABLE 0x0042037c /* T2 rcvr top inst clock enable */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_ENABLE_STATUS 0x00420380 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_MEMORY_STANDBY_ENABLE 0x00420384 /* T2 rcvr top inst memory standby enable */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY0 0x00420388 /* T2 rcvr top inst power switch memory0 */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY1 0x0042038c /* T2 rcvr top inst power switch memory1 */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY2 0x00420390 /* T2 rcvr top inst power switch memory2 */ |
| #define BCHP_CLKGEN_TESTPORT 0x00420394 /* Special Testport Controls */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_CM0 0x00420398 /* Tm registers inst cm0 */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_CM1 0x0042039c /* Tm registers inst cm1 */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_CM2 0x004203a0 /* Tm registers inst cm2 */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_CM3 0x004203a4 /* Tm registers inst cm3 */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_MEMCTRL 0x004203a8 /* Tm registers inst memctrl */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_MEMCTRL2 0x004203ac /* Tm registers inst memctrl2 */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_OSCCLKEN 0x004203b0 /* Tm registers inst oscclken */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_PWRDN 0x004203b4 /* Tm registers inst pwrdn */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_REVID 0x004203b8 /* Tm registers inst revid */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT0 0x004203bc /* Tm registers inst sft0 */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT1 0x004203c0 /* Tm registers inst sft1 */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT2 0x004203c4 /* Tm registers inst sft2 */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT3 0x004203c8 /* Tm registers inst sft3 */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT4 0x004203cc /* Tm registers inst sft4 */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT5 0x004203d0 /* Tm registers inst sft5 */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT6 0x004203d4 /* Tm registers inst sft6 */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT7 0x004203d8 /* Tm registers inst sft7 */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFTRST 0x004203dc /* Tm registers inst sftrst */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSCLKEN 0x004203e0 /* Tm registers inst sysclken */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLCLK216 0x004203e4 /* Tm registers inst syspllclk216 */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLCLKT2B 0x004203e8 /* Tm registers inst syspllclkt2b */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLNDIVINT 0x004203ec /* Tm registers inst syspllndivint */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLPDIV 0x004203f0 /* Tm registers inst syspllpdiv */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLRST 0x004203f4 /* Tm registers inst syspllrst */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLSTATUS 0x004203f8 /* Tm registers inst syspllstatus */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_TSCTRL 0x004203fc /* Tm registers inst tsctrl */ |
| #define BCHP_CLKGEN_UFE_TOP_INST_CLOCK_ENABLE 0x00420400 /* Ufe top inst clock enable */ |
| #define BCHP_CLKGEN_UFE_TOP_INST_CLOCK_ENABLE_STATUS 0x00420404 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_UFE_TOP_INST_MEMORY_STANDBY_ENABLE 0x00420408 /* Ufe top inst memory standby enable */ |
| #define BCHP_CLKGEN_UFE_TOP_INST_OBSERVE_CLOCK 0x0042040c /* Ufe top inst observe clock */ |
| #define BCHP_CLKGEN_UFE_TOP_INST_POWER_SWITCH_MEMORY 0x00420410 /* Ufe top inst power switch memory */ |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE 0x00420414 /* Usb clock enable */ |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_STATUS 0x00420418 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE 0x0042041c /* Usb memory standby enable */ |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK 0x00420420 /* Usb observe clock */ |
| #define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY 0x00420424 /* Usb power switch memory */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE 0x00420428 /* Disable VEC_AIO_TOP's clocks */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_STATUS 0x0042042c /* Clock Disable Status */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE 0x00420430 /* Vec aio top clock enable */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_STATUS 0x00420434 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A 0x00420438 /* Vec aio top memory standby enable a */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B 0x0042043c /* Vec aio top memory standby enable b */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK 0x00420440 /* Vec aio top observe clock */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC 0x00420444 /* Vec aio top observe clock vec */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A 0x00420448 /* Vec aio top power switch memory a */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B 0x0042044c /* Vec aio top power switch memory b */ |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [02:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [02:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000005 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000008 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000006 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000005 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x0000000a |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000005 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_MIPS_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_MIPS_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: PDIV [12:10] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_DEFAULT 0x0000004c |
| |
| /*************************************************************************** |
| *PLL_AVD_MIPS_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_MIPS_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AVD_MIPS_PLL_MISC - Miscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: reserved0 [31:31] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_reserved0_MASK 0x80000000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_reserved0_SHIFT 31 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: VCO_DLY [30:29] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_MASK 0x60000000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: VCODIV2 [28:28] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_UPDATE [27:27] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_SELECT [26:24] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_MASK 0x07000000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_RESET_ [23:23] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__SHIFT 23 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_MODE [22:21] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_MASK 0x00600000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_SHIFT 21 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: REFCLKOUT [20:20] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_MASK 0x00100000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: PWM_RATE [19:18] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_MASK 0x000c0000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: POR_BYPASS [17:17] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_MASK 0x00020000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_SHIFT 17 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: NDIV_RELOCK [16:16] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_MASK 0x00010000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: LDO_REF_SEL [15:15] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: FAST_LOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_MIPS_PLL_MISC2 - Miscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_MISC2 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_MISC2 :: SPARE [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_MIPS_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_MIPS_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_MIPS_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000028 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000028 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000008 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000032 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_SC_PLL_DIV :: PDIV [12:10] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_SC_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_DEFAULT 0x00000040 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_SC_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007 |
| |
| /* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_SC_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_MISC :: reserved0 [31:30] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_MASK 0xc0000000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_SHIFT 30 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: VCO_DLY [29:28] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_MASK 0x30000000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2_POST [27:27] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2 [26:26] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_MASK 0x04000000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_SHIFT 26 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: STAT_UPDATE [25:25] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_MASK 0x02000000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_SHIFT 25 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: STAT_SELECT [24:22] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_MASK 0x01c00000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: STAT_RESET_ [21:21] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__MASK 0x00200000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__SHIFT 21 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: STAT_MODE [20:19] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_MASK 0x00180000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_SHIFT 19 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: REFCLKOUT [18:18] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_MASK 0x00040000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: PWM_RATE [17:16] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_MASK 0x00030000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: MDIV_RELOCK [15:15] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: FAST_LOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SC_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_SC_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000006 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000c |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000008 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000c |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000060 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000036 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [12:10] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT 0x00000060 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_MISC - Miscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: reserved0 [31:31] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_MASK 0x80000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_SHIFT 31 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DLY [30:29] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_MASK 0x60000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: VCODIV2 [28:28] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [27:27] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [26:24] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK 0x07000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET_ [23:23] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__SHIFT 23 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [22:21] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK 0x00600000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT 21 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: REFCLKOUT [20:20] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_MASK 0x00100000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [19:18] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK 0x000c0000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: POR_BYPASS [17:17] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_MASK 0x00020000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_SHIFT 17 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK 0x00010000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: LDO_REF_SEL [15:15] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_MISC2 - Miscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_MISC2 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC2 :: SPARE [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_RESET :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_RESET :: RESETD [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000012 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000005a |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000009 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x0000005a |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_DIV :: PDIV [12:10] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_DEFAULT 0x0000007d |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: reserved0 [31:30] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_MASK 0xc0000000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_SHIFT 30 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: VCO_DLY [29:28] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_MASK 0x30000000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2_POST [27:27] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2 [26:26] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_MASK 0x04000000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_SHIFT 26 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_UPDATE [25:25] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_MASK 0x02000000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_SHIFT 25 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_SELECT [24:22] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_MASK 0x01c00000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_RESET_ [21:21] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__MASK 0x00200000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__SHIFT 21 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_MODE [20:19] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_MASK 0x00180000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_SHIFT 19 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: REFCLKOUT [18:18] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_MASK 0x00040000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: PWM_RATE [17:16] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_MASK 0x00030000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: MDIV_RELOCK [15:15] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: FAST_LOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_STATUS - Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000004b |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000004b |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x000000fa |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_DIV :: PDIV [12:10] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_DEFAULT 0x00000040 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_FRAC - Fractional |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_FRAC :: reserved0 [31:20] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_MASK 0xfff00000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_SHIFT 20 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_FRAC :: FRAC_CONTROL [19:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: reserved0 [31:30] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_MASK 0xc0000000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_SHIFT 30 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: VCO_DLY [29:28] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_MASK 0x30000000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2_POST [27:27] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2 [26:26] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_MASK 0x04000000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_SHIFT 26 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_UPDATE [25:25] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_MASK 0x02000000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_SHIFT 25 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_SELECT [24:22] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_MASK 0x01c00000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_RESET_ [21:21] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__MASK 0x00200000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__SHIFT 21 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_MODE [20:19] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_MASK 0x00180000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_SHIFT 19 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: REFCLKOUT [18:18] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_MASK 0x00040000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: PWM_RATE [17:16] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_MASK 0x00030000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: MDIV_RELOCK [15:15] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: FAST_LOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_STATUS - Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *AVD0_TOP_CLOCK_ENABLE - Avd0 top clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_SCB_CLOCK_ENABLE [04:04] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_MASK 0x00000010 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_SHIFT 4 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_CPU_CLOCK_ENABLE [03:03] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_MASK 0x00000008 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_SHIFT 3 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_AVD_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_ALTERNATE_SCB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *AVD0_TOP_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE_STATUS :: SVD_SCB_CLOCK_ENABLE_STATUS [04:04] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_SVD_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_SVD_SCB_CLOCK_ENABLE_STATUS_SHIFT 4 |
| |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE_STATUS :: SVD_CPU_CLOCK_ENABLE_STATUS [03:03] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_SVD_CPU_CLOCK_ENABLE_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_SVD_CPU_CLOCK_ENABLE_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE_STATUS :: SVD_AVD_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_SVD_AVD_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_SVD_AVD_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE_STATUS :: SVD_ALTERNATE_SCB_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_SVD_ALTERNATE_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_SVD_ALTERNATE_SCB_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE_STATUS :: SVD_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_SVD_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_SVD_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *AVD0_TOP_MEMORY_STANDBY_ENABLE - Avd0 top memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: AVD0_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: AVD0_TOP_MEMORY_STANDBY_ENABLE :: SVD_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *AVD0_TOP_OBSERVE_CLOCK - Avd0 top observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *AVD0_TOP_POWER_SWITCH_MEMORY - Avd0 top power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: AVD0_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: AVD0_TOP_POWER_SWITCH_MEMORY :: SVD_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BCM_MIPS_TOP_CLOCK_ENABLE - Bcm mips top clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_SCB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_216_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *BCM_MIPS_TOP_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE_STATUS :: MIPS_SCB_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_MIPS_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_MIPS_SCB_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE_STATUS :: MIPS_216_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_MIPS_216_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_MIPS_216_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE_STATUS :: MIPS_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_MIPS_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_MIPS_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE - Bcm mips top memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: MIPS_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BCM_MIPS_TOP_OBSERVE_CLOCK - Bcm mips top observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BCM_MIPS_TOP_POWER_SWITCH_MEMORY - Bcm mips top power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: MIPS_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BSPI_CLOCK_MUX_SELECT - Mux selects for BSPI_CLOCK clocks |
| ***************************************************************************/ |
| /* CLKGEN :: BSPI_CLOCK_MUX_SELECT :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_BSPI_CLOCK_MUX_SELECT_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_BSPI_CLOCK_MUX_SELECT_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: BSPI_CLOCK_MUX_SELECT :: HIF_SPI_CLOCK [02:01] */ |
| #define BCHP_CLKGEN_BSPI_CLOCK_MUX_SELECT_HIF_SPI_CLOCK_MASK 0x00000006 |
| #define BCHP_CLKGEN_BSPI_CLOCK_MUX_SELECT_HIF_SPI_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_BSPI_CLOCK_MUX_SELECT_HIF_SPI_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: BSPI_CLOCK_MUX_SELECT :: STRAP_OVERRIDE_HIF_SPI_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_BSPI_CLOCK_MUX_SELECT_STRAP_OVERRIDE_HIF_SPI_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_BSPI_CLOCK_MUX_SELECT_STRAP_OVERRIDE_HIF_SPI_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_BSPI_CLOCK_MUX_SELECT_STRAP_OVERRIDE_HIF_SPI_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BVN_TOP_ENABLE - Bvn top enable |
| ***************************************************************************/ |
| /* CLKGEN :: BVN_TOP_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_BVN_TOP_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_BVN_TOP_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: BVN_TOP_ENABLE :: BVN_SCB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: BVN_TOP_ENABLE :: BVN_216_CLK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: BVN_TOP_ENABLE :: BVN_108_CLK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *BVN_TOP_MEMORY_STANDBY_ENABLE - Bvn top memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: BVN_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: BVN_TOP_MEMORY_STANDBY_ENABLE :: BVN_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BVN_TOP_POWER_SWITCH_MEMORY - Bvn top power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: BVN_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: BVN_TOP_POWER_SWITCH_MEMORY :: BVN_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 0 cktap cpu adjustment selection |
| ***************************************************************************/ |
| /* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION [31:28] */ |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0xf0000000 |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 28 |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */ |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000 |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24 |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */ |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000 |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20 |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */ |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000 |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16 |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */ |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000 |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12 |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */ |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00 |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8 |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */ |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0 |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4 |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */ |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0 |
| #define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 1 cktap cpu adjustment selection |
| ***************************************************************************/ |
| /* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION [31:28] */ |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0xf0000000 |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 28 |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */ |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000 |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24 |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: UFE_108_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */ |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_UFE_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000 |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_UFE_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20 |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_UFE_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: T2_RCVR_108_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */ |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_T2_RCVR_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000 |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_T2_RCVR_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16 |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_T2_RCVR_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: T2_BICM_108_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */ |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_T2_BICM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000 |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_T2_BICM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12 |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_T2_BICM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */ |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00 |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8 |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */ |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0 |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4 |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */ |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0 |
| #define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 2 cktap cpu adjustment selection |
| ***************************************************************************/ |
| /* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: LEAP_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */ |
| #define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_LEAP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f |
| #define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_LEAP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0 |
| #define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_LEAP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 216 0 cktap cpu adjustment selection |
| ***************************************************************************/ |
| /* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:28] */ |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xf0000000 |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 28 |
| |
| /* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */ |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000 |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24 |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */ |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000 |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20 |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */ |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000 |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16 |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: LEAP_216_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */ |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_LEAP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000 |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_LEAP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12 |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_LEAP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */ |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00 |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8 |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */ |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0 |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4 |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */ |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0 |
| #define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK - CKTAP CPU Adjustment System 108 Clock |
| ***************************************************************************/ |
| /* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: CKTAP_UPDATE [01:01] */ |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_MASK 0x00000002 |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_SHIFT 1 |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: CKTAP_REG_SELECT [00:00] */ |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001 |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_SHIFT 0 |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK - CKTAP CPU Adjustment System 216 Clock |
| ***************************************************************************/ |
| /* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: CKTAP_UPDATE [01:01] */ |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_MASK 0x00000002 |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_SHIFT 1 |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: CKTAP_REG_SELECT [00:00] */ |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001 |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_SHIFT 0 |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK - CKTAP CPU Adjustment System Scb Clock |
| ***************************************************************************/ |
| /* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: CKTAP_UPDATE [01:01] */ |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_MASK 0x00000002 |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_SHIFT 1 |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: CKTAP_REG_SELECT [00:00] */ |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001 |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_SHIFT 0 |
| #define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap scb 0 cktap cpu adjustment selection |
| ***************************************************************************/ |
| /* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [31:28] */ |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0xf0000000 |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 28 |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */ |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000 |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24 |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */ |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000 |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20 |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */ |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000 |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16 |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */ |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000 |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12 |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */ |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00 |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8 |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */ |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0 |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4 |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */ |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0 |
| #define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap scb 1 cktap cpu adjustment selection |
| ***************************************************************************/ |
| /* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: T2_RCVR_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */ |
| #define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_T2_RCVR_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000 |
| #define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_T2_RCVR_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12 |
| #define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_T2_RCVR_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */ |
| #define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00 |
| #define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8 |
| #define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */ |
| #define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0 |
| #define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4 |
| #define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */ |
| #define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f |
| #define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0 |
| #define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_OSC_DIGITAL_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_AVS_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CLKGEN_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: DISABLE_OSC_DIGITAL_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_OSC_DIGITAL_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_OSC_DIGITAL_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: DISABLE_AVS_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_AVS_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_AVS_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *CLKGEN_TS_CONTROL - Clkgen ts control |
| ***************************************************************************/ |
| /* CLKGEN :: CLKGEN_TS_CONTROL :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_CLKGEN_TS_CONTROL_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_CLKGEN_TS_CONTROL_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: CLKGEN_TS_CONTROL :: CLKGEN_TS_CONTROL [04:00] */ |
| #define BCHP_CLKGEN_CLKGEN_TS_CONTROL_CLKGEN_TS_CONTROL_MASK 0x0000001f |
| #define BCHP_CLKGEN_CLKGEN_TS_CONTROL_CLKGEN_TS_CONTROL_SHIFT 0 |
| #define BCHP_CLKGEN_CLKGEN_TS_CONTROL_CLKGEN_TS_CONTROL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CLKGEN_TS_DATA - Clkgen ts data |
| ***************************************************************************/ |
| /* CLKGEN :: CLKGEN_TS_DATA :: reserved0 [31:20] */ |
| #define BCHP_CLKGEN_CLKGEN_TS_DATA_reserved0_MASK 0xfff00000 |
| #define BCHP_CLKGEN_CLKGEN_TS_DATA_reserved0_SHIFT 20 |
| |
| /* CLKGEN :: CLKGEN_TS_DATA :: CLKGEN_TS_DATA [19:00] */ |
| #define BCHP_CLKGEN_CLKGEN_TS_DATA_CLKGEN_TS_DATA_MASK 0x000fffff |
| #define BCHP_CLKGEN_CLKGEN_TS_DATA_CLKGEN_TS_DATA_SHIFT 0 |
| #define BCHP_CLKGEN_CLKGEN_TS_DATA_CLKGEN_TS_DATA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CLKGEN_TS_STATUS - Clkgen ts status |
| ***************************************************************************/ |
| /* CLKGEN :: CLKGEN_TS_STATUS :: reserved0 [31:21] */ |
| #define BCHP_CLKGEN_CLKGEN_TS_STATUS_reserved0_MASK 0xffe00000 |
| #define BCHP_CLKGEN_CLKGEN_TS_STATUS_reserved0_SHIFT 21 |
| |
| /* CLKGEN :: CLKGEN_TS_STATUS :: CLKGEN_TS_STATUS [20:00] */ |
| #define BCHP_CLKGEN_CLKGEN_TS_STATUS_CLKGEN_TS_STATUS_MASK 0x001fffff |
| #define BCHP_CLKGEN_CLKGEN_TS_STATUS_CLKGEN_TS_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_CONTROL - Clock Monitor Control |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK 0x00000008 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT 3 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK 0x00000004 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT 2 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK 0x00000002 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT 1 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff |
| #define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 0xffffffff |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK 0xffffffff |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK 0x00000001 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT 0 |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff |
| #define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *CORE_XPT_CLOCK_DISABLE - Disable CORE_XPT's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CORE_XPT_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE_STATUS :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE_STATUS :: DISABLE_XPT_81_CLOCK_STATUS [04:04] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_81_CLOCK_STATUS_MASK 0x00000010 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_81_CLOCK_STATUS_SHIFT 4 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE_STATUS :: DISABLE_XPT_54_CLOCK_STATUS [03:03] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_54_CLOCK_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_54_CLOCK_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE_STATUS :: DISABLE_XPT_40P5_CLOCK_STATUS [02:02] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_40P5_CLOCK_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_40P5_CLOCK_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE_STATUS :: DISABLE_XPT_27_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_27_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_27_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE_STATUS :: DISABLE_XPT_20P25_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_20P25_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_20P25_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *CORE_XPT_CLOCK_ENABLE - Core xpt clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_216_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *CORE_XPT_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_ENABLE_STATUS :: XPT_SCB_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_XPT_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_XPT_SCB_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_ENABLE_STATUS :: XPT_216_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_XPT_216_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_XPT_216_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_ENABLE_STATUS :: XPT_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *CORE_XPT_MEMORY_STANDBY_ENABLE - Core xpt memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: XPT_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CORE_XPT_OBSERVE_CLOCK - Core xpt observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CORE_XPT_POWER_SWITCH_MEMORY - Core xpt power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: XPT_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DVP_HT_CLOCK_DISABLE - Disable DVP_HT's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DVP_HT_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DVP_HT_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DVP_HT_CLOCK_DISABLE_STATUS :: DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DVP_HT_CLOCK_ENABLE - Dvp ht clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_CLOCK_ENABLE :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_ALTERNATE_216_CLOCK_ENABLE [03:03] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_ALTERNATE_108_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_216_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DVP_HT_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: DVP_HT_CLOCK_ENABLE_STATUS :: DVPHT_ALTERNATE_216_CLOCK_ENABLE_STATUS [03:03] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_DVPHT_ALTERNATE_216_CLOCK_ENABLE_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_DVPHT_ALTERNATE_216_CLOCK_ENABLE_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: DVP_HT_CLOCK_ENABLE_STATUS :: DVPHT_ALTERNATE_108_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_DVPHT_ALTERNATE_108_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_DVPHT_ALTERNATE_108_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: DVP_HT_CLOCK_ENABLE_STATUS :: DVPHT_216_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_DVPHT_216_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_DVPHT_216_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: DVP_HT_CLOCK_ENABLE_STATUS :: DVPHT_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DVP_HT_ENABLE - Dvp ht enable |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DVP_HT_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DVP_HT_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DVP_HT_ENABLE :: DVPHT_CLK_MAX_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DVP_HT_MEMORY_STANDBY_ENABLE - Dvp ht memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: DVPHT_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DVP_HT_OBSERVE_CLOCK - Dvp ht observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DVP_HT_POWER_SWITCH_MEMORY - Dvp ht power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: DVPHT_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENET_TOP_RGMII_INST_BYPASS - Genet top rgmii inst bypass |
| ***************************************************************************/ |
| /* CLKGEN :: GENET_TOP_RGMII_INST_BYPASS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_BYPASS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_BYPASS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_BYPASS :: GENET0_CLK_25_EEE_25_CLOCK_BYPASS [00:00] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_BYPASS_GENET0_CLK_25_EEE_25_CLOCK_BYPASS_MASK 0x00000001 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_BYPASS_GENET0_CLK_25_EEE_25_CLOCK_BYPASS_SHIFT 0 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_BYPASS_GENET0_CLK_25_EEE_25_CLOCK_BYPASS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENET_TOP_RGMII_INST_CLOCK_DISABLE - Disable GENET_TOP_RGMII_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET_ALWAYSON_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET_25_PHY_SCANCLOCK [04:04] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_25_PHY_SCANCLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_25_PHY_SCANCLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_25_PHY_SCANCLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET_125_PHY_SCANCLOCK [03:03] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_125_PHY_SCANCLOCK_MASK 0x00000008 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_125_PHY_SCANCLOCK_SHIFT 3 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_125_PHY_SCANCLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_FAST_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET_ALWAYSON_CLOCK_STATUS [05:05] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET_ALWAYSON_CLOCK_STATUS_MASK 0x00000020 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET_ALWAYSON_CLOCK_STATUS_SHIFT 5 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET_25_PHY_SCANCLOCK_STATUS [04:04] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET_25_PHY_SCANCLOCK_STATUS_MASK 0x00000010 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET_25_PHY_SCANCLOCK_STATUS_SHIFT 4 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET_125_PHY_SCANCLOCK_STATUS [03:03] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET_125_PHY_SCANCLOCK_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET_125_PHY_SCANCLOCK_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS [02:02] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENET_TOP_RGMII_INST_CLOCK_ENABLE - Genet top rgmii inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [08:08] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00000100 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 8 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_108_CLOCK_ENABLE [07:07] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_MASK 0x00000080 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_SHIFT 7 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE [06:06] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00000040 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 6 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE [05:05] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00000020 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 5 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_L2INTR_CLOCK_ENABLE [04:04] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_MASK 0x00000010 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_SHIFT 4 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_HFB_CLOCK_ENABLE [03:03] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_MASK 0x00000008 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_SHIFT 3 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_GMII_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_EEE_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_CLK_250_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS :: GENET_SCB_CLOCK_ENABLE_STATUS [08:08] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000100 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET_SCB_CLOCK_ENABLE_STATUS_SHIFT 8 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS :: GENET_108_CLOCK_ENABLE_STATUS [07:07] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET_108_CLOCK_ENABLE_STATUS_MASK 0x00000080 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET_108_CLOCK_ENABLE_STATUS_SHIFT 7 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_STATUS [06:06] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_STATUS_MASK 0x00000040 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_STATUS_SHIFT 6 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_STATUS [05:05] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_STATUS_MASK 0x00000020 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_STATUS_SHIFT 5 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS :: GENET0_L2INTR_CLOCK_ENABLE_STATUS [04:04] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET0_L2INTR_CLOCK_ENABLE_STATUS_MASK 0x00000010 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET0_L2INTR_CLOCK_ENABLE_STATUS_SHIFT 4 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS :: GENET0_HFB_CLOCK_ENABLE_STATUS [03:03] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET0_HFB_CLOCK_ENABLE_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET0_HFB_CLOCK_ENABLE_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS :: GENET0_GMII_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET0_GMII_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET0_GMII_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS :: GENET0_EEE_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET0_EEE_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET0_EEE_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS :: GENET0_CLK_250_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET0_CLK_250_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET0_CLK_250_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENET_TOP_RGMII_INST_CLOCK_SELECT - Genet top rgmii inst clock select |
| ***************************************************************************/ |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET0_GMII_CLOCK_SELECT [01:01] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_MASK 0x00000002 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_SHIFT 1 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET0_CLOCK_SELECT [00:00] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_MASK 0x00000001 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_SHIFT 0 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A - Genet top rgmii inst memory standby enable a |
| ***************************************************************************/ |
| /* CLKGEN :: GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: GENET0_MEMORY_STANDBY_ENABLE_A [00:00] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_SHIFT 0 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENET_TOP_RGMII_INST_OBSERVE_CLOCK - Genet top rgmii inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A - Genet top rgmii inst power switch memory a |
| ***************************************************************************/ |
| /* CLKGEN :: GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A :: GENET0_POWER_SWITCH_MEMORY_A [01:00] */ |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_MASK 0x00000003 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_SHIFT 0 |
| #define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GRAPHICS_CLOCK_DISABLE - Disable GRAPHICS's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: GRAPHICS_CLOCK_DISABLE :: DISABLE_GFX_M2MC_CORE_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GRAPHICS_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: GRAPHICS_CLOCK_DISABLE_STATUS :: DISABLE_GFX_M2MC_CORE_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_STATUS_DISABLE_GFX_M2MC_CORE_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_STATUS_DISABLE_GFX_M2MC_CORE_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *GRAPHICS_CLOCK_ENABLE - Graphics clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_SCB_CLOCK_ENABLE [03:03] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_MASK 0x00000008 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_SHIFT 3 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_M2MC_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_ALTERNATE_108_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *GRAPHICS_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE_STATUS :: GFX_SCB_CLOCK_ENABLE_STATUS [03:03] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_STATUS_GFX_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_STATUS_GFX_SCB_CLOCK_ENABLE_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE_STATUS :: GFX_M2MC_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_STATUS_GFX_M2MC_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_STATUS_GFX_M2MC_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE_STATUS :: GFX_ALTERNATE_108_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_STATUS_GFX_ALTERNATE_108_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_STATUS_GFX_ALTERNATE_108_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE_STATUS :: GFX_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_STATUS_GFX_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_STATUS_GFX_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *GRAPHICS_MEMORY_STANDBY_ENABLE - Graphics memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE :: GFX_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GRAPHICS_OBSERVE_CLOCK - Graphics observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GRAPHICS_POWER_SWITCH_MEMORY - Graphics power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY :: GFX_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *HIF_CLOCK_DISABLE - Disable HIF's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_CLOCK_DISABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_SDIO_48_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *HIF_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: HIF_CLOCK_DISABLE_STATUS :: DISABLE_SDIO_48_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_STATUS_DISABLE_SDIO_48_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_STATUS_DISABLE_SDIO_48_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: HIF_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SPI_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *HIF_CLOCK_ENABLE - Hif clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_SCB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_216_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *HIF_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: HIF_CLOCK_ENABLE_STATUS :: HIF_SCB_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_STATUS_HIF_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_STATUS_HIF_SCB_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: HIF_CLOCK_ENABLE_STATUS :: HIF_216_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_STATUS_HIF_216_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_STATUS_HIF_216_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: HIF_CLOCK_ENABLE_STATUS :: HIF_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_STATUS_HIF_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_STATUS_HIF_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *HIF_MEMORY_STANDBY_ENABLE - Hif memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE :: HIF_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *HIF_POWER_SWITCH_MEMORY - Hif power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: HIF_POWER_SWITCH_MEMORY :: HIF_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *INTERNAL_MUX_SELECT - Mux selects for Internal clocks |
| ***************************************************************************/ |
| /* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: INTERNAL_MUX_SELECT :: T2R_MASTER_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_T2R_MASTER_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_T2R_MASTER_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_T2R_MASTER_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: INTERNAL_MUX_SELECT :: T2B_432_CLOCK [03:03] */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_T2B_432_CLOCK_MASK 0x00000008 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_T2B_432_CLOCK_SHIFT 3 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_T2B_432_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: INTERNAL_MUX_SELECT :: GFX_M2MC_CORE_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *LEAP_TOP_INST_CLOCK_DISABLE - Disable LEAP_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: DISABLE_LEAP_27_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_27_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_27_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_27_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *LEAP_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_LEAP_27_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_LEAP_27_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_LEAP_27_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LEAP_TOP_INST_CLOCK_ENABLE - Leap top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: LEAP_216_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_216_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_216_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: LEAP_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *LEAP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: LEAP_216_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_216_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_216_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: LEAP_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LEAP_TOP_INST_DATA - Leap top inst data |
| ***************************************************************************/ |
| /* CLKGEN :: LEAP_TOP_INST_DATA :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_DATA_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_DATA_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: LEAP_TOP_INST_DATA :: LEAP_POWER_SWITCH_MEMORY_DATA [02:01] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_DATA_LEAP_POWER_SWITCH_MEMORY_DATA_MASK 0x00000006 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_DATA_LEAP_POWER_SWITCH_MEMORY_DATA_SHIFT 1 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_DATA_LEAP_POWER_SWITCH_MEMORY_DATA_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: LEAP_TOP_INST_DATA :: LEAP_MEMORY_STANDBY_ENABLE_DATA [00:00] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_DATA_LEAP_MEMORY_STANDBY_ENABLE_DATA_MASK 0x00000001 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_DATA_LEAP_MEMORY_STANDBY_ENABLE_DATA_SHIFT 0 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_DATA_LEAP_MEMORY_STANDBY_ENABLE_DATA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEMSYS_16_CLOCK_ENABLE - Memsys 16 clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: DDR1_SCB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: DDR1_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *MEMSYS_16_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_16_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: MEMSYS_16_CLOCK_ENABLE_STATUS :: DDR1_SCB_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_STATUS_DDR1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_STATUS_DDR1_SCB_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: MEMSYS_16_CLOCK_ENABLE_STATUS :: DDR1_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_STATUS_DDR1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_STATUS_DDR1_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *MEMSYS_16_MEMORY_STANDBY_ENABLE - Memsys 16 memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_16_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: MEMSYS_16_MEMORY_STANDBY_ENABLE :: DDR1_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEMSYS_16_OBSERVE_CLOCK - Memsys 16 observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEMSYS_16_POWER_SWITCH_MEMORY - Memsys 16 power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_16_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: MEMSYS_16_POWER_SWITCH_MEMORY :: DDR1_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEMSYS_16_STATUS - Memsys 16 status |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_16_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_MEMSYS_16_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_MEMSYS_16_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: MEMSYS_16_STATUS :: MEMSYS_PLL_LOCKED_STATUS [00:00] */ |
| #define BCHP_CLKGEN_MEMSYS_16_STATUS_MEMSYS_PLL_LOCKED_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMSYS_16_STATUS_MEMSYS_PLL_LOCKED_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PAD_CLK_OBSRV0_OBSERVATION - Select observation clk |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: reserved0 [31:08] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_MASK 0xffffff00 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_SHIFT 8 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PAD_CLK_OBSRV1_OBSERVATION - Select observation clk |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: reserved0 [31:08] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_MASK 0xffffff00 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_SHIFT 8 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PAD_CLK_OBSRV2_OBSERVATION - Select observation clk |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: reserved0 [31:08] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_MASK 0xffffff00 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_SHIFT 8 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PAD_CLK_OBSRV3_OBSERVATION - Select observation clk |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: reserved0 [31:08] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_MASK 0xffffff00 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_SHIFT 8 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PAD_CLOCK_DISABLE - Disable PAD's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_SC_OUT_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK27_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PAD_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_SC_OUT_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_SC_OUT_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_SC_OUT_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CLK27_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK27_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK27_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PAD_MUX_SELECT - Mux selects for Pad clocks |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK27_CLOCK [02:00] */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000007 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_RESET_STATUS - PLL_AUDIO0 Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_RESET_STATUS - PLL_AUDIO1 Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST - PLL_AVD_MIPS Glitchless Clock Switching |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST :: TRANSACTION_WAIT [08:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_DEFAULT 0x0000001f |
| |
| /* CLKGEN :: PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST :: PLL_BYPASS_REQUEST [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_MIPS_GLITCHLESS_SWITCH_STATUS - PLL_AVD_MIPS Glitchless Switching |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_MIPS_GLITCHLESS_SWITCH_STATUS :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_STATUS_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_GLITCHLESS_SWITCH_STATUS :: PLL_BYPASS_STATUS [03:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_MASK 0x0000000f |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AVD_MIPS_PLL_RESET_STATUS - PLL_AVD_MIPS Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AVD_MIPS_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_RESET_STATUS - PLL_SC Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_RESET_STATUS - PLL_SYS1 Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_RESET_STATUS - PLL_VCXO Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PM_CLOCK_108_ALIVE_SEL - Select clocks that can stay alive during power management standby mode. |
| ***************************************************************************/ |
| /* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_USB [00:00] */ |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_USB_MASK 0x00000001 |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_USB_SHIFT 0 |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_USB_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PM_CLOCK_216_ALIVE_SEL - Select clocks that can stay alive during power management standby mode. |
| ***************************************************************************/ |
| /* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */ |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_MASK 0x00000001 |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT 0 |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode |
| ***************************************************************************/ |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys_PLL [02:02] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_MASK 0x00000004 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_SHIFT 2 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [01:01] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK 0x00000002 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT 1 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_AVD_MIPS [00:00] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_SHIFT 0 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PM_PLL_LDO_POWERUP_SM - Power management LDO PLL state machine |
| ***************************************************************************/ |
| /* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: reserved0 [31:27] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_MASK 0xf8000000 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_SHIFT 27 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_POWERUP_WAIT_TIME [26:14] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_MASK 0x07ffc000 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_SHIFT 14 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_DEFAULT 0x00001518 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_CLK_STOP_WAIT_TIME [13:01] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_MASK 0x00003ffe |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_SHIFT 1 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_DEFAULT 0x000000c8 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: GISB_OVERRIDE_SM [00:00] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_MASK 0x00000001 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_SHIFT 0 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_CLOCK_ENABLE - Raaga dsp top clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_SCB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_DSP_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS :: RAAGA_SCB_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS_RAAGA_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS_RAAGA_SCB_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS :: RAAGA_DSP_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS_RAAGA_DSP_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS_RAAGA_DSP_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS :: RAAGA_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS_RAAGA_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS_RAAGA_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE - Raaga dsp top memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE :: RAAGAA_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_OBSERVE_CLOCK - Raaga dsp top observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: RAAGA0_ENABLE_OBSERVE_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA0_ENABLE_OBSERVE_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA0_ENABLE_OBSERVE_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_POWER_SWITCH_MEMORY - Raaga dsp top power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_POWER_SWITCH_MEMORY :: RAAGA_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SECTOP_INST_CLOCK_ENABLE - Sectop inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: SEC_ALTERNATE_SCB_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SECTOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_STATUS :: SEC_ALTERNATE_SCB_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_SEC_ALTERNATE_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_SEC_ALTERNATE_SCB_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *SECTOP_INST_MEMORY_STANDBY_ENABLE - Sectop inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: SECTOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SECTOP_INST_MEMORY_STANDBY_ENABLE :: SEC_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks |
| ***************************************************************************/ |
| /* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: SMARTCARD_MUX_SELECT :: SC_OUT_CLOCK [10:08] */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_MASK 0x00000700 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_SHIFT 8 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [07:05] */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK 0x000000e0 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [04:02] */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK 0x0000001c |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SMARTCARD_MUX_SELECT :: PLLSC_REFERENCE_CLOCK [01:00] */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_MASK 0x00000003 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SPARE - Spares |
| ***************************************************************************/ |
| /* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */ |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK 0xfffff000 |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT 12 |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */ |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK 0x00000fff |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT 0 |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SYS_AON_OBSERVE_CLOCK - Sys aon observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SYS_CTRL_CLOCK_DISABLE - Disable SYS_CTRL's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SYS_CTRL_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_CLOCK_DISABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: SYS_CTRL_CLOCK_DISABLE_STATUS :: DISABLE_SYSCTRL_UPG_CLOCK_STATUS [02:02] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: SYS_CTRL_CLOCK_DISABLE_STATUS :: DISABLE_SC1_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: SYS_CTRL_CLOCK_DISABLE_STATUS :: DISABLE_SC0_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *SYS_CTRL_CLOCK_ENABLE - Sys ctrl clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: SYS_CTRL_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SYS_CTRL_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SYS_CTRL_CLOCK_ENABLE_STATUS :: SYS_CTRL_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_STATUS_SYS_CTRL_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_STATUS_SYS_CTRL_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *SYS_CTRL_MEMORY_STANDBY_ENABLE - Sys ctrl memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: SYS_CTRL_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SYS_CTRL_OBSERVE_CLOCK - Sys ctrl observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SYS_CTRL_POWER_SWITCH_MEMORY - Sys ctrl power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SYS_CTRL_POWER_SWITCH_MEMORY :: SYS_CTRL_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *T2_BICM_TOP_INST_CLOCK_DISABLE - Disable T2_BICM_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: T2_BICM_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: T2_BICM_TOP_INST_CLOCK_DISABLE :: DISABLE_T2B_432_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_DISABLE_DISABLE_T2B_432_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_DISABLE_DISABLE_T2B_432_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_DISABLE_DISABLE_T2B_432_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *T2_BICM_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: T2_BICM_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: T2_BICM_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_T2B_432_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_T2B_432_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_T2B_432_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *T2_BICM_TOP_INST_CLOCK_ENABLE - T2 bicm top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: T2_BICM_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: T2_BICM_TOP_INST_CLOCK_ENABLE :: T2B_PLL_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_ENABLE_T2B_PLL_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_ENABLE_T2B_PLL_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_ENABLE_T2B_PLL_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: T2_BICM_TOP_INST_CLOCK_ENABLE :: T2B_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_ENABLE_T2B_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_ENABLE_T2B_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_ENABLE_T2B_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *T2_BICM_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: T2_BICM_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: T2_BICM_TOP_INST_CLOCK_ENABLE_STATUS :: T2B_PLL_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_ENABLE_STATUS_T2B_PLL_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_ENABLE_STATUS_T2B_PLL_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: T2_BICM_TOP_INST_CLOCK_ENABLE_STATUS :: T2B_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_ENABLE_STATUS_T2B_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_CLOCK_ENABLE_STATUS_T2B_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *T2_BICM_TOP_INST_MEMORY_STANDBY_ENABLE - T2 bicm top inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: T2_BICM_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: T2_BICM_TOP_INST_MEMORY_STANDBY_ENABLE :: T2B_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_MEMORY_STANDBY_ENABLE_T2B_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_MEMORY_STANDBY_ENABLE_T2B_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_MEMORY_STANDBY_ENABLE_T2B_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *T2_BICM_TOP_INST_POWER_SWITCH_MEMORY0 - T2 bicm top inst power switch memory0 |
| ***************************************************************************/ |
| /* CLKGEN :: T2_BICM_TOP_INST_POWER_SWITCH_MEMORY0 :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_POWER_SWITCH_MEMORY0_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_POWER_SWITCH_MEMORY0_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: T2_BICM_TOP_INST_POWER_SWITCH_MEMORY0 :: T2B_POWER_SWITCH_MEMORY0 [01:00] */ |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_POWER_SWITCH_MEMORY0_T2B_POWER_SWITCH_MEMORY0_MASK 0x00000003 |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_POWER_SWITCH_MEMORY0_T2B_POWER_SWITCH_MEMORY0_SHIFT 0 |
| #define BCHP_CLKGEN_T2_BICM_TOP_INST_POWER_SWITCH_MEMORY0_T2B_POWER_SWITCH_MEMORY0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *T2_RCVR_TOP_INST_CLOCK_DISABLE - Disable T2_RCVR_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: T2_RCVR_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: T2_RCVR_TOP_INST_CLOCK_DISABLE :: DISABLE_T2R_MASTER_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_DISABLE_DISABLE_T2R_MASTER_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_DISABLE_DISABLE_T2R_MASTER_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_DISABLE_DISABLE_T2R_MASTER_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *T2_RCVR_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: T2_RCVR_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: T2_RCVR_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_T2R_MASTER_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_T2R_MASTER_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_T2R_MASTER_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *T2_RCVR_TOP_INST_CLOCK_ENABLE - T2 rcvr top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: T2_RCVR_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: T2_RCVR_TOP_INST_CLOCK_ENABLE :: T2R_SCB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_ENABLE_T2R_SCB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_ENABLE_T2R_SCB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_ENABLE_T2R_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: T2_RCVR_TOP_INST_CLOCK_ENABLE :: T2R_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_ENABLE_T2R_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_ENABLE_T2R_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_ENABLE_T2R_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *T2_RCVR_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: T2_RCVR_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: T2_RCVR_TOP_INST_CLOCK_ENABLE_STATUS :: T2R_SCB_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_ENABLE_STATUS_T2R_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_ENABLE_STATUS_T2R_SCB_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: T2_RCVR_TOP_INST_CLOCK_ENABLE_STATUS :: T2R_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_ENABLE_STATUS_T2R_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_CLOCK_ENABLE_STATUS_T2R_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *T2_RCVR_TOP_INST_MEMORY_STANDBY_ENABLE - T2 rcvr top inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: T2_RCVR_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: T2_RCVR_TOP_INST_MEMORY_STANDBY_ENABLE :: T2R_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_MEMORY_STANDBY_ENABLE_T2R_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_MEMORY_STANDBY_ENABLE_T2R_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_MEMORY_STANDBY_ENABLE_T2R_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY0 - T2 rcvr top inst power switch memory0 |
| ***************************************************************************/ |
| /* CLKGEN :: T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY0 :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY0_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY0_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY0 :: T2R_POWER_SWITCH_MEMORY0 [01:00] */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY0_T2R_POWER_SWITCH_MEMORY0_MASK 0x00000003 |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY0_T2R_POWER_SWITCH_MEMORY0_SHIFT 0 |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY0_T2R_POWER_SWITCH_MEMORY0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY1 - T2 rcvr top inst power switch memory1 |
| ***************************************************************************/ |
| /* CLKGEN :: T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY1 :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY1_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY1_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY1 :: T2R_POWER_SWITCH_MEMORY1 [01:00] */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY1_T2R_POWER_SWITCH_MEMORY1_MASK 0x00000003 |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY1_T2R_POWER_SWITCH_MEMORY1_SHIFT 0 |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY1_T2R_POWER_SWITCH_MEMORY1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY2 - T2 rcvr top inst power switch memory2 |
| ***************************************************************************/ |
| /* CLKGEN :: T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY2 :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY2_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY2_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY2 :: T2R_POWER_SWITCH_MEMORY2 [01:00] */ |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY2_T2R_POWER_SWITCH_MEMORY2_MASK 0x00000003 |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY2_T2R_POWER_SWITCH_MEMORY2_SHIFT 0 |
| #define BCHP_CLKGEN_T2_RCVR_TOP_INST_POWER_SWITCH_MEMORY2_T2R_POWER_SWITCH_MEMORY2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TESTPORT - Special Testport Controls |
| ***************************************************************************/ |
| /* CLKGEN :: TESTPORT :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_TESTPORT_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [02:00] */ |
| #define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK 0x00000007 |
| #define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT 0 |
| #define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_CM0 - Tm registers inst cm0 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_CM0 :: TM_CM0 [31:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_CM0_TM_CM0_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_CM0_TM_CM0_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_CM0_TM_CM0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_CM1 - Tm registers inst cm1 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_CM1 :: TM_CM1 [31:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_CM1_TM_CM1_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_CM1_TM_CM1_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_CM1_TM_CM1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_CM2 - Tm registers inst cm2 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_CM2 :: TM_CM2 [31:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_CM2_TM_CM2_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_CM2_TM_CM2_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_CM2_TM_CM2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_CM3 - Tm registers inst cm3 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_CM3 :: TM_CM3 [31:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_CM3_TM_CM3_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_CM3_TM_CM3_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_CM3_TM_CM3_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_MEMCTRL - Tm registers inst memctrl |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_MEMCTRL :: TM_MEMCTRL [31:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_MEMCTRL_TM_MEMCTRL_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_MEMCTRL_TM_MEMCTRL_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_MEMCTRL_TM_MEMCTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_MEMCTRL2 - Tm registers inst memctrl2 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_MEMCTRL2 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_MEMCTRL2_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_MEMCTRL2_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: TM_REGISTERS_INST_MEMCTRL2 :: TM_MEMCTRL2 [00:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_MEMCTRL2_TM_MEMCTRL2_MASK 0x00000001 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_MEMCTRL2_TM_MEMCTRL2_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_MEMCTRL2_TM_MEMCTRL2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_OSCCLKEN - Tm registers inst oscclken |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_OSCCLKEN :: reserved0 [31:08] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_OSCCLKEN_reserved0_MASK 0xffffff00 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_OSCCLKEN_reserved0_SHIFT 8 |
| |
| /* CLKGEN :: TM_REGISTERS_INST_OSCCLKEN :: TM_OSCCLKEN [07:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_OSCCLKEN_TM_OSCCLKEN_MASK 0x000000ff |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_OSCCLKEN_TM_OSCCLKEN_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_OSCCLKEN_TM_OSCCLKEN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_PWRDN - Tm registers inst pwrdn |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_PWRDN :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_PWRDN_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_PWRDN_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: TM_REGISTERS_INST_PWRDN :: TM_PWRDN [01:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_PWRDN_TM_PWRDN_MASK 0x00000003 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_PWRDN_TM_PWRDN_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_PWRDN_TM_PWRDN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_REVID - Tm registers inst revid |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_REVID :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_REVID_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_REVID_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: TM_REGISTERS_INST_REVID :: TM_REVID [15:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_REVID_TM_REVID_MASK 0x0000ffff |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_REVID_TM_REVID_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_REVID_TM_REVID_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_SFT0 - Tm registers inst sft0 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_SFT0 :: TM_SFT0 [31:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT0_TM_SFT0_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT0_TM_SFT0_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT0_TM_SFT0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_SFT1 - Tm registers inst sft1 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_SFT1 :: TM_SFT1 [31:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT1_TM_SFT1_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT1_TM_SFT1_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT1_TM_SFT1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_SFT2 - Tm registers inst sft2 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_SFT2 :: TM_SFT2 [31:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT2_TM_SFT2_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT2_TM_SFT2_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT2_TM_SFT2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_SFT3 - Tm registers inst sft3 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_SFT3 :: TM_SFT3 [31:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT3_TM_SFT3_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT3_TM_SFT3_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT3_TM_SFT3_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_SFT4 - Tm registers inst sft4 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_SFT4 :: TM_SFT4 [31:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT4_TM_SFT4_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT4_TM_SFT4_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT4_TM_SFT4_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_SFT5 - Tm registers inst sft5 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_SFT5 :: TM_SFT5 [31:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT5_TM_SFT5_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT5_TM_SFT5_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT5_TM_SFT5_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_SFT6 - Tm registers inst sft6 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_SFT6 :: TM_SFT6 [31:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT6_TM_SFT6_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT6_TM_SFT6_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT6_TM_SFT6_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_SFT7 - Tm registers inst sft7 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_SFT7 :: TM_SFT7 [31:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT7_TM_SFT7_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT7_TM_SFT7_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFT7_TM_SFT7_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_SFTRST - Tm registers inst sftrst |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_SFTRST :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFTRST_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFTRST_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: TM_REGISTERS_INST_SFTRST :: TM_SFTRST [15:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFTRST_TM_SFTRST_MASK 0x0000ffff |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFTRST_TM_SFTRST_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SFTRST_TM_SFTRST_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_SYSCLKEN - Tm registers inst sysclken |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_SYSCLKEN :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSCLKEN_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSCLKEN_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: TM_REGISTERS_INST_SYSCLKEN :: TM_SYSCLKEN [15:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSCLKEN_TM_SYSCLKEN_MASK 0x0000ffff |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSCLKEN_TM_SYSCLKEN_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSCLKEN_TM_SYSCLKEN_DEFAULT 0x0000ffff |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_SYSPLLCLK216 - Tm registers inst syspllclk216 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_SYSPLLCLK216 :: reserved0 [31:17] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLCLK216_reserved0_MASK 0xfffe0000 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLCLK216_reserved0_SHIFT 17 |
| |
| /* CLKGEN :: TM_REGISTERS_INST_SYSPLLCLK216 :: TM_SYSPLLCLK216 [16:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLCLK216_TM_SYSPLLCLK216_MASK 0x0001ffff |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLCLK216_TM_SYSPLLCLK216_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLCLK216_TM_SYSPLLCLK216_DEFAULT 0x0000000a |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_SYSPLLCLKT2B - Tm registers inst syspllclkt2b |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_SYSPLLCLKT2B :: reserved0 [31:17] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLCLKT2B_reserved0_MASK 0xfffe0000 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLCLKT2B_reserved0_SHIFT 17 |
| |
| /* CLKGEN :: TM_REGISTERS_INST_SYSPLLCLKT2B :: TM_SYSPLLCLKT2B [16:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLCLKT2B_TM_SYSPLLCLKT2B_MASK 0x0001ffff |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLCLKT2B_TM_SYSPLLCLKT2B_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLCLKT2B_TM_SYSPLLCLKT2B_DEFAULT 0x00000005 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_SYSPLLNDIVINT - Tm registers inst syspllndivint |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_SYSPLLNDIVINT :: reserved0 [31:08] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLNDIVINT_reserved0_MASK 0xffffff00 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLNDIVINT_reserved0_SHIFT 8 |
| |
| /* CLKGEN :: TM_REGISTERS_INST_SYSPLLNDIVINT :: TM_SYSPLLNDIVINT [07:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLNDIVINT_TM_SYSPLLNDIVINT_MASK 0x000000ff |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLNDIVINT_TM_SYSPLLNDIVINT_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLNDIVINT_TM_SYSPLLNDIVINT_DEFAULT 0x00000050 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_SYSPLLPDIV - Tm registers inst syspllpdiv |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_SYSPLLPDIV :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLPDIV_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLPDIV_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: TM_REGISTERS_INST_SYSPLLPDIV :: TM_SYSPLLPDIV [03:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLPDIV_TM_SYSPLLPDIV_MASK 0x0000000f |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLPDIV_TM_SYSPLLPDIV_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLPDIV_TM_SYSPLLPDIV_DEFAULT 0x00000002 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_SYSPLLRST - Tm registers inst syspllrst |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_SYSPLLRST :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLRST_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLRST_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: TM_REGISTERS_INST_SYSPLLRST :: TM_SYSPLLRST [01:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLRST_TM_SYSPLLRST_MASK 0x00000003 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLRST_TM_SYSPLLRST_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLRST_TM_SYSPLLRST_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_SYSPLLSTATUS - Tm registers inst syspllstatus |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_SYSPLLSTATUS :: reserved0 [31:17] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLSTATUS_reserved0_MASK 0xfffe0000 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLSTATUS_reserved0_SHIFT 17 |
| |
| /* CLKGEN :: TM_REGISTERS_INST_SYSPLLSTATUS :: TM_SYSPLLSTATUS [16:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLSTATUS_TM_SYSPLLSTATUS_MASK 0x0001ffff |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_SYSPLLSTATUS_TM_SYSPLLSTATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *TM_REGISTERS_INST_TSCTRL - Tm registers inst tsctrl |
| ***************************************************************************/ |
| /* CLKGEN :: TM_REGISTERS_INST_TSCTRL :: reserved0 [31:08] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_TSCTRL_reserved0_MASK 0xffffff00 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_TSCTRL_reserved0_SHIFT 8 |
| |
| /* CLKGEN :: TM_REGISTERS_INST_TSCTRL :: TM_TSCTRL [07:00] */ |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_TSCTRL_TM_TSCTRL_MASK 0x000000ff |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_TSCTRL_TM_TSCTRL_SHIFT 0 |
| #define BCHP_CLKGEN_TM_REGISTERS_INST_TSCTRL_TM_TSCTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UFE_TOP_INST_CLOCK_ENABLE - Ufe top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: UFE_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_UFE_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_UFE_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: UFE_TOP_INST_CLOCK_ENABLE :: UFE_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_UFE_TOP_INST_CLOCK_ENABLE_UFE_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_UFE_TOP_INST_CLOCK_ENABLE_UFE_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_UFE_TOP_INST_CLOCK_ENABLE_UFE_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *UFE_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: UFE_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_UFE_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_UFE_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: UFE_TOP_INST_CLOCK_ENABLE_STATUS :: UFE_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_UFE_TOP_INST_CLOCK_ENABLE_STATUS_UFE_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_UFE_TOP_INST_CLOCK_ENABLE_STATUS_UFE_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *UFE_TOP_INST_MEMORY_STANDBY_ENABLE - Ufe top inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: UFE_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_UFE_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_UFE_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: UFE_TOP_INST_MEMORY_STANDBY_ENABLE :: UFE_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_UFE_TOP_INST_MEMORY_STANDBY_ENABLE_UFE_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_UFE_TOP_INST_MEMORY_STANDBY_ENABLE_UFE_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_UFE_TOP_INST_MEMORY_STANDBY_ENABLE_UFE_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UFE_TOP_INST_OBSERVE_CLOCK - Ufe top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: UFE_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_UFE_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_UFE_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: UFE_TOP_INST_OBSERVE_CLOCK :: UFE_ENABLE_OBSERVE_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_UFE_TOP_INST_OBSERVE_CLOCK_UFE_ENABLE_OBSERVE_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_UFE_TOP_INST_OBSERVE_CLOCK_UFE_ENABLE_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_UFE_TOP_INST_OBSERVE_CLOCK_UFE_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UFE_TOP_INST_POWER_SWITCH_MEMORY - Ufe top inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: UFE_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_UFE_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_UFE_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: UFE_TOP_INST_POWER_SWITCH_MEMORY :: UFE_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_UFE_TOP_INST_POWER_SWITCH_MEMORY_UFE_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_UFE_TOP_INST_POWER_SWITCH_MEMORY_UFE_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_UFE_TOP_INST_POWER_SWITCH_MEMORY_UFE_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *USB_CLOCK_ENABLE - Usb clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: USB_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: USB_CLOCK_ENABLE :: USB0_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *USB_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: USB_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB_CLOCK_ENABLE_STATUS :: USB0_SCB_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: USB_CLOCK_ENABLE_STATUS :: USB0_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_STATUS_USB0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_STATUS_USB0_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *USB_MEMORY_STANDBY_ENABLE - Usb memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: USB_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: USB_MEMORY_STANDBY_ENABLE :: USB0_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *USB_OBSERVE_CLOCK - Usb observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: USB_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *USB_POWER_SWITCH_MEMORY - Usb power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: USB_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB_POWER_SWITCH_MEMORY :: USB0_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_CLOCK_DISABLE - Disable VEC_AIO_TOP's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE_STATUS :: DISABLE_VEC_DACADC_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_CLOCK_ENABLE - Vec aio top clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: reserved0 [31:07] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_reserved0_MASK 0xffffff80 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_reserved0_SHIFT 7 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_SCB_CLOCK_ENABLE [06:06] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_MASK 0x00000040 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_SHIFT 6 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_SCB_CLOCK_ENABLE [05:05] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000020 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 5 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_216_CLOCK_ENABLE [04:04] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000010 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_SHIFT 4 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_108_CLOCK_ENABLE [03:03] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000008 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_SHIFT 3 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE2_108_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_216_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_STATUS :: reserved0 [31:07] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffff80 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_STATUS_reserved0_SHIFT 7 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_STATUS :: VEC_SCB_CLOCK_ENABLE_STATUS [06:06] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_STATUS_VEC_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000040 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_STATUS_VEC_SCB_CLOCK_ENABLE_STATUS_SHIFT 6 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_STATUS :: VEC_ALTERNATE_SCB_CLOCK_ENABLE_STATUS [05:05] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_STATUS_VEC_ALTERNATE_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000020 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_STATUS_VEC_ALTERNATE_SCB_CLOCK_ENABLE_STATUS_SHIFT 5 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_STATUS :: VEC_ALTERNATE_216_CLOCK_ENABLE_STATUS [04:04] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_STATUS_VEC_ALTERNATE_216_CLOCK_ENABLE_STATUS_MASK 0x00000010 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_STATUS_VEC_ALTERNATE_216_CLOCK_ENABLE_STATUS_SHIFT 4 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_STATUS :: VEC_ALTERNATE_108_CLOCK_ENABLE_STATUS [03:03] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_STATUS_VEC_ALTERNATE_108_CLOCK_ENABLE_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_STATUS_VEC_ALTERNATE_108_CLOCK_ENABLE_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_STATUS :: VEC_ALTERNATE2_108_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_STATUS_VEC_ALTERNATE2_108_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_STATUS_VEC_ALTERNATE2_108_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_STATUS :: VEC_216_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_STATUS_VEC_216_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_STATUS_VEC_216_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_STATUS :: VEC_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_STATUS_VEC_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_STATUS_VEC_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A - Vec aio top memory standby enable a |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A :: VEC_MEMORY_STANDBY_ENABLE_A [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B - Vec aio top memory standby enable b |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B :: AIO_MEMORY_STANDBY_ENABLE_B [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_OBSERVE_CLOCK - Vec aio top observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_OBSERVE_CLOCK_VEC - Vec aio top observe clock vec |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK_VEC :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK_VEC :: VEC_ENABLE_OBSERVE_CLOCK_VEC [05:05] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_VEC_ENABLE_OBSERVE_CLOCK_VEC_MASK 0x00000020 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_VEC_ENABLE_OBSERVE_CLOCK_VEC_SHIFT 5 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_VEC_ENABLE_OBSERVE_CLOCK_VEC_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK_VEC :: VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_VEC [04:04] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_VEC_MASK 0x00000010 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_VEC_SHIFT 4 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_VEC_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK_VEC :: VEC_CONTROL_OBSERVE_CLOCK_VEC [03:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_VEC_CONTROL_OBSERVE_CLOCK_VEC_MASK 0x0000000f |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_VEC_CONTROL_OBSERVE_CLOCK_VEC_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_VEC_CONTROL_OBSERVE_CLOCK_VEC_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_POWER_SWITCH_MEMORY_A - Vec aio top power switch memory a |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_A :: VEC_POWER_SWITCH_MEMORY_A [01:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_MASK 0x00000003 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_POWER_SWITCH_MEMORY_B - Vec aio top power switch memory b |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_B :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_B :: AIO_POWER_SWITCH_MEMORY_B [01:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_MASK 0x00000003 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_DEFAULT 0x00000000 |
| |
| #endif /* #ifndef BCHP_CLKGEN_H__ */ |
| |
| /* End of File */ |
