blob: b558ac803f55ce2b3f4ad028548a518726e61475 [file] [log] [blame]
/***************************************************************************
* Copyright (c) 1999-2011, Broadcom Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* Module Description:
* DO NOT EDIT THIS FILE DIRECTLY
*
* This module was generated magically with RDB from a source description
* file. You must edit the source file for changes to be made to this file.
*
*
* Date: Generated on Thu Oct 27 10:23:30 2011
* MD5 Checksum 1dc065bf3d1dc88383610b02195770fc
*
* Compiled with: RDB Utility combo_header.pl
* RDB Parser 3.0
* unknown unknown
* Perl Interpreter 5.008008
* Operating System linux
*
* Revision History:
*
* $brcm_Log: $
*
***************************************************************************/
#ifndef BCHP_AON_PM_L2_H__
#define BCHP_AON_PM_L2_H__
/***************************************************************************
*AON_PM_L2 - AON Power Management L2 Interrupt Controller Registers
***************************************************************************/
#define BCHP_AON_PM_L2_CPU_STATUS 0x00408440 /* CPU interrupt Status Register */
#define BCHP_AON_PM_L2_CPU_SET 0x00408444 /* CPU interrupt Set Register */
#define BCHP_AON_PM_L2_CPU_CLEAR 0x00408448 /* CPU interrupt Clear Register */
#define BCHP_AON_PM_L2_CPU_MASK_STATUS 0x0040844c /* CPU interrupt Mask Status Register */
#define BCHP_AON_PM_L2_CPU_MASK_SET 0x00408450 /* CPU interrupt Mask Set Register */
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR 0x00408454 /* CPU interrupt Mask Clear Register */
#define BCHP_AON_PM_L2_PCI_STATUS 0x00408458 /* PCI interrupt Status Register */
#define BCHP_AON_PM_L2_PCI_SET 0x0040845c /* PCI interrupt Set Register */
#define BCHP_AON_PM_L2_PCI_CLEAR 0x00408460 /* PCI interrupt Clear Register */
#define BCHP_AON_PM_L2_PCI_MASK_STATUS 0x00408464 /* PCI interrupt Mask Status Register */
#define BCHP_AON_PM_L2_PCI_MASK_SET 0x00408468 /* PCI interrupt Mask Set Register */
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR 0x0040846c /* PCI interrupt Mask Clear Register */
/***************************************************************************
*CPU_STATUS - CPU interrupt Status Register
***************************************************************************/
/* AON_PM_L2 :: CPU_STATUS :: reserved0 [31:13] */
#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_MASK 0xffffe000
#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_SHIFT 13
/* AON_PM_L2 :: CPU_STATUS :: WOL_ENET1 [12:12] */
#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET1_MASK 0x00001000
#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET1_SHIFT 12
#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET1_DEFAULT 0
/* AON_PM_L2 :: CPU_STATUS :: FP_RESET [11:11] */
#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_MASK 0x00000800
#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_SHIFT 11
#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_DEFAULT 0
/* AON_PM_L2 :: CPU_STATUS :: BOUNDARY_SCAN_REQ [10:10] */
#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_MASK 0x00000400
#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_SHIFT 10
#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_DEFAULT 0
/* AON_PM_L2 :: CPU_STATUS :: USB1 [09:09] */
#define BCHP_AON_PM_L2_CPU_STATUS_USB1_MASK 0x00000200
#define BCHP_AON_PM_L2_CPU_STATUS_USB1_SHIFT 9
#define BCHP_AON_PM_L2_CPU_STATUS_USB1_DEFAULT 0
/* AON_PM_L2 :: CPU_STATUS :: USB0 [08:08] */
#define BCHP_AON_PM_L2_CPU_STATUS_USB0_MASK 0x00000100
#define BCHP_AON_PM_L2_CPU_STATUS_USB0_SHIFT 8
#define BCHP_AON_PM_L2_CPU_STATUS_USB0_DEFAULT 0
/* AON_PM_L2 :: CPU_STATUS :: XPT_PMU [07:07] */
#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_MASK 0x00000080
#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_SHIFT 7
#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_DEFAULT 0
/* AON_PM_L2 :: CPU_STATUS :: WOL_ENET [06:06] */
#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_MASK 0x00000040
#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_SHIFT 6
#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_DEFAULT 0
/* AON_PM_L2 :: CPU_STATUS :: GPIO [05:05] */
#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_MASK 0x00000020
#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_SHIFT 5
#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_DEFAULT 0
/* AON_PM_L2 :: CPU_STATUS :: NMI_B_INTR [04:04] */
#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_MASK 0x00000010
#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_SHIFT 4
#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_DEFAULT 0
/* AON_PM_L2 :: CPU_STATUS :: TIMER_INTR [03:03] */
#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK 0x00000008
#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_SHIFT 3
#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_DEFAULT 0
/* AON_PM_L2 :: CPU_STATUS :: KPD_INTR [02:02] */
#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_MASK 0x00000004
#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_SHIFT 2
#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_DEFAULT 0
/* AON_PM_L2 :: CPU_STATUS :: IRR_INTR [01:01] */
#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_MASK 0x00000002
#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_SHIFT 1
#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_DEFAULT 0
/* AON_PM_L2 :: CPU_STATUS :: CEC_INTR [00:00] */
#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_MASK 0x00000001
#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_SHIFT 0
#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_DEFAULT 0
/***************************************************************************
*CPU_SET - CPU interrupt Set Register
***************************************************************************/
/* AON_PM_L2 :: CPU_SET :: reserved0 [31:13] */
#define BCHP_AON_PM_L2_CPU_SET_reserved0_MASK 0xffffe000
#define BCHP_AON_PM_L2_CPU_SET_reserved0_SHIFT 13
/* AON_PM_L2 :: CPU_SET :: WOL_ENET1 [12:12] */
#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET1_MASK 0x00001000
#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET1_SHIFT 12
#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET1_DEFAULT 0
/* AON_PM_L2 :: CPU_SET :: FP_RESET [11:11] */
#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_MASK 0x00000800
#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_SHIFT 11
#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_DEFAULT 0
/* AON_PM_L2 :: CPU_SET :: BOUNDARY_SCAN_REQ [10:10] */
#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_MASK 0x00000400
#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_SHIFT 10
#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_DEFAULT 0
/* AON_PM_L2 :: CPU_SET :: USB1 [09:09] */
#define BCHP_AON_PM_L2_CPU_SET_USB1_MASK 0x00000200
#define BCHP_AON_PM_L2_CPU_SET_USB1_SHIFT 9
#define BCHP_AON_PM_L2_CPU_SET_USB1_DEFAULT 0
/* AON_PM_L2 :: CPU_SET :: USB0 [08:08] */
#define BCHP_AON_PM_L2_CPU_SET_USB0_MASK 0x00000100
#define BCHP_AON_PM_L2_CPU_SET_USB0_SHIFT 8
#define BCHP_AON_PM_L2_CPU_SET_USB0_DEFAULT 0
/* AON_PM_L2 :: CPU_SET :: XPT_PMU [07:07] */
#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_MASK 0x00000080
#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_SHIFT 7
#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_DEFAULT 0
/* AON_PM_L2 :: CPU_SET :: WOL_ENET [06:06] */
#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_MASK 0x00000040
#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_SHIFT 6
#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_DEFAULT 0
/* AON_PM_L2 :: CPU_SET :: GPIO [05:05] */
#define BCHP_AON_PM_L2_CPU_SET_GPIO_MASK 0x00000020
#define BCHP_AON_PM_L2_CPU_SET_GPIO_SHIFT 5
#define BCHP_AON_PM_L2_CPU_SET_GPIO_DEFAULT 0
/* AON_PM_L2 :: CPU_SET :: NMI_B_INTR [04:04] */
#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_MASK 0x00000010
#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_SHIFT 4
#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_DEFAULT 0
/* AON_PM_L2 :: CPU_SET :: TIMER_INTR [03:03] */
#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_MASK 0x00000008
#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_SHIFT 3
#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_DEFAULT 0
/* AON_PM_L2 :: CPU_SET :: KPD_INTR [02:02] */
#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_MASK 0x00000004
#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_SHIFT 2
#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_DEFAULT 0
/* AON_PM_L2 :: CPU_SET :: IRR_INTR [01:01] */
#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_MASK 0x00000002
#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_SHIFT 1
#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_DEFAULT 0
/* AON_PM_L2 :: CPU_SET :: CEC_INTR [00:00] */
#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_MASK 0x00000001
#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_SHIFT 0
#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_DEFAULT 0
/***************************************************************************
*CPU_CLEAR - CPU interrupt Clear Register
***************************************************************************/
/* AON_PM_L2 :: CPU_CLEAR :: reserved0 [31:13] */
#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_MASK 0xffffe000
#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_SHIFT 13
/* AON_PM_L2 :: CPU_CLEAR :: WOL_ENET1 [12:12] */
#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET1_MASK 0x00001000
#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET1_SHIFT 12
#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET1_DEFAULT 0
/* AON_PM_L2 :: CPU_CLEAR :: FP_RESET [11:11] */
#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_MASK 0x00000800
#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_SHIFT 11
#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_DEFAULT 0
/* AON_PM_L2 :: CPU_CLEAR :: BOUNDARY_SCAN_REQ [10:10] */
#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_MASK 0x00000400
#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_SHIFT 10
#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT 0
/* AON_PM_L2 :: CPU_CLEAR :: USB1 [09:09] */
#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_MASK 0x00000200
#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_SHIFT 9
#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_DEFAULT 0
/* AON_PM_L2 :: CPU_CLEAR :: USB0 [08:08] */
#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_MASK 0x00000100
#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_SHIFT 8
#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_DEFAULT 0
/* AON_PM_L2 :: CPU_CLEAR :: XPT_PMU [07:07] */
#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_MASK 0x00000080
#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_SHIFT 7
#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_DEFAULT 0
/* AON_PM_L2 :: CPU_CLEAR :: WOL_ENET [06:06] */
#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_MASK 0x00000040
#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_SHIFT 6
#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_DEFAULT 0
/* AON_PM_L2 :: CPU_CLEAR :: GPIO [05:05] */
#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_MASK 0x00000020
#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_SHIFT 5
#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_DEFAULT 0
/* AON_PM_L2 :: CPU_CLEAR :: NMI_B_INTR [04:04] */
#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_MASK 0x00000010
#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_SHIFT 4
#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_DEFAULT 0
/* AON_PM_L2 :: CPU_CLEAR :: TIMER_INTR [03:03] */
#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_MASK 0x00000008
#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_SHIFT 3
#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_DEFAULT 0
/* AON_PM_L2 :: CPU_CLEAR :: KPD_INTR [02:02] */
#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_MASK 0x00000004
#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_SHIFT 2
#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_DEFAULT 0
/* AON_PM_L2 :: CPU_CLEAR :: IRR_INTR [01:01] */
#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_MASK 0x00000002
#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_SHIFT 1
#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_DEFAULT 0
/* AON_PM_L2 :: CPU_CLEAR :: CEC_INTR [00:00] */
#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_MASK 0x00000001
#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_SHIFT 0
#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_DEFAULT 0
/***************************************************************************
*CPU_MASK_STATUS - CPU interrupt Mask Status Register
***************************************************************************/
/* AON_PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:13] */
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_MASK 0xffffe000
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT 13
/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_ENET1 [12:12] */
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET1_MASK 0x00001000
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET1_SHIFT 12
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET1_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_STATUS :: FP_RESET [11:11] */
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_MASK 0x00000800
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_SHIFT 11
/* AON_PM_L2 :: CPU_MASK_STATUS :: BOUNDARY_SCAN_REQ [10:10] */
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK 0x00000400
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT 10
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_STATUS :: USB1 [09:09] */
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_MASK 0x00000200
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_SHIFT 9
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_STATUS :: USB0 [08:08] */
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_MASK 0x00000100
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_SHIFT 8
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_STATUS :: XPT_PMU [07:07] */
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_MASK 0x00000080
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_SHIFT 7
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_ENET [06:06] */
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_MASK 0x00000040
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_SHIFT 6
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_STATUS :: GPIO [05:05] */
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_MASK 0x00000020
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_SHIFT 5
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_STATUS :: NMI_B_INTR [04:04] */
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_MASK 0x00000010
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_SHIFT 4
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_STATUS :: TIMER_INTR [03:03] */
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_MASK 0x00000008
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_SHIFT 3
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_STATUS :: KPD_INTR [02:02] */
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_MASK 0x00000004
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_SHIFT 2
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_STATUS :: IRR_INTR [01:01] */
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_MASK 0x00000002
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_SHIFT 1
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_STATUS :: CEC_INTR [00:00] */
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_MASK 0x00000001
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_SHIFT 0
#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_DEFAULT 1
/***************************************************************************
*CPU_MASK_SET - CPU interrupt Mask Set Register
***************************************************************************/
/* AON_PM_L2 :: CPU_MASK_SET :: reserved0 [31:13] */
#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_MASK 0xffffe000
#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_SHIFT 13
/* AON_PM_L2 :: CPU_MASK_SET :: WOL_ENET1 [12:12] */
#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET1_MASK 0x00001000
#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET1_SHIFT 12
#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET1_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_SET :: FP_RESET [11:11] */
#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_MASK 0x00000800
#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_SHIFT 11
/* AON_PM_L2 :: CPU_MASK_SET :: BOUNDARY_SCAN_REQ [10:10] */
#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_MASK 0x00000400
#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT 10
#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_SET :: USB1 [09:09] */
#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_MASK 0x00000200
#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_SHIFT 9
#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_SET :: USB0 [08:08] */
#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_MASK 0x00000100
#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_SHIFT 8
#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_SET :: XPT_PMU [07:07] */
#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_MASK 0x00000080
#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_SHIFT 7
#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_SET :: WOL_ENET [06:06] */
#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_MASK 0x00000040
#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_SHIFT 6
#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_SET :: GPIO [05:05] */
#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_MASK 0x00000020
#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_SHIFT 5
#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_SET :: NMI_B_INTR [04:04] */
#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_MASK 0x00000010
#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_SHIFT 4
#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_SET :: TIMER_INTR [03:03] */
#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_MASK 0x00000008
#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_SHIFT 3
#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_SET :: KPD_INTR [02:02] */
#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_MASK 0x00000004
#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_SHIFT 2
#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_SET :: IRR_INTR [01:01] */
#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_MASK 0x00000002
#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_SHIFT 1
#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_SET :: CEC_INTR [00:00] */
#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_MASK 0x00000001
#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_SHIFT 0
#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_DEFAULT 1
/***************************************************************************
*CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
***************************************************************************/
/* AON_PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:13] */
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_MASK 0xffffe000
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT 13
/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_ENET1 [12:12] */
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET1_MASK 0x00001000
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET1_SHIFT 12
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET1_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_CLEAR :: FP_RESET [11:11] */
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_MASK 0x00000800
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_SHIFT 11
/* AON_PM_L2 :: CPU_MASK_CLEAR :: BOUNDARY_SCAN_REQ [10:10] */
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK 0x00000400
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT 10
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB1 [09:09] */
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_MASK 0x00000200
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_SHIFT 9
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB0 [08:08] */
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_MASK 0x00000100
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_SHIFT 8
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_CLEAR :: XPT_PMU [07:07] */
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_MASK 0x00000080
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_SHIFT 7
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_ENET [06:06] */
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_MASK 0x00000040
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_SHIFT 6
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_CLEAR :: GPIO [05:05] */
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_MASK 0x00000020
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_SHIFT 5
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_CLEAR :: NMI_B_INTR [04:04] */
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_MASK 0x00000010
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_SHIFT 4
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_CLEAR :: TIMER_INTR [03:03] */
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_MASK 0x00000008
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_SHIFT 3
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_CLEAR :: KPD_INTR [02:02] */
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_MASK 0x00000004
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_SHIFT 2
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_CLEAR :: IRR_INTR [01:01] */
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK 0x00000002
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_SHIFT 1
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_DEFAULT 1
/* AON_PM_L2 :: CPU_MASK_CLEAR :: CEC_INTR [00:00] */
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_MASK 0x00000001
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_SHIFT 0
#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_DEFAULT 1
/***************************************************************************
*PCI_STATUS - PCI interrupt Status Register
***************************************************************************/
/* AON_PM_L2 :: PCI_STATUS :: reserved0 [31:13] */
#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_MASK 0xffffe000
#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_SHIFT 13
/* AON_PM_L2 :: PCI_STATUS :: WOL_ENET1 [12:12] */
#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET1_MASK 0x00001000
#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET1_SHIFT 12
#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET1_DEFAULT 0
/* AON_PM_L2 :: PCI_STATUS :: FP_RESET [11:11] */
#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_MASK 0x00000800
#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_SHIFT 11
#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_DEFAULT 0
/* AON_PM_L2 :: PCI_STATUS :: BOUNDARY_SCAN_REQ [10:10] */
#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_MASK 0x00000400
#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_SHIFT 10
#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_DEFAULT 0
/* AON_PM_L2 :: PCI_STATUS :: USB1 [09:09] */
#define BCHP_AON_PM_L2_PCI_STATUS_USB1_MASK 0x00000200
#define BCHP_AON_PM_L2_PCI_STATUS_USB1_SHIFT 9
#define BCHP_AON_PM_L2_PCI_STATUS_USB1_DEFAULT 0
/* AON_PM_L2 :: PCI_STATUS :: USB0 [08:08] */
#define BCHP_AON_PM_L2_PCI_STATUS_USB0_MASK 0x00000100
#define BCHP_AON_PM_L2_PCI_STATUS_USB0_SHIFT 8
#define BCHP_AON_PM_L2_PCI_STATUS_USB0_DEFAULT 0
/* AON_PM_L2 :: PCI_STATUS :: XPT_PMU [07:07] */
#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_MASK 0x00000080
#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_SHIFT 7
#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_DEFAULT 0
/* AON_PM_L2 :: PCI_STATUS :: WOL_ENET [06:06] */
#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_MASK 0x00000040
#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_SHIFT 6
#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_DEFAULT 0
/* AON_PM_L2 :: PCI_STATUS :: GPIO [05:05] */
#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_MASK 0x00000020
#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_SHIFT 5
#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_DEFAULT 0
/* AON_PM_L2 :: PCI_STATUS :: NMI_B_INTR [04:04] */
#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_MASK 0x00000010
#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_SHIFT 4
#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_DEFAULT 0
/* AON_PM_L2 :: PCI_STATUS :: TIMER_INTR [03:03] */
#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_MASK 0x00000008
#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_SHIFT 3
#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_DEFAULT 0
/* AON_PM_L2 :: PCI_STATUS :: KPD_INTR [02:02] */
#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_MASK 0x00000004
#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_SHIFT 2
#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_DEFAULT 0
/* AON_PM_L2 :: PCI_STATUS :: IRR_INTR [01:01] */
#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_MASK 0x00000002
#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_SHIFT 1
#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_DEFAULT 0
/* AON_PM_L2 :: PCI_STATUS :: CEC_INTR [00:00] */
#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_MASK 0x00000001
#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_SHIFT 0
#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_DEFAULT 0
/***************************************************************************
*PCI_SET - PCI interrupt Set Register
***************************************************************************/
/* AON_PM_L2 :: PCI_SET :: reserved0 [31:13] */
#define BCHP_AON_PM_L2_PCI_SET_reserved0_MASK 0xffffe000
#define BCHP_AON_PM_L2_PCI_SET_reserved0_SHIFT 13
/* AON_PM_L2 :: PCI_SET :: WOL_ENET1 [12:12] */
#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET1_MASK 0x00001000
#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET1_SHIFT 12
#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET1_DEFAULT 0
/* AON_PM_L2 :: PCI_SET :: FP_RESET [11:11] */
#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_MASK 0x00000800
#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_SHIFT 11
#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_DEFAULT 0
/* AON_PM_L2 :: PCI_SET :: BOUNDARY_SCAN_REQ [10:10] */
#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_MASK 0x00000400
#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_SHIFT 10
#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_DEFAULT 0
/* AON_PM_L2 :: PCI_SET :: USB1 [09:09] */
#define BCHP_AON_PM_L2_PCI_SET_USB1_MASK 0x00000200
#define BCHP_AON_PM_L2_PCI_SET_USB1_SHIFT 9
#define BCHP_AON_PM_L2_PCI_SET_USB1_DEFAULT 0
/* AON_PM_L2 :: PCI_SET :: USB0 [08:08] */
#define BCHP_AON_PM_L2_PCI_SET_USB0_MASK 0x00000100
#define BCHP_AON_PM_L2_PCI_SET_USB0_SHIFT 8
#define BCHP_AON_PM_L2_PCI_SET_USB0_DEFAULT 0
/* AON_PM_L2 :: PCI_SET :: XPT_PMU [07:07] */
#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_MASK 0x00000080
#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_SHIFT 7
#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_DEFAULT 0
/* AON_PM_L2 :: PCI_SET :: WOL_ENET [06:06] */
#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_MASK 0x00000040
#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_SHIFT 6
#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_DEFAULT 0
/* AON_PM_L2 :: PCI_SET :: GPIO [05:05] */
#define BCHP_AON_PM_L2_PCI_SET_GPIO_MASK 0x00000020
#define BCHP_AON_PM_L2_PCI_SET_GPIO_SHIFT 5
#define BCHP_AON_PM_L2_PCI_SET_GPIO_DEFAULT 0
/* AON_PM_L2 :: PCI_SET :: NMI_B_INTR [04:04] */
#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_MASK 0x00000010
#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_SHIFT 4
#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_DEFAULT 0
/* AON_PM_L2 :: PCI_SET :: TIMER_INTR [03:03] */
#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_MASK 0x00000008
#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_SHIFT 3
#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_DEFAULT 0
/* AON_PM_L2 :: PCI_SET :: KPD_INTR [02:02] */
#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_MASK 0x00000004
#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_SHIFT 2
#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_DEFAULT 0
/* AON_PM_L2 :: PCI_SET :: IRR_INTR [01:01] */
#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_MASK 0x00000002
#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_SHIFT 1
#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_DEFAULT 0
/* AON_PM_L2 :: PCI_SET :: CEC_INTR [00:00] */
#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_MASK 0x00000001
#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_SHIFT 0
#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_DEFAULT 0
/***************************************************************************
*PCI_CLEAR - PCI interrupt Clear Register
***************************************************************************/
/* AON_PM_L2 :: PCI_CLEAR :: reserved0 [31:13] */
#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_MASK 0xffffe000
#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_SHIFT 13
/* AON_PM_L2 :: PCI_CLEAR :: WOL_ENET1 [12:12] */
#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET1_MASK 0x00001000
#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET1_SHIFT 12
#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET1_DEFAULT 0
/* AON_PM_L2 :: PCI_CLEAR :: FP_RESET [11:11] */
#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_MASK 0x00000800
#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_SHIFT 11
#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_DEFAULT 0
/* AON_PM_L2 :: PCI_CLEAR :: BOUNDARY_SCAN_REQ [10:10] */
#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_MASK 0x00000400
#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_SHIFT 10
#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT 0
/* AON_PM_L2 :: PCI_CLEAR :: USB1 [09:09] */
#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_MASK 0x00000200
#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_SHIFT 9
#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_DEFAULT 0
/* AON_PM_L2 :: PCI_CLEAR :: USB0 [08:08] */
#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_MASK 0x00000100
#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_SHIFT 8
#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_DEFAULT 0
/* AON_PM_L2 :: PCI_CLEAR :: XPT_PMU [07:07] */
#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_MASK 0x00000080
#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_SHIFT 7
#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_DEFAULT 0
/* AON_PM_L2 :: PCI_CLEAR :: WOL_ENET [06:06] */
#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_MASK 0x00000040
#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_SHIFT 6
#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_DEFAULT 0
/* AON_PM_L2 :: PCI_CLEAR :: GPIO [05:05] */
#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_MASK 0x00000020
#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_SHIFT 5
#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_DEFAULT 0
/* AON_PM_L2 :: PCI_CLEAR :: NMI_B_INTR [04:04] */
#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_MASK 0x00000010
#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_SHIFT 4
#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_DEFAULT 0
/* AON_PM_L2 :: PCI_CLEAR :: TIMER_INTR [03:03] */
#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_MASK 0x00000008
#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_SHIFT 3
#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_DEFAULT 0
/* AON_PM_L2 :: PCI_CLEAR :: KPD_INTR [02:02] */
#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_MASK 0x00000004
#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_SHIFT 2
#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_DEFAULT 0
/* AON_PM_L2 :: PCI_CLEAR :: IRR_INTR [01:01] */
#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_MASK 0x00000002
#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_SHIFT 1
#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_DEFAULT 0
/* AON_PM_L2 :: PCI_CLEAR :: CEC_INTR [00:00] */
#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_MASK 0x00000001
#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_SHIFT 0
#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_DEFAULT 0
/***************************************************************************
*PCI_MASK_STATUS - PCI interrupt Mask Status Register
***************************************************************************/
/* AON_PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:13] */
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_MASK 0xffffe000
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT 13
/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_ENET1 [12:12] */
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET1_MASK 0x00001000
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET1_SHIFT 12
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET1_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_STATUS :: FP_RESET [11:11] */
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_MASK 0x00000800
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_SHIFT 11
/* AON_PM_L2 :: PCI_MASK_STATUS :: BOUNDARY_SCAN_REQ [10:10] */
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK 0x00000400
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT 10
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_STATUS :: USB1 [09:09] */
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_MASK 0x00000200
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_SHIFT 9
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_STATUS :: USB0 [08:08] */
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_MASK 0x00000100
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_SHIFT 8
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_STATUS :: XPT_PMU [07:07] */
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_MASK 0x00000080
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_SHIFT 7
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_ENET [06:06] */
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_MASK 0x00000040
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_SHIFT 6
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_STATUS :: GPIO [05:05] */
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_MASK 0x00000020
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_SHIFT 5
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_STATUS :: NMI_B_INTR [04:04] */
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_MASK 0x00000010
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_SHIFT 4
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_STATUS :: TIMER_INTR [03:03] */
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_MASK 0x00000008
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_SHIFT 3
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_STATUS :: KPD_INTR [02:02] */
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_MASK 0x00000004
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_SHIFT 2
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_STATUS :: IRR_INTR [01:01] */
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_MASK 0x00000002
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_SHIFT 1
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_STATUS :: CEC_INTR [00:00] */
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_MASK 0x00000001
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_SHIFT 0
#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_DEFAULT 1
/***************************************************************************
*PCI_MASK_SET - PCI interrupt Mask Set Register
***************************************************************************/
/* AON_PM_L2 :: PCI_MASK_SET :: reserved0 [31:13] */
#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_MASK 0xffffe000
#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_SHIFT 13
/* AON_PM_L2 :: PCI_MASK_SET :: WOL_ENET1 [12:12] */
#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET1_MASK 0x00001000
#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET1_SHIFT 12
#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET1_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_SET :: FP_RESET [11:11] */
#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_MASK 0x00000800
#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_SHIFT 11
/* AON_PM_L2 :: PCI_MASK_SET :: BOUNDARY_SCAN_REQ [10:10] */
#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_MASK 0x00000400
#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT 10
#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_SET :: USB1 [09:09] */
#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_MASK 0x00000200
#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_SHIFT 9
#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_SET :: USB0 [08:08] */
#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_MASK 0x00000100
#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_SHIFT 8
#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_SET :: XPT_PMU [07:07] */
#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_MASK 0x00000080
#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_SHIFT 7
#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_SET :: WOL_ENET [06:06] */
#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_MASK 0x00000040
#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_SHIFT 6
#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_SET :: GPIO [05:05] */
#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_MASK 0x00000020
#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_SHIFT 5
#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_SET :: NMI_B_INTR [04:04] */
#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_MASK 0x00000010
#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_SHIFT 4
#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_SET :: TIMER_INTR [03:03] */
#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_MASK 0x00000008
#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_SHIFT 3
#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_SET :: KPD_INTR [02:02] */
#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_MASK 0x00000004
#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_SHIFT 2
#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_SET :: IRR_INTR [01:01] */
#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_MASK 0x00000002
#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_SHIFT 1
#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_SET :: CEC_INTR [00:00] */
#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_MASK 0x00000001
#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_SHIFT 0
#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_DEFAULT 1
/***************************************************************************
*PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
***************************************************************************/
/* AON_PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:13] */
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_MASK 0xffffe000
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT 13
/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_ENET1 [12:12] */
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET1_MASK 0x00001000
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET1_SHIFT 12
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET1_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_CLEAR :: FP_RESET [11:11] */
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_MASK 0x00000800
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_SHIFT 11
/* AON_PM_L2 :: PCI_MASK_CLEAR :: BOUNDARY_SCAN_REQ [10:10] */
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK 0x00000400
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT 10
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB1 [09:09] */
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_MASK 0x00000200
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_SHIFT 9
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB0 [08:08] */
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_MASK 0x00000100
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_SHIFT 8
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_CLEAR :: XPT_PMU [07:07] */
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_MASK 0x00000080
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_SHIFT 7
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_ENET [06:06] */
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_MASK 0x00000040
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_SHIFT 6
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_CLEAR :: GPIO [05:05] */
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_MASK 0x00000020
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_SHIFT 5
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_CLEAR :: NMI_B_INTR [04:04] */
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_MASK 0x00000010
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_SHIFT 4
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_CLEAR :: TIMER_INTR [03:03] */
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_MASK 0x00000008
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_SHIFT 3
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_CLEAR :: KPD_INTR [02:02] */
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_MASK 0x00000004
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_SHIFT 2
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_CLEAR :: IRR_INTR [01:01] */
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_MASK 0x00000002
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_SHIFT 1
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_DEFAULT 1
/* AON_PM_L2 :: PCI_MASK_CLEAR :: CEC_INTR [00:00] */
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_MASK 0x00000001
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_SHIFT 0
#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_DEFAULT 1
#endif /* #ifndef BCHP_AON_PM_L2_H__ */
/* End of File */