| /* |
| * MPC8555 CDS Device Tree Source |
| * |
| * Copyright 2006, 2008 Freescale Semiconductor Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify it |
| * under the terms of the GNU General Public License as published by the |
| * Free Software Foundation; either version 2 of the License, or (at your |
| * option) any later version. |
| */ |
| |
| /dts-v1/; |
| |
| /include/ "fsl/e500v2_power_isa.dtsi" |
| |
| / { |
| model = "MPC8555CDS"; |
| compatible = "MPC8555CDS", "MPC85xxCDS"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| aliases { |
| ethernet0 = &enet0; |
| ethernet1 = &enet1; |
| serial0 = &serial0; |
| serial1 = &serial1; |
| pci0 = &pci0; |
| pci1 = &pci1; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| PowerPC,8555@0 { |
| device_type = "cpu"; |
| reg = <0x0>; |
| d-cache-line-size = <32>; // 32 bytes |
| i-cache-line-size = <32>; // 32 bytes |
| d-cache-size = <0x8000>; // L1, 32K |
| i-cache-size = <0x8000>; // L1, 32K |
| timebase-frequency = <0>; // 33 MHz, from uboot |
| bus-frequency = <0>; // 166 MHz |
| clock-frequency = <0>; // 825 MHz, from uboot |
| next-level-cache = <&L2>; |
| }; |
| }; |
| |
| memory { |
| device_type = "memory"; |
| reg = <0x0 0x8000000>; // 128M at 0x0 |
| }; |
| |
| soc8555@e0000000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| device_type = "soc"; |
| compatible = "simple-bus"; |
| ranges = <0x0 0xe0000000 0x100000>; |
| bus-frequency = <0>; |
| |
| ecm-law@0 { |
| compatible = "fsl,ecm-law"; |
| reg = <0x0 0x1000>; |
| fsl,num-laws = <8>; |
| }; |
| |
| ecm@1000 { |
| compatible = "fsl,mpc8555-ecm", "fsl,ecm"; |
| reg = <0x1000 0x1000>; |
| interrupts = <17 2>; |
| interrupt-parent = <&mpic>; |
| }; |
| |
| memory-controller@2000 { |
| compatible = "fsl,mpc8555-memory-controller"; |
| reg = <0x2000 0x1000>; |
| interrupt-parent = <&mpic>; |
| interrupts = <18 2>; |
| }; |
| |
| L2: l2-cache-controller@20000 { |
| compatible = "fsl,mpc8555-l2-cache-controller"; |
| reg = <0x20000 0x1000>; |
| cache-line-size = <32>; // 32 bytes |
| cache-size = <0x40000>; // L2, 256K |
| interrupt-parent = <&mpic>; |
| interrupts = <16 2>; |
| }; |
| |
| i2c@3000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| cell-index = <0>; |
| compatible = "fsl-i2c"; |
| reg = <0x3000 0x100>; |
| interrupts = <43 2>; |
| interrupt-parent = <&mpic>; |
| dfsrr; |
| }; |
| |
| dma@21300 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma"; |
| reg = <0x21300 0x4>; |
| ranges = <0x0 0x21100 0x200>; |
| cell-index = <0>; |
| dma-channel@0 { |
| compatible = "fsl,mpc8555-dma-channel", |
| "fsl,eloplus-dma-channel"; |
| reg = <0x0 0x80>; |
| cell-index = <0>; |
| interrupt-parent = <&mpic>; |
| interrupts = <20 2>; |
| }; |
| dma-channel@80 { |
| compatible = "fsl,mpc8555-dma-channel", |
| "fsl,eloplus-dma-channel"; |
| reg = <0x80 0x80>; |
| cell-index = <1>; |
| interrupt-parent = <&mpic>; |
| interrupts = <21 2>; |
| }; |
| dma-channel@100 { |
| compatible = "fsl,mpc8555-dma-channel", |
| "fsl,eloplus-dma-channel"; |
| reg = <0x100 0x80>; |
| cell-index = <2>; |
| interrupt-parent = <&mpic>; |
| interrupts = <22 2>; |
| }; |
| dma-channel@180 { |
| compatible = "fsl,mpc8555-dma-channel", |
| "fsl,eloplus-dma-channel"; |
| reg = <0x180 0x80>; |
| cell-index = <3>; |
| interrupt-parent = <&mpic>; |
| interrupts = <23 2>; |
| }; |
| }; |
| |
| enet0: ethernet@24000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| cell-index = <0>; |
| device_type = "network"; |
| model = "TSEC"; |
| compatible = "gianfar"; |
| reg = <0x24000 0x1000>; |
| ranges = <0x0 0x24000 0x1000>; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| interrupts = <29 2 30 2 34 2>; |
| interrupt-parent = <&mpic>; |
| tbi-handle = <&tbi0>; |
| phy-handle = <&phy0>; |
| |
| mdio@520 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,gianfar-mdio"; |
| reg = <0x520 0x20>; |
| |
| phy0: ethernet-phy@0 { |
| interrupt-parent = <&mpic>; |
| interrupts = <5 1>; |
| reg = <0x0>; |
| }; |
| phy1: ethernet-phy@1 { |
| interrupt-parent = <&mpic>; |
| interrupts = <5 1>; |
| reg = <0x1>; |
| }; |
| tbi0: tbi-phy@11 { |
| reg = <0x11>; |
| device_type = "tbi-phy"; |
| }; |
| }; |
| }; |
| |
| enet1: ethernet@25000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| cell-index = <1>; |
| device_type = "network"; |
| model = "TSEC"; |
| compatible = "gianfar"; |
| reg = <0x25000 0x1000>; |
| ranges = <0x0 0x25000 0x1000>; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| interrupts = <35 2 36 2 40 2>; |
| interrupt-parent = <&mpic>; |
| tbi-handle = <&tbi1>; |
| phy-handle = <&phy1>; |
| |
| mdio@520 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,gianfar-tbi"; |
| reg = <0x520 0x20>; |
| |
| tbi1: tbi-phy@11 { |
| reg = <0x11>; |
| device_type = "tbi-phy"; |
| }; |
| }; |
| }; |
| |
| serial0: serial@4500 { |
| cell-index = <0>; |
| device_type = "serial"; |
| compatible = "fsl,ns16550", "ns16550"; |
| reg = <0x4500 0x100>; // reg base, size |
| clock-frequency = <0>; // should we fill in in uboot? |
| interrupts = <42 2>; |
| interrupt-parent = <&mpic>; |
| }; |
| |
| serial1: serial@4600 { |
| cell-index = <1>; |
| device_type = "serial"; |
| compatible = "fsl,ns16550", "ns16550"; |
| reg = <0x4600 0x100>; // reg base, size |
| clock-frequency = <0>; // should we fill in in uboot? |
| interrupts = <42 2>; |
| interrupt-parent = <&mpic>; |
| }; |
| |
| crypto@30000 { |
| compatible = "fsl,sec2.0"; |
| reg = <0x30000 0x10000>; |
| interrupts = <45 2>; |
| interrupt-parent = <&mpic>; |
| fsl,num-channels = <4>; |
| fsl,channel-fifo-len = <24>; |
| fsl,exec-units-mask = <0x7e>; |
| fsl,descriptor-types-mask = <0x01010ebf>; |
| }; |
| |
| mpic: pic@40000 { |
| interrupt-controller; |
| #address-cells = <0>; |
| #interrupt-cells = <2>; |
| reg = <0x40000 0x40000>; |
| compatible = "chrp,open-pic"; |
| device_type = "open-pic"; |
| }; |
| |
| cpm@919c0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "fsl,mpc8555-cpm", "fsl,cpm2"; |
| reg = <0x919c0 0x30>; |
| ranges; |
| |
| muram@80000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x80000 0x10000>; |
| |
| data@0 { |
| compatible = "fsl,cpm-muram-data"; |
| reg = <0x0 0x2000 0x9000 0x1000>; |
| }; |
| }; |
| |
| brg@919f0 { |
| compatible = "fsl,mpc8555-brg", |
| "fsl,cpm2-brg", |
| "fsl,cpm-brg"; |
| reg = <0x919f0 0x10 0x915f0 0x10>; |
| }; |
| |
| cpmpic: pic@90c00 { |
| interrupt-controller; |
| #address-cells = <0>; |
| #interrupt-cells = <2>; |
| interrupts = <46 2>; |
| interrupt-parent = <&mpic>; |
| reg = <0x90c00 0x80>; |
| compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic"; |
| }; |
| }; |
| }; |
| |
| pci0: pci@e0008000 { |
| interrupt-map-mask = <0x1f800 0x0 0x0 0x7>; |
| interrupt-map = < |
| |
| /* IDSEL 0x10 */ |
| 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1 |
| 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1 |
| 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1 |
| 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1 |
| |
| /* IDSEL 0x11 */ |
| 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1 |
| 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1 |
| 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1 |
| 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1 |
| |
| /* IDSEL 0x12 (Slot 1) */ |
| 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1 |
| 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1 |
| 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 |
| 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1 |
| |
| /* IDSEL 0x13 (Slot 2) */ |
| 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1 |
| 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1 |
| 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1 |
| 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1 |
| |
| /* IDSEL 0x14 (Slot 3) */ |
| 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1 |
| 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1 |
| 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1 |
| 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1 |
| |
| /* IDSEL 0x15 (Slot 4) */ |
| 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1 |
| 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1 |
| 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1 |
| 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1 |
| |
| /* Bus 1 (Tundra Bridge) */ |
| /* IDSEL 0x12 (ISA bridge) */ |
| 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1 |
| 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1 |
| 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1 |
| 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>; |
| interrupt-parent = <&mpic>; |
| interrupts = <24 2>; |
| bus-range = <0 0>; |
| ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 |
| 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>; |
| clock-frequency = <66666666>; |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| reg = <0xe0008000 0x1000>; |
| compatible = "fsl,mpc8540-pci"; |
| device_type = "pci"; |
| |
| i8259@19000 { |
| interrupt-controller; |
| device_type = "interrupt-controller"; |
| reg = <0x19000 0x0 0x0 0x0 0x1>; |
| #address-cells = <0>; |
| #interrupt-cells = <2>; |
| compatible = "chrp,iic"; |
| interrupts = <1>; |
| interrupt-parent = <&pci0>; |
| }; |
| }; |
| |
| pci1: pci@e0009000 { |
| interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| interrupt-map = < |
| |
| /* IDSEL 0x15 */ |
| 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 |
| 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1 |
| 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1 |
| 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>; |
| interrupt-parent = <&mpic>; |
| interrupts = <25 2>; |
| bus-range = <0 0>; |
| ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 |
| 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>; |
| clock-frequency = <66666666>; |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| reg = <0xe0009000 0x1000>; |
| compatible = "fsl,mpc8540-pci"; |
| device_type = "pci"; |
| }; |
| }; |
