| /* |
| * This file contains the simple DMA Implementation for Blackfin |
| * |
| * Copyright 2007-2008 Analog Devices Inc. |
| * |
| * Licensed under the GPL-2 or later. |
| */ |
| |
| #include <linux/module.h> |
| |
| #include <asm/blackfin.h> |
| #include <asm/dma.h> |
| |
| struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = { |
| (struct dma_register *) DMA0_NEXT_DESC_PTR, |
| (struct dma_register *) DMA1_NEXT_DESC_PTR, |
| (struct dma_register *) DMA2_NEXT_DESC_PTR, |
| (struct dma_register *) DMA3_NEXT_DESC_PTR, |
| (struct dma_register *) DMA4_NEXT_DESC_PTR, |
| (struct dma_register *) DMA5_NEXT_DESC_PTR, |
| (struct dma_register *) DMA6_NEXT_DESC_PTR, |
| (struct dma_register *) DMA7_NEXT_DESC_PTR, |
| (struct dma_register *) DMA8_NEXT_DESC_PTR, |
| (struct dma_register *) DMA9_NEXT_DESC_PTR, |
| (struct dma_register *) DMA10_NEXT_DESC_PTR, |
| (struct dma_register *) DMA11_NEXT_DESC_PTR, |
| (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, |
| (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, |
| (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, |
| (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, |
| }; |
| EXPORT_SYMBOL(dma_io_base_addr); |
| |
| int channel2irq(unsigned int channel) |
| { |
| int ret_irq = -1; |
| |
| switch (channel) { |
| case CH_PPI: |
| ret_irq = IRQ_PPI; |
| break; |
| |
| case CH_EMAC_RX: |
| ret_irq = IRQ_MAC_RX; |
| break; |
| |
| case CH_EMAC_TX: |
| ret_irq = IRQ_MAC_TX; |
| break; |
| |
| case CH_UART1_RX: |
| ret_irq = IRQ_UART1_RX; |
| break; |
| |
| case CH_UART1_TX: |
| ret_irq = IRQ_UART1_TX; |
| break; |
| |
| case CH_SPORT0_RX: |
| ret_irq = IRQ_SPORT0_RX; |
| break; |
| |
| case CH_SPORT0_TX: |
| ret_irq = IRQ_SPORT0_TX; |
| break; |
| |
| case CH_SPORT1_RX: |
| ret_irq = IRQ_SPORT1_RX; |
| break; |
| |
| case CH_SPORT1_TX: |
| ret_irq = IRQ_SPORT1_TX; |
| break; |
| |
| case CH_SPI: |
| ret_irq = IRQ_SPI; |
| break; |
| |
| case CH_UART0_RX: |
| ret_irq = IRQ_UART0_RX; |
| break; |
| |
| case CH_UART0_TX: |
| ret_irq = IRQ_UART0_TX; |
| break; |
| |
| case CH_MEM_STREAM0_SRC: |
| case CH_MEM_STREAM0_DEST: |
| ret_irq = IRQ_MEM_DMA0; |
| break; |
| |
| case CH_MEM_STREAM1_SRC: |
| case CH_MEM_STREAM1_DEST: |
| ret_irq = IRQ_MEM_DMA1; |
| break; |
| } |
| return ret_irq; |
| } |