| /*************************************************************************** |
| * Copyright (c) 1999-2009, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Mon May 4 16:33:40 2009 |
| * MD5 Checksum 41a22724f57416cfb69cc3f3286da43f |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: /magnum/basemodules/chp/7550/rdb/a0/bchp_irq0.h $ |
| * |
| * Hydra_Software_Devel/1 5/4/09 7:07p albertl |
| * PR54730: Initial revision. |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_IRQ0_H__ |
| #define BCHP_IRQ0_H__ |
| |
| /*************************************************************************** |
| *IRQ0 - Level 2 CPU Interrupt Enable/Status |
| ***************************************************************************/ |
| #define BCHP_IRQ0_IRQEN 0x00406780 /* UPG Shared Interrupt Enable */ |
| #define BCHP_IRQ0_IRQSTAT 0x00406784 /* UPG Shared Interrupt Status */ |
| #define BCHP_IRQ0_SPI_IRQEN 0x00406788 /* SPI Master Interrupt Enable */ |
| #define BCHP_IRQ0_SPI_IRQSTAT 0x0040678c /* SPI Master Interrupt Status */ |
| #define BCHP_IRQ0_BSC_IRQEN 0x00406790 /* BSC Master Interrupt Enable */ |
| #define BCHP_IRQ0_BSC_IRQSTAT 0x00406794 /* BSC Master Interrupt Status */ |
| #define BCHP_IRQ0_UART_IRQEN 0x00406798 /* UART Channel 0 Interrupt Enable */ |
| #define BCHP_IRQ0_UART_IRQSTAT 0x0040679c /* UART Channel 0 Interrupt Status */ |
| #define BCHP_IRQ0_GPIO_IRQEN 0x004067a0 /* GPIO Interrupt Enable */ |
| #define BCHP_IRQ0_GPIO_IRQSTAT 0x004067a4 /* GPIO Interrupt Status */ |
| #define BCHP_IRQ0_ANT_IRQEN 0x004067a8 /* Antenna Interface Interrupt Enable */ |
| #define BCHP_IRQ0_ANT_IRQSTAT 0x004067ac /* Antenna Interface Interrupt Status */ |
| |
| /*************************************************************************** |
| *IRQEN - UPG Shared Interrupt Enable |
| ***************************************************************************/ |
| /* IRQ0 :: IRQEN :: reserved0 [31:10] */ |
| #define BCHP_IRQ0_IRQEN_reserved0_MASK 0xfffffc00 |
| #define BCHP_IRQ0_IRQEN_reserved0_SHIFT 10 |
| |
| /* IRQ0 :: IRQEN :: uc [09:09] */ |
| #define BCHP_IRQ0_IRQEN_uc_MASK 0x00000200 |
| #define BCHP_IRQ0_IRQEN_uc_SHIFT 9 |
| |
| /* IRQ0 :: IRQEN :: reserved1 [08:08] */ |
| #define BCHP_IRQ0_IRQEN_reserved1_MASK 0x00000100 |
| #define BCHP_IRQ0_IRQEN_reserved1_SHIFT 8 |
| |
| /* IRQ0 :: IRQEN :: icap [07:07] */ |
| #define BCHP_IRQ0_IRQEN_icap_MASK 0x00000080 |
| #define BCHP_IRQ0_IRQEN_icap_SHIFT 7 |
| |
| /* IRQ0 :: IRQEN :: reserved_for_eco2 [06:05] */ |
| #define BCHP_IRQ0_IRQEN_reserved_for_eco2_MASK 0x00000060 |
| #define BCHP_IRQ0_IRQEN_reserved_for_eco2_SHIFT 5 |
| |
| /* IRQ0 :: IRQEN :: ua [04:04] */ |
| #define BCHP_IRQ0_IRQEN_ua_MASK 0x00000010 |
| #define BCHP_IRQ0_IRQEN_ua_SHIFT 4 |
| |
| /* IRQ0 :: IRQEN :: ub [03:03] */ |
| #define BCHP_IRQ0_IRQEN_ub_MASK 0x00000008 |
| #define BCHP_IRQ0_IRQEN_ub_SHIFT 3 |
| |
| /* IRQ0 :: IRQEN :: irb [02:02] */ |
| #define BCHP_IRQ0_IRQEN_irb_MASK 0x00000004 |
| #define BCHP_IRQ0_IRQEN_irb_SHIFT 2 |
| |
| /* IRQ0 :: IRQEN :: ldk [01:01] */ |
| #define BCHP_IRQ0_IRQEN_ldk_MASK 0x00000002 |
| #define BCHP_IRQ0_IRQEN_ldk_SHIFT 1 |
| |
| /* IRQ0 :: IRQEN :: kbd1 [00:00] */ |
| #define BCHP_IRQ0_IRQEN_kbd1_MASK 0x00000001 |
| #define BCHP_IRQ0_IRQEN_kbd1_SHIFT 0 |
| |
| /*************************************************************************** |
| *IRQSTAT - UPG Shared Interrupt Status |
| ***************************************************************************/ |
| /* IRQ0 :: IRQSTAT :: reserved0 [31:10] */ |
| #define BCHP_IRQ0_IRQSTAT_reserved0_MASK 0xfffffc00 |
| #define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT 10 |
| |
| /* IRQ0 :: IRQSTAT :: uc [09:09] */ |
| #define BCHP_IRQ0_IRQSTAT_uc_MASK 0x00000200 |
| #define BCHP_IRQ0_IRQSTAT_uc_SHIFT 9 |
| |
| /* IRQ0 :: IRQSTAT :: reserved1 [08:08] */ |
| #define BCHP_IRQ0_IRQSTAT_reserved1_MASK 0x00000100 |
| #define BCHP_IRQ0_IRQSTAT_reserved1_SHIFT 8 |
| |
| /* IRQ0 :: IRQSTAT :: icap [07:07] */ |
| #define BCHP_IRQ0_IRQSTAT_icap_MASK 0x00000080 |
| #define BCHP_IRQ0_IRQSTAT_icap_SHIFT 7 |
| |
| /* IRQ0 :: IRQSTAT :: reserved2 [06:05] */ |
| #define BCHP_IRQ0_IRQSTAT_reserved2_MASK 0x00000060 |
| #define BCHP_IRQ0_IRQSTAT_reserved2_SHIFT 5 |
| |
| /* IRQ0 :: IRQSTAT :: ua [04:04] */ |
| #define BCHP_IRQ0_IRQSTAT_ua_MASK 0x00000010 |
| #define BCHP_IRQ0_IRQSTAT_ua_SHIFT 4 |
| |
| /* IRQ0 :: IRQSTAT :: ub [03:03] */ |
| #define BCHP_IRQ0_IRQSTAT_ub_MASK 0x00000008 |
| #define BCHP_IRQ0_IRQSTAT_ub_SHIFT 3 |
| |
| /* IRQ0 :: IRQSTAT :: irb [02:02] */ |
| #define BCHP_IRQ0_IRQSTAT_irb_MASK 0x00000004 |
| #define BCHP_IRQ0_IRQSTAT_irb_SHIFT 2 |
| |
| /* IRQ0 :: IRQSTAT :: ldk [01:01] */ |
| #define BCHP_IRQ0_IRQSTAT_ldk_MASK 0x00000002 |
| #define BCHP_IRQ0_IRQSTAT_ldk_SHIFT 1 |
| |
| /* IRQ0 :: IRQSTAT :: kbd1 [00:00] */ |
| #define BCHP_IRQ0_IRQSTAT_kbd1_MASK 0x00000001 |
| #define BCHP_IRQ0_IRQSTAT_kbd1_SHIFT 0 |
| |
| /*************************************************************************** |
| *SPI_IRQEN - SPI Master Interrupt Enable |
| ***************************************************************************/ |
| /* IRQ0 :: SPI_IRQEN :: reserved0 [31:01] */ |
| #define BCHP_IRQ0_SPI_IRQEN_reserved0_MASK 0xfffffffe |
| #define BCHP_IRQ0_SPI_IRQEN_reserved0_SHIFT 1 |
| |
| /* IRQ0 :: SPI_IRQEN :: spi [00:00] */ |
| #define BCHP_IRQ0_SPI_IRQEN_spi_MASK 0x00000001 |
| #define BCHP_IRQ0_SPI_IRQEN_spi_SHIFT 0 |
| |
| /*************************************************************************** |
| *SPI_IRQSTAT - SPI Master Interrupt Status |
| ***************************************************************************/ |
| /* IRQ0 :: SPI_IRQSTAT :: reserved0 [31:01] */ |
| #define BCHP_IRQ0_SPI_IRQSTAT_reserved0_MASK 0xfffffffe |
| #define BCHP_IRQ0_SPI_IRQSTAT_reserved0_SHIFT 1 |
| |
| /* IRQ0 :: SPI_IRQSTAT :: spi [00:00] */ |
| #define BCHP_IRQ0_SPI_IRQSTAT_spi_MASK 0x00000001 |
| #define BCHP_IRQ0_SPI_IRQSTAT_spi_SHIFT 0 |
| |
| /*************************************************************************** |
| *BSC_IRQEN - BSC Master Interrupt Enable |
| ***************************************************************************/ |
| /* IRQ0 :: BSC_IRQEN :: reserved0 [31:04] */ |
| #define BCHP_IRQ0_BSC_IRQEN_reserved0_MASK 0xfffffff0 |
| #define BCHP_IRQ0_BSC_IRQEN_reserved0_SHIFT 4 |
| |
| /* IRQ0 :: BSC_IRQEN :: iicd [03:03] */ |
| #define BCHP_IRQ0_BSC_IRQEN_iicd_MASK 0x00000008 |
| #define BCHP_IRQ0_BSC_IRQEN_iicd_SHIFT 3 |
| |
| /* IRQ0 :: BSC_IRQEN :: iicc [02:02] */ |
| #define BCHP_IRQ0_BSC_IRQEN_iicc_MASK 0x00000004 |
| #define BCHP_IRQ0_BSC_IRQEN_iicc_SHIFT 2 |
| |
| /* IRQ0 :: BSC_IRQEN :: iicb [01:01] */ |
| #define BCHP_IRQ0_BSC_IRQEN_iicb_MASK 0x00000002 |
| #define BCHP_IRQ0_BSC_IRQEN_iicb_SHIFT 1 |
| |
| /* IRQ0 :: BSC_IRQEN :: iica [00:00] */ |
| #define BCHP_IRQ0_BSC_IRQEN_iica_MASK 0x00000001 |
| #define BCHP_IRQ0_BSC_IRQEN_iica_SHIFT 0 |
| |
| /*************************************************************************** |
| *BSC_IRQSTAT - BSC Master Interrupt Status |
| ***************************************************************************/ |
| /* IRQ0 :: BSC_IRQSTAT :: reserved0 [31:04] */ |
| #define BCHP_IRQ0_BSC_IRQSTAT_reserved0_MASK 0xfffffff0 |
| #define BCHP_IRQ0_BSC_IRQSTAT_reserved0_SHIFT 4 |
| |
| /* IRQ0 :: BSC_IRQSTAT :: iicd [03:03] */ |
| #define BCHP_IRQ0_BSC_IRQSTAT_iicd_MASK 0x00000008 |
| #define BCHP_IRQ0_BSC_IRQSTAT_iicd_SHIFT 3 |
| |
| /* IRQ0 :: BSC_IRQSTAT :: iicc [02:02] */ |
| #define BCHP_IRQ0_BSC_IRQSTAT_iicc_MASK 0x00000004 |
| #define BCHP_IRQ0_BSC_IRQSTAT_iicc_SHIFT 2 |
| |
| /* IRQ0 :: BSC_IRQSTAT :: iicb [01:01] */ |
| #define BCHP_IRQ0_BSC_IRQSTAT_iicb_MASK 0x00000002 |
| #define BCHP_IRQ0_BSC_IRQSTAT_iicb_SHIFT 1 |
| |
| /* IRQ0 :: BSC_IRQSTAT :: iica [00:00] */ |
| #define BCHP_IRQ0_BSC_IRQSTAT_iica_MASK 0x00000001 |
| #define BCHP_IRQ0_BSC_IRQSTAT_iica_SHIFT 0 |
| |
| /*************************************************************************** |
| *UART_IRQEN - UART Channel 0 Interrupt Enable |
| ***************************************************************************/ |
| /* IRQ0 :: UART_IRQEN :: reserved0 [31:03] */ |
| #define BCHP_IRQ0_UART_IRQEN_reserved0_MASK 0xfffffff8 |
| #define BCHP_IRQ0_UART_IRQEN_reserved0_SHIFT 3 |
| |
| /* IRQ0 :: UART_IRQEN :: uartc [02:02] */ |
| #define BCHP_IRQ0_UART_IRQEN_uartc_MASK 0x00000004 |
| #define BCHP_IRQ0_UART_IRQEN_uartc_SHIFT 2 |
| |
| /* IRQ0 :: UART_IRQEN :: uartb [01:01] */ |
| #define BCHP_IRQ0_UART_IRQEN_uartb_MASK 0x00000002 |
| #define BCHP_IRQ0_UART_IRQEN_uartb_SHIFT 1 |
| |
| /* IRQ0 :: UART_IRQEN :: uarta [00:00] */ |
| #define BCHP_IRQ0_UART_IRQEN_uarta_MASK 0x00000001 |
| #define BCHP_IRQ0_UART_IRQEN_uarta_SHIFT 0 |
| |
| /*************************************************************************** |
| *UART_IRQSTAT - UART Channel 0 Interrupt Status |
| ***************************************************************************/ |
| /* IRQ0 :: UART_IRQSTAT :: reserved0 [31:03] */ |
| #define BCHP_IRQ0_UART_IRQSTAT_reserved0_MASK 0xfffffff8 |
| #define BCHP_IRQ0_UART_IRQSTAT_reserved0_SHIFT 3 |
| |
| /* IRQ0 :: UART_IRQSTAT :: uartc [02:02] */ |
| #define BCHP_IRQ0_UART_IRQSTAT_uartc_MASK 0x00000004 |
| #define BCHP_IRQ0_UART_IRQSTAT_uartc_SHIFT 2 |
| |
| /* IRQ0 :: UART_IRQSTAT :: uartb [01:01] */ |
| #define BCHP_IRQ0_UART_IRQSTAT_uartb_MASK 0x00000002 |
| #define BCHP_IRQ0_UART_IRQSTAT_uartb_SHIFT 1 |
| |
| /* IRQ0 :: UART_IRQSTAT :: uarta [00:00] */ |
| #define BCHP_IRQ0_UART_IRQSTAT_uarta_MASK 0x00000001 |
| #define BCHP_IRQ0_UART_IRQSTAT_uarta_SHIFT 0 |
| |
| /*************************************************************************** |
| *GPIO_IRQEN - GPIO Interrupt Enable |
| ***************************************************************************/ |
| /* IRQ0 :: GPIO_IRQEN :: reserved0 [31:01] */ |
| #define BCHP_IRQ0_GPIO_IRQEN_reserved0_MASK 0xfffffffe |
| #define BCHP_IRQ0_GPIO_IRQEN_reserved0_SHIFT 1 |
| |
| /* IRQ0 :: GPIO_IRQEN :: gio [00:00] */ |
| #define BCHP_IRQ0_GPIO_IRQEN_gio_MASK 0x00000001 |
| #define BCHP_IRQ0_GPIO_IRQEN_gio_SHIFT 0 |
| |
| /*************************************************************************** |
| *GPIO_IRQSTAT - GPIO Interrupt Status |
| ***************************************************************************/ |
| /* IRQ0 :: GPIO_IRQSTAT :: reserved0 [31:01] */ |
| #define BCHP_IRQ0_GPIO_IRQSTAT_reserved0_MASK 0xfffffffe |
| #define BCHP_IRQ0_GPIO_IRQSTAT_reserved0_SHIFT 1 |
| |
| /* IRQ0 :: GPIO_IRQSTAT :: gio [00:00] */ |
| #define BCHP_IRQ0_GPIO_IRQSTAT_gio_MASK 0x00000001 |
| #define BCHP_IRQ0_GPIO_IRQSTAT_gio_SHIFT 0 |
| |
| /*************************************************************************** |
| *ANT_IRQEN - Antenna Interface Interrupt Enable |
| ***************************************************************************/ |
| /* IRQ0 :: ANT_IRQEN :: reserved0 [31:01] */ |
| #define BCHP_IRQ0_ANT_IRQEN_reserved0_MASK 0xfffffffe |
| #define BCHP_IRQ0_ANT_IRQEN_reserved0_SHIFT 1 |
| |
| /* IRQ0 :: ANT_IRQEN :: ant [00:00] */ |
| #define BCHP_IRQ0_ANT_IRQEN_ant_MASK 0x00000001 |
| #define BCHP_IRQ0_ANT_IRQEN_ant_SHIFT 0 |
| |
| /*************************************************************************** |
| *ANT_IRQSTAT - Antenna Interface Interrupt Status |
| ***************************************************************************/ |
| /* IRQ0 :: ANT_IRQSTAT :: reserved0 [31:01] */ |
| #define BCHP_IRQ0_ANT_IRQSTAT_reserved0_MASK 0xfffffffe |
| #define BCHP_IRQ0_ANT_IRQSTAT_reserved0_SHIFT 1 |
| |
| /* IRQ0 :: ANT_IRQSTAT :: ant [00:00] */ |
| #define BCHP_IRQ0_ANT_IRQSTAT_ant_MASK 0x00000001 |
| #define BCHP_IRQ0_ANT_IRQSTAT_ant_SHIFT 0 |
| |
| #endif /* #ifndef BCHP_IRQ0_H__ */ |
| |
| /* End of File */ |
