| /*************************************************************************** |
| * Copyright (c) 1999-2010, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Wed Aug 4 16:42:41 2010 |
| * MD5 Checksum 27c5a1259680e8176595e9e88d9958c6 |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: /magnum/basemodules/chp/7408/rdb/b0/bchp_memc_ddr23_shim_addr_cntl.h $ |
| * |
| * Hydra_Software_Devel/1 8/4/10 7:44p pntruong |
| * SW7408-118: Initial version. |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_H__ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_H__ |
| |
| /*************************************************************************** |
| *MEMC_DDR23_SHIM_ADDR_CNTL - DDR23 SHIM Control Registers |
| ***************************************************************************/ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CONFIG 0x003b8000 /* DDR23_SHIM Config register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR23_SHIM_REV_ID 0x003b8004 /* DDR23_SHIM Revision ID Register. */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RESET 0x003b8008 /* DDR soft reset register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_ODT_CONFIG 0x003b8038 /* ODT Configuration register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PLL_LOCK_STATUS 0x003b8040 /* DDR PLL lock status register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHY_USE_DYN_VDL 0x003b8044 /* DDR PHY USE DYN VDL Control register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_IDLE_POWER_SAVING 0x003b8048 /* DDR PHY Idle power saving Control register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_EXT_PLL_CNTL 0x003b804c /* DDR PHY PLL External Control register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_ANALOG_BYPASS_CNTRL 0x003b806c /* Analog macro register bypass control */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PLL_EXT_CLKSEL 0x003b8070 /* DDR PLL external clock select register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_TEST_MODE_CNTRL_REG 0x003b8074 /* DDR23_SHIM testport control register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DISABLE_CHIP_BYPASS_PLL 0x003b807c /* DDR bypass pll mode disable register. */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_VECTOR_MODE_CLK_SEL 0x003b8088 /* DDR VECTOR PLL bypass mode clock select */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PAD_CNTRL 0x003b808c /* DDR Pad control register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CLK_GATE 0x003b8098 /* CLK_667_ENABLE Register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR23_SHIM_STATUS 0x003b809c /* DDR23_SHIM Status Register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DRAM_FIFO_LEVEL 0x003b80a0 /* DRAM FIFO LEVEL register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CMD_DATA_FIFO 0x003b8028 /* Command and Data FIFO Status Register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RD_DATAPATH 0x003b802c /* Read Datapath Status Register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_FLAG_BUS 0x003b8030 /* TP_OUT bus value Register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC 0x003b8034 /* Miscellaneous Register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_SPARE0_RW 0x003b80a4 /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_SPARE1_RW 0x003b80a8 /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_SPARE0_RO 0x003b80ac /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_SPARE1_RO 0x003b80b0 /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CNTRL 0x003b8058 /* DDR Phy-Bist Control and Status */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_SEED 0x003b805c /* DDR Phy-Bist PRPG Seed Value */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CTL_STATUS 0x003b8060 /* DDR Phy-Bist Address & Control Status */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_DQ_STATUS 0x003b8064 /* DDR Phy-Bist DQ Status */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_MISC_STATUS 0x003b8068 /* DDR Phy-Bist Miscellaneous Status */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR3_RESET_CNTRL 0x003b80b4 /* FORCE_DDR3_RESET Deassert Register */ |
| |
| /*************************************************************************** |
| *CONFIG - DDR23_SHIM Config register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: CONFIG :: reserved0 [31:26] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CONFIG_reserved0_MASK 0xfc000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CONFIG_reserved0_SHIFT 26 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: CONFIG :: ODT_LATENCY [25:21] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CONFIG_ODT_LATENCY_MASK 0x03e00000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CONFIG_ODT_LATENCY_SHIFT 21 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: CONFIG :: LAST_READ_LATENCY [20:15] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CONFIG_LAST_READ_LATENCY_MASK 0x001f8000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CONFIG_LAST_READ_LATENCY_SHIFT 15 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: CONFIG :: READ_LATENCY [14:08] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CONFIG_READ_LATENCY_MASK 0x00007f00 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CONFIG_READ_LATENCY_SHIFT 8 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: CONFIG :: WRITE_LATENCY [07:03] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CONFIG_WRITE_LATENCY_MASK 0x000000f8 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CONFIG_WRITE_LATENCY_SHIFT 3 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: CONFIG :: DRAM_WIDTH [02:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CONFIG_DRAM_WIDTH_MASK 0x00000006 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CONFIG_DRAM_WIDTH_SHIFT 1 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: CONFIG :: DDR_MODE [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CONFIG_DDR_MODE_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CONFIG_DDR_MODE_SHIFT 0 |
| |
| /*************************************************************************** |
| *DDR23_SHIM_REV_ID - DDR23_SHIM Revision ID Register. |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DDR23_SHIM_REV_ID :: reserved0 [31:16] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR23_SHIM_REV_ID_reserved0_MASK 0xffff0000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR23_SHIM_REV_ID_reserved0_SHIFT 16 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DDR23_SHIM_REV_ID :: MAJOR_ID [15:08] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR23_SHIM_REV_ID_MAJOR_ID_MASK 0x0000ff00 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR23_SHIM_REV_ID_MAJOR_ID_SHIFT 8 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DDR23_SHIM_REV_ID :: MINOR_ID [07:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR23_SHIM_REV_ID_MINOR_ID_MASK 0x000000ff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR23_SHIM_REV_ID_MINOR_ID_SHIFT 0 |
| |
| /*************************************************************************** |
| *RESET - DDR soft reset register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: RESET :: reserved0 [31:03] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RESET_reserved0_MASK 0xfffffff8 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RESET_reserved0_SHIFT 3 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: RESET :: DATAPATH_216_RESET [02:02] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RESET_DATAPATH_216_RESET_MASK 0x00000004 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RESET_DATAPATH_216_RESET_SHIFT 2 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: RESET :: DATAPATH_DDR_RESET [01:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RESET_DATAPATH_DDR_RESET_MASK 0x00000002 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RESET_DATAPATH_DDR_RESET_SHIFT 1 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: RESET :: reserved1 [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RESET_reserved1_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RESET_reserved1_SHIFT 0 |
| |
| /*************************************************************************** |
| *ODT_CONFIG - ODT Configuration register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: ODT_CONFIG :: reserved0 [31:14] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_ODT_CONFIG_reserved0_MASK 0xffffc000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_ODT_CONFIG_reserved0_SHIFT 14 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: ODT_CONFIG :: DDR2_1066MHz [13:13] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_ODT_CONFIG_DDR2_1066MHz_MASK 0x00002000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_ODT_CONFIG_DDR2_1066MHz_SHIFT 13 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: ODT_CONFIG :: STRETCH [12:11] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_ODT_CONFIG_STRETCH_MASK 0x00001800 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_ODT_CONFIG_STRETCH_SHIFT 11 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: ODT_CONFIG :: EARLY [10:06] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_ODT_CONFIG_EARLY_MASK 0x000007c0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_ODT_CONFIG_EARLY_SHIFT 6 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: ODT_CONFIG :: DELAY [05:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_ODT_CONFIG_DELAY_MASK 0x0000003f |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_ODT_CONFIG_DELAY_SHIFT 0 |
| |
| /*************************************************************************** |
| *DDR_PLL_LOCK_STATUS - DDR PLL lock status register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DDR_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DDR_PLL_LOCK_STATUS :: LOCK_STATUS [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PLL_LOCK_STATUS_LOCK_STATUS_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PLL_LOCK_STATUS_LOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PHY_USE_DYN_VDL - DDR PHY USE DYN VDL Control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHY_USE_DYN_VDL :: reserved0 [31:06] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHY_USE_DYN_VDL_reserved0_MASK 0xffffffc0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHY_USE_DYN_VDL_reserved0_SHIFT 6 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHY_USE_DYN_VDL :: PhyAddrCntl [05:04] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHY_USE_DYN_VDL_PhyAddrCntl_MASK 0x00000030 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHY_USE_DYN_VDL_PhyAddrCntl_SHIFT 4 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHY_USE_DYN_VDL :: ByteLane3 [03:03] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHY_USE_DYN_VDL_ByteLane3_MASK 0x00000008 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHY_USE_DYN_VDL_ByteLane3_SHIFT 3 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHY_USE_DYN_VDL :: ByteLane2 [02:02] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHY_USE_DYN_VDL_ByteLane2_MASK 0x00000004 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHY_USE_DYN_VDL_ByteLane2_SHIFT 2 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHY_USE_DYN_VDL :: ByteLane1 [01:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHY_USE_DYN_VDL_ByteLane1_MASK 0x00000002 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHY_USE_DYN_VDL_ByteLane1_SHIFT 1 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHY_USE_DYN_VDL :: ByteLane0 [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHY_USE_DYN_VDL_ByteLane0_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHY_USE_DYN_VDL_ByteLane0_SHIFT 0 |
| |
| /*************************************************************************** |
| *IDLE_POWER_SAVING - DDR PHY Idle power saving Control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: IDLE_POWER_SAVING :: reserved0 [31:06] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_IDLE_POWER_SAVING_reserved0_MASK 0xffffffc0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_IDLE_POWER_SAVING_reserved0_SHIFT 6 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: IDLE_POWER_SAVING :: PhyAddrCntl [05:04] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_IDLE_POWER_SAVING_PhyAddrCntl_MASK 0x00000030 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_IDLE_POWER_SAVING_PhyAddrCntl_SHIFT 4 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: IDLE_POWER_SAVING :: ByteLane3 [03:03] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_IDLE_POWER_SAVING_ByteLane3_MASK 0x00000008 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_IDLE_POWER_SAVING_ByteLane3_SHIFT 3 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: IDLE_POWER_SAVING :: ByteLane2 [02:02] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_IDLE_POWER_SAVING_ByteLane2_MASK 0x00000004 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_IDLE_POWER_SAVING_ByteLane2_SHIFT 2 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: IDLE_POWER_SAVING :: ByteLane1 [01:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_IDLE_POWER_SAVING_ByteLane1_MASK 0x00000002 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_IDLE_POWER_SAVING_ByteLane1_SHIFT 1 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: IDLE_POWER_SAVING :: ByteLane0 [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_IDLE_POWER_SAVING_ByteLane0_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_IDLE_POWER_SAVING_ByteLane0_SHIFT 0 |
| |
| /*************************************************************************** |
| *EXT_PLL_CNTL - DDR PHY PLL External Control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: EXT_PLL_CNTL :: reserved0 [31:25] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_EXT_PLL_CNTL_reserved0_MASK 0xfe000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_EXT_PLL_CNTL_reserved0_SHIFT 25 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: EXT_PLL_CNTL :: p2div [24:21] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_EXT_PLL_CNTL_p2div_MASK 0x01e00000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_EXT_PLL_CNTL_p2div_SHIFT 21 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: EXT_PLL_CNTL :: p1div [20:17] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_EXT_PLL_CNTL_p1div_MASK 0x001e0000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_EXT_PLL_CNTL_p1div_SHIFT 17 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: EXT_PLL_CNTL :: m1div [16:09] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_EXT_PLL_CNTL_m1div_MASK 0x0001fe00 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_EXT_PLL_CNTL_m1div_SHIFT 9 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: EXT_PLL_CNTL :: ndiv_int [08:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_EXT_PLL_CNTL_ndiv_int_MASK 0x000001ff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_EXT_PLL_CNTL_ndiv_int_SHIFT 0 |
| |
| /*************************************************************************** |
| *ANALOG_BYPASS_CNTRL - Analog macro register bypass control |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: ANALOG_BYPASS_CNTRL :: reserved0 [31:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_ANALOG_BYPASS_CNTRL_reserved0_MASK 0xfffffffe |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_ANALOG_BYPASS_CNTRL_reserved0_SHIFT 1 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: ANALOG_BYPASS_CNTRL :: BYPASS_PLL [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_ANALOG_BYPASS_CNTRL_BYPASS_PLL_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_ANALOG_BYPASS_CNTRL_BYPASS_PLL_SHIFT 0 |
| |
| /*************************************************************************** |
| *DDR_PLL_EXT_CLKSEL - DDR PLL external clock select register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DDR_PLL_EXT_CLKSEL :: reserved0 [31:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PLL_EXT_CLKSEL_reserved0_MASK 0xfffffffe |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PLL_EXT_CLKSEL_reserved0_SHIFT 1 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DDR_PLL_EXT_CLKSEL :: EXT_CLK_SEL [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_MODE_CNTRL_REG - DDR23_SHIM testport control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: TEST_MODE_CNTRL_REG :: reserved_for_eco0 [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_TEST_MODE_CNTRL_REG_reserved_for_eco0_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_TEST_MODE_CNTRL_REG_reserved_for_eco0_SHIFT 0 |
| |
| /*************************************************************************** |
| *DISABLE_CHIP_BYPASS_PLL - DDR bypass pll mode disable register. |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DISABLE_CHIP_BYPASS_PLL :: reserved0 [31:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DISABLE_CHIP_BYPASS_PLL_reserved0_MASK 0xfffffffe |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DISABLE_CHIP_BYPASS_PLL_reserved0_SHIFT 1 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DISABLE_CHIP_BYPASS_PLL :: DISABLE_BYPASS_PLL [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_SHIFT 0 |
| |
| /*************************************************************************** |
| *VECTOR_MODE_CLK_SEL - DDR VECTOR PLL bypass mode clock select |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: VECTOR_MODE_CLK_SEL :: reserved0 [31:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_VECTOR_MODE_CLK_SEL_reserved0_MASK 0xfffffffe |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_VECTOR_MODE_CLK_SEL_reserved0_SHIFT 1 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: VECTOR_MODE_CLK_SEL :: SEL [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_VECTOR_MODE_CLK_SEL_SEL_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_VECTOR_MODE_CLK_SEL_SEL_SHIFT 0 |
| |
| /*************************************************************************** |
| *DDR_PAD_CNTRL - DDR Pad control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DDR_PAD_CNTRL :: reserved0 [31:07] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PAD_CNTRL_reserved0_MASK 0xffffff80 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PAD_CNTRL_reserved0_SHIFT 7 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DDR_PAD_CNTRL :: IDDQ_MODE_ON_SELFREF [06:06] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK 0x00000040 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_SHIFT 6 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DDR_PAD_CNTRL :: DEVCLK_OFF_ON_SELFREF [05:05] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PAD_CNTRL_DEVCLK_OFF_ON_SELFREF_MASK 0x00000020 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PAD_CNTRL_DEVCLK_OFF_ON_SELFREF_SHIFT 5 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DDR_PAD_CNTRL :: HIZ_ON_SELFREF [04:04] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PAD_CNTRL_HIZ_ON_SELFREF_MASK 0x00000010 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PAD_CNTRL_HIZ_ON_SELFREF_SHIFT 4 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DDR_PAD_CNTRL :: CNTRL [03:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PAD_CNTRL_CNTRL_MASK 0x0000000f |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PAD_CNTRL_CNTRL_SHIFT 0 |
| |
| /*************************************************************************** |
| *CLK_GATE - CLK_667_ENABLE Register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: CLK_GATE :: UNUSED [31:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CLK_GATE_UNUSED_MASK 0xfffffffe |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CLK_GATE_UNUSED_SHIFT 1 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: CLK_GATE :: CLK_667_ENABLE [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CLK_GATE_CLK_667_ENABLE_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CLK_GATE_CLK_667_ENABLE_SHIFT 0 |
| |
| /*************************************************************************** |
| *DDR23_SHIM_STATUS - DDR23_SHIM Status Register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DDR23_SHIM_STATUS :: reserved0 [31:04] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR23_SHIM_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR23_SHIM_STATUS_reserved0_SHIFT 4 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DDR23_SHIM_STATUS :: BL0_AND_BL1_RDY_SLIP [03:03] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR23_SHIM_STATUS_BL0_AND_BL1_RDY_SLIP_MASK 0x00000008 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR23_SHIM_STATUS_BL0_AND_BL1_RDY_SLIP_SHIFT 3 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DDR23_SHIM_STATUS :: BL0_RDY_SLIP [02:02] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR23_SHIM_STATUS_BL0_RDY_SLIP_MASK 0x00000004 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR23_SHIM_STATUS_BL0_RDY_SLIP_SHIFT 2 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DDR23_SHIM_STATUS :: BL1_RDY_SLIP [01:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR23_SHIM_STATUS_BL1_RDY_SLIP_MASK 0x00000002 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR23_SHIM_STATUS_BL1_RDY_SLIP_SHIFT 1 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DDR23_SHIM_STATUS :: READY [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR23_SHIM_STATUS_READY_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR23_SHIM_STATUS_READY_SHIFT 0 |
| |
| /*************************************************************************** |
| *DRAM_FIFO_LEVEL - DRAM FIFO LEVEL register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DRAM_FIFO_LEVEL :: reserved0 [31:07] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DRAM_FIFO_LEVEL_reserved0_MASK 0xffffff80 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DRAM_FIFO_LEVEL_reserved0_SHIFT 7 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DRAM_FIFO_LEVEL :: VALUE [06:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DRAM_FIFO_LEVEL_VALUE_MASK 0x0000007e |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DRAM_FIFO_LEVEL_VALUE_SHIFT 1 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DRAM_FIFO_LEVEL :: ENABLE [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DRAM_FIFO_LEVEL_ENABLE_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DRAM_FIFO_LEVEL_ENABLE_SHIFT 0 |
| |
| /*************************************************************************** |
| *CMD_DATA_FIFO - Command and Data FIFO Status Register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: CMD_DATA_FIFO :: reserved0 [31:27] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CMD_DATA_FIFO_reserved0_MASK 0xf8000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CMD_DATA_FIFO_reserved0_SHIFT 27 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: CMD_DATA_FIFO :: CMD_FULL [26:26] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CMD_DATA_FIFO_CMD_FULL_MASK 0x04000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CMD_DATA_FIFO_CMD_FULL_SHIFT 26 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: CMD_DATA_FIFO :: FIFO_FULL [25:25] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CMD_DATA_FIFO_FIFO_FULL_MASK 0x02000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CMD_DATA_FIFO_FIFO_FULL_SHIFT 25 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: CMD_DATA_FIFO :: FIFO_EMPTY [24:24] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CMD_DATA_FIFO_FIFO_EMPTY_MASK 0x01000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CMD_DATA_FIFO_FIFO_EMPTY_SHIFT 24 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: CMD_DATA_FIFO :: CMD_WR_PNTR [23:16] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CMD_DATA_FIFO_CMD_WR_PNTR_MASK 0x00ff0000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CMD_DATA_FIFO_CMD_WR_PNTR_SHIFT 16 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: CMD_DATA_FIFO :: CMD_RD_PNTR [15:08] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CMD_DATA_FIFO_CMD_RD_PNTR_MASK 0x0000ff00 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CMD_DATA_FIFO_CMD_RD_PNTR_SHIFT 8 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: CMD_DATA_FIFO :: WR_PNTR [07:04] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CMD_DATA_FIFO_WR_PNTR_MASK 0x000000f0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CMD_DATA_FIFO_WR_PNTR_SHIFT 4 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: CMD_DATA_FIFO :: RD_PNTR [03:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CMD_DATA_FIFO_RD_PNTR_MASK 0x0000000f |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_CMD_DATA_FIFO_RD_PNTR_SHIFT 0 |
| |
| /*************************************************************************** |
| *RD_DATAPATH - Read Datapath Status Register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: RD_DATAPATH :: reserved0 [31:28] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RD_DATAPATH_reserved0_MASK 0xf0000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RD_DATAPATH_reserved0_SHIFT 28 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: RD_DATAPATH :: F_RDY_3 [27:27] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RD_DATAPATH_F_RDY_3_MASK 0x08000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RD_DATAPATH_F_RDY_3_SHIFT 27 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: RD_DATAPATH :: F_RDY_2 [26:26] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RD_DATAPATH_F_RDY_2_MASK 0x04000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RD_DATAPATH_F_RDY_2_SHIFT 26 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: RD_DATAPATH :: F_RDY_1 [25:25] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RD_DATAPATH_F_RDY_1_MASK 0x02000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RD_DATAPATH_F_RDY_1_SHIFT 25 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: RD_DATAPATH :: F_RDY_0 [24:24] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RD_DATAPATH_F_RDY_0_MASK 0x01000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RD_DATAPATH_F_RDY_0_SHIFT 24 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: RD_DATAPATH :: DWORD3_CNT [23:20] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RD_DATAPATH_DWORD3_CNT_MASK 0x00f00000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RD_DATAPATH_DWORD3_CNT_SHIFT 20 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: RD_DATAPATH :: DWORD2_CNT [19:16] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RD_DATAPATH_DWORD2_CNT_MASK 0x000f0000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RD_DATAPATH_DWORD2_CNT_SHIFT 16 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: RD_DATAPATH :: DWORD1_CNT [15:12] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RD_DATAPATH_DWORD1_CNT_MASK 0x0000f000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RD_DATAPATH_DWORD1_CNT_SHIFT 12 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: RD_DATAPATH :: DWORD0_CNT [11:08] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RD_DATAPATH_DWORD0_CNT_MASK 0x00000f00 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RD_DATAPATH_DWORD0_CNT_SHIFT 8 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: RD_DATAPATH :: WR_PNTR [07:04] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RD_DATAPATH_WR_PNTR_MASK 0x000000f0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RD_DATAPATH_WR_PNTR_SHIFT 4 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: RD_DATAPATH :: RD_PNTR [03:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RD_DATAPATH_RD_PNTR_MASK 0x0000000f |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_RD_DATAPATH_RD_PNTR_SHIFT 0 |
| |
| /*************************************************************************** |
| *FLAG_BUS - TP_OUT bus value Register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: FLAG_BUS :: FLAG_BUS [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_FLAG_BUS_FLAG_BUS_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_FLAG_BUS_FLAG_BUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *MISC - Miscellaneous Register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: MISC :: reserved_for_eco0 [31:12] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_reserved_for_eco0_MASK 0xfffff000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_reserved_for_eco0_SHIFT 12 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: MISC :: BL0_AND_BL1_RDY_SLIP_CLR [11:11] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_BL0_AND_BL1_RDY_SLIP_CLR_MASK 0x00000800 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_BL0_AND_BL1_RDY_SLIP_CLR_SHIFT 11 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: MISC :: BL0_RDY_SLIP_CLR [10:10] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_BL0_RDY_SLIP_CLR_MASK 0x00000400 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_BL0_RDY_SLIP_CLR_SHIFT 10 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: MISC :: BL1_RDY_SLIP_CLR [09:09] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_BL1_RDY_SLIP_CLR_MASK 0x00000200 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_BL1_RDY_SLIP_CLR_SHIFT 9 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: MISC :: FUNC1 [08:08] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_FUNC1_MASK 0x00000100 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_FUNC1_SHIFT 8 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: MISC :: FUNC0 [07:07] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_FUNC0_MASK 0x00000080 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_FUNC0_SHIFT 7 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: MISC :: C2IO_INIT_RDY_OVR [06:06] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_C2IO_INIT_RDY_OVR_MASK 0x00000040 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_C2IO_INIT_RDY_OVR_SHIFT 6 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: MISC :: RD_FIFO_HOLD_CLR [05:05] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_RD_FIFO_HOLD_CLR_MASK 0x00000020 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_RD_FIFO_HOLD_CLR_SHIFT 5 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: MISC :: CMD_FIFO_HOLD_CLR [04:04] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_CMD_FIFO_HOLD_CLR_MASK 0x00000010 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_CMD_FIFO_HOLD_CLR_SHIFT 4 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: MISC :: DWORD3_OVERRUN_CLR [03:03] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_DWORD3_OVERRUN_CLR_MASK 0x00000008 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_DWORD3_OVERRUN_CLR_SHIFT 3 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: MISC :: DWORD2_OVERRUN_CLR [02:02] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_DWORD2_OVERRUN_CLR_MASK 0x00000004 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_DWORD2_OVERRUN_CLR_SHIFT 2 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: MISC :: DWORD1_OVERRUN_CLR [01:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_DWORD1_OVERRUN_CLR_MASK 0x00000002 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_DWORD1_OVERRUN_CLR_SHIFT 1 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: MISC :: DWORD0_OVERRUN_CLR [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_DWORD0_OVERRUN_CLR_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_MISC_DWORD0_OVERRUN_CLR_SHIFT 0 |
| |
| /*************************************************************************** |
| *SPARE0_RW - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: SPARE0_RW :: reserved_for_eco0 [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_SPARE0_RW_reserved_for_eco0_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_SPARE0_RW_reserved_for_eco0_SHIFT 0 |
| |
| /*************************************************************************** |
| *SPARE1_RW - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: SPARE1_RW :: reserved_for_eco0 [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_SPARE1_RW_reserved_for_eco0_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_SPARE1_RW_reserved_for_eco0_SHIFT 0 |
| |
| /*************************************************************************** |
| *SPARE0_RO - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: SPARE0_RO :: reserved_for_eco0 [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_SPARE0_RO_reserved_for_eco0_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_SPARE0_RO_reserved_for_eco0_SHIFT 0 |
| |
| /*************************************************************************** |
| *SPARE1_RO - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: SPARE1_RO :: reserved_for_eco0 [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_SPARE1_RO_reserved_for_eco0_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_SPARE1_RO_reserved_for_eco0_SHIFT 0 |
| |
| /*************************************************************************** |
| *PHYBIST_CNTRL - DDR Phy-Bist Control and Status |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_CNTRL :: reserved0 [31:18] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CNTRL_reserved0_MASK 0xfffc0000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CNTRL_reserved0_SHIFT 18 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_CNTRL :: force_error_pos [17:16] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CNTRL_force_error_pos_MASK 0x00030000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CNTRL_force_error_pos_SHIFT 16 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_CNTRL :: reserved1 [15:14] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CNTRL_reserved1_MASK 0x0000c000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CNTRL_reserved1_SHIFT 14 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_CNTRL :: force_error_sel [13:08] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CNTRL_force_error_sel_MASK 0x00003f00 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CNTRL_force_error_sel_SHIFT 8 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_CNTRL :: reserved2 [07:05] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CNTRL_reserved2_MASK 0x000000e0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CNTRL_reserved2_SHIFT 5 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_CNTRL :: force_dat_error [04:04] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CNTRL_force_dat_error_MASK 0x00000010 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CNTRL_force_dat_error_SHIFT 4 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_CNTRL :: force_ctl_error [03:03] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CNTRL_force_ctl_error_MASK 0x00000008 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CNTRL_force_ctl_error_SHIFT 3 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_CNTRL :: force_cs_n [02:02] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CNTRL_force_cs_n_MASK 0x00000004 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CNTRL_force_cs_n_SHIFT 2 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_CNTRL :: force_odt [01:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CNTRL_force_odt_MASK 0x00000002 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CNTRL_force_odt_SHIFT 1 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_CNTRL :: enable [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CNTRL_enable_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CNTRL_enable_SHIFT 0 |
| |
| /*************************************************************************** |
| *PHYBIST_SEED - DDR Phy-Bist PRPG Seed Value |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_SEED :: seed [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_SEED_seed_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_SEED_seed_SHIFT 0 |
| |
| /*************************************************************************** |
| *PHYBIST_CTL_STATUS - DDR Phy-Bist Address & Control Status |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_CTL_STATUS :: reserved0 [31:27] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CTL_STATUS_reserved0_MASK 0xf8000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CTL_STATUS_reserved0_SHIFT 27 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_CTL_STATUS :: ddr_ras_n [26:26] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CTL_STATUS_ddr_ras_n_MASK 0x04000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CTL_STATUS_ddr_ras_n_SHIFT 26 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_CTL_STATUS :: ddr_cas_n [25:25] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CTL_STATUS_ddr_cas_n_MASK 0x02000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CTL_STATUS_ddr_cas_n_SHIFT 25 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_CTL_STATUS :: ddr_we_n [24:24] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CTL_STATUS_ddr_we_n_MASK 0x01000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CTL_STATUS_ddr_we_n_SHIFT 24 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_CTL_STATUS :: ddr_cke [23:23] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CTL_STATUS_ddr_cke_MASK 0x00800000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CTL_STATUS_ddr_cke_SHIFT 23 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_CTL_STATUS :: ddr_odt [22:22] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CTL_STATUS_ddr_odt_MASK 0x00400000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CTL_STATUS_ddr_odt_SHIFT 22 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_CTL_STATUS :: ddr_reset [21:21] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CTL_STATUS_ddr_reset_MASK 0x00200000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CTL_STATUS_ddr_reset_SHIFT 21 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_CTL_STATUS :: ddr_ad [20:07] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CTL_STATUS_ddr_ad_MASK 0x001fff80 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CTL_STATUS_ddr_ad_SHIFT 7 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_CTL_STATUS :: ddr_ba [06:04] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CTL_STATUS_ddr_ba_MASK 0x00000070 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CTL_STATUS_ddr_ba_SHIFT 4 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_CTL_STATUS :: ddr_aux [03:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CTL_STATUS_ddr_aux_MASK 0x0000000f |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_CTL_STATUS_ddr_aux_SHIFT 0 |
| |
| /*************************************************************************** |
| *PHYBIST_DQ_STATUS - DDR Phy-Bist DQ Status |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_DQ_STATUS :: ddr_dq3 [31:24] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_DQ_STATUS_ddr_dq3_MASK 0xff000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_DQ_STATUS_ddr_dq3_SHIFT 24 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_DQ_STATUS :: ddr_dq2 [23:16] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_DQ_STATUS_ddr_dq2_MASK 0x00ff0000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_DQ_STATUS_ddr_dq2_SHIFT 16 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_DQ_STATUS :: ddr_dq1 [15:08] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_DQ_STATUS_ddr_dq1_MASK 0x0000ff00 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_DQ_STATUS_ddr_dq1_SHIFT 8 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_DQ_STATUS :: ddr_dq0 [07:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_DQ_STATUS_ddr_dq0_MASK 0x000000ff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_DQ_STATUS_ddr_dq0_SHIFT 0 |
| |
| /*************************************************************************** |
| *PHYBIST_MISC_STATUS - DDR Phy-Bist Miscellaneous Status |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_MISC_STATUS :: dat_done [31:31] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_MISC_STATUS_dat_done_MASK 0x80000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_MISC_STATUS_dat_done_SHIFT 31 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_MISC_STATUS :: ctl_done [30:30] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_MISC_STATUS_ctl_done_MASK 0x40000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_MISC_STATUS_ctl_done_SHIFT 30 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_MISC_STATUS :: reserved0 [29:08] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_MISC_STATUS_reserved0_MASK 0x3fffff00 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_MISC_STATUS_reserved0_SHIFT 8 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_MISC_STATUS :: ddr_dm [07:04] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_MISC_STATUS_ddr_dm_MASK 0x000000f0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_MISC_STATUS_ddr_dm_SHIFT 4 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: PHYBIST_MISC_STATUS :: ddr_clk [03:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_MISC_STATUS_ddr_clk_MASK 0x0000000f |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_PHYBIST_MISC_STATUS_ddr_clk_SHIFT 0 |
| |
| /*************************************************************************** |
| *DDR3_RESET_CNTRL - FORCE_DDR3_RESET Deassert Register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DDR3_RESET_CNTRL :: UNUSED [31:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR3_RESET_CNTRL_UNUSED_MASK 0xfffffffe |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR3_RESET_CNTRL_UNUSED_SHIFT 1 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL :: DDR3_RESET_CNTRL :: FORCE_DDR3_RESET [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_SHIFT 0 |
| |
| #endif /* #ifndef BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_H__ */ |
| |
| /* End of File */ |
