| /*************************************************************************** |
| * Copyright (c) 1999-2010, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Thu Jul 8 04:25:18 2010 |
| * MD5 Checksum c117dafa96b291524c709d7f12b94905 |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: $ |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_CLK_H__ |
| #define BCHP_CLK_H__ |
| |
| /*************************************************************************** |
| *CLK - CLOCK_GEN Registers |
| ***************************************************************************/ |
| #define BCHP_CLK_REVISION 0x00462000 /* clock_gen Revision register */ |
| #define BCHP_CLK_BVN_TOP_CLK_PM_CTRL 0x00462004 /* Software power management control to turn off BVN_TOP system 216/108 MHz clocks */ |
| #define BCHP_CLK_MEMSYS_CLK_PM_CTRL 0x0046203c /* Software power management control to turn off MEMSYS system 216/108 MHz clocks */ |
| #define BCHP_CLK_USB_CLK_PM_CTRL 0x00462044 /* Software power management control to turn off USB system 216/108 and 54 MHz clocks */ |
| #define BCHP_CLK_DVP_HT_CLK_PM_CTRL 0x00462048 /* Software power management control to turn off DVP_HT clock */ |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL 0x0046204c /* Software power management control to turn off MOCA clocks */ |
| #define BCHP_CLK_VEC_CLK_PM_CTRL 0x00462050 /* Software power management control to turn off VEC clocks */ |
| #define BCHP_CLK_AIO_CLK_PM_CTRL 0x00462054 /* Software power management control to turn off AIO clocks */ |
| #define BCHP_CLK_GFX_3D_CLK_PM_CTRL 0x00462058 /* Software power management control to turn off GFX_3D system 216/108 MHz clocks */ |
| #define BCHP_CLK_GFX_2D_CLK_PM_CTRL 0x0046205c /* Software power management control to turn off GFX_2D system 216/108 MHz clocks */ |
| #define BCHP_CLK_AVD0_CLK_PM_CTRL 0x00462060 /* Software power management control to turn off AVD0 clocks */ |
| #define BCHP_CLK_XPT_CLK_PM_CTRL 0x00462064 /* Software power management control to turn off core_xpt clocks */ |
| #define BCHP_CLK_SUN_UART_CLK_PM_CTRL 0x00462068 /* Software power management control to turn off UART clocks in sundry */ |
| #define BCHP_CLK_SUN_27M_CLK_PM_CTRL 0x00462070 /* Software power management control to turn off 27 MHz clock in sundry */ |
| #define BCHP_CLK_UHFR_CLK_PM_CTRL 0x00462074 /* Software power management control to turn off UHFR clocks */ |
| #define BCHP_CLK_HIF_SPI_CLK_PM_CTRL 0x00462080 /* Software power management control to turn off clocks in hif */ |
| #define BCHP_CLK_PM_PLL_ALIVE_SEL 0x0046209c /* Software power management control to select certain PLL still alive even in standby mode with all PLLs off */ |
| #define BCHP_CLK_PLL_TIMER_SELECT 0x004620a0 /* Chip PLL programmable wait time after leaving the standby mode */ |
| #define BCHP_CLK_MISC 0x004620a4 /* clock_gen block output clock selection */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1 0x004620a8 /* Low 3rd Overtone Oscillator Control registers */ |
| #define BCHP_CLK_PLL_LOCK_STATUS 0x004620ac /* current lock status of main PLL */ |
| #define BCHP_CLK_SYS_PLL_1_CTLBUS_HI 0x004620c0 /* SYS 1 PLL control bus higher word */ |
| #define BCHP_CLK_SYS_PLL_1_CTLBUS_LO 0x004620c4 /* SYS 1 PLL control bus lower word */ |
| #define BCHP_CLK_SYS_PLL_1_CLOCK_ENA 0x004620c8 /* SYS PLL 1 clock outputs enable */ |
| #define BCHP_CLK_SYS_PLL_1_1 0x004620d0 /* SYS_PLL_1 channel 1: 257.1429 MHz AVD clock, PLL source post divider powerdown */ |
| #define BCHP_CLK_SYS_PLL_1_2 0x004620d4 /* SYS_PLL_1 channel 2: 50 MHz SPI_NOR PHY clock, PLL source post divider powerdown and cml buffer enable */ |
| #define BCHP_CLK_SYS_PLL_1_3 0x004620d8 /* SYS_PLL_1 channel 3: 225 MHz MOCA PHY clock, PLL source post divider powerdown and cml buffer enable */ |
| #define BCHP_CLK_SYS_PLL_1_4 0x004620dc /* SYS_PLL_1 channel 4: 225 MHz MOCA CPU, PLL source post divider powerdown and cml buffer enable */ |
| #define BCHP_CLK_SYS_PLL_1_5 0x004620e0 /* SYS_PLL_1 channel 5: 50 MHz USDS clock, PLL source post divider powerdown and cml buffer enable */ |
| #define BCHP_CLK_SYS_PLL_1_6 0x004620e4 /* SYS_PLL_1 channel 6: 100 MHz MOCA digital clock, PLL source post divider powerdown */ |
| #define BCHP_CLK_SYS_PLL_0_1 0x004620f0 /* SYS_PLL_0 channel 1: 216 MHz system clock, PLL source post divider powerdown */ |
| #define BCHP_CLK_SYS_PLL_0_3 0x004620f8 /* SYS_PLL_0 channel 2: 81/40.5/20.25 MHz clocks to core_xpt, PLL source post divider powerdown */ |
| #define BCHP_CLK_SYS_PLL_0_4 0x004620fc /* SYS_PLL_0 channel 3: 48 MHz USB PLL reference, PLL source post divider powerdown and cml buffer enable */ |
| #define BCHP_CLK_SYS_PLL_1_CTRL 0x00462108 /* SYS PLL 1 reset, output_delay */ |
| #define BCHP_CLK_SYS_PLL_0_CTRL 0x0046210c /* SYS PLL 0 reset, output_delay */ |
| #define BCHP_CLK_MIPS_PLL_CTRL 0x00462110 /* MIPS PLL reset, ch_disable, cpu frequency select, output_delay and powerdown */ |
| #define BCHP_CLK_AVD_DIV 0x00462114 /* SYS PLL 1 AVD clock divider settings */ |
| #define BCHP_CLK_SPI_50_DIV 0x00462118 /* SYS PLL 1 SPI 50 MHz clock divider settings */ |
| #define BCHP_CLK_MOCA_PHY_DIV 0x0046211c /* SYS PLL 1 MOCA_PHY clock divider settings */ |
| #define BCHP_CLK_MOCA_CPU_DIV 0x00462120 /* SYS PLL 1 MOCA_CPU clock divider settings */ |
| #define BCHP_CLK_USDS_DIV 0x00462124 /* SYS PLL 1 USDS clock divider settings */ |
| #define BCHP_CLK_D2CDIFF_AC_CTRL 0x0046212c /* AC_CTRL for D2CDIFF */ |
| #define BCHP_CLK_VIEW_CLOCK_SELECT 0x00462140 /* View clock counter clock/lock_bit selection */ |
| #define BCHP_CLK_RING_OSC_ENABLE 0x00462144 /* Enable Ring Oscillators */ |
| #define BCHP_CLK_REF_CLOCK_COUNTER 0x00462148 /* Reference Clock Counter */ |
| #define BCHP_CLK_VIEW_CLOCK_COUNTER 0x0046214c /* View Clock Counter */ |
| #define BCHP_CLK_RESET_COUNTER 0x00462150 /* Reset counters */ |
| #define BCHP_CLK_STOP_COUNTER 0x00462154 /* Stop counters */ |
| #define BCHP_CLK_IN_RANGE 0x00462158 /* View clock counter is in range */ |
| #define BCHP_CLK_SWREG_VALUE 0x0046215c /* Hold SWREG related control values */ |
| #define BCHP_CLK_OTP_SWREG_VALUE 0x00462160 /* Hold SWREG related control values from OTP */ |
| #define BCHP_CLK_UVREG_VALUE 0x00462164 /* Hold UVREG related control values */ |
| #define BCHP_CLK_OTP_UVREG_VALUE 0x00462168 /* Hold UVREG related control values from OTP */ |
| #define BCHP_CLK_RO_TEST_SUB_BLOCK_SEL 0x0046216c /* additional select/control values that can be used for OSC pads */ |
| #define BCHP_CLK_SCRATCH 0x0046223c /* clock_gen Scratch register */ |
| |
| /*************************************************************************** |
| *REVISION - clock_gen Revision register |
| ***************************************************************************/ |
| /* CLK :: REVISION :: reserved0 [31:16] */ |
| #define BCHP_CLK_REVISION_reserved0_MASK 0xffff0000 |
| #define BCHP_CLK_REVISION_reserved0_SHIFT 16 |
| |
| /* CLK :: REVISION :: MAJOR [15:08] */ |
| #define BCHP_CLK_REVISION_MAJOR_MASK 0x0000ff00 |
| #define BCHP_CLK_REVISION_MAJOR_SHIFT 8 |
| |
| /* CLK :: REVISION :: MINOR [07:00] */ |
| #define BCHP_CLK_REVISION_MINOR_MASK 0x000000ff |
| #define BCHP_CLK_REVISION_MINOR_SHIFT 0 |
| |
| /*************************************************************************** |
| *BVN_TOP_CLK_PM_CTRL - Software power management control to turn off BVN_TOP system 216/108 MHz clocks |
| ***************************************************************************/ |
| /* CLK :: BVN_TOP_CLK_PM_CTRL :: reserved0 [31:04] */ |
| #define BCHP_CLK_BVN_TOP_CLK_PM_CTRL_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLK_BVN_TOP_CLK_PM_CTRL_reserved0_SHIFT 4 |
| |
| /* CLK :: BVN_TOP_CLK_PM_CTRL :: DIS_2ND_108M_CLK [03:03] */ |
| #define BCHP_CLK_BVN_TOP_CLK_PM_CTRL_DIS_2ND_108M_CLK_MASK 0x00000008 |
| #define BCHP_CLK_BVN_TOP_CLK_PM_CTRL_DIS_2ND_108M_CLK_SHIFT 3 |
| |
| /* CLK :: BVN_TOP_CLK_PM_CTRL :: DIS_2ND_216M_CLK [02:02] */ |
| #define BCHP_CLK_BVN_TOP_CLK_PM_CTRL_DIS_2ND_216M_CLK_MASK 0x00000004 |
| #define BCHP_CLK_BVN_TOP_CLK_PM_CTRL_DIS_2ND_216M_CLK_SHIFT 2 |
| |
| /* CLK :: BVN_TOP_CLK_PM_CTRL :: DIS_108M_CLK [01:01] */ |
| #define BCHP_CLK_BVN_TOP_CLK_PM_CTRL_DIS_108M_CLK_MASK 0x00000002 |
| #define BCHP_CLK_BVN_TOP_CLK_PM_CTRL_DIS_108M_CLK_SHIFT 1 |
| |
| /* CLK :: BVN_TOP_CLK_PM_CTRL :: DIS_216M_CLK [00:00] */ |
| #define BCHP_CLK_BVN_TOP_CLK_PM_CTRL_DIS_216M_CLK_MASK 0x00000001 |
| #define BCHP_CLK_BVN_TOP_CLK_PM_CTRL_DIS_216M_CLK_SHIFT 0 |
| |
| /*************************************************************************** |
| *MEMSYS_CLK_PM_CTRL - Software power management control to turn off MEMSYS system 216/108 MHz clocks |
| ***************************************************************************/ |
| /* CLK :: MEMSYS_CLK_PM_CTRL :: reserved0 [31:02] */ |
| #define BCHP_CLK_MEMSYS_CLK_PM_CTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLK_MEMSYS_CLK_PM_CTRL_reserved0_SHIFT 2 |
| |
| /* CLK :: MEMSYS_CLK_PM_CTRL :: DIS_108M_CLK [01:01] */ |
| #define BCHP_CLK_MEMSYS_CLK_PM_CTRL_DIS_108M_CLK_MASK 0x00000002 |
| #define BCHP_CLK_MEMSYS_CLK_PM_CTRL_DIS_108M_CLK_SHIFT 1 |
| |
| /* CLK :: MEMSYS_CLK_PM_CTRL :: DIS_216M_CLK [00:00] */ |
| #define BCHP_CLK_MEMSYS_CLK_PM_CTRL_DIS_216M_CLK_MASK 0x00000001 |
| #define BCHP_CLK_MEMSYS_CLK_PM_CTRL_DIS_216M_CLK_SHIFT 0 |
| |
| /*************************************************************************** |
| *USB_CLK_PM_CTRL - Software power management control to turn off USB system 216/108 and 54 MHz clocks |
| ***************************************************************************/ |
| /* CLK :: USB_CLK_PM_CTRL :: reserved0 [31:03] */ |
| #define BCHP_CLK_USB_CLK_PM_CTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLK_USB_CLK_PM_CTRL_reserved0_SHIFT 3 |
| |
| /* CLK :: USB_CLK_PM_CTRL :: DIS_54M_CLK [02:02] */ |
| #define BCHP_CLK_USB_CLK_PM_CTRL_DIS_54M_CLK_MASK 0x00000004 |
| #define BCHP_CLK_USB_CLK_PM_CTRL_DIS_54M_CLK_SHIFT 2 |
| |
| /* CLK :: USB_CLK_PM_CTRL :: DIS_108M_CLK [01:01] */ |
| #define BCHP_CLK_USB_CLK_PM_CTRL_DIS_108M_CLK_MASK 0x00000002 |
| #define BCHP_CLK_USB_CLK_PM_CTRL_DIS_108M_CLK_SHIFT 1 |
| |
| /* CLK :: USB_CLK_PM_CTRL :: DIS_216M_CLK [00:00] */ |
| #define BCHP_CLK_USB_CLK_PM_CTRL_DIS_216M_CLK_MASK 0x00000001 |
| #define BCHP_CLK_USB_CLK_PM_CTRL_DIS_216M_CLK_SHIFT 0 |
| |
| /*************************************************************************** |
| *DVP_HT_CLK_PM_CTRL - Software power management control to turn off DVP_HT clock |
| ***************************************************************************/ |
| /* CLK :: DVP_HT_CLK_PM_CTRL :: reserved0 [31:07] */ |
| #define BCHP_CLK_DVP_HT_CLK_PM_CTRL_reserved0_MASK 0xffffff80 |
| #define BCHP_CLK_DVP_HT_CLK_PM_CTRL_reserved0_SHIFT 7 |
| |
| /* CLK :: DVP_HT_CLK_PM_CTRL :: DIS_2ND_108M_CLK [06:06] */ |
| #define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_2ND_108M_CLK_MASK 0x00000040 |
| #define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_2ND_108M_CLK_SHIFT 6 |
| |
| /* CLK :: DVP_HT_CLK_PM_CTRL :: DIS_VEC_216M_CLK [05:05] */ |
| #define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_VEC_216M_CLK_MASK 0x00000020 |
| #define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_VEC_216M_CLK_SHIFT 5 |
| |
| /* CLK :: DVP_HT_CLK_PM_CTRL :: DIS_HDMI_MAX_PROG_CLK [04:04] */ |
| #define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_HDMI_MAX_PROG_CLK_MASK 0x00000010 |
| #define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_HDMI_MAX_PROG_CLK_SHIFT 4 |
| |
| /* CLK :: DVP_HT_CLK_PM_CTRL :: DIS_HDMI_27M_CLK [03:03] */ |
| #define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_HDMI_27M_CLK_MASK 0x00000008 |
| #define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_HDMI_27M_CLK_SHIFT 3 |
| |
| /* CLK :: DVP_HT_CLK_PM_CTRL :: DIS_HDMI_PM_27M_CLK [02:02] */ |
| #define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_HDMI_PM_27M_CLK_MASK 0x00000004 |
| #define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_HDMI_PM_27M_CLK_SHIFT 2 |
| |
| /* CLK :: DVP_HT_CLK_PM_CTRL :: DIS_108M_CLK [01:01] */ |
| #define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_108M_CLK_MASK 0x00000002 |
| #define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_108M_CLK_SHIFT 1 |
| |
| /* CLK :: DVP_HT_CLK_PM_CTRL :: DIS_216M_CLK [00:00] */ |
| #define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_216M_CLK_MASK 0x00000001 |
| #define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_216M_CLK_SHIFT 0 |
| |
| /*************************************************************************** |
| *MOCA_CLK_PM_CTRL - Software power management control to turn off MOCA clocks |
| ***************************************************************************/ |
| /* CLK :: MOCA_CLK_PM_CTRL :: reserved0 [31:11] */ |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_reserved0_MASK 0xfffff800 |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_reserved0_SHIFT 11 |
| |
| /* CLK :: MOCA_CLK_PM_CTRL :: DIS_MOCA_54M_CLK [10:10] */ |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_54M_CLK_MASK 0x00000400 |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_54M_CLK_SHIFT 10 |
| |
| /* CLK :: MOCA_CLK_PM_CTRL :: DIS_GENET_RGMII_216M_CLK [09:09] */ |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_GENET_RGMII_216M_CLK_MASK 0x00000200 |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_GENET_RGMII_216M_CLK_SHIFT 9 |
| |
| /* CLK :: MOCA_CLK_PM_CTRL :: DIS_MOCA_ENET_UNIMAC_SYS_RX_27_108M_CLK [08:08] */ |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_ENET_UNIMAC_SYS_RX_27_108M_CLK_MASK 0x00000100 |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_ENET_UNIMAC_SYS_RX_27_108M_CLK_SHIFT 8 |
| |
| /* CLK :: MOCA_CLK_PM_CTRL :: DIS_MOCA_ENET_UNIMAC_SYS_TX_27_108M_CLK [07:07] */ |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_ENET_UNIMAC_SYS_TX_27_108M_CLK_MASK 0x00000080 |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_ENET_UNIMAC_SYS_TX_27_108M_CLK_SHIFT 7 |
| |
| /* CLK :: MOCA_CLK_PM_CTRL :: reserved1 [06:06] */ |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_reserved1_MASK 0x00000040 |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_reserved1_SHIFT 6 |
| |
| /* CLK :: MOCA_CLK_PM_CTRL :: DIS_MOCA_ENET_L2_INTR_27_108M_CLK [05:05] */ |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_ENET_L2_INTR_27_108M_CLK_MASK 0x00000020 |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_ENET_L2_INTR_27_108M_CLK_SHIFT 5 |
| |
| /* CLK :: MOCA_CLK_PM_CTRL :: DIS_MOCA_ENET_HFB_27_108M_CLK [04:04] */ |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_ENET_HFB_27_108M_CLK_MASK 0x00000010 |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_ENET_HFB_27_108M_CLK_SHIFT 4 |
| |
| /* CLK :: MOCA_CLK_PM_CTRL :: DIS_MOCA_ENET_GMII_TX_27_108M_CLK [03:03] */ |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_ENET_GMII_TX_27_108M_CLK_MASK 0x00000008 |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_ENET_GMII_TX_27_108M_CLK_SHIFT 3 |
| |
| /* CLK :: MOCA_CLK_PM_CTRL :: DIS_MOCA_PM_27M_CLK [02:02] */ |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_PM_27M_CLK_MASK 0x00000004 |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_PM_27M_CLK_SHIFT 2 |
| |
| /* CLK :: MOCA_CLK_PM_CTRL :: DIS_108M_CLK [01:01] */ |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_108M_CLK_MASK 0x00000002 |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_108M_CLK_SHIFT 1 |
| |
| /* CLK :: MOCA_CLK_PM_CTRL :: DIS_216M_CLK [00:00] */ |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_216M_CLK_MASK 0x00000001 |
| #define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_216M_CLK_SHIFT 0 |
| |
| /*************************************************************************** |
| *VEC_CLK_PM_CTRL - Software power management control to turn off VEC clocks |
| ***************************************************************************/ |
| /* CLK :: VEC_CLK_PM_CTRL :: reserved0 [31:03] */ |
| #define BCHP_CLK_VEC_CLK_PM_CTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLK_VEC_CLK_PM_CTRL_reserved0_SHIFT 3 |
| |
| /* CLK :: VEC_CLK_PM_CTRL :: DIS_VEC_108M_CLK [02:02] */ |
| #define BCHP_CLK_VEC_CLK_PM_CTRL_DIS_VEC_108M_CLK_MASK 0x00000004 |
| #define BCHP_CLK_VEC_CLK_PM_CTRL_DIS_VEC_108M_CLK_SHIFT 2 |
| |
| /* CLK :: VEC_CLK_PM_CTRL :: DIS_VEC_DAC_108M_CLK [01:01] */ |
| #define BCHP_CLK_VEC_CLK_PM_CTRL_DIS_VEC_DAC_108M_CLK_MASK 0x00000002 |
| #define BCHP_CLK_VEC_CLK_PM_CTRL_DIS_VEC_DAC_108M_CLK_SHIFT 1 |
| |
| /* CLK :: VEC_CLK_PM_CTRL :: DIS_VEC_216M_CLK [00:00] */ |
| #define BCHP_CLK_VEC_CLK_PM_CTRL_DIS_VEC_216M_CLK_MASK 0x00000001 |
| #define BCHP_CLK_VEC_CLK_PM_CTRL_DIS_VEC_216M_CLK_SHIFT 0 |
| |
| /*************************************************************************** |
| *AIO_CLK_PM_CTRL - Software power management control to turn off AIO clocks |
| ***************************************************************************/ |
| /* CLK :: AIO_CLK_PM_CTRL :: reserved0 [31:02] */ |
| #define BCHP_CLK_AIO_CLK_PM_CTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLK_AIO_CLK_PM_CTRL_reserved0_SHIFT 2 |
| |
| /* CLK :: AIO_CLK_PM_CTRL :: DIS_AIO_108M_CLK [01:01] */ |
| #define BCHP_CLK_AIO_CLK_PM_CTRL_DIS_AIO_108M_CLK_MASK 0x00000002 |
| #define BCHP_CLK_AIO_CLK_PM_CTRL_DIS_AIO_108M_CLK_SHIFT 1 |
| |
| /* CLK :: AIO_CLK_PM_CTRL :: DIS_AIO_216M_CLK [00:00] */ |
| #define BCHP_CLK_AIO_CLK_PM_CTRL_DIS_AIO_216M_CLK_MASK 0x00000001 |
| #define BCHP_CLK_AIO_CLK_PM_CTRL_DIS_AIO_216M_CLK_SHIFT 0 |
| |
| /*************************************************************************** |
| *GFX_3D_CLK_PM_CTRL - Software power management control to turn off GFX_3D system 216/108 MHz clocks |
| ***************************************************************************/ |
| /* CLK :: GFX_3D_CLK_PM_CTRL :: reserved0 [31:02] */ |
| #define BCHP_CLK_GFX_3D_CLK_PM_CTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLK_GFX_3D_CLK_PM_CTRL_reserved0_SHIFT 2 |
| |
| /* CLK :: GFX_3D_CLK_PM_CTRL :: DIS_108M_CLK [01:01] */ |
| #define BCHP_CLK_GFX_3D_CLK_PM_CTRL_DIS_108M_CLK_MASK 0x00000002 |
| #define BCHP_CLK_GFX_3D_CLK_PM_CTRL_DIS_108M_CLK_SHIFT 1 |
| |
| /* CLK :: GFX_3D_CLK_PM_CTRL :: DIS_216M_CLK [00:00] */ |
| #define BCHP_CLK_GFX_3D_CLK_PM_CTRL_DIS_216M_CLK_MASK 0x00000001 |
| #define BCHP_CLK_GFX_3D_CLK_PM_CTRL_DIS_216M_CLK_SHIFT 0 |
| |
| /*************************************************************************** |
| *GFX_2D_CLK_PM_CTRL - Software power management control to turn off GFX_2D system 216/108 MHz clocks |
| ***************************************************************************/ |
| /* CLK :: GFX_2D_CLK_PM_CTRL :: reserved0 [31:02] */ |
| #define BCHP_CLK_GFX_2D_CLK_PM_CTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLK_GFX_2D_CLK_PM_CTRL_reserved0_SHIFT 2 |
| |
| /* CLK :: GFX_2D_CLK_PM_CTRL :: DIS_108M_CLK [01:01] */ |
| #define BCHP_CLK_GFX_2D_CLK_PM_CTRL_DIS_108M_CLK_MASK 0x00000002 |
| #define BCHP_CLK_GFX_2D_CLK_PM_CTRL_DIS_108M_CLK_SHIFT 1 |
| |
| /* CLK :: GFX_2D_CLK_PM_CTRL :: DIS_216M_CLK [00:00] */ |
| #define BCHP_CLK_GFX_2D_CLK_PM_CTRL_DIS_216M_CLK_MASK 0x00000001 |
| #define BCHP_CLK_GFX_2D_CLK_PM_CTRL_DIS_216M_CLK_SHIFT 0 |
| |
| /*************************************************************************** |
| *AVD0_CLK_PM_CTRL - Software power management control to turn off AVD0 clocks |
| ***************************************************************************/ |
| /* CLK :: AVD0_CLK_PM_CTRL :: reserved0 [31:03] */ |
| #define BCHP_CLK_AVD0_CLK_PM_CTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLK_AVD0_CLK_PM_CTRL_reserved0_SHIFT 3 |
| |
| /* CLK :: AVD0_CLK_PM_CTRL :: DIS_AVD0_PROG_CLK [02:02] */ |
| #define BCHP_CLK_AVD0_CLK_PM_CTRL_DIS_AVD0_PROG_CLK_MASK 0x00000004 |
| #define BCHP_CLK_AVD0_CLK_PM_CTRL_DIS_AVD0_PROG_CLK_SHIFT 2 |
| |
| /* CLK :: AVD0_CLK_PM_CTRL :: DIS_108M_CLK [01:01] */ |
| #define BCHP_CLK_AVD0_CLK_PM_CTRL_DIS_108M_CLK_MASK 0x00000002 |
| #define BCHP_CLK_AVD0_CLK_PM_CTRL_DIS_108M_CLK_SHIFT 1 |
| |
| /* CLK :: AVD0_CLK_PM_CTRL :: DIS_216M_CLK [00:00] */ |
| #define BCHP_CLK_AVD0_CLK_PM_CTRL_DIS_216M_CLK_MASK 0x00000001 |
| #define BCHP_CLK_AVD0_CLK_PM_CTRL_DIS_216M_CLK_SHIFT 0 |
| |
| /*************************************************************************** |
| *XPT_CLK_PM_CTRL - Software power management control to turn off core_xpt clocks |
| ***************************************************************************/ |
| /* CLK :: XPT_CLK_PM_CTRL :: reserved0 [31:03] */ |
| #define BCHP_CLK_XPT_CLK_PM_CTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLK_XPT_CLK_PM_CTRL_reserved0_SHIFT 3 |
| |
| /* CLK :: XPT_CLK_PM_CTRL :: DIS_XPT_27M_CLK [02:02] */ |
| #define BCHP_CLK_XPT_CLK_PM_CTRL_DIS_XPT_27M_CLK_MASK 0x00000004 |
| #define BCHP_CLK_XPT_CLK_PM_CTRL_DIS_XPT_27M_CLK_SHIFT 2 |
| |
| /* CLK :: XPT_CLK_PM_CTRL :: DIS_108M_CLK [01:01] */ |
| #define BCHP_CLK_XPT_CLK_PM_CTRL_DIS_108M_CLK_MASK 0x00000002 |
| #define BCHP_CLK_XPT_CLK_PM_CTRL_DIS_108M_CLK_SHIFT 1 |
| |
| /* CLK :: XPT_CLK_PM_CTRL :: DIS_216M_CLK [00:00] */ |
| #define BCHP_CLK_XPT_CLK_PM_CTRL_DIS_216M_CLK_MASK 0x00000001 |
| #define BCHP_CLK_XPT_CLK_PM_CTRL_DIS_216M_CLK_SHIFT 0 |
| |
| /*************************************************************************** |
| *SUN_UART_CLK_PM_CTRL - Software power management control to turn off UART clocks in sundry |
| ***************************************************************************/ |
| /* CLK :: SUN_UART_CLK_PM_CTRL :: reserved0 [31:01] */ |
| #define BCHP_CLK_SUN_UART_CLK_PM_CTRL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLK_SUN_UART_CLK_PM_CTRL_reserved0_SHIFT 1 |
| |
| /* CLK :: SUN_UART_CLK_PM_CTRL :: DIS_SUN_UART_108M_CLK [00:00] */ |
| #define BCHP_CLK_SUN_UART_CLK_PM_CTRL_DIS_SUN_UART_108M_CLK_MASK 0x00000001 |
| #define BCHP_CLK_SUN_UART_CLK_PM_CTRL_DIS_SUN_UART_108M_CLK_SHIFT 0 |
| |
| /*************************************************************************** |
| *SUN_27M_CLK_PM_CTRL - Software power management control to turn off 27 MHz clock in sundry |
| ***************************************************************************/ |
| /* CLK :: SUN_27M_CLK_PM_CTRL :: reserved0 [31:01] */ |
| #define BCHP_CLK_SUN_27M_CLK_PM_CTRL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLK_SUN_27M_CLK_PM_CTRL_reserved0_SHIFT 1 |
| |
| /* CLK :: SUN_27M_CLK_PM_CTRL :: DIS_SUN_27M_CLK [00:00] */ |
| #define BCHP_CLK_SUN_27M_CLK_PM_CTRL_DIS_SUN_27M_CLK_MASK 0x00000001 |
| #define BCHP_CLK_SUN_27M_CLK_PM_CTRL_DIS_SUN_27M_CLK_SHIFT 0 |
| |
| /*************************************************************************** |
| *UHFR_CLK_PM_CTRL - Software power management control to turn off UHFR clocks |
| ***************************************************************************/ |
| /* CLK :: UHFR_CLK_PM_CTRL :: reserved0 [31:02] */ |
| #define BCHP_CLK_UHFR_CLK_PM_CTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLK_UHFR_CLK_PM_CTRL_reserved0_SHIFT 2 |
| |
| /* CLK :: UHFR_CLK_PM_CTRL :: DIS_ANA_UHFR_CLK [01:01] */ |
| #define BCHP_CLK_UHFR_CLK_PM_CTRL_DIS_ANA_UHFR_CLK_MASK 0x00000002 |
| #define BCHP_CLK_UHFR_CLK_PM_CTRL_DIS_ANA_UHFR_CLK_SHIFT 1 |
| |
| /* CLK :: UHFR_CLK_PM_CTRL :: DIS_DIGI_UHFR_CLK [00:00] */ |
| #define BCHP_CLK_UHFR_CLK_PM_CTRL_DIS_DIGI_UHFR_CLK_MASK 0x00000001 |
| #define BCHP_CLK_UHFR_CLK_PM_CTRL_DIS_DIGI_UHFR_CLK_SHIFT 0 |
| |
| /*************************************************************************** |
| *HIF_SPI_CLK_PM_CTRL - Software power management control to turn off clocks in hif |
| ***************************************************************************/ |
| /* CLK :: HIF_SPI_CLK_PM_CTRL :: reserved0 [31:04] */ |
| #define BCHP_CLK_HIF_SPI_CLK_PM_CTRL_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLK_HIF_SPI_CLK_PM_CTRL_reserved0_SHIFT 4 |
| |
| /* CLK :: HIF_SPI_CLK_PM_CTRL :: DIS_SPI_OUT_CLK [03:03] */ |
| #define BCHP_CLK_HIF_SPI_CLK_PM_CTRL_DIS_SPI_OUT_CLK_MASK 0x00000008 |
| #define BCHP_CLK_HIF_SPI_CLK_PM_CTRL_DIS_SPI_OUT_CLK_SHIFT 3 |
| |
| /* CLK :: HIF_SPI_CLK_PM_CTRL :: DIS_PROG_CLK [02:02] */ |
| #define BCHP_CLK_HIF_SPI_CLK_PM_CTRL_DIS_PROG_CLK_MASK 0x00000004 |
| #define BCHP_CLK_HIF_SPI_CLK_PM_CTRL_DIS_PROG_CLK_SHIFT 2 |
| |
| /* CLK :: HIF_SPI_CLK_PM_CTRL :: DIS_54M_CLK [01:01] */ |
| #define BCHP_CLK_HIF_SPI_CLK_PM_CTRL_DIS_54M_CLK_MASK 0x00000002 |
| #define BCHP_CLK_HIF_SPI_CLK_PM_CTRL_DIS_54M_CLK_SHIFT 1 |
| |
| /* CLK :: HIF_SPI_CLK_PM_CTRL :: DIS_27M_CLK [00:00] */ |
| #define BCHP_CLK_HIF_SPI_CLK_PM_CTRL_DIS_27M_CLK_MASK 0x00000001 |
| #define BCHP_CLK_HIF_SPI_CLK_PM_CTRL_DIS_27M_CLK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PM_PLL_ALIVE_SEL - Software power management control to select certain PLL still alive even in standby mode with all PLLs off |
| ***************************************************************************/ |
| /* CLK :: PM_PLL_ALIVE_SEL :: reserved0 [31:03] */ |
| #define BCHP_CLK_PM_PLL_ALIVE_SEL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLK_PM_PLL_ALIVE_SEL_reserved0_SHIFT 3 |
| |
| /* CLK :: PM_PLL_ALIVE_SEL :: DDR_PLL [02:02] */ |
| #define BCHP_CLK_PM_PLL_ALIVE_SEL_DDR_PLL_MASK 0x00000004 |
| #define BCHP_CLK_PM_PLL_ALIVE_SEL_DDR_PLL_SHIFT 2 |
| |
| /* CLK :: PM_PLL_ALIVE_SEL :: MIPS_PLL [01:01] */ |
| #define BCHP_CLK_PM_PLL_ALIVE_SEL_MIPS_PLL_MASK 0x00000002 |
| #define BCHP_CLK_PM_PLL_ALIVE_SEL_MIPS_PLL_SHIFT 1 |
| |
| /* CLK :: PM_PLL_ALIVE_SEL :: SYS_PLL_0 [00:00] */ |
| #define BCHP_CLK_PM_PLL_ALIVE_SEL_SYS_PLL_0_MASK 0x00000001 |
| #define BCHP_CLK_PM_PLL_ALIVE_SEL_SYS_PLL_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_TIMER_SELECT - Chip PLL programmable wait time after leaving the standby mode |
| ***************************************************************************/ |
| /* CLK :: PLL_TIMER_SELECT :: reserved0 [31:02] */ |
| #define BCHP_CLK_PLL_TIMER_SELECT_reserved0_MASK 0xfffffffc |
| #define BCHP_CLK_PLL_TIMER_SELECT_reserved0_SHIFT 2 |
| |
| /* CLK :: PLL_TIMER_SELECT :: TIMER [01:00] */ |
| #define BCHP_CLK_PLL_TIMER_SELECT_TIMER_MASK 0x00000003 |
| #define BCHP_CLK_PLL_TIMER_SELECT_TIMER_SHIFT 0 |
| |
| /*************************************************************************** |
| *MISC - clock_gen block output clock selection |
| ***************************************************************************/ |
| /* CLK :: MISC :: reserved0 [31:11] */ |
| #define BCHP_CLK_MISC_reserved0_MASK 0xfffff800 |
| #define BCHP_CLK_MISC_reserved0_SHIFT 11 |
| |
| /* CLK :: MISC :: RO_TESTOUT_EN [10:10] */ |
| #define BCHP_CLK_MISC_RO_TESTOUT_EN_MASK 0x00000400 |
| #define BCHP_CLK_MISC_RO_TESTOUT_EN_SHIFT 10 |
| |
| /* CLK :: MISC :: OBSRV_PLL_EN [09:09] */ |
| #define BCHP_CLK_MISC_OBSRV_PLL_EN_MASK 0x00000200 |
| #define BCHP_CLK_MISC_OBSRV_PLL_EN_SHIFT 9 |
| |
| /* CLK :: MISC :: HIF_SPI_CLK_SEL [08:08] */ |
| #define BCHP_CLK_MISC_HIF_SPI_CLK_SEL_MASK 0x00000100 |
| #define BCHP_CLK_MISC_HIF_SPI_CLK_SEL_SHIFT 8 |
| |
| /* CLK :: MISC :: reserved1 [07:05] */ |
| #define BCHP_CLK_MISC_reserved1_MASK 0x000000e0 |
| #define BCHP_CLK_MISC_reserved1_SHIFT 5 |
| |
| /* CLK :: MISC :: MOCA_ENET_CLK_SEL [04:04] */ |
| #define BCHP_CLK_MISC_MOCA_ENET_CLK_SEL_MASK 0x00000010 |
| #define BCHP_CLK_MISC_MOCA_ENET_CLK_SEL_SHIFT 4 |
| |
| /* CLK :: MISC :: MOCA_ENET_GMII_TX_CLK_SEL [03:03] */ |
| #define BCHP_CLK_MISC_MOCA_ENET_GMII_TX_CLK_SEL_MASK 0x00000008 |
| #define BCHP_CLK_MISC_MOCA_ENET_GMII_TX_CLK_SEL_SHIFT 3 |
| |
| /* CLK :: MISC :: VCXOA_OUTCLK_SRC_SEL [02:02] */ |
| #define BCHP_CLK_MISC_VCXOA_OUTCLK_SRC_SEL_MASK 0x00000004 |
| #define BCHP_CLK_MISC_VCXOA_OUTCLK_SRC_SEL_SHIFT 2 |
| |
| /* CLK :: MISC :: VCXOA_OUTCLK_ENABLE [01:01] */ |
| #define BCHP_CLK_MISC_VCXOA_OUTCLK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLK_MISC_VCXOA_OUTCLK_ENABLE_SHIFT 1 |
| |
| /* CLK :: MISC :: INV_VCXO_OUTCLK_SRCA [00:00] */ |
| #define BCHP_CLK_MISC_INV_VCXO_OUTCLK_SRCA_MASK 0x00000001 |
| #define BCHP_CLK_MISC_INV_VCXO_OUTCLK_SRCA_SHIFT 0 |
| |
| /*************************************************************************** |
| *THIRD_OT_CONTROL_1 - Low 3rd Overtone Oscillator Control registers |
| ***************************************************************************/ |
| /* CLK :: THIRD_OT_CONTROL_1 :: reserved0 [31:16] */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_reserved0_MASK 0xffff0000 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_reserved0_SHIFT 16 |
| |
| /* CLK :: THIRD_OT_CONTROL_1 :: GAIN_AMPLIFIER_CURRENT_CTRL [15:14] */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_GAIN_AMPLIFIER_CURRENT_CTRL_MASK 0x0000c000 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_GAIN_AMPLIFIER_CURRENT_CTRL_SHIFT 14 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_GAIN_AMPLIFIER_CURRENT_CTRL_ONE_HUNDRED_FIFTY_MICRO_AMP 0 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_GAIN_AMPLIFIER_CURRENT_CTRL_TWO_HUNDRED_MICRO_AMP 1 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_GAIN_AMPLIFIER_CURRENT_CTRL_TWO_HUNDRED_FIFTY_MICRO_AMP 2 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_GAIN_AMPLIFIER_CURRENT_CTRL_THREE_HUNDRED_MICRO_AMP 3 |
| |
| /* CLK :: THIRD_OT_CONTROL_1 :: ICBUF_CURRENT_CTRL [13:12] */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_ICBUF_CURRENT_CTRL_MASK 0x00003000 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_ICBUF_CURRENT_CTRL_SHIFT 12 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_ICBUF_CURRENT_CTRL_ONE_HUNDRED_FIFTY_MICRO_AMP 0 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_ICBUF_CURRENT_CTRL_TWO_HUNDRED_MICRO_AMP 1 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_ICBUF_CURRENT_CTRL_TWO_HUNDRED_FIFTY_MICRO_AMP 2 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_ICBUF_CURRENT_CTRL_THREE_HUNDRED_MICRO_AMP 3 |
| |
| /* CLK :: THIRD_OT_CONTROL_1 :: FREQ_DUBLER_CURRENT_CTRL [11:11] */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_DUBLER_CURRENT_CTRL_MASK 0x00000800 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_DUBLER_CURRENT_CTRL_SHIFT 11 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_DUBLER_CURRENT_CTRL_TWO_HUNDRED_MICRO_AMP 0 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_DUBLER_CURRENT_CTRL_THREE_HUNDRED_MICRO_AMP 1 |
| |
| /* CLK :: THIRD_OT_CONTROL_1 :: AMPLITUDE_LIMITER_ACTIVE [10:10] */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_AMPLITUDE_LIMITER_ACTIVE_MASK 0x00000400 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_AMPLITUDE_LIMITER_ACTIVE_SHIFT 10 |
| |
| /* CLK :: THIRD_OT_CONTROL_1 :: COMMON_MODE_VOLT_CTRL [09:08] */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_COMMON_MODE_VOLT_CTRL_MASK 0x00000300 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_COMMON_MODE_VOLT_CTRL_SHIFT 8 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_COMMON_MODE_VOLT_CTRL_ONE_POINT_FOUR_FIVE_VOLT 1 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_COMMON_MODE_VOLT_CTRL_ONE_POINT_FIVE_FOUR_VOLT 0 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_COMMON_MODE_VOLT_CTRL_ONE_POINT_SIX_TWO_VOLT 2 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_COMMON_MODE_VOLT_CTRL_ONE_POINT_SIX_SIX_VOLT 3 |
| |
| /* CLK :: THIRD_OT_CONTROL_1 :: FREQ_DOUBLER_BYPASS_EN [07:07] */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_DOUBLER_BYPASS_EN_MASK 0x00000080 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_DOUBLER_BYPASS_EN_SHIFT 7 |
| |
| /* CLK :: THIRD_OT_CONTROL_1 :: CML_6_N_P_EN [06:06] */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_CML_6_N_P_EN_MASK 0x00000040 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_CML_6_N_P_EN_SHIFT 6 |
| |
| /* CLK :: THIRD_OT_CONTROL_1 :: CML_5_N_P_EN [05:05] */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_CML_5_N_P_EN_MASK 0x00000020 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_CML_5_N_P_EN_SHIFT 5 |
| |
| /* CLK :: THIRD_OT_CONTROL_1 :: CML_4_N_P_EN [04:04] */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_CML_4_N_P_EN_MASK 0x00000010 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_CML_4_N_P_EN_SHIFT 4 |
| |
| /* CLK :: THIRD_OT_CONTROL_1 :: CML_3_N_P_EN [03:03] */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_CML_3_N_P_EN_MASK 0x00000008 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_CML_3_N_P_EN_SHIFT 3 |
| |
| /* CLK :: THIRD_OT_CONTROL_1 :: CML_2_N_P_EN [02:02] */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_CML_2_N_P_EN_MASK 0x00000004 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_CML_2_N_P_EN_SHIFT 2 |
| |
| /* CLK :: THIRD_OT_CONTROL_1 :: FREQ_MONITOR_OUTPUT_EN [01:01] */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_MONITOR_OUTPUT_EN_MASK 0x00000002 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_MONITOR_OUTPUT_EN_SHIFT 1 |
| |
| /* CLK :: THIRD_OT_CONTROL_1 :: FREQ_DOUBLER_POWER_DOWN [00:00] */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_DOUBLER_POWER_DOWN_MASK 0x00000001 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_DOUBLER_POWER_DOWN_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_LOCK_STATUS - current lock status of main PLL |
| ***************************************************************************/ |
| /* CLK :: PLL_LOCK_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLK_PLL_LOCK_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLK_PLL_LOCK_STATUS_reserved0_SHIFT 3 |
| |
| /* CLK :: PLL_LOCK_STATUS :: MIPS_PLL_LOCK [02:02] */ |
| #define BCHP_CLK_PLL_LOCK_STATUS_MIPS_PLL_LOCK_MASK 0x00000004 |
| #define BCHP_CLK_PLL_LOCK_STATUS_MIPS_PLL_LOCK_SHIFT 2 |
| |
| /* CLK :: PLL_LOCK_STATUS :: SYSTEM_PLL_0_LOCK [01:01] */ |
| #define BCHP_CLK_PLL_LOCK_STATUS_SYSTEM_PLL_0_LOCK_MASK 0x00000002 |
| #define BCHP_CLK_PLL_LOCK_STATUS_SYSTEM_PLL_0_LOCK_SHIFT 1 |
| |
| /* CLK :: PLL_LOCK_STATUS :: SYSTEM_PLL_1_LOCK [00:00] */ |
| #define BCHP_CLK_PLL_LOCK_STATUS_SYSTEM_PLL_1_LOCK_MASK 0x00000001 |
| #define BCHP_CLK_PLL_LOCK_STATUS_SYSTEM_PLL_1_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *SYS_PLL_1_CTLBUS_HI - SYS 1 PLL control bus higher word |
| ***************************************************************************/ |
| /* CLK :: SYS_PLL_1_CTLBUS_HI :: reserved0 [31:06] */ |
| #define BCHP_CLK_SYS_PLL_1_CTLBUS_HI_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLK_SYS_PLL_1_CTLBUS_HI_reserved0_SHIFT 6 |
| |
| /* CLK :: SYS_PLL_1_CTLBUS_HI :: CTL_BITS_37_32 [05:00] */ |
| #define BCHP_CLK_SYS_PLL_1_CTLBUS_HI_CTL_BITS_37_32_MASK 0x0000003f |
| #define BCHP_CLK_SYS_PLL_1_CTLBUS_HI_CTL_BITS_37_32_SHIFT 0 |
| |
| /*************************************************************************** |
| *SYS_PLL_1_CTLBUS_LO - SYS 1 PLL control bus lower word |
| ***************************************************************************/ |
| /* CLK :: SYS_PLL_1_CTLBUS_LO :: CTL_BITS_31_0 [31:00] */ |
| #define BCHP_CLK_SYS_PLL_1_CTLBUS_LO_CTL_BITS_31_0_MASK 0xffffffff |
| #define BCHP_CLK_SYS_PLL_1_CTLBUS_LO_CTL_BITS_31_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *SYS_PLL_1_CLOCK_ENA - SYS PLL 1 clock outputs enable |
| ***************************************************************************/ |
| /* CLK :: SYS_PLL_1_CLOCK_ENA :: reserved0 [31:06] */ |
| #define BCHP_CLK_SYS_PLL_1_CLOCK_ENA_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLK_SYS_PLL_1_CLOCK_ENA_reserved0_SHIFT 6 |
| |
| /* CLK :: SYS_PLL_1_CLOCK_ENA :: CLOCK_ENA [05:00] */ |
| #define BCHP_CLK_SYS_PLL_1_CLOCK_ENA_CLOCK_ENA_MASK 0x0000003f |
| #define BCHP_CLK_SYS_PLL_1_CLOCK_ENA_CLOCK_ENA_SHIFT 0 |
| #define BCHP_CLK_SYS_PLL_1_CLOCK_ENA_CLOCK_ENA_Enable 1 |
| #define BCHP_CLK_SYS_PLL_1_CLOCK_ENA_CLOCK_ENA_Disable 0 |
| |
| /*************************************************************************** |
| *SYS_PLL_1_1 - SYS_PLL_1 channel 1: 257.1429 MHz AVD clock, PLL source post divider powerdown |
| ***************************************************************************/ |
| /* CLK :: SYS_PLL_1_1 :: reserved0 [31:02] */ |
| #define BCHP_CLK_SYS_PLL_1_1_reserved0_MASK 0xfffffffc |
| #define BCHP_CLK_SYS_PLL_1_1_reserved0_SHIFT 2 |
| |
| /* CLK :: SYS_PLL_1_1 :: DIS_CH [01:01] */ |
| #define BCHP_CLK_SYS_PLL_1_1_DIS_CH_MASK 0x00000002 |
| #define BCHP_CLK_SYS_PLL_1_1_DIS_CH_SHIFT 1 |
| |
| /* CLK :: SYS_PLL_1_1 :: EN_CMLBUF [00:00] */ |
| #define BCHP_CLK_SYS_PLL_1_1_EN_CMLBUF_MASK 0x00000001 |
| #define BCHP_CLK_SYS_PLL_1_1_EN_CMLBUF_SHIFT 0 |
| |
| /*************************************************************************** |
| *SYS_PLL_1_2 - SYS_PLL_1 channel 2: 50 MHz SPI_NOR PHY clock, PLL source post divider powerdown and cml buffer enable |
| ***************************************************************************/ |
| /* CLK :: SYS_PLL_1_2 :: reserved0 [31:02] */ |
| #define BCHP_CLK_SYS_PLL_1_2_reserved0_MASK 0xfffffffc |
| #define BCHP_CLK_SYS_PLL_1_2_reserved0_SHIFT 2 |
| |
| /* CLK :: SYS_PLL_1_2 :: DIS_CH [01:01] */ |
| #define BCHP_CLK_SYS_PLL_1_2_DIS_CH_MASK 0x00000002 |
| #define BCHP_CLK_SYS_PLL_1_2_DIS_CH_SHIFT 1 |
| |
| /* CLK :: SYS_PLL_1_2 :: EN_CMLBUF [00:00] */ |
| #define BCHP_CLK_SYS_PLL_1_2_EN_CMLBUF_MASK 0x00000001 |
| #define BCHP_CLK_SYS_PLL_1_2_EN_CMLBUF_SHIFT 0 |
| |
| /*************************************************************************** |
| *SYS_PLL_1_3 - SYS_PLL_1 channel 3: 225 MHz MOCA PHY clock, PLL source post divider powerdown and cml buffer enable |
| ***************************************************************************/ |
| /* CLK :: SYS_PLL_1_3 :: reserved0 [31:02] */ |
| #define BCHP_CLK_SYS_PLL_1_3_reserved0_MASK 0xfffffffc |
| #define BCHP_CLK_SYS_PLL_1_3_reserved0_SHIFT 2 |
| |
| /* CLK :: SYS_PLL_1_3 :: DIS_CH [01:01] */ |
| #define BCHP_CLK_SYS_PLL_1_3_DIS_CH_MASK 0x00000002 |
| #define BCHP_CLK_SYS_PLL_1_3_DIS_CH_SHIFT 1 |
| |
| /* CLK :: SYS_PLL_1_3 :: EN_CMLBUF [00:00] */ |
| #define BCHP_CLK_SYS_PLL_1_3_EN_CMLBUF_MASK 0x00000001 |
| #define BCHP_CLK_SYS_PLL_1_3_EN_CMLBUF_SHIFT 0 |
| |
| /*************************************************************************** |
| *SYS_PLL_1_4 - SYS_PLL_1 channel 4: 225 MHz MOCA CPU, PLL source post divider powerdown and cml buffer enable |
| ***************************************************************************/ |
| /* CLK :: SYS_PLL_1_4 :: reserved0 [31:02] */ |
| #define BCHP_CLK_SYS_PLL_1_4_reserved0_MASK 0xfffffffc |
| #define BCHP_CLK_SYS_PLL_1_4_reserved0_SHIFT 2 |
| |
| /* CLK :: SYS_PLL_1_4 :: DIS_CH [01:01] */ |
| #define BCHP_CLK_SYS_PLL_1_4_DIS_CH_MASK 0x00000002 |
| #define BCHP_CLK_SYS_PLL_1_4_DIS_CH_SHIFT 1 |
| |
| /* CLK :: SYS_PLL_1_4 :: EN_CMLBUF [00:00] */ |
| #define BCHP_CLK_SYS_PLL_1_4_EN_CMLBUF_MASK 0x00000001 |
| #define BCHP_CLK_SYS_PLL_1_4_EN_CMLBUF_SHIFT 0 |
| |
| /*************************************************************************** |
| *SYS_PLL_1_5 - SYS_PLL_1 channel 5: 50 MHz USDS clock, PLL source post divider powerdown and cml buffer enable |
| ***************************************************************************/ |
| /* CLK :: SYS_PLL_1_5 :: reserved0 [31:02] */ |
| #define BCHP_CLK_SYS_PLL_1_5_reserved0_MASK 0xfffffffc |
| #define BCHP_CLK_SYS_PLL_1_5_reserved0_SHIFT 2 |
| |
| /* CLK :: SYS_PLL_1_5 :: DIS_CH [01:01] */ |
| #define BCHP_CLK_SYS_PLL_1_5_DIS_CH_MASK 0x00000002 |
| #define BCHP_CLK_SYS_PLL_1_5_DIS_CH_SHIFT 1 |
| |
| /* CLK :: SYS_PLL_1_5 :: EN_CMLBUF [00:00] */ |
| #define BCHP_CLK_SYS_PLL_1_5_EN_CMLBUF_MASK 0x00000001 |
| #define BCHP_CLK_SYS_PLL_1_5_EN_CMLBUF_SHIFT 0 |
| |
| /*************************************************************************** |
| *SYS_PLL_1_6 - SYS_PLL_1 channel 6: 100 MHz MOCA digital clock, PLL source post divider powerdown |
| ***************************************************************************/ |
| /* CLK :: SYS_PLL_1_6 :: reserved0 [31:01] */ |
| #define BCHP_CLK_SYS_PLL_1_6_reserved0_MASK 0xfffffffe |
| #define BCHP_CLK_SYS_PLL_1_6_reserved0_SHIFT 1 |
| |
| /* CLK :: SYS_PLL_1_6 :: DIS_CH [00:00] */ |
| #define BCHP_CLK_SYS_PLL_1_6_DIS_CH_MASK 0x00000001 |
| #define BCHP_CLK_SYS_PLL_1_6_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *SYS_PLL_0_1 - SYS_PLL_0 channel 1: 216 MHz system clock, PLL source post divider powerdown |
| ***************************************************************************/ |
| /* CLK :: SYS_PLL_0_1 :: reserved0 [31:02] */ |
| #define BCHP_CLK_SYS_PLL_0_1_reserved0_MASK 0xfffffffc |
| #define BCHP_CLK_SYS_PLL_0_1_reserved0_SHIFT 2 |
| |
| /* CLK :: SYS_PLL_0_1 :: DIS_CH [01:01] */ |
| #define BCHP_CLK_SYS_PLL_0_1_DIS_CH_MASK 0x00000002 |
| #define BCHP_CLK_SYS_PLL_0_1_DIS_CH_SHIFT 1 |
| |
| /* CLK :: SYS_PLL_0_1 :: EN_CMLBUF [00:00] */ |
| #define BCHP_CLK_SYS_PLL_0_1_EN_CMLBUF_MASK 0x00000001 |
| #define BCHP_CLK_SYS_PLL_0_1_EN_CMLBUF_SHIFT 0 |
| |
| /*************************************************************************** |
| *SYS_PLL_0_3 - SYS_PLL_0 channel 2: 81/40.5/20.25 MHz clocks to core_xpt, PLL source post divider powerdown |
| ***************************************************************************/ |
| /* CLK :: SYS_PLL_0_3 :: reserved0 [31:01] */ |
| #define BCHP_CLK_SYS_PLL_0_3_reserved0_MASK 0xfffffffe |
| #define BCHP_CLK_SYS_PLL_0_3_reserved0_SHIFT 1 |
| |
| /* CLK :: SYS_PLL_0_3 :: DIS_CH [00:00] */ |
| #define BCHP_CLK_SYS_PLL_0_3_DIS_CH_MASK 0x00000001 |
| #define BCHP_CLK_SYS_PLL_0_3_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *SYS_PLL_0_4 - SYS_PLL_0 channel 3: 48 MHz USB PLL reference, PLL source post divider powerdown and cml buffer enable |
| ***************************************************************************/ |
| /* CLK :: SYS_PLL_0_4 :: reserved0 [31:02] */ |
| #define BCHP_CLK_SYS_PLL_0_4_reserved0_MASK 0xfffffffc |
| #define BCHP_CLK_SYS_PLL_0_4_reserved0_SHIFT 2 |
| |
| /* CLK :: SYS_PLL_0_4 :: DIS_CH [01:01] */ |
| #define BCHP_CLK_SYS_PLL_0_4_DIS_CH_MASK 0x00000002 |
| #define BCHP_CLK_SYS_PLL_0_4_DIS_CH_SHIFT 1 |
| |
| /* CLK :: SYS_PLL_0_4 :: EN_CMLBUF [00:00] */ |
| #define BCHP_CLK_SYS_PLL_0_4_EN_CMLBUF_MASK 0x00000001 |
| #define BCHP_CLK_SYS_PLL_0_4_EN_CMLBUF_SHIFT 0 |
| |
| /*************************************************************************** |
| *SYS_PLL_1_CTRL - SYS PLL 1 reset, output_delay |
| ***************************************************************************/ |
| /* CLK :: SYS_PLL_1_CTRL :: LDO_CTRL [31:30] */ |
| #define BCHP_CLK_SYS_PLL_1_CTRL_LDO_CTRL_MASK 0xc0000000 |
| #define BCHP_CLK_SYS_PLL_1_CTRL_LDO_CTRL_SHIFT 30 |
| |
| /* CLK :: SYS_PLL_1_CTRL :: reserved0 [29:08] */ |
| #define BCHP_CLK_SYS_PLL_1_CTRL_reserved0_MASK 0x3fffff00 |
| #define BCHP_CLK_SYS_PLL_1_CTRL_reserved0_SHIFT 8 |
| |
| /* CLK :: SYS_PLL_1_CTRL :: POWERDOWN [07:07] */ |
| #define BCHP_CLK_SYS_PLL_1_CTRL_POWERDOWN_MASK 0x00000080 |
| #define BCHP_CLK_SYS_PLL_1_CTRL_POWERDOWN_SHIFT 7 |
| #define BCHP_CLK_SYS_PLL_1_CTRL_POWERDOWN_Powerdown 1 |
| #define BCHP_CLK_SYS_PLL_1_CTRL_POWERDOWN_Normal 0 |
| |
| /* CLK :: SYS_PLL_1_CTRL :: reserved_for_eco1 [06:02] */ |
| #define BCHP_CLK_SYS_PLL_1_CTRL_reserved_for_eco1_MASK 0x0000007c |
| #define BCHP_CLK_SYS_PLL_1_CTRL_reserved_for_eco1_SHIFT 2 |
| |
| /* CLK :: SYS_PLL_1_CTRL :: DRESET [01:01] */ |
| #define BCHP_CLK_SYS_PLL_1_CTRL_DRESET_MASK 0x00000002 |
| #define BCHP_CLK_SYS_PLL_1_CTRL_DRESET_SHIFT 1 |
| #define BCHP_CLK_SYS_PLL_1_CTRL_DRESET_Reset 1 |
| #define BCHP_CLK_SYS_PLL_1_CTRL_DRESET_Normal 0 |
| |
| /* CLK :: SYS_PLL_1_CTRL :: ARESET [00:00] */ |
| #define BCHP_CLK_SYS_PLL_1_CTRL_ARESET_MASK 0x00000001 |
| #define BCHP_CLK_SYS_PLL_1_CTRL_ARESET_SHIFT 0 |
| #define BCHP_CLK_SYS_PLL_1_CTRL_ARESET_Reset 1 |
| #define BCHP_CLK_SYS_PLL_1_CTRL_ARESET_Normal 0 |
| |
| /*************************************************************************** |
| *SYS_PLL_0_CTRL - SYS PLL 0 reset, output_delay |
| ***************************************************************************/ |
| /* CLK :: SYS_PLL_0_CTRL :: RST_STATUS [31:31] */ |
| #define BCHP_CLK_SYS_PLL_0_CTRL_RST_STATUS_MASK 0x80000000 |
| #define BCHP_CLK_SYS_PLL_0_CTRL_RST_STATUS_SHIFT 31 |
| |
| /* CLK :: SYS_PLL_0_CTRL :: reserved0 [30:12] */ |
| #define BCHP_CLK_SYS_PLL_0_CTRL_reserved0_MASK 0x7ffff000 |
| #define BCHP_CLK_SYS_PLL_0_CTRL_reserved0_SHIFT 12 |
| |
| /* CLK :: SYS_PLL_0_CTRL :: SYS_PLL_0_DLY_CH6 [11:10] */ |
| #define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH6_MASK 0x00000c00 |
| #define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH6_SHIFT 10 |
| |
| /* CLK :: SYS_PLL_0_CTRL :: SYS_PLL_0_DLY_CH5 [09:08] */ |
| #define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH5_MASK 0x00000300 |
| #define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH5_SHIFT 8 |
| |
| /* CLK :: SYS_PLL_0_CTRL :: SYS_PLL_0_DLY_CH4 [07:06] */ |
| #define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH4_MASK 0x000000c0 |
| #define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH4_SHIFT 6 |
| |
| /* CLK :: SYS_PLL_0_CTRL :: SYS_PLL_0_DLY_CH3 [05:04] */ |
| #define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH3_MASK 0x00000030 |
| #define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH3_SHIFT 4 |
| |
| /* CLK :: SYS_PLL_0_CTRL :: SYS_PLL_0_DLY_CH2 [03:02] */ |
| #define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH2_MASK 0x0000000c |
| #define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH2_SHIFT 2 |
| |
| /* CLK :: SYS_PLL_0_CTRL :: SYS_PLL_0_DLY_CH1 [01:00] */ |
| #define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH1_MASK 0x00000003 |
| #define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH1_SHIFT 0 |
| |
| /*************************************************************************** |
| *MIPS_PLL_CTRL - MIPS PLL reset, ch_disable, cpu frequency select, output_delay and powerdown |
| ***************************************************************************/ |
| /* CLK :: MIPS_PLL_CTRL :: RST_STATUS [31:31] */ |
| #define BCHP_CLK_MIPS_PLL_CTRL_RST_STATUS_MASK 0x80000000 |
| #define BCHP_CLK_MIPS_PLL_CTRL_RST_STATUS_SHIFT 31 |
| |
| /* CLK :: MIPS_PLL_CTRL :: BYPASS_PLL_RQ [30:30] */ |
| #define BCHP_CLK_MIPS_PLL_CTRL_BYPASS_PLL_RQ_MASK 0x40000000 |
| #define BCHP_CLK_MIPS_PLL_CTRL_BYPASS_PLL_RQ_SHIFT 30 |
| |
| /* CLK :: MIPS_PLL_CTRL :: BYPASS_PLL_STATE [29:29] */ |
| #define BCHP_CLK_MIPS_PLL_CTRL_BYPASS_PLL_STATE_MASK 0x20000000 |
| #define BCHP_CLK_MIPS_PLL_CTRL_BYPASS_PLL_STATE_SHIFT 29 |
| #define BCHP_CLK_MIPS_PLL_CTRL_BYPASS_PLL_STATE_normal_PLL_mode 0 |
| #define BCHP_CLK_MIPS_PLL_CTRL_BYPASS_PLL_STATE_bypassed_PLL_mode 1 |
| |
| /* union - case normal_PLL_mode [28:22] */ |
| /* CLK :: MIPS_PLL_CTRL :: normal_PLL_mode :: A_RST_PLL [28:28] */ |
| #define BCHP_CLK_MIPS_PLL_CTRL_normal_PLL_mode_A_RST_PLL_MASK 0x10000000 |
| #define BCHP_CLK_MIPS_PLL_CTRL_normal_PLL_mode_A_RST_PLL_SHIFT 28 |
| |
| /* CLK :: MIPS_PLL_CTRL :: normal_PLL_mode :: D_RST_PLL [27:27] */ |
| #define BCHP_CLK_MIPS_PLL_CTRL_normal_PLL_mode_D_RST_PLL_MASK 0x08000000 |
| #define BCHP_CLK_MIPS_PLL_CTRL_normal_PLL_mode_D_RST_PLL_SHIFT 27 |
| |
| /* CLK :: MIPS_PLL_CTRL :: normal_PLL_mode :: CPU_FREQ [26:23] */ |
| #define BCHP_CLK_MIPS_PLL_CTRL_normal_PLL_mode_CPU_FREQ_MASK 0x07800000 |
| #define BCHP_CLK_MIPS_PLL_CTRL_normal_PLL_mode_CPU_FREQ_SHIFT 23 |
| |
| /* CLK :: MIPS_PLL_CTRL :: normal_PLL_mode :: OVERRIDE_CPU_FREQ_PIN_STRAP [22:22] */ |
| #define BCHP_CLK_MIPS_PLL_CTRL_normal_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_MASK 0x00400000 |
| #define BCHP_CLK_MIPS_PLL_CTRL_normal_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_SHIFT 22 |
| |
| /* union - case bypassed_PLL_mode [28:22] */ |
| /* CLK :: MIPS_PLL_CTRL :: bypassed_PLL_mode :: A_RST_PLL [28:28] */ |
| #define BCHP_CLK_MIPS_PLL_CTRL_bypassed_PLL_mode_A_RST_PLL_MASK 0x10000000 |
| #define BCHP_CLK_MIPS_PLL_CTRL_bypassed_PLL_mode_A_RST_PLL_SHIFT 28 |
| |
| /* CLK :: MIPS_PLL_CTRL :: bypassed_PLL_mode :: D_RST_PLL [27:27] */ |
| #define BCHP_CLK_MIPS_PLL_CTRL_bypassed_PLL_mode_D_RST_PLL_MASK 0x08000000 |
| #define BCHP_CLK_MIPS_PLL_CTRL_bypassed_PLL_mode_D_RST_PLL_SHIFT 27 |
| |
| /* CLK :: MIPS_PLL_CTRL :: bypassed_PLL_mode :: CPU_FREQ [26:23] */ |
| #define BCHP_CLK_MIPS_PLL_CTRL_bypassed_PLL_mode_CPU_FREQ_MASK 0x07800000 |
| #define BCHP_CLK_MIPS_PLL_CTRL_bypassed_PLL_mode_CPU_FREQ_SHIFT 23 |
| |
| /* CLK :: MIPS_PLL_CTRL :: bypassed_PLL_mode :: OVERRIDE_CPU_FREQ_PIN_STRAP [22:22] */ |
| #define BCHP_CLK_MIPS_PLL_CTRL_bypassed_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_MASK 0x00400000 |
| #define BCHP_CLK_MIPS_PLL_CTRL_bypassed_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_SHIFT 22 |
| |
| /* CLK :: MIPS_PLL_CTRL :: reserved0 [21:19] */ |
| #define BCHP_CLK_MIPS_PLL_CTRL_reserved0_MASK 0x00380000 |
| #define BCHP_CLK_MIPS_PLL_CTRL_reserved0_SHIFT 19 |
| |
| /* CLK :: MIPS_PLL_CTRL :: DIS_MIPS_PLL_CH1 [18:18] */ |
| #define BCHP_CLK_MIPS_PLL_CTRL_DIS_MIPS_PLL_CH1_MASK 0x00040000 |
| #define BCHP_CLK_MIPS_PLL_CTRL_DIS_MIPS_PLL_CH1_SHIFT 18 |
| |
| /* CLK :: MIPS_PLL_CTRL :: MIPS_DLY_CH3 [17:16] */ |
| #define BCHP_CLK_MIPS_PLL_CTRL_MIPS_DLY_CH3_MASK 0x00030000 |
| #define BCHP_CLK_MIPS_PLL_CTRL_MIPS_DLY_CH3_SHIFT 16 |
| |
| /* CLK :: MIPS_PLL_CTRL :: MIPS_DLY_CH2 [15:14] */ |
| #define BCHP_CLK_MIPS_PLL_CTRL_MIPS_DLY_CH2_MASK 0x0000c000 |
| #define BCHP_CLK_MIPS_PLL_CTRL_MIPS_DLY_CH2_SHIFT 14 |
| |
| /* CLK :: MIPS_PLL_CTRL :: MIPS_DLY_CH1 [13:12] */ |
| #define BCHP_CLK_MIPS_PLL_CTRL_MIPS_DLY_CH1_MASK 0x00003000 |
| #define BCHP_CLK_MIPS_PLL_CTRL_MIPS_DLY_CH1_SHIFT 12 |
| |
| /* CLK :: MIPS_PLL_CTRL :: reserved1 [11:00] */ |
| #define BCHP_CLK_MIPS_PLL_CTRL_reserved1_MASK 0x00000fff |
| #define BCHP_CLK_MIPS_PLL_CTRL_reserved1_SHIFT 0 |
| |
| /*************************************************************************** |
| *AVD_DIV - SYS PLL 1 AVD clock divider settings |
| ***************************************************************************/ |
| /* CLK :: AVD_DIV :: reserved0 [31:08] */ |
| #define BCHP_CLK_AVD_DIV_reserved0_MASK 0xffffff00 |
| #define BCHP_CLK_AVD_DIV_reserved0_SHIFT 8 |
| |
| /* CLK :: AVD_DIV :: M1DIV [07:00] */ |
| #define BCHP_CLK_AVD_DIV_M1DIV_MASK 0x000000ff |
| #define BCHP_CLK_AVD_DIV_M1DIV_SHIFT 0 |
| |
| /*************************************************************************** |
| *SPI_50_DIV - SYS PLL 1 SPI 50 MHz clock divider settings |
| ***************************************************************************/ |
| /* CLK :: SPI_50_DIV :: reserved0 [31:08] */ |
| #define BCHP_CLK_SPI_50_DIV_reserved0_MASK 0xffffff00 |
| #define BCHP_CLK_SPI_50_DIV_reserved0_SHIFT 8 |
| |
| /* CLK :: SPI_50_DIV :: M2DIV [07:00] */ |
| #define BCHP_CLK_SPI_50_DIV_M2DIV_MASK 0x000000ff |
| #define BCHP_CLK_SPI_50_DIV_M2DIV_SHIFT 0 |
| |
| /*************************************************************************** |
| *MOCA_PHY_DIV - SYS PLL 1 MOCA_PHY clock divider settings |
| ***************************************************************************/ |
| /* CLK :: MOCA_PHY_DIV :: reserved0 [31:08] */ |
| #define BCHP_CLK_MOCA_PHY_DIV_reserved0_MASK 0xffffff00 |
| #define BCHP_CLK_MOCA_PHY_DIV_reserved0_SHIFT 8 |
| |
| /* CLK :: MOCA_PHY_DIV :: M3DIV [07:00] */ |
| #define BCHP_CLK_MOCA_PHY_DIV_M3DIV_MASK 0x000000ff |
| #define BCHP_CLK_MOCA_PHY_DIV_M3DIV_SHIFT 0 |
| |
| /*************************************************************************** |
| *MOCA_CPU_DIV - SYS PLL 1 MOCA_CPU clock divider settings |
| ***************************************************************************/ |
| /* CLK :: MOCA_CPU_DIV :: reserved0 [31:08] */ |
| #define BCHP_CLK_MOCA_CPU_DIV_reserved0_MASK 0xffffff00 |
| #define BCHP_CLK_MOCA_CPU_DIV_reserved0_SHIFT 8 |
| |
| /* CLK :: MOCA_CPU_DIV :: M4DIV [07:00] */ |
| #define BCHP_CLK_MOCA_CPU_DIV_M4DIV_MASK 0x000000ff |
| #define BCHP_CLK_MOCA_CPU_DIV_M4DIV_SHIFT 0 |
| |
| /*************************************************************************** |
| *USDS_DIV - SYS PLL 1 USDS clock divider settings |
| ***************************************************************************/ |
| /* CLK :: USDS_DIV :: reserved0 [31:08] */ |
| #define BCHP_CLK_USDS_DIV_reserved0_MASK 0xffffff00 |
| #define BCHP_CLK_USDS_DIV_reserved0_SHIFT 8 |
| |
| /* CLK :: USDS_DIV :: M5DIV [07:00] */ |
| #define BCHP_CLK_USDS_DIV_M5DIV_MASK 0x000000ff |
| #define BCHP_CLK_USDS_DIV_M5DIV_SHIFT 0 |
| |
| /*************************************************************************** |
| *D2CDIFF_AC_CTRL - AC_CTRL for D2CDIFF |
| ***************************************************************************/ |
| /* CLK :: D2CDIFF_AC_CTRL :: reserved_for_eco0 [31:23] */ |
| #define B0_BCHP_CLK_D2CDIFF_AC_CTRL_reserved_for_eco0_MASK 0xff800000 |
| #define B0_BCHP_CLK_D2CDIFF_AC_CTRL_reserved_for_eco0_SHIFT 23 |
| |
| /* CLK :: D2CDIFF_AC_CTRL :: CML_RPT_1_STATUS [22:22] */ |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPT_1_STATUS_MASK 0x00400000 |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPT_1_STATUS_SHIFT 22 |
| |
| /* CLK :: D2CDIFF_AC_CTRL :: CML_RPT_0_STATUS [21:21] */ |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPT_0_STATUS_MASK 0x00200000 |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPT_0_STATUS_SHIFT 21 |
| |
| /* CLK :: D2CDIFF_AC_CTRL :: MOCA_STATUS [20:20] */ |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_MOCA_STATUS_MASK 0x00100000 |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_MOCA_STATUS_SHIFT 20 |
| |
| /* CLK :: D2CDIFF_AC_CTRL :: USB_STATUS [19:19] */ |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_USB_STATUS_MASK 0x00080000 |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_USB_STATUS_SHIFT 19 |
| |
| /* CLK :: D2CDIFF_AC_CTRL :: AVD_STATUS [18:18] */ |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_AVD_STATUS_MASK 0x00040000 |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_AVD_STATUS_SHIFT 18 |
| |
| /* CLK :: D2CDIFF_AC_CTRL :: MIPS_STATUS [17:17] */ |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_MIPS_STATUS_MASK 0x00020000 |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_MIPS_STATUS_SHIFT 17 |
| |
| /* CLK :: D2CDIFF_AC_CTRL :: MAIN_STATUS [16:16] */ |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_MAIN_STATUS_MASK 0x00010000 |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_MAIN_STATUS_SHIFT 16 |
| |
| /* CLK :: D2CDIFF_AC_CTRL :: reserved_for_eco0 [15:07] */ |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_reserved_for_eco0_MASK 0x0000ff80 |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_reserved_for_eco0_SHIFT 7 |
| |
| /* CLK :: D2CDIFF_AC_CTRL :: CML_RPT_1_XOR [06:06] */ |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPT_1_XOR_MASK 0x00000040 |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPT_1_XOR_SHIFT 6 |
| |
| /* CLK :: D2CDIFF_AC_CTRL :: CML_RPT_0_XOR [05:05] */ |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPT_0_XOR_MASK 0x00000020 |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPT_0_XOR_SHIFT 5 |
| |
| /* CLK :: D2CDIFF_AC_CTRL :: MOCA_XOR [04:04] */ |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_MOCA_XOR_MASK 0x00000010 |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_MOCA_XOR_SHIFT 4 |
| |
| /* CLK :: D2CDIFF_AC_CTRL :: USB_XOR [03:03] */ |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_USB_XOR_MASK 0x00000008 |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_USB_XOR_SHIFT 3 |
| |
| /* CLK :: D2CDIFF_AC_CTRL :: AVD_XOR [02:02] */ |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_AVD_XOR_MASK 0x00000004 |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_AVD_XOR_SHIFT 2 |
| |
| /* CLK :: D2CDIFF_AC_CTRL :: MIPS_XOR [01:01] */ |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_MIPS_XOR_MASK 0x00000002 |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_MIPS_XOR_SHIFT 1 |
| |
| /* CLK :: D2CDIFF_AC_CTRL :: MAIN_XOR [00:00] */ |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_MAIN_XOR_MASK 0x00000001 |
| #define BCHP_CLK_D2CDIFF_AC_CTRL_MAIN_XOR_SHIFT 0 |
| |
| /*************************************************************************** |
| *VIEW_CLOCK_SELECT - View clock counter clock/lock_bit selection |
| ***************************************************************************/ |
| /* CLK :: VIEW_CLOCK_SELECT :: reserved0 [31:11] */ |
| #define BCHP_CLK_VIEW_CLOCK_SELECT_reserved0_MASK 0xfffff800 |
| #define BCHP_CLK_VIEW_CLOCK_SELECT_reserved0_SHIFT 11 |
| |
| /* CLK :: VIEW_CLOCK_SELECT :: ena_divide_by_8 [10:10] */ |
| #define BCHP_CLK_VIEW_CLOCK_SELECT_ena_divide_by_8_MASK 0x00000400 |
| #define BCHP_CLK_VIEW_CLOCK_SELECT_ena_divide_by_8_SHIFT 10 |
| |
| /* CLK :: VIEW_CLOCK_SELECT :: ena_divide_by_4 [09:09] */ |
| #define BCHP_CLK_VIEW_CLOCK_SELECT_ena_divide_by_4_MASK 0x00000200 |
| #define BCHP_CLK_VIEW_CLOCK_SELECT_ena_divide_by_4_SHIFT 9 |
| |
| /* CLK :: VIEW_CLOCK_SELECT :: ena_divide_by_2 [08:08] */ |
| #define BCHP_CLK_VIEW_CLOCK_SELECT_ena_divide_by_2_MASK 0x00000100 |
| #define BCHP_CLK_VIEW_CLOCK_SELECT_ena_divide_by_2_SHIFT 8 |
| |
| /* CLK :: VIEW_CLOCK_SELECT :: reserved1 [07:06] */ |
| #define BCHP_CLK_VIEW_CLOCK_SELECT_reserved1_MASK 0x000000c0 |
| #define BCHP_CLK_VIEW_CLOCK_SELECT_reserved1_SHIFT 6 |
| |
| /* CLK :: VIEW_CLOCK_SELECT :: view_clock_select [05:00] */ |
| #define BCHP_CLK_VIEW_CLOCK_SELECT_view_clock_select_MASK 0x0000003f |
| #define BCHP_CLK_VIEW_CLOCK_SELECT_view_clock_select_SHIFT 0 |
| |
| /*************************************************************************** |
| *RING_OSC_ENABLE - Enable Ring Oscillators |
| ***************************************************************************/ |
| /* CLK :: RING_OSC_ENABLE :: reserved0 [31:14] */ |
| #define BCHP_CLK_RING_OSC_ENABLE_reserved0_MASK 0xffffc000 |
| #define BCHP_CLK_RING_OSC_ENABLE_reserved0_SHIFT 14 |
| |
| /* CLK :: RING_OSC_ENABLE :: enable_ring_osc_13 [13:13] */ |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_13_MASK 0x00002000 |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_13_SHIFT 13 |
| |
| /* CLK :: RING_OSC_ENABLE :: enable_ring_osc_12 [12:12] */ |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_12_MASK 0x00001000 |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_12_SHIFT 12 |
| |
| /* CLK :: RING_OSC_ENABLE :: enable_ring_osc_11 [11:11] */ |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_11_MASK 0x00000800 |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_11_SHIFT 11 |
| |
| /* CLK :: RING_OSC_ENABLE :: enable_ring_osc_10 [10:10] */ |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_10_MASK 0x00000400 |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_10_SHIFT 10 |
| |
| /* CLK :: RING_OSC_ENABLE :: enable_ring_osc_9 [09:09] */ |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_9_MASK 0x00000200 |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_9_SHIFT 9 |
| |
| /* CLK :: RING_OSC_ENABLE :: enable_ring_osc_8 [08:08] */ |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_8_MASK 0x00000100 |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_8_SHIFT 8 |
| |
| /* CLK :: RING_OSC_ENABLE :: enable_ring_osc_7 [07:07] */ |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_7_MASK 0x00000080 |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_7_SHIFT 7 |
| |
| /* CLK :: RING_OSC_ENABLE :: enable_ring_osc_6 [06:06] */ |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_6_MASK 0x00000040 |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_6_SHIFT 6 |
| |
| /* CLK :: RING_OSC_ENABLE :: enable_ring_osc_5 [05:05] */ |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_5_MASK 0x00000020 |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_5_SHIFT 5 |
| |
| /* CLK :: RING_OSC_ENABLE :: enable_ring_osc_4 [04:04] */ |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_4_MASK 0x00000010 |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_4_SHIFT 4 |
| |
| /* CLK :: RING_OSC_ENABLE :: enable_ring_osc_3 [03:03] */ |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_3_MASK 0x00000008 |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_3_SHIFT 3 |
| |
| /* CLK :: RING_OSC_ENABLE :: enable_ring_osc_2 [02:02] */ |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_2_MASK 0x00000004 |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_2_SHIFT 2 |
| |
| /* CLK :: RING_OSC_ENABLE :: enable_ring_osc_1 [01:01] */ |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_1_MASK 0x00000002 |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_1_SHIFT 1 |
| |
| /* CLK :: RING_OSC_ENABLE :: enable_ring_osc_0 [00:00] */ |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_0_MASK 0x00000001 |
| #define BCHP_CLK_RING_OSC_ENABLE_enable_ring_osc_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *REF_CLOCK_COUNTER - Reference Clock Counter |
| ***************************************************************************/ |
| /* CLK :: REF_CLOCK_COUNTER :: reserved0 [31:20] */ |
| #define BCHP_CLK_REF_CLOCK_COUNTER_reserved0_MASK 0xfff00000 |
| #define BCHP_CLK_REF_CLOCK_COUNTER_reserved0_SHIFT 20 |
| |
| /* CLK :: REF_CLOCK_COUNTER :: ref_clock_cntr [19:00] */ |
| #define BCHP_CLK_REF_CLOCK_COUNTER_ref_clock_cntr_MASK 0x000fffff |
| #define BCHP_CLK_REF_CLOCK_COUNTER_ref_clock_cntr_SHIFT 0 |
| |
| /*************************************************************************** |
| *VIEW_CLOCK_COUNTER - View Clock Counter |
| ***************************************************************************/ |
| /* CLK :: VIEW_CLOCK_COUNTER :: reserved0 [31:24] */ |
| #define BCHP_CLK_VIEW_CLOCK_COUNTER_reserved0_MASK 0xff000000 |
| #define BCHP_CLK_VIEW_CLOCK_COUNTER_reserved0_SHIFT 24 |
| |
| /* CLK :: VIEW_CLOCK_COUNTER :: view_clock_cntr [23:00] */ |
| #define BCHP_CLK_VIEW_CLOCK_COUNTER_view_clock_cntr_MASK 0x00ffffff |
| #define BCHP_CLK_VIEW_CLOCK_COUNTER_view_clock_cntr_SHIFT 0 |
| |
| /*************************************************************************** |
| *RESET_COUNTER - Reset counters |
| ***************************************************************************/ |
| /* CLK :: RESET_COUNTER :: reserved0 [31:02] */ |
| #define BCHP_CLK_RESET_COUNTER_reserved0_MASK 0xfffffffc |
| #define BCHP_CLK_RESET_COUNTER_reserved0_SHIFT 2 |
| |
| /* CLK :: RESET_COUNTER :: reset_full_ref_count_done [01:01] */ |
| #define BCHP_CLK_RESET_COUNTER_reset_full_ref_count_done_MASK 0x00000002 |
| #define BCHP_CLK_RESET_COUNTER_reset_full_ref_count_done_SHIFT 1 |
| |
| /* CLK :: RESET_COUNTER :: reset_counter [00:00] */ |
| #define BCHP_CLK_RESET_COUNTER_reset_counter_MASK 0x00000001 |
| #define BCHP_CLK_RESET_COUNTER_reset_counter_SHIFT 0 |
| |
| /*************************************************************************** |
| *STOP_COUNTER - Stop counters |
| ***************************************************************************/ |
| /* CLK :: STOP_COUNTER :: reserved0 [31:03] */ |
| #define BCHP_CLK_STOP_COUNTER_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLK_STOP_COUNTER_reserved0_SHIFT 3 |
| |
| /* CLK :: STOP_COUNTER :: launch_full_ref_count [02:02] */ |
| #define BCHP_CLK_STOP_COUNTER_launch_full_ref_count_MASK 0x00000004 |
| #define BCHP_CLK_STOP_COUNTER_launch_full_ref_count_SHIFT 2 |
| |
| /* CLK :: STOP_COUNTER :: stop_ref_clock_cntr [01:01] */ |
| #define BCHP_CLK_STOP_COUNTER_stop_ref_clock_cntr_MASK 0x00000002 |
| #define BCHP_CLK_STOP_COUNTER_stop_ref_clock_cntr_SHIFT 1 |
| |
| /* CLK :: STOP_COUNTER :: stop_view_clock_cntr [00:00] */ |
| #define BCHP_CLK_STOP_COUNTER_stop_view_clock_cntr_MASK 0x00000001 |
| #define BCHP_CLK_STOP_COUNTER_stop_view_clock_cntr_SHIFT 0 |
| |
| /*************************************************************************** |
| *IN_RANGE - View clock counter is in range |
| ***************************************************************************/ |
| /* CLK :: IN_RANGE :: reserved0 [31:02] */ |
| #define BCHP_CLK_IN_RANGE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLK_IN_RANGE_reserved0_SHIFT 2 |
| |
| /* CLK :: IN_RANGE :: full_ref_count_done [01:01] */ |
| #define BCHP_CLK_IN_RANGE_full_ref_count_done_MASK 0x00000002 |
| #define BCHP_CLK_IN_RANGE_full_ref_count_done_SHIFT 1 |
| |
| /* CLK :: IN_RANGE :: in_range [00:00] */ |
| #define BCHP_CLK_IN_RANGE_in_range_MASK 0x00000001 |
| #define BCHP_CLK_IN_RANGE_in_range_SHIFT 0 |
| |
| /*************************************************************************** |
| *SWREG_VALUE - Hold SWREG related control values |
| ***************************************************************************/ |
| /* CLK :: SWREG_VALUE :: swreg_osc_freq [31:30] */ |
| #define BCHP_CLK_SWREG_VALUE_swreg_osc_freq_MASK 0xc0000000 |
| #define BCHP_CLK_SWREG_VALUE_swreg_osc_freq_SHIFT 30 |
| |
| /* CLK :: SWREG_VALUE :: swreg_novl_delay1p2 [29:26] */ |
| #define BCHP_CLK_SWREG_VALUE_swreg_novl_delay1p2_MASK 0x3c000000 |
| #define BCHP_CLK_SWREG_VALUE_swreg_novl_delay1p2_SHIFT 26 |
| |
| /* CLK :: SWREG_VALUE :: swreg_ovcur_prot [25:24] */ |
| #define BCHP_CLK_SWREG_VALUE_swreg_ovcur_prot_MASK 0x03000000 |
| #define BCHP_CLK_SWREG_VALUE_swreg_ovcur_prot_SHIFT 24 |
| |
| /* CLK :: SWREG_VALUE :: swreg_ramp1p2 [23:21] */ |
| #define BCHP_CLK_SWREG_VALUE_swreg_ramp1p2_MASK 0x00e00000 |
| #define BCHP_CLK_SWREG_VALUE_swreg_ramp1p2_SHIFT 21 |
| |
| /* CLK :: SWREG_VALUE :: swreg_adj [20:17] */ |
| #define BCHP_CLK_SWREG_VALUE_swreg_adj_MASK 0x001e0000 |
| #define BCHP_CLK_SWREG_VALUE_swreg_adj_SHIFT 17 |
| |
| /* CLK :: SWREG_VALUE :: swreg_adj1p2 [16:13] */ |
| #define BCHP_CLK_SWREG_VALUE_swreg_adj1p2_MASK 0x0001e000 |
| #define BCHP_CLK_SWREG_VALUE_swreg_adj1p2_SHIFT 13 |
| |
| /* CLK :: SWREG_VALUE :: swreg_ldo_ctrl [12:11] */ |
| #define BCHP_CLK_SWREG_VALUE_swreg_ldo_ctrl_MASK 0x00001800 |
| #define BCHP_CLK_SWREG_VALUE_swreg_ldo_ctrl_SHIFT 11 |
| |
| /* CLK :: SWREG_VALUE :: reserved0 [10:06] */ |
| #define BCHP_CLK_SWREG_VALUE_reserved0_MASK 0x000007c0 |
| #define BCHP_CLK_SWREG_VALUE_reserved0_SHIFT 6 |
| |
| /* CLK :: SWREG_VALUE :: swreg_value_lock [05:05] */ |
| #define BCHP_CLK_SWREG_VALUE_swreg_value_lock_MASK 0x00000020 |
| #define BCHP_CLK_SWREG_VALUE_swreg_value_lock_SHIFT 5 |
| |
| /* CLK :: SWREG_VALUE :: swreg_vselect [04:00] */ |
| #define BCHP_CLK_SWREG_VALUE_swreg_vselect_MASK 0x0000001f |
| #define BCHP_CLK_SWREG_VALUE_swreg_vselect_SHIFT 0 |
| |
| /*************************************************************************** |
| *OTP_SWREG_VALUE - Hold SWREG related control values from OTP |
| ***************************************************************************/ |
| /* CLK :: OTP_SWREG_VALUE :: reserved0 [31:05] */ |
| #define BCHP_CLK_OTP_SWREG_VALUE_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLK_OTP_SWREG_VALUE_reserved0_SHIFT 5 |
| |
| /* CLK :: OTP_SWREG_VALUE :: swreg_vselect [04:00] */ |
| #define BCHP_CLK_OTP_SWREG_VALUE_swreg_vselect_MASK 0x0000001f |
| #define BCHP_CLK_OTP_SWREG_VALUE_swreg_vselect_SHIFT 0 |
| |
| /*************************************************************************** |
| *UVREG_VALUE - Hold UVREG related control values |
| ***************************************************************************/ |
| /* CLK :: UVREG_VALUE :: reserved0 [31:06] */ |
| #define BCHP_CLK_UVREG_VALUE_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLK_UVREG_VALUE_reserved0_SHIFT 6 |
| |
| /* CLK :: UVREG_VALUE :: uvreg_value_lock [05:05] */ |
| #define BCHP_CLK_UVREG_VALUE_uvreg_value_lock_MASK 0x00000020 |
| #define BCHP_CLK_UVREG_VALUE_uvreg_value_lock_SHIFT 5 |
| |
| /* CLK :: UVREG_VALUE :: uvreg_sel1pt2 [04:00] */ |
| #define BCHP_CLK_UVREG_VALUE_uvreg_sel1pt2_MASK 0x0000001f |
| #define BCHP_CLK_UVREG_VALUE_uvreg_sel1pt2_SHIFT 0 |
| |
| /*************************************************************************** |
| *OTP_UVREG_VALUE - Hold UVREG related control values from OTP |
| ***************************************************************************/ |
| /* CLK :: OTP_UVREG_VALUE :: reserved0 [31:05] */ |
| #define BCHP_CLK_OTP_UVREG_VALUE_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLK_OTP_UVREG_VALUE_reserved0_SHIFT 5 |
| |
| /* CLK :: OTP_UVREG_VALUE :: uvreg_sel1pt2 [04:00] */ |
| #define BCHP_CLK_OTP_UVREG_VALUE_uvreg_sel1pt2_MASK 0x0000001f |
| #define BCHP_CLK_OTP_UVREG_VALUE_uvreg_sel1pt2_SHIFT 0 |
| |
| /*************************************************************************** |
| *RO_TEST_SUB_BLOCK_SEL - additional select/control values that can be used for OSC pads |
| ***************************************************************************/ |
| /* CLK :: RO_TEST_SUB_BLOCK_SEL :: reserved0 [31:02] */ |
| #define BCHP_CLK_RO_TEST_SUB_BLOCK_SEL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLK_RO_TEST_SUB_BLOCK_SEL_reserved0_SHIFT 2 |
| |
| /* CLK :: RO_TEST_SUB_BLOCK_SEL :: ro_test_sub_block_select [01:00] */ |
| #define BCHP_CLK_RO_TEST_SUB_BLOCK_SEL_ro_test_sub_block_select_MASK 0x00000003 |
| #define BCHP_CLK_RO_TEST_SUB_BLOCK_SEL_ro_test_sub_block_select_SHIFT 0 |
| |
| /*************************************************************************** |
| *SCRATCH - clock_gen Scratch register |
| ***************************************************************************/ |
| /* CLK :: SCRATCH :: VALUE [31:00] */ |
| #define BCHP_CLK_SCRATCH_VALUE_MASK 0xffffffff |
| #define BCHP_CLK_SCRATCH_VALUE_SHIFT 0 |
| |
| #endif /* #ifndef BCHP_CLK_H__ */ |
| |
| /* End of File */ |
