| /*************************************************************************** |
| * Copyright (c) 1999-2013, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Tue Apr 16 03:20:11 2013 |
| * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: $ |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_CLKGEN_H__ |
| #define BCHP_CLKGEN_H__ |
| |
| /*************************************************************************** |
| *CLKGEN - clkgen registers |
| ***************************************************************************/ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL 0x00420000 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV 0x00420004 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN 0x00420008 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS 0x0042000c /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN 0x00420010 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET 0x00420014 /* Resets */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x00420018 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x0042001c /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS 0x00420020 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL 0x00420024 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV 0x00420028 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN 0x0042002c /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS 0x00420030 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN 0x00420034 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET 0x00420038 /* Resets */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x0042003c /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x00420040 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS 0x00420044 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0 0x00420048 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1 0x0042004c /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2 0x00420050 /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3 0x00420054 /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4 0x00420058 /* PLL CHANNEL control CH 4 */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL 0x0042005c /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_DIV 0x00420060 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN 0x00420064 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS 0x00420068 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC 0x0042006c /* Miscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC2 0x00420070 /* Miscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN 0x00420074 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET 0x00420078 /* Resets */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH 0x0042007c /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW 0x00420080 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_STATUS 0x00420084 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 0x00420088 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL 0x0042008c /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV 0x00420090 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN 0x00420094 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS 0x00420098 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC 0x0042009c /* Miscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2 0x004200a0 /* Miscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN 0x004200a4 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET 0x004200a8 /* Resets */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH 0x004200ac /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW 0x004200b0 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS 0x004200b4 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0 0x004200b8 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1 0x004200bc /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3 0x004200c0 /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CONTROL 0x004200c4 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV 0x004200c8 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN 0x004200cc /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS 0x004200d0 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC 0x004200d4 /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_PWRDN 0x004200d8 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET 0x004200dc /* Resets */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH 0x004200e0 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW 0x004200e4 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_STATUS 0x004200e8 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x004200ec /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x004200f0 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x004200f4 /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x004200f8 /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x004200fc /* PLL CHANNEL control CH 4 */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x00420100 /* PLL CHANNEL control CH 5 */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL 0x00420104 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV 0x00420108 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN 0x0042010c /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS 0x00420110 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC 0x00420114 /* Miscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2 0x00420118 /* Miscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN 0x0042011c /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_RESET 0x00420120 /* Resets */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x00420124 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x00420128 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS 0x0042012c /* Test Status */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 0x00420130 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 0x00420134 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 0x00420138 /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 0x0042013c /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 0x00420140 /* PLL CHANNEL control CH 4 */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL 0x00420144 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV 0x00420148 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN 0x0042014c /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS 0x00420150 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC 0x00420154 /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN 0x00420158 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET 0x0042015c /* Resets */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH 0x00420160 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW 0x00420164 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS 0x00420168 /* Status */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 0x0042016c /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 0x00420170 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 0x00420174 /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL 0x00420178 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV 0x0042017c /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC 0x00420180 /* Fractional */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN 0x00420184 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS 0x00420188 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC 0x0042018c /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN 0x00420190 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET 0x00420194 /* Resets */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH 0x00420198 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW 0x0042019c /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS 0x004201a0 /* Status */ |
| #define BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE 0x004201a4 /* Disable ANA_QDAC40G_M7FC's clocks */ |
| #define BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE_STATUS 0x004201a8 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE 0x004201ac /* Avd0 top clock enable */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SID 0x004201b0 /* Avd0 top clock enable sid */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SID_STATUS 0x004201b4 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS 0x004201b8 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE 0x004201bc /* Avd0 top memory standby enable */ |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK 0x004201c0 /* Avd0 top observe clock */ |
| #define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY 0x004201c4 /* Avd0 top power switch memory */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE 0x004201c8 /* Bcm mips top clock enable */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS 0x004201cc /* Clock Enable Status */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE 0x004201d0 /* Bcm mips top memory standby enable */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK 0x004201d4 /* Bcm mips top observe clock */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY 0x004201d8 /* Bcm mips top power switch memory */ |
| #define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE 0x004201dc /* Bvn top clock enable */ |
| #define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_STATUS 0x004201e0 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE 0x004201e4 /* Bvn top memory standby enable */ |
| #define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY 0x004201e8 /* Bvn top power switch memory */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE 0x004201ec /* Disable CLKGEN's clocks */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS 0x004201f0 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_ENABLE 0x004201f4 /* Clkgen clock enable */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_ENABLE_STATUS 0x004201f8 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL 0x004201fc /* Clock Monitor Control */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT 0x00420200 /* Clock Monitor Max Reference Count */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER 0x00420204 /* Clock Monitor Reference Counter */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE 0x00420208 /* Clock Monitor Reference Counter */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER 0x0042020c /* Clock Monitor View Counter */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE 0x00420210 /* Disable CORE_XPT's clocks */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS 0x00420214 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE 0x00420218 /* Core xpt clock enable */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS 0x0042021c /* Clock Enable Status */ |
| #define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE 0x00420220 /* Core xpt memory standby enable */ |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK 0x00420224 /* Core xpt observe clock */ |
| #define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY 0x00420228 /* Core xpt power switch memory */ |
| #define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_OBSERVE_CLOCK 0x0042022c /* Cpuwrap 3375 bcm mips observe clock */ |
| #define BCHP_CLKGEN_DS_TOPA_CLOCK_ENABLE 0x00420230 /* Ds topa clock enable */ |
| #define BCHP_CLKGEN_DS_TOPA_CLOCK_ENABLE_STATUS 0x00420234 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_DS_TOPA_DATA 0x00420238 /* Ds topa data */ |
| #define BCHP_CLKGEN_DS_TOPA_OBSERVE_CLOCK 0x0042023c /* Ds topa observe clock */ |
| #define BCHP_CLKGEN_DS_WFE_TOP_CLOCK_ENABLE 0x00420240 /* Ds wfe top clock enable */ |
| #define BCHP_CLKGEN_DS_WFE_TOP_CLOCK_ENABLE_STATUS 0x00420244 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_DS_WFE_TOP_DATA 0x00420248 /* Ds wfe top data */ |
| #define BCHP_CLKGEN_DS_WFE_TOP_OBSERVE_CLOCK 0x0042024c /* Ds wfe top observe clock */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE 0x00420250 /* Disable DUAL_GENET_TOP_DUAL_RGMII's clocks */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS 0x00420254 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE 0x00420258 /* Dual genet top dual rgmii clock enable */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1 0x0042025c /* Dual genet top dual rgmii clock enable genet1 */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_STATUS 0x00420260 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS 0x00420264 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT 0x00420268 /* Dual genet top dual rgmii clock select */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE_A 0x0042026c /* Dual genet top dual rgmii memory standby enable a */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK 0x00420270 /* Dual genet top dual rgmii observe clock */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY_A 0x00420274 /* Dual genet top dual rgmii power switch memory a */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE 0x00420278 /* Disable DVP_HT's clocks */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_STATUS 0x0042027c /* Clock Disable Status */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE 0x00420280 /* Dvp ht clock enable */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS 0x00420284 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE 0x00420288 /* Dvp ht memory standby enable */ |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK 0x0042028c /* Dvp ht observe clock */ |
| #define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY 0x00420290 /* Dvp ht power switch memory */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE 0x00420294 /* Graphics clock enable */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC 0x00420298 /* Graphics clock enable m2mc */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_STATUS 0x0042029c /* Clock Enable Status */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_STATUS 0x004202a0 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D 0x004202a4 /* Graphics clock enable v3d */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_STATUS 0x004202a8 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC 0x004202ac /* Graphics memory standby enable m2mc */ |
| #define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_V3D 0x004202b0 /* Graphics memory standby enable v3d */ |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK 0x004202b4 /* Graphics observe clock */ |
| #define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_M2MC 0x004202b8 /* Graphics power switch memory m2mc */ |
| #define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_V3D 0x004202bc /* Graphics power switch memory v3d */ |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE 0x004202c0 /* Disable HIF's clocks */ |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_STATUS 0x004202c4 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE 0x004202c8 /* Hif clock enable */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO 0x004202cc /* Hif clock enable sdio */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_STATUS 0x004202d0 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_STATUS 0x004202d4 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE 0x004202d8 /* Hif memory standby enable */ |
| #define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SDIO 0x004202dc /* Hif memory standby enable sdio */ |
| #define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY 0x004202e0 /* Hif power switch memory */ |
| #define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SDIO 0x004202e4 /* Hif power switch memory sdio */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT 0x004202e8 /* Mux selects for Internal clocks */ |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_DISABLE 0x004202ec /* Disable LEAP_TOP's clocks */ |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_DISABLE_STATUS 0x004202f0 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_ENABLE 0x004202f4 /* Leap top clock enable */ |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_ENABLE_STATUS 0x004202f8 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_LEAP_TOP_DATA 0x004202fc /* Leap top data */ |
| #define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE 0x00420300 /* Memsys clock enable */ |
| #define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_STATUS 0x00420304 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_MEMSYS_MEMORY_STANDBY_ENABLE 0x00420308 /* Memsys memory standby enable */ |
| #define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK 0x0042030c /* Memsys observe clock */ |
| #define BCHP_CLKGEN_MEMSYS_POWER_SWITCH_MEMORY 0x00420310 /* Memsys power switch memory */ |
| #define BCHP_CLKGEN_MEMSYS_STATUS 0x00420314 /* Memsys status */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION 0x00420318 /* Select observation clk */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION 0x0042031c /* Select observation clk */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION 0x00420320 /* Select observation clk */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION 0x00420324 /* Select observation clk */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE 0x00420328 /* Disable PAD's clocks */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS 0x0042032c /* Clock Disable Status */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT 0x00420330 /* Mux selects for Pad clocks */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS 0x00420334 /* PLL_AUDIO0 Reset Status */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS 0x00420338 /* PLL_AUDIO1 Reset Status */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS 0x0042033c /* PLL_AVD Reset Status */ |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST 0x00420340 /* PLL_MIPS Glitchless Clock Switching */ |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS 0x00420344 /* PLL_MIPS Glitchless Switching */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS 0x00420348 /* PLL_MIPS Reset Status */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS 0x0042034c /* PLL_SC Reset Status */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS 0x00420350 /* PLL_SYS1 Reset Status */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS 0x00420354 /* PLL_VCXO Reset Status */ |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL 0x00420358 /* Select clocks that can stay alive during power management standby mode. */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL 0x0042035c /* PLL Alive in Standby Mode */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP 0x00420360 /* Power management LDO PLL */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM 0x00420364 /* Power management LDO PLL state machine */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE 0x00420368 /* Raaga dsp top clock enable */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS 0x0042036c /* Clock Enable Status */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE 0x00420370 /* Raaga dsp top memory standby enable */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK 0x00420374 /* Raaga dsp top observe clock */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY 0x00420378 /* Raaga dsp top power switch memory */ |
| #define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE 0x0042037c /* Rfm top clock enable */ |
| #define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_STATUS 0x00420380 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE 0x00420384 /* Rfm top memory standby enable */ |
| #define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK 0x00420388 /* Rfm top observe clock */ |
| #define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY 0x0042038c /* Rfm top power switch memory */ |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE 0x00420390 /* Disable SATA3_TOP's clocks */ |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_STATUS 0x00420394 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE 0x00420398 /* Sata3 top clock enable */ |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_STATUS 0x0042039c /* Clock Enable Status */ |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_SELECT 0x004203a0 /* Sata3 top clock select */ |
| #define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE 0x004203a4 /* Sata3 top memory standby enable */ |
| #define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK 0x004203a8 /* Sata3 top observe clock */ |
| #define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY 0x004203ac /* Sata3 top power switch memory */ |
| #define BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA 0x004203b0 /* Sectop clock enable m2mdma */ |
| #define BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA_STATUS 0x004203b4 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK 0x004203b8 /* Sectop observe clock */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT 0x004203bc /* Mux selects for Smartcard clocks */ |
| #define BCHP_CLKGEN_SPARE 0x004203c0 /* Spares */ |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK 0x004203c4 /* Sys aon observe clock */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE 0x004203c8 /* Disable SYS_CTRL's clocks */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS 0x004203cc /* Clock Disable Status */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE 0x004203d0 /* Sys ctrl clock enable */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_STATUS 0x004203d4 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE 0x004203d8 /* Sys ctrl memory standby enable */ |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK 0x004203dc /* Sys ctrl observe clock */ |
| #define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY 0x004203e0 /* Sys ctrl power switch memory */ |
| #define BCHP_CLKGEN_TESTPORT 0x004203e4 /* Special Testport Controls */ |
| #define BCHP_CLKGEN_USB_CLOCK_DISABLE 0x004203e8 /* Disable USB's clocks */ |
| #define BCHP_CLKGEN_USB_CLOCK_DISABLE_STATUS 0x004203ec /* Clock Disable Status */ |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE 0x004203f0 /* Usb clock enable */ |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_STATUS 0x004203f4 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE 0x004203f8 /* Usb memory standby enable */ |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK 0x004203fc /* Usb observe clock */ |
| #define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY 0x00420400 /* Usb power switch memory */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE 0x00420404 /* Disable VEC_AIO_TOP's clocks */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_STATUS 0x00420408 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE 0x0042040c /* Vec aio top clock enable */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO 0x00420410 /* Vec aio top clock enable aio */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_STATUS 0x00420414 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_STATUS 0x00420418 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC 0x0042041c /* Vec aio top clock enable vec */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS 0x00420420 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO 0x00420424 /* Vec aio top memory standby enable aio */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC 0x00420428 /* Vec aio top memory standby enable vec */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK 0x0042042c /* Vec aio top observe clock */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO 0x00420430 /* Vec aio top observe clock aio */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC 0x00420434 /* Vec aio top observe clock vec */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO 0x00420438 /* Vec aio top power switch memory aio */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC 0x0042043c /* Vec aio top power switch memory vec */ |
| #define BCHP_CLKGEN_TM_TS_CTRL 0x004204b0 /* TS_CTRL */ |
| #define BCHP_CLKGEN_TM_MEM_CTRL 0x004204b4 /* MEM_CTRL */ |
| #define BCHP_CLKGEN_TM_MEM_CTRL2 0x004204b8 /* MEM_CTRL2 */ |
| #define BCHP_CLKGEN_TM_PWRDN 0x004204bc /* PWRDN */ |
| #define BCHP_CLKGEN_TM_SFT_RST 0x004204c0 /* SFT_RST */ |
| #define BCHP_CLKGEN_TM_SYS_PLL_STATUS 0x004204c4 /* SYS_PLL_STATUS */ |
| #define BCHP_CLKGEN_TM_SYS_PLL_RST 0x004204c8 /* SYS_PLL_RST */ |
| #define BCHP_CLKGEN_TM_SYS_PLL_CLK_216 0x004204cc /* SYS_PLL_CLK_216 */ |
| #define BCHP_CLKGEN_TM_SYS_PLL_CLK_T2B 0x004204d0 /* SYS_PLL_CLK_T2B */ |
| #define BCHP_CLKGEN_TM_SYS_CLK_EN 0x004204d4 /* SYS_CLK_EN */ |
| #define BCHP_CLKGEN_TM_SYS_REV_ID 0x004204d8 /* SYS_REV_ID */ |
| #define BCHP_CLKGEN_TM_OSC_CLK_EN 0x004204dc /* OSC_CLK_EN */ |
| #define BCHP_CLKGEN_TM_SYS_PLL_PDIV 0x004204e0 /* SYS_PLL_PDIV */ |
| #define BCHP_CLKGEN_TM_SYS_PLL_NDIV_INT 0x004204e4 /* SYS_PLL_NDIV_INT */ |
| #define BCHP_CLKGEN_TM_SFT0 0x004204e8 /* SFT0 */ |
| #define BCHP_CLKGEN_TM_SFT1 0x004204ec /* SFT1 */ |
| #define BCHP_CLKGEN_TM_SFT2 0x004204f0 /* SFT2 */ |
| #define BCHP_CLKGEN_TM_SFT3 0x004204f4 /* SFT3 */ |
| #define BCHP_CLKGEN_TM_SFT4 0x004204f8 /* SFT4 */ |
| #define BCHP_CLKGEN_TM_SFT5 0x004204fc /* SFT5 */ |
| #define BCHP_CLKGEN_TM_SFT6 0x00420500 /* SFT6 */ |
| #define BCHP_CLKGEN_TM_SFT7 0x00420504 /* SFT7 */ |
| #define BCHP_CLKGEN_TM_CM0 0x00420508 /* CM0 */ |
| #define BCHP_CLKGEN_TM_CM1 0x0042050c /* CM1 */ |
| #define BCHP_CLKGEN_TM_CM2 0x00420510 /* CM2 */ |
| #define BCHP_CLKGEN_TM_CM3 0x00420514 /* CM3 */ |
| #define BCHP_CLKGEN_BSPI_CLOCK_SELECT 0x00420518 /* BSPI CLOCK SELECT - spi clock control */ |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [02:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [02:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000006 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000008 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000006 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000008 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000006 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_AVD_PLL_DIV :: PDIV [12:10] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: PLL_AVD_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_DEFAULT 0x00000087 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_AVD_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000006 |
| |
| /* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_AVD_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_MISC - Miscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: reserved0 [31:31] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_reserved0_MASK 0x80000000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_reserved0_SHIFT 31 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: VCO_DLY [30:29] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_MASK 0x60000000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: VCODIV2 [28:28] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_UPDATE [27:27] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_SELECT [26:24] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_MASK 0x07000000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_RESET_ [23:23] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__SHIFT 23 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_MODE [22:21] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_MASK 0x00600000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_SHIFT 21 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: REFCLKOUT [20:20] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_MASK 0x00100000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: PWM_RATE [19:18] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_MASK 0x000c0000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: POR_BYPASS [17:17] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_MASK 0x00020000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_SHIFT 17 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: NDIV_RELOCK [16:16] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_MASK 0x00010000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: LDO_REF_SEL [15:15] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: FAST_LOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_MISC2 - Miscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_MISC2 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC2 :: SPARE [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AVD_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AVD_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_AVD_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000004 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_DIV :: PDIV [12:10] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_DEFAULT 0x00000058 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_MISC - Miscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: reserved0 [31:31] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_MASK 0x80000000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_SHIFT 31 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: VCO_DLY [30:29] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_MASK 0x60000000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: VCODIV2 [28:28] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_UPDATE [27:27] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_SELECT [26:24] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_MASK 0x07000000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_RESET_ [23:23] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__SHIFT 23 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_MODE [22:21] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_MASK 0x00600000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_SHIFT 21 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: REFCLKOUT [20:20] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_MASK 0x00100000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: PWM_RATE [19:18] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_MASK 0x000c0000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: POR_BYPASS [17:17] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_MASK 0x00020000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_SHIFT 17 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: NDIV_RELOCK [16:16] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_MASK 0x00010000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: LDO_REF_SEL [15:15] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: FAST_LOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_MISC2 - Miscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_MISC2 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC2 :: SPARE [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000028 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000028 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000032 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_SC_PLL_DIV :: PDIV [12:10] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_SC_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_DEFAULT 0x00000040 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_SC_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007 |
| |
| /* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_SC_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_MISC :: reserved0 [31:30] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_MASK 0xc0000000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_SHIFT 30 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: VCO_DLY [29:28] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_MASK 0x30000000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2_POST [27:27] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2 [26:26] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_MASK 0x04000000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_SHIFT 26 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: STAT_UPDATE [25:25] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_MASK 0x02000000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_SHIFT 25 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: STAT_SELECT [24:22] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_MASK 0x01c00000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: STAT_RESET_ [21:21] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__MASK 0x00200000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__SHIFT 21 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: STAT_MODE [20:19] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_MASK 0x00180000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_SHIFT 19 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: REFCLKOUT [18:18] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_MASK 0x00040000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: PWM_RATE [17:16] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_MASK 0x00030000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: MDIV_RELOCK [15:15] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: FAST_LOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SC_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_SC_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000006 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000001a |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000008 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000009 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000060 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000036 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [12:10] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT 0x00000060 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_MISC - Miscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: reserved0 [31:31] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_MASK 0x80000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_SHIFT 31 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DLY [30:29] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_MASK 0x60000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: VCODIV2 [28:28] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [27:27] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [26:24] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK 0x07000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET_ [23:23] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__SHIFT 23 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [22:21] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK 0x00600000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT 21 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: REFCLKOUT [20:20] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_MASK 0x00100000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [19:18] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK 0x000c0000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: POR_BYPASS [17:17] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_MASK 0x00020000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_SHIFT 17 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK 0x00010000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: LDO_REF_SEL [15:15] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_MISC2 - Miscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_MISC2 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC2 :: SPARE [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_RESET :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_RESET :: RESETD [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000012 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000009 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000005a |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x0000005a |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_DIV :: PDIV [12:10] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_DEFAULT 0x0000007d |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: reserved0 [31:30] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_MASK 0xc0000000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_SHIFT 30 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: VCO_DLY [29:28] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_MASK 0x30000000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2_POST [27:27] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2 [26:26] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_MASK 0x04000000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_SHIFT 26 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_UPDATE [25:25] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_MASK 0x02000000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_SHIFT 25 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_SELECT [24:22] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_MASK 0x01c00000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_RESET_ [21:21] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__MASK 0x00200000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__SHIFT 21 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_MODE [20:19] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_MASK 0x00180000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_SHIFT 19 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: REFCLKOUT [18:18] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_MASK 0x00040000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: PWM_RATE [17:16] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_MASK 0x00030000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: MDIV_RELOCK [15:15] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: FAST_LOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_STATUS - Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000004b |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_DIV :: PDIV [12:10] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_DEFAULT 0x00000040 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_FRAC - Fractional |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_FRAC :: reserved0 [31:20] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_MASK 0xfff00000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_SHIFT 20 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_FRAC :: FRAC_CONTROL [19:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: reserved0 [31:30] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_MASK 0xc0000000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_SHIFT 30 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: VCO_DLY [29:28] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_MASK 0x30000000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2_POST [27:27] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2 [26:26] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_MASK 0x04000000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_SHIFT 26 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_UPDATE [25:25] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_MASK 0x02000000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_SHIFT 25 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_SELECT [24:22] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_MASK 0x01c00000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_RESET_ [21:21] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__MASK 0x00200000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__SHIFT 21 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_MODE [20:19] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_MASK 0x00180000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_SHIFT 19 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: REFCLKOUT [18:18] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_MASK 0x00040000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: PWM_RATE [17:16] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_MASK 0x00030000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: MDIV_RELOCK [15:15] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: FAST_LOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_STATUS - Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *ANA_QDAC40G_M7FC_CLOCK_DISABLE - Disable ANA_QDAC40G_M7FC's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: ANA_QDAC40G_M7FC_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: ANA_QDAC40G_M7FC_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ANA_QDAC40G_M7FC_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: ANA_QDAC40G_M7FC_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: ANA_QDAC40G_M7FC_CLOCK_DISABLE_STATUS :: DISABLE_VEC_DACADC_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *AVD0_TOP_CLOCK_ENABLE - Avd0 top clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: AVD0_SCB_CLOCK_ENABLE [03:03] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_SCB_CLOCK_ENABLE_MASK 0x00000008 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_SCB_CLOCK_ENABLE_SHIFT 3 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: AVD0_CPU_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_CPU_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_CPU_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_CPU_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: AVD0_CORE_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_CORE_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_CORE_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_CORE_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: AVD0_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *AVD0_TOP_CLOCK_ENABLE_SID - Avd0 top clock enable sid |
| ***************************************************************************/ |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE_SID :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SID_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SID_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE_SID :: SID_324_CLOCK_ENABLE_SID [00:00] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SID_SID_324_CLOCK_ENABLE_SID_MASK 0x00000001 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SID_SID_324_CLOCK_ENABLE_SID_SHIFT 0 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SID_SID_324_CLOCK_ENABLE_SID_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *AVD0_TOP_CLOCK_ENABLE_SID_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE_SID_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SID_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SID_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE_SID_STATUS :: SID_324_CLOCK_ENABLE_SID_STATUS [00:00] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SID_STATUS_SID_324_CLOCK_ENABLE_SID_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SID_STATUS_SID_324_CLOCK_ENABLE_SID_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *AVD0_TOP_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE_STATUS :: AVD0_SCB_CLOCK_ENABLE_STATUS [03:03] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_AVD0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_AVD0_SCB_CLOCK_ENABLE_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE_STATUS :: AVD0_CPU_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_AVD0_CPU_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_AVD0_CPU_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE_STATUS :: AVD0_CORE_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_AVD0_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_AVD0_CORE_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: AVD0_TOP_CLOCK_ENABLE_STATUS :: AVD0_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_AVD0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_AVD0_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *AVD0_TOP_MEMORY_STANDBY_ENABLE - Avd0 top memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: AVD0_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: AVD0_TOP_MEMORY_STANDBY_ENABLE :: AVD0_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_AVD0_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_AVD0_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_AVD0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *AVD0_TOP_OBSERVE_CLOCK - Avd0 top observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD0_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD0_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD0_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD0_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *AVD0_TOP_POWER_SWITCH_MEMORY - Avd0 top power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: AVD0_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: AVD0_TOP_POWER_SWITCH_MEMORY :: AVD0_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_AVD0_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_AVD0_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_AVD0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BCM_MIPS_TOP_CLOCK_ENABLE - Bcm mips top clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_SCB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_216_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *BCM_MIPS_TOP_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE_STATUS :: MIPS_SCB_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_MIPS_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_MIPS_SCB_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE_STATUS :: MIPS_216_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_MIPS_216_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_MIPS_216_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE_STATUS :: MIPS_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_MIPS_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_MIPS_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE - Bcm mips top memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: MIPS_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BCM_MIPS_TOP_OBSERVE_CLOCK - Bcm mips top observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BCM_MIPS_TOP_POWER_SWITCH_MEMORY - Bcm mips top power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: MIPS_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BVN_TOP_CLOCK_ENABLE - Bvn top clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: BVN_TOP_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: BVN_TOP_CLOCK_ENABLE :: BVN_SCB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: BVN_TOP_CLOCK_ENABLE :: BVN_216_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: BVN_TOP_CLOCK_ENABLE :: BVN_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *BVN_TOP_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: BVN_TOP_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: BVN_TOP_CLOCK_ENABLE_STATUS :: BVN_SCB_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_STATUS_BVN_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_STATUS_BVN_SCB_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: BVN_TOP_CLOCK_ENABLE_STATUS :: BVN_216_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_STATUS_BVN_216_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_STATUS_BVN_216_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: BVN_TOP_CLOCK_ENABLE_STATUS :: BVN_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_STATUS_BVN_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_STATUS_BVN_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *BVN_TOP_MEMORY_STANDBY_ENABLE - Bvn top memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: BVN_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: BVN_TOP_MEMORY_STANDBY_ENABLE :: BVN_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BVN_TOP_POWER_SWITCH_MEMORY - Bvn top power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: BVN_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: BVN_TOP_POWER_SWITCH_MEMORY :: BVN_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_AVS_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CLKGEN_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: DISABLE_AVS_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_AVS_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_AVS_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *CLKGEN_CLOCK_ENABLE - Clkgen clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: CLKGEN_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: CLKGEN_CLOCK_ENABLE :: CG_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_ENABLE_CG_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_ENABLE_CG_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_ENABLE_CG_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *CLKGEN_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: CLKGEN_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: CLKGEN_CLOCK_ENABLE_STATUS :: CG_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_ENABLE_STATUS_CG_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_ENABLE_STATUS_CG_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_CONTROL - Clock Monitor Control |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK 0x00000008 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT 3 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK 0x00000004 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT 2 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK 0x00000002 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT 1 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff |
| #define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 0xffffffff |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK 0xffffffff |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK 0x00000001 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT 0 |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff |
| #define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *CORE_XPT_CLOCK_DISABLE - Disable CORE_XPT's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CORE_XPT_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE_STATUS :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE_STATUS :: DISABLE_XPT_81_CLOCK_STATUS [04:04] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_81_CLOCK_STATUS_MASK 0x00000010 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_81_CLOCK_STATUS_SHIFT 4 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE_STATUS :: DISABLE_XPT_54_CLOCK_STATUS [03:03] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_54_CLOCK_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_54_CLOCK_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE_STATUS :: DISABLE_XPT_40P5_CLOCK_STATUS [02:02] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_40P5_CLOCK_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_40P5_CLOCK_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE_STATUS :: DISABLE_XPT_27_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_27_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_27_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_DISABLE_STATUS :: DISABLE_XPT_20P25_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_20P25_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_20P25_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *CORE_XPT_CLOCK_ENABLE - Core xpt clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_216_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *CORE_XPT_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_ENABLE_STATUS :: XPT_SCB_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_XPT_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_XPT_SCB_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_ENABLE_STATUS :: XPT_216_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_XPT_216_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_XPT_216_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: CORE_XPT_CLOCK_ENABLE_STATUS :: XPT_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *CORE_XPT_MEMORY_STANDBY_ENABLE - Core xpt memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: XPT_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CORE_XPT_OBSERVE_CLOCK - Core xpt observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CORE_XPT_POWER_SWITCH_MEMORY - Core xpt power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: XPT_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPUWRAP_3375_BCM_MIPS_OBSERVE_CLOCK - Cpuwrap 3375 bcm mips observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: CPUWRAP_3375_BCM_MIPS_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: CPUWRAP_3375_BCM_MIPS_OBSERVE_CLOCK :: SCPU_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_OBSERVE_CLOCK_SCPU_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_OBSERVE_CLOCK_SCPU_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_OBSERVE_CLOCK_SCPU_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CPUWRAP_3375_BCM_MIPS_OBSERVE_CLOCK :: SCPU_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_OBSERVE_CLOCK_SCPU_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_OBSERVE_CLOCK_SCPU_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_OBSERVE_CLOCK_SCPU_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CPUWRAP_3375_BCM_MIPS_OBSERVE_CLOCK :: SCPU_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_OBSERVE_CLOCK_SCPU_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_OBSERVE_CLOCK_SCPU_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_OBSERVE_CLOCK_SCPU_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DS_TOPA_CLOCK_ENABLE - Ds topa clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: DS_TOPA_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DS_TOPA_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DS_TOPA_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DS_TOPA_CLOCK_ENABLE :: DSTOP_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_DS_TOPA_CLOCK_ENABLE_DSTOP_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DS_TOPA_CLOCK_ENABLE_DSTOP_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_DS_TOPA_CLOCK_ENABLE_DSTOP_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DS_TOPA_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: DS_TOPA_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DS_TOPA_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DS_TOPA_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DS_TOPA_CLOCK_ENABLE_STATUS :: DSTOP_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_DS_TOPA_CLOCK_ENABLE_STATUS_DSTOP_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DS_TOPA_CLOCK_ENABLE_STATUS_DSTOP_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DS_TOPA_DATA - Ds topa data |
| ***************************************************************************/ |
| /* CLKGEN :: DS_TOPA_DATA :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_DS_TOPA_DATA_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_DS_TOPA_DATA_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: DS_TOPA_DATA :: DSTOP_POWER_SWITCH_MEMORY_3_DATA [12:11] */ |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_POWER_SWITCH_MEMORY_3_DATA_MASK 0x00001800 |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_POWER_SWITCH_MEMORY_3_DATA_SHIFT 11 |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_POWER_SWITCH_MEMORY_3_DATA_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DS_TOPA_DATA :: DSTOP_POWER_SWITCH_MEMORY_2_DATA [10:09] */ |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_POWER_SWITCH_MEMORY_2_DATA_MASK 0x00000600 |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_POWER_SWITCH_MEMORY_2_DATA_SHIFT 9 |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_POWER_SWITCH_MEMORY_2_DATA_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DS_TOPA_DATA :: DSTOP_POWER_SWITCH_MEMORY_1_DATA [08:07] */ |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_POWER_SWITCH_MEMORY_1_DATA_MASK 0x00000180 |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_POWER_SWITCH_MEMORY_1_DATA_SHIFT 7 |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_POWER_SWITCH_MEMORY_1_DATA_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DS_TOPA_DATA :: DSTOP_POWER_SWITCH_MEMORY_0_DATA [06:05] */ |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_POWER_SWITCH_MEMORY_0_DATA_MASK 0x00000060 |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_POWER_SWITCH_MEMORY_0_DATA_SHIFT 5 |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_POWER_SWITCH_MEMORY_0_DATA_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DS_TOPA_DATA :: DSTOP_MEMORY_STANDBY_ENABLE_OB_DATA [04:04] */ |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_MEMORY_STANDBY_ENABLE_OB_DATA_MASK 0x00000010 |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_MEMORY_STANDBY_ENABLE_OB_DATA_SHIFT 4 |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_MEMORY_STANDBY_ENABLE_OB_DATA_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DS_TOPA_DATA :: DSTOP_MEMORY_STANDBY_ENABLE_3_DATA [03:03] */ |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_MEMORY_STANDBY_ENABLE_3_DATA_MASK 0x00000008 |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_MEMORY_STANDBY_ENABLE_3_DATA_SHIFT 3 |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_MEMORY_STANDBY_ENABLE_3_DATA_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DS_TOPA_DATA :: DSTOP_MEMORY_STANDBY_ENABLE_2_DATA [02:02] */ |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_MEMORY_STANDBY_ENABLE_2_DATA_MASK 0x00000004 |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_MEMORY_STANDBY_ENABLE_2_DATA_SHIFT 2 |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_MEMORY_STANDBY_ENABLE_2_DATA_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DS_TOPA_DATA :: DSTOP_MEMORY_STANDBY_ENABLE_1_DATA [01:01] */ |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_MEMORY_STANDBY_ENABLE_1_DATA_MASK 0x00000002 |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_MEMORY_STANDBY_ENABLE_1_DATA_SHIFT 1 |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_MEMORY_STANDBY_ENABLE_1_DATA_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DS_TOPA_DATA :: DSTOP_MEMORY_STANDBY_ENABLE_0_DATA [00:00] */ |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_MEMORY_STANDBY_ENABLE_0_DATA_MASK 0x00000001 |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_MEMORY_STANDBY_ENABLE_0_DATA_SHIFT 0 |
| #define BCHP_CLKGEN_DS_TOPA_DATA_DSTOP_MEMORY_STANDBY_ENABLE_0_DATA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DS_TOPA_OBSERVE_CLOCK - Ds topa observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: DS_TOPA_OBSERVE_CLOCK :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DS_TOPA_OBSERVE_CLOCK_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DS_TOPA_OBSERVE_CLOCK_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DS_TOPA_OBSERVE_CLOCK :: DSTOP_ENABLE_OBSERVE_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_DS_TOPA_OBSERVE_CLOCK_DSTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_DS_TOPA_OBSERVE_CLOCK_DSTOP_ENABLE_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_DS_TOPA_OBSERVE_CLOCK_DSTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DS_WFE_TOP_CLOCK_ENABLE - Ds wfe top clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: DS_WFE_TOP_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DS_WFE_TOP_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DS_WFE_TOP_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DS_WFE_TOP_CLOCK_ENABLE :: DSWFE_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_DS_WFE_TOP_CLOCK_ENABLE_DSWFE_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DS_WFE_TOP_CLOCK_ENABLE_DSWFE_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_DS_WFE_TOP_CLOCK_ENABLE_DSWFE_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DS_WFE_TOP_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: DS_WFE_TOP_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DS_WFE_TOP_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DS_WFE_TOP_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DS_WFE_TOP_CLOCK_ENABLE_STATUS :: DSWFE_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_DS_WFE_TOP_CLOCK_ENABLE_STATUS_DSWFE_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DS_WFE_TOP_CLOCK_ENABLE_STATUS_DSWFE_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DS_WFE_TOP_DATA - Ds wfe top data |
| ***************************************************************************/ |
| /* CLKGEN :: DS_WFE_TOP_DATA :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_DS_WFE_TOP_DATA_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_DS_WFE_TOP_DATA_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: DS_WFE_TOP_DATA :: DSWFE_POWER_SWITCH_MEMORY_DATA [01:00] */ |
| #define BCHP_CLKGEN_DS_WFE_TOP_DATA_DSWFE_POWER_SWITCH_MEMORY_DATA_MASK 0x00000003 |
| #define BCHP_CLKGEN_DS_WFE_TOP_DATA_DSWFE_POWER_SWITCH_MEMORY_DATA_SHIFT 0 |
| #define BCHP_CLKGEN_DS_WFE_TOP_DATA_DSWFE_POWER_SWITCH_MEMORY_DATA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DS_WFE_TOP_OBSERVE_CLOCK - Ds wfe top observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: DS_WFE_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_DS_WFE_TOP_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_DS_WFE_TOP_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: DS_WFE_TOP_OBSERVE_CLOCK :: DSWFE_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_DS_WFE_TOP_OBSERVE_CLOCK_DSWFE_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_DS_WFE_TOP_OBSERVE_CLOCK_DSWFE_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_DS_WFE_TOP_OBSERVE_CLOCK_DSWFE_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DS_WFE_TOP_OBSERVE_CLOCK :: DSWFE_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_DS_WFE_TOP_OBSERVE_CLOCK_DSWFE_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_DS_WFE_TOP_OBSERVE_CLOCK_DSWFE_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_DS_WFE_TOP_OBSERVE_CLOCK_DSWFE_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DS_WFE_TOP_OBSERVE_CLOCK :: DSWFE_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_DS_WFE_TOP_OBSERVE_CLOCK_DSWFE_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_DS_WFE_TOP_OBSERVE_CLOCK_DSWFE_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_DS_WFE_TOP_OBSERVE_CLOCK_DSWFE_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE - Disable DUAL_GENET_TOP_DUAL_RGMII's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET_PLL_CLOCK [08:08] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET_PLL_CLOCK_MASK 0x00000100 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET_PLL_CLOCK_SHIFT 8 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET_PLL_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK [07:07] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_MASK 0x00000080 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_SHIFT 7 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_PM_CLOCK [06:06] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_MASK 0x00000040 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_SHIFT 6 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_FAST_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET1_ALWAYSON_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_ALWAYSON_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_ALWAYSON_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_ALWAYSON_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [03:03] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000008 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 3 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_FAST_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET0_ALWAYSON_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_ALWAYSON_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_ALWAYSON_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_ALWAYSON_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS :: DISABLE_GENET_PLL_CLOCK_STATUS [08:08] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS_DISABLE_GENET_PLL_CLOCK_STATUS_MASK 0x00000100 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS_DISABLE_GENET_PLL_CLOCK_STATUS_SHIFT 8 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK_STATUS [07:07] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_STATUS_MASK 0x00000080 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_STATUS_SHIFT 7 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_SYSTEM_PM_CLOCK_STATUS [06:06] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_PM_CLOCK_STATUS_MASK 0x00000040 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_PM_CLOCK_STATUS_SHIFT 6 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_SYSTEM_FAST_CLOCK_STATUS [05:05] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_FAST_CLOCK_STATUS_MASK 0x00000020 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_FAST_CLOCK_STATUS_SHIFT 5 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_ALWAYSON_CLOCK_STATUS [04:04] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS_DISABLE_GENET1_ALWAYSON_CLOCK_STATUS_MASK 0x00000010 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS_DISABLE_GENET1_ALWAYSON_CLOCK_STATUS_SHIFT 4 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS [03:03] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS [02:02] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_ALWAYSON_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS_DISABLE_GENET0_ALWAYSON_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_STATUS_DISABLE_GENET0_ALWAYSON_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE - Dual genet top dual rgmii clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: reserved0 [31:17] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_reserved0_MASK 0xfffe0000 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_reserved0_SHIFT 17 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [16:16] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00010000 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 16 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET_108_CLOCK_ENABLE [15:15] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_MASK 0x00008000 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_SHIFT 15 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE [14:14] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00004000 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 14 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET1_L2INTR_CLOCK_ENABLE [12:12] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_MASK 0x00001000 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_SHIFT 12 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET1_HFB_CLOCK_ENABLE [11:11] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_MASK 0x00000800 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_SHIFT 11 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET1_GMII_CLOCK_ENABLE [10:10] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_MASK 0x00000400 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_SHIFT 10 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET1_EEE_CLOCK_ENABLE [09:09] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_MASK 0x00000200 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_SHIFT 9 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET1_CLK_250_CLOCK_ENABLE [08:08] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_MASK 0x00000100 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_SHIFT 8 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE [07:07] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00000080 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 7 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE [06:06] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00000040 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 6 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET0_SCB_CLOCK_ENABLE [05:05] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_SCB_CLOCK_ENABLE_MASK 0x00000020 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_SCB_CLOCK_ENABLE_SHIFT 5 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET0_L2INTR_CLOCK_ENABLE [04:04] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_MASK 0x00000010 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_SHIFT 4 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET0_HFB_CLOCK_ENABLE [03:03] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_MASK 0x00000008 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_SHIFT 3 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET0_GMII_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET0_EEE_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET0_CLK_250_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1 - Dual genet top dual rgmii clock enable genet1 |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1 :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1 :: GENET_108_CLOCK_ENABLE_GENET1 [01:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_GENET_108_CLOCK_ENABLE_GENET1_MASK 0x00000002 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_GENET_108_CLOCK_ENABLE_GENET1_SHIFT 1 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_GENET_108_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1 :: GENET1_SCB_CLOCK_ENABLE_GENET1 [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_GENET1_SCB_CLOCK_ENABLE_GENET1_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_GENET1_SCB_CLOCK_ENABLE_GENET1_SHIFT 0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_GENET1_SCB_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_STATUS :: GENET_108_CLOCK_ENABLE_GENET1_STATUS [01:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_STATUS_GENET_108_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_STATUS_GENET_108_CLOCK_ENABLE_GENET1_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_STATUS :: GENET1_SCB_CLOCK_ENABLE_GENET1_STATUS [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_STATUS_GENET1_SCB_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_STATUS_GENET1_SCB_CLOCK_ENABLE_GENET1_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS :: reserved0 [31:17] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffe0000 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_reserved0_SHIFT 17 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS :: GENET_SCB_CLOCK_ENABLE_STATUS [16:16] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET_SCB_CLOCK_ENABLE_STATUS_MASK 0x00010000 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET_SCB_CLOCK_ENABLE_STATUS_SHIFT 16 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS :: GENET_108_CLOCK_ENABLE_STATUS [15:15] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET_108_CLOCK_ENABLE_STATUS_MASK 0x00008000 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET_108_CLOCK_ENABLE_STATUS_SHIFT 15 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_STATUS [14:14] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_STATUS_MASK 0x00004000 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_STATUS_SHIFT 14 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_STATUS [13:13] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_STATUS_MASK 0x00002000 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_STATUS_SHIFT 13 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS :: GENET1_L2INTR_CLOCK_ENABLE_STATUS [12:12] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET1_L2INTR_CLOCK_ENABLE_STATUS_MASK 0x00001000 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET1_L2INTR_CLOCK_ENABLE_STATUS_SHIFT 12 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS :: GENET1_HFB_CLOCK_ENABLE_STATUS [11:11] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET1_HFB_CLOCK_ENABLE_STATUS_MASK 0x00000800 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET1_HFB_CLOCK_ENABLE_STATUS_SHIFT 11 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS :: GENET1_GMII_CLOCK_ENABLE_STATUS [10:10] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET1_GMII_CLOCK_ENABLE_STATUS_MASK 0x00000400 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET1_GMII_CLOCK_ENABLE_STATUS_SHIFT 10 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS :: GENET1_EEE_CLOCK_ENABLE_STATUS [09:09] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET1_EEE_CLOCK_ENABLE_STATUS_MASK 0x00000200 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET1_EEE_CLOCK_ENABLE_STATUS_SHIFT 9 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS :: GENET1_CLK_250_CLOCK_ENABLE_STATUS [08:08] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET1_CLK_250_CLOCK_ENABLE_STATUS_MASK 0x00000100 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET1_CLK_250_CLOCK_ENABLE_STATUS_SHIFT 8 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_STATUS [07:07] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_STATUS_MASK 0x00000080 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_STATUS_SHIFT 7 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_STATUS [06:06] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_STATUS_MASK 0x00000040 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_STATUS_SHIFT 6 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS :: GENET0_SCB_CLOCK_ENABLE_STATUS [05:05] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000020 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET0_SCB_CLOCK_ENABLE_STATUS_SHIFT 5 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS :: GENET0_L2INTR_CLOCK_ENABLE_STATUS [04:04] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET0_L2INTR_CLOCK_ENABLE_STATUS_MASK 0x00000010 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET0_L2INTR_CLOCK_ENABLE_STATUS_SHIFT 4 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS :: GENET0_HFB_CLOCK_ENABLE_STATUS [03:03] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET0_HFB_CLOCK_ENABLE_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET0_HFB_CLOCK_ENABLE_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS :: GENET0_GMII_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET0_GMII_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET0_GMII_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS :: GENET0_EEE_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET0_EEE_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET0_EEE_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS :: GENET0_CLK_250_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET0_CLK_250_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_STATUS_GENET0_CLK_250_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT - Dual genet top dual rgmii clock select |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT :: GENET1_GMII_CLOCK_SELECT [03:03] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_MASK 0x00000008 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_SHIFT 3 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT :: GENET1_CLOCK_SELECT [02:02] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET1_CLOCK_SELECT_MASK 0x00000004 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET1_CLOCK_SELECT_SHIFT 2 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET1_CLOCK_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT :: GENET0_GMII_CLOCK_SELECT [01:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_MASK 0x00000002 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_SHIFT 1 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT :: GENET0_CLOCK_SELECT [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET0_CLOCK_SELECT_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET0_CLOCK_SELECT_SHIFT 0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET0_CLOCK_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE_A - Dual genet top dual rgmii memory standby enable a |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE_A :: GENET0_MEMORY_STANDBY_ENABLE_A [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_SHIFT 0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK - Dual genet top dual rgmii observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK :: GENET_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK :: GENET_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK :: GENET_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY_A - Dual genet top dual rgmii power switch memory a |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY_A :: GENET0_POWER_SWITCH_MEMORY_A [01:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_MASK 0x00000003 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_SHIFT 0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DVP_HT_CLOCK_DISABLE - Disable DVP_HT's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DVP_HT_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DVP_HT_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DVP_HT_CLOCK_DISABLE_STATUS :: DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DVP_HT_CLOCK_ENABLE - Dvp ht clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_CLOCK_ENABLE :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: DVP_HT_CLOCK_ENABLE :: VEC_IF_216_CLOCK_ENABLE [03:03] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_VEC_IF_216_CLOCK_ENABLE_MASK 0x00000008 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_VEC_IF_216_CLOCK_ENABLE_SHIFT 3 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_VEC_IF_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_MAX_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_MAX_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_MAX_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_MAX_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_216_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DVP_HT_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: DVP_HT_CLOCK_ENABLE_STATUS :: VEC_IF_216_CLOCK_ENABLE_STATUS [03:03] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_VEC_IF_216_CLOCK_ENABLE_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_VEC_IF_216_CLOCK_ENABLE_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: DVP_HT_CLOCK_ENABLE_STATUS :: DVPHT_MAX_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_DVPHT_MAX_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_DVPHT_MAX_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: DVP_HT_CLOCK_ENABLE_STATUS :: DVPHT_216_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_DVPHT_216_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_DVPHT_216_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: DVP_HT_CLOCK_ENABLE_STATUS :: DVPHT_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DVP_HT_MEMORY_STANDBY_ENABLE - Dvp ht memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: DVPHT_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DVP_HT_OBSERVE_CLOCK - Dvp ht observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DVP_HT_POWER_SWITCH_MEMORY - Dvp ht power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: DVPHT_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GRAPHICS_CLOCK_ENABLE - Graphics clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *GRAPHICS_CLOCK_ENABLE_M2MC - Graphics clock enable m2mc |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE_M2MC :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE_M2MC :: M2MC_SCB_CLOCK_ENABLE_M2MC [01:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_M2MC_SCB_CLOCK_ENABLE_M2MC_MASK 0x00000002 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_M2MC_SCB_CLOCK_ENABLE_M2MC_SHIFT 1 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_M2MC_SCB_CLOCK_ENABLE_M2MC_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE_M2MC :: M2MC_CORE_CLOCK_ENABLE_M2MC [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_M2MC_CORE_CLOCK_ENABLE_M2MC_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_M2MC_CORE_CLOCK_ENABLE_M2MC_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_M2MC_CORE_CLOCK_ENABLE_M2MC_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *GRAPHICS_CLOCK_ENABLE_M2MC_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE_M2MC_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE_M2MC_STATUS :: M2MC_SCB_CLOCK_ENABLE_M2MC_STATUS [01:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_STATUS_M2MC_SCB_CLOCK_ENABLE_M2MC_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_STATUS_M2MC_SCB_CLOCK_ENABLE_M2MC_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE_M2MC_STATUS :: M2MC_CORE_CLOCK_ENABLE_M2MC_STATUS [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_STATUS_M2MC_CORE_CLOCK_ENABLE_M2MC_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_STATUS_M2MC_CORE_CLOCK_ENABLE_M2MC_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *GRAPHICS_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE_STATUS :: GFX_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_STATUS_GFX_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_STATUS_GFX_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *GRAPHICS_CLOCK_ENABLE_V3D - Graphics clock enable v3d |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE_V3D :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE_V3D :: V3D_SCB_CLOCK_ENABLE_V3D [01:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_V3D_SCB_CLOCK_ENABLE_V3D_MASK 0x00000002 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_V3D_SCB_CLOCK_ENABLE_V3D_SHIFT 1 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_V3D_SCB_CLOCK_ENABLE_V3D_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE_V3D :: V3D_CORE_CLOCK_ENABLE_V3D [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_V3D_CORE_CLOCK_ENABLE_V3D_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_V3D_CORE_CLOCK_ENABLE_V3D_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_V3D_CORE_CLOCK_ENABLE_V3D_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *GRAPHICS_CLOCK_ENABLE_V3D_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE_V3D_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE_V3D_STATUS :: V3D_SCB_CLOCK_ENABLE_V3D_STATUS [01:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_STATUS_V3D_SCB_CLOCK_ENABLE_V3D_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_STATUS_V3D_SCB_CLOCK_ENABLE_V3D_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: GRAPHICS_CLOCK_ENABLE_V3D_STATUS :: V3D_CORE_CLOCK_ENABLE_V3D_STATUS [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_STATUS_V3D_CORE_CLOCK_ENABLE_V3D_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_STATUS_V3D_CORE_CLOCK_ENABLE_V3D_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC - Graphics memory standby enable m2mc |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC :: M2MC_MEMORY_STANDBY_ENABLE_M2MC [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC_M2MC_MEMORY_STANDBY_ENABLE_M2MC_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC_M2MC_MEMORY_STANDBY_ENABLE_M2MC_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC_M2MC_MEMORY_STANDBY_ENABLE_M2MC_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GRAPHICS_MEMORY_STANDBY_ENABLE_V3D - Graphics memory standby enable v3d |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE_V3D :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_V3D_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_V3D_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE_V3D :: V3D_MEMORY_STANDBY_ENABLE_V3D [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_V3D_V3D_MEMORY_STANDBY_ENABLE_V3D_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_V3D_V3D_MEMORY_STANDBY_ENABLE_V3D_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_V3D_V3D_MEMORY_STANDBY_ENABLE_V3D_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GRAPHICS_OBSERVE_CLOCK - Graphics observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GRAPHICS_POWER_SWITCH_MEMORY_M2MC - Graphics power switch memory m2mc |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY_M2MC :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_M2MC_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_M2MC_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY_M2MC :: GFX_POWER_SWITCH_MEMORY_M2MC [01:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_M2MC_GFX_POWER_SWITCH_MEMORY_M2MC_MASK 0x00000003 |
| #define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_M2MC_GFX_POWER_SWITCH_MEMORY_M2MC_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_M2MC_GFX_POWER_SWITCH_MEMORY_M2MC_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GRAPHICS_POWER_SWITCH_MEMORY_V3D - Graphics power switch memory v3d |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY_V3D :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_V3D_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_V3D_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY_V3D :: GFX_POWER_SWITCH_MEMORY_V3D [01:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_V3D_GFX_POWER_SWITCH_MEMORY_V3D_MASK 0x00000003 |
| #define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_V3D_GFX_POWER_SWITCH_MEMORY_V3D_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_V3D_GFX_POWER_SWITCH_MEMORY_V3D_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *HIF_CLOCK_DISABLE - Disable HIF's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_CLOCK_DISABLE :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [03:03] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK 0x00000008 |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT 3 |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_SDIO_EMMC_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CARD_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_EBI_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *HIF_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_CLOCK_DISABLE_STATUS :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_STATUS_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: HIF_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SPI_CLOCK_STATUS [03:03] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: HIF_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS [02:02] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: HIF_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SDIO_CARD_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: HIF_CLOCK_DISABLE_STATUS :: DISABLE_HIF_EBI_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_STATUS_DISABLE_HIF_EBI_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_HIF_CLOCK_DISABLE_STATUS_DISABLE_HIF_EBI_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *HIF_CLOCK_ENABLE - Hif clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_216_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *HIF_CLOCK_ENABLE_SDIO - Hif clock enable sdio |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_CLOCK_ENABLE_SDIO :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: HIF_CLOCK_ENABLE_SDIO :: SDIO_SCB_CLOCK_ENABLE_SDIO [01:01] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_SDIO_SCB_CLOCK_ENABLE_SDIO_MASK 0x00000002 |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_SDIO_SCB_CLOCK_ENABLE_SDIO_SHIFT 1 |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_SDIO_SCB_CLOCK_ENABLE_SDIO_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: HIF_CLOCK_ENABLE_SDIO :: SDIO_216_CLOCK_ENABLE_SDIO [00:00] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_SDIO_216_CLOCK_ENABLE_SDIO_MASK 0x00000001 |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_SDIO_216_CLOCK_ENABLE_SDIO_SHIFT 0 |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_SDIO_216_CLOCK_ENABLE_SDIO_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *HIF_CLOCK_ENABLE_SDIO_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_CLOCK_ENABLE_SDIO_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: HIF_CLOCK_ENABLE_SDIO_STATUS :: SDIO_SCB_CLOCK_ENABLE_SDIO_STATUS [01:01] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_STATUS_SDIO_SCB_CLOCK_ENABLE_SDIO_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_STATUS_SDIO_SCB_CLOCK_ENABLE_SDIO_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: HIF_CLOCK_ENABLE_SDIO_STATUS :: SDIO_216_CLOCK_ENABLE_SDIO_STATUS [00:00] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_STATUS_SDIO_216_CLOCK_ENABLE_SDIO_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_STATUS_SDIO_216_CLOCK_ENABLE_SDIO_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *HIF_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: HIF_CLOCK_ENABLE_STATUS :: HIF_216_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_STATUS_HIF_216_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_STATUS_HIF_216_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: HIF_CLOCK_ENABLE_STATUS :: HIF_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_STATUS_HIF_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_HIF_CLOCK_ENABLE_STATUS_HIF_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *HIF_MEMORY_STANDBY_ENABLE - Hif memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE :: HIF_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *HIF_MEMORY_STANDBY_ENABLE_SDIO - Hif memory standby enable sdio |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE_SDIO :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SDIO_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SDIO_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE_SDIO :: SDIO_MEMORY_STANDBY_ENABLE_SDIO [00:00] */ |
| #define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SDIO_SDIO_MEMORY_STANDBY_ENABLE_SDIO_MASK 0x00000001 |
| #define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SDIO_SDIO_MEMORY_STANDBY_ENABLE_SDIO_SHIFT 0 |
| #define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SDIO_SDIO_MEMORY_STANDBY_ENABLE_SDIO_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *HIF_POWER_SWITCH_MEMORY - Hif power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: HIF_POWER_SWITCH_MEMORY :: HIF_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *HIF_POWER_SWITCH_MEMORY_SDIO - Hif power switch memory sdio |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_POWER_SWITCH_MEMORY_SDIO :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SDIO_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SDIO_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: HIF_POWER_SWITCH_MEMORY_SDIO :: SDIO_POWER_SWITCH_MEMORY_SDIO [01:00] */ |
| #define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SDIO_SDIO_POWER_SWITCH_MEMORY_SDIO_MASK 0x00000003 |
| #define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SDIO_SDIO_POWER_SWITCH_MEMORY_SDIO_SHIFT 0 |
| #define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SDIO_SDIO_POWER_SWITCH_MEMORY_SDIO_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *INTERNAL_MUX_SELECT - Mux selects for Internal clocks |
| ***************************************************************************/ |
| /* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:08] */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK 0xffffff00 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT 8 |
| |
| /* CLKGEN :: INTERNAL_MUX_SELECT :: SID_CORE_CLOCK [07:07] */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_SID_CORE_CLOCK_MASK 0x00000080 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_SID_CORE_CLOCK_SHIFT 7 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_SID_CORE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [06:06] */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x00000040 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 6 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: INTERNAL_MUX_SELECT :: reserved1 [04:03] */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved1_MASK 0x00000018 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved1_SHIFT 3 |
| |
| /* CLKGEN :: INTERNAL_MUX_SELECT :: GFX_M2MC_CORE_CLOCK [02:01] */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_MASK 0x00000006 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: INTERNAL_MUX_SELECT :: CPU_216_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_CPU_216_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_CPU_216_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_CPU_216_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *LEAP_TOP_CLOCK_DISABLE - Disable LEAP_TOP's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: LEAP_TOP_CLOCK_DISABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_DISABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_DISABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: LEAP_TOP_CLOCK_DISABLE :: DISABLE_LEAP_27_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_DISABLE_DISABLE_LEAP_27_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_DISABLE_DISABLE_LEAP_27_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_DISABLE_DISABLE_LEAP_27_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: LEAP_TOP_CLOCK_DISABLE :: DISABLE_CPU_216_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_DISABLE_DISABLE_CPU_216_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_DISABLE_DISABLE_CPU_216_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_DISABLE_DISABLE_CPU_216_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *LEAP_TOP_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: LEAP_TOP_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: LEAP_TOP_CLOCK_DISABLE_STATUS :: DISABLE_LEAP_27_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_DISABLE_STATUS_DISABLE_LEAP_27_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_DISABLE_STATUS_DISABLE_LEAP_27_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: LEAP_TOP_CLOCK_DISABLE_STATUS :: DISABLE_CPU_216_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_DISABLE_STATUS_DISABLE_CPU_216_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_DISABLE_STATUS_DISABLE_CPU_216_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LEAP_TOP_CLOCK_ENABLE - Leap top clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: LEAP_TOP_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: LEAP_TOP_CLOCK_ENABLE :: LEAP_216_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_ENABLE_LEAP_216_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_ENABLE_LEAP_216_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_ENABLE_LEAP_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: LEAP_TOP_CLOCK_ENABLE :: LEAP_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_ENABLE_LEAP_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_ENABLE_LEAP_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_ENABLE_LEAP_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *LEAP_TOP_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: LEAP_TOP_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: LEAP_TOP_CLOCK_ENABLE_STATUS :: LEAP_216_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_ENABLE_STATUS_LEAP_216_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_ENABLE_STATUS_LEAP_216_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: LEAP_TOP_CLOCK_ENABLE_STATUS :: LEAP_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_ENABLE_STATUS_LEAP_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_LEAP_TOP_CLOCK_ENABLE_STATUS_LEAP_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LEAP_TOP_DATA - Leap top data |
| ***************************************************************************/ |
| /* CLKGEN :: LEAP_TOP_DATA :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_LEAP_TOP_DATA_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_LEAP_TOP_DATA_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: LEAP_TOP_DATA :: LEAP_POWER_SWITCH_MEMORY_DATA [02:01] */ |
| #define BCHP_CLKGEN_LEAP_TOP_DATA_LEAP_POWER_SWITCH_MEMORY_DATA_MASK 0x00000006 |
| #define BCHP_CLKGEN_LEAP_TOP_DATA_LEAP_POWER_SWITCH_MEMORY_DATA_SHIFT 1 |
| #define BCHP_CLKGEN_LEAP_TOP_DATA_LEAP_POWER_SWITCH_MEMORY_DATA_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: LEAP_TOP_DATA :: LEAP_MEMORY_STANDBY_ENABLE_DATA [00:00] */ |
| #define BCHP_CLKGEN_LEAP_TOP_DATA_LEAP_MEMORY_STANDBY_ENABLE_DATA_MASK 0x00000001 |
| #define BCHP_CLKGEN_LEAP_TOP_DATA_LEAP_MEMORY_STANDBY_ENABLE_DATA_SHIFT 0 |
| #define BCHP_CLKGEN_LEAP_TOP_DATA_LEAP_MEMORY_STANDBY_ENABLE_DATA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEMSYS_CLOCK_ENABLE - Memsys clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: MEMSYS_CLOCK_ENABLE :: DDR1_SCB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: MEMSYS_CLOCK_ENABLE :: DDR1_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *MEMSYS_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: MEMSYS_CLOCK_ENABLE_STATUS :: DDR1_SCB_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_STATUS_DDR1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_STATUS_DDR1_SCB_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: MEMSYS_CLOCK_ENABLE_STATUS :: DDR1_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_STATUS_DDR1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_STATUS_DDR1_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *MEMSYS_MEMORY_STANDBY_ENABLE - Memsys memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_MEMSYS_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_MEMSYS_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: MEMSYS_MEMORY_STANDBY_ENABLE :: DDR1_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_MEMSYS_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMSYS_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_MEMSYS_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEMSYS_OBSERVE_CLOCK - Memsys observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: MEMSYS_OBSERVE_CLOCK :: MEMSYS_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MEMSYS_OBSERVE_CLOCK :: MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MEMSYS_OBSERVE_CLOCK :: MEMSYS_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEMSYS_POWER_SWITCH_MEMORY - Memsys power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_MEMSYS_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_MEMSYS_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: MEMSYS_POWER_SWITCH_MEMORY :: DDR1_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_MEMSYS_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_MEMSYS_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_MEMSYS_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEMSYS_STATUS - Memsys status |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_MEMSYS_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_MEMSYS_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: MEMSYS_STATUS :: MEMSYS_PLL_LOCKED_STATUS [00:00] */ |
| #define BCHP_CLKGEN_MEMSYS_STATUS_MEMSYS_PLL_LOCKED_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMSYS_STATUS_MEMSYS_PLL_LOCKED_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PAD_CLK_OBSRV0_OBSERVATION - Select observation clk |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: reserved0 [31:08] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_MASK 0xffffff00 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_SHIFT 8 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PAD_CLK_OBSRV1_OBSERVATION - Select observation clk |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: reserved0 [31:08] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_MASK 0xffffff00 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_SHIFT 8 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PAD_CLK_OBSRV2_OBSERVATION - Select observation clk |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: reserved0 [31:08] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_MASK 0xffffff00 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_SHIFT 8 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PAD_CLK_OBSRV3_OBSERVATION - Select observation clk |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: reserved0 [31:08] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_MASK 0xffffff00 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_SHIFT 8 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PAD_CLOCK_DISABLE - Disable PAD's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK27_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PAD_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CLK27_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK27_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK27_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PAD_MUX_SELECT - Mux selects for Pad clocks |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK27_CLOCK [02:00] */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000007 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_RESET_STATUS - PLL_AUDIO0 Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_RESET_STATUS - PLL_AUDIO1 Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_RESET_STATUS - PLL_AVD Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MIPS_GLITCHLESS_SWITCH_REQUEST - PLL_MIPS Glitchless Clock Switching |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: TRANSACTION_WAIT [08:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_DEFAULT 0x0000001f |
| |
| /* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: PLL_BYPASS_REQUEST [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MIPS_GLITCHLESS_SWITCH_STATUS - PLL_MIPS Glitchless Switching |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_STATUS :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_STATUS :: PLL_BYPASS_STATUS [03:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_MASK 0x0000000f |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_RESET_STATUS - PLL_MIPS Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_RESET_STATUS - PLL_SC Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_RESET_STATUS - PLL_SYS1 Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_RESET_STATUS - PLL_VCXO Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PM_CLOCK_216_ALIVE_SEL - Select clocks that can stay alive during power management standby mode. |
| ***************************************************************************/ |
| /* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */ |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_MASK 0x00000001 |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT 0 |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode |
| ***************************************************************************/ |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys_PLL [02:02] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_MASK 0x00000004 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_SHIFT 2 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [01:01] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK 0x00000002 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT 1 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_MIPS [00:00] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_SHIFT 0 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PM_PLL_LDO_POWERUP - Power management LDO PLL |
| ***************************************************************************/ |
| /* CLKGEN :: PM_PLL_LDO_POWERUP :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_AVD [00:00] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_MASK 0x00000001 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_SHIFT 0 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PM_PLL_LDO_POWERUP_SM - Power management LDO PLL state machine |
| ***************************************************************************/ |
| /* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: reserved0 [31:27] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_MASK 0xf8000000 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_SHIFT 27 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_POWERUP_WAIT_TIME [26:14] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_MASK 0x07ffc000 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_SHIFT 14 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_DEFAULT 0x00001518 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_CLK_STOP_WAIT_TIME [13:01] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_MASK 0x00003ffe |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_SHIFT 1 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_DEFAULT 0x000000c8 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: GISB_OVERRIDE_SM [00:00] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_MASK 0x00000001 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_SHIFT 0 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_CLOCK_ENABLE - Raaga dsp top clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_SCB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_DSP_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS :: RAAGA_SCB_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS_RAAGA_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS_RAAGA_SCB_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS :: RAAGA_DSP_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS_RAAGA_DSP_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS_RAAGA_DSP_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS :: RAAGA_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS_RAAGA_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_STATUS_RAAGA_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE - Raaga dsp top memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE :: RAAGA_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGA_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGA_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_OBSERVE_CLOCK - Raaga dsp top observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: RAAGA_ENABLE_OBSERVE_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: RAAGAS_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGAS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGAS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGAS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_POWER_SWITCH_MEMORY - Raaga dsp top power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_POWER_SWITCH_MEMORY :: RAAGA_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RFM_TOP_CLOCK_ENABLE - Rfm top clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: RFM_TOP_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: RFM_TOP_CLOCK_ENABLE :: RFM_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *RFM_TOP_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: RFM_TOP_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: RFM_TOP_CLOCK_ENABLE_STATUS :: RFM_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_STATUS_RFM_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_STATUS_RFM_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *RFM_TOP_MEMORY_STANDBY_ENABLE - Rfm top memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: RFM_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: RFM_TOP_MEMORY_STANDBY_ENABLE :: RFMA_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *RFM_TOP_OBSERVE_CLOCK - Rfm top observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RFM_TOP_POWER_SWITCH_MEMORY - Rfm top power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: RFM_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: RFM_TOP_POWER_SWITCH_MEMORY :: RFM_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SATA3_TOP_CLOCK_DISABLE - Disable SATA3_TOP's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: SATA3_TOP_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SATA3_TOP_CLOCK_DISABLE :: DISABLE_SATA_LV_CLK_30 [00:00] */ |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_LV_CLK_30_MASK 0x00000001 |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_LV_CLK_30_SHIFT 0 |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_LV_CLK_30_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SATA3_TOP_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: SATA3_TOP_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SATA3_TOP_CLOCK_DISABLE_STATUS :: DISABLE_SATA_LV_CLK_30_STATUS [00:00] */ |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_STATUS_DISABLE_SATA_LV_CLK_30_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_STATUS_DISABLE_SATA_LV_CLK_30_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *SATA3_TOP_CLOCK_ENABLE - Sata3 top clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: SATA3_SCB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: SATA3_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SATA3_TOP_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: SATA3_TOP_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SATA3_TOP_CLOCK_ENABLE_STATUS :: SATA3_SCB_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_STATUS_SATA3_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_STATUS_SATA3_SCB_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: SATA3_TOP_CLOCK_ENABLE_STATUS :: SATA3_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_STATUS_SATA3_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_STATUS_SATA3_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *SATA3_TOP_CLOCK_SELECT - Sata3 top clock select |
| ***************************************************************************/ |
| /* CLKGEN :: SATA3_TOP_CLOCK_SELECT :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_SELECT_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_SELECT_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SATA3_TOP_CLOCK_SELECT :: SATA3_REF_CLOCK_SELECT [00:00] */ |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_MASK 0x00000001 |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_SHIFT 0 |
| #define BCHP_CLKGEN_SATA3_TOP_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SATA3_TOP_MEMORY_STANDBY_ENABLE - Sata3 top memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: SATA3_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SATA3_TOP_MEMORY_STANDBY_ENABLE :: SATA3_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SATA3_TOP_OBSERVE_CLOCK - Sata3 top observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: SATA3_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: SATA3_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SATA3_TOP_POWER_SWITCH_MEMORY - Sata3 top power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: SATA3_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SATA3_TOP_POWER_SWITCH_MEMORY :: SATA3_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SECTOP_CLOCK_ENABLE_M2MDMA - Sectop clock enable m2mdma |
| ***************************************************************************/ |
| /* CLKGEN :: SECTOP_CLOCK_ENABLE_M2MDMA :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SECTOP_CLOCK_ENABLE_M2MDMA :: M2M_DMA_SCB_CLOCK_ENABLE_M2MDMA [00:00] */ |
| #define BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA_M2M_DMA_SCB_CLOCK_ENABLE_M2MDMA_MASK 0x00000001 |
| #define BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA_M2M_DMA_SCB_CLOCK_ENABLE_M2MDMA_SHIFT 0 |
| #define BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA_M2M_DMA_SCB_CLOCK_ENABLE_M2MDMA_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SECTOP_CLOCK_ENABLE_M2MDMA_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: SECTOP_CLOCK_ENABLE_M2MDMA_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SECTOP_CLOCK_ENABLE_M2MDMA_STATUS :: M2M_DMA_SCB_CLOCK_ENABLE_M2MDMA_STATUS [00:00] */ |
| #define BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA_STATUS_M2M_DMA_SCB_CLOCK_ENABLE_M2MDMA_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA_STATUS_M2M_DMA_SCB_CLOCK_ENABLE_M2MDMA_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *SECTOP_OBSERVE_CLOCK - Sectop observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: SECTOP_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: SECTOP_OBSERVE_CLOCK :: SEC_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK_SEC_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK_SEC_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK_SEC_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SECTOP_OBSERVE_CLOCK :: SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SECTOP_OBSERVE_CLOCK :: SECTOP_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks |
| ***************************************************************************/ |
| /* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: SMARTCARD_MUX_SELECT :: SC_OUT_CLOCK [10:08] */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_MASK 0x00000700 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_SHIFT 8 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [07:05] */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK 0x000000e0 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [04:02] */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK 0x0000001c |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SMARTCARD_MUX_SELECT :: PLLSC_REFERENCE_CLOCK [01:00] */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_MASK 0x00000003 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SPARE - Spares |
| ***************************************************************************/ |
| /* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */ |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK 0xfffff000 |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT 12 |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */ |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK 0x00000fff |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT 0 |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SYS_AON_OBSERVE_CLOCK - Sys aon observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SYS_CTRL_CLOCK_DISABLE - Disable SYS_CTRL's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [03:03] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000008 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 3 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SYS_CTRL_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_CLOCK_DISABLE_STATUS :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: SYS_CTRL_CLOCK_DISABLE_STATUS :: DISABLE_SYSCTRL_UPG_CLOCK_STATUS [03:03] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: SYS_CTRL_CLOCK_DISABLE_STATUS :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK_STATUS [02:02] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: SYS_CTRL_CLOCK_DISABLE_STATUS :: DISABLE_SC1_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: SYS_CTRL_CLOCK_DISABLE_STATUS :: DISABLE_SC0_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *SYS_CTRL_CLOCK_ENABLE - Sys ctrl clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: SYS_CTRL_SCB_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SYS_CTRL_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SYS_CTRL_CLOCK_ENABLE_STATUS :: SYS_CTRL_SCB_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_STATUS_SYS_CTRL_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_STATUS_SYS_CTRL_SCB_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *SYS_CTRL_MEMORY_STANDBY_ENABLE - Sys ctrl memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: SYS_CTRL_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SYS_CTRL_OBSERVE_CLOCK - Sys ctrl observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SYS_CTRL_POWER_SWITCH_MEMORY - Sys ctrl power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SYS_CTRL_POWER_SWITCH_MEMORY :: SYS_CTRL_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TESTPORT - Special Testport Controls |
| ***************************************************************************/ |
| /* CLKGEN :: TESTPORT :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_TESTPORT_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [02:00] */ |
| #define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK 0x00000007 |
| #define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT 0 |
| #define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *USB_CLOCK_DISABLE - Disable USB's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: USB_CLOCK_DISABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB_CLOCK_DISABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB_CLOCK_DISABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB_CLOCK_DISABLE :: DISABLE_USB_54_MDIO_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: USB_CLOCK_DISABLE :: DISABLE_USB_27_FREERUN_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_27_FREERUN_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_27_FREERUN_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_27_FREERUN_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *USB_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: USB_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB_CLOCK_DISABLE_STATUS :: DISABLE_USB_54_MDIO_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_USB_CLOCK_DISABLE_STATUS_DISABLE_USB_54_MDIO_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_USB_CLOCK_DISABLE_STATUS_DISABLE_USB_54_MDIO_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: USB_CLOCK_DISABLE_STATUS :: DISABLE_USB_27_FREERUN_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_USB_CLOCK_DISABLE_STATUS_DISABLE_USB_27_FREERUN_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB_CLOCK_DISABLE_STATUS_DISABLE_USB_27_FREERUN_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *USB_CLOCK_ENABLE - Usb clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: USB_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: USB_CLOCK_ENABLE :: USB0_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *USB_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: USB_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB_CLOCK_ENABLE_STATUS :: USB0_SCB_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: USB_CLOCK_ENABLE_STATUS :: USB0_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_STATUS_USB0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB_CLOCK_ENABLE_STATUS_USB0_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *USB_MEMORY_STANDBY_ENABLE - Usb memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: USB_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: USB_MEMORY_STANDBY_ENABLE :: USB0_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *USB_OBSERVE_CLOCK - Usb observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: USB_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *USB_POWER_SWITCH_MEMORY - Usb power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: USB_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB_POWER_SWITCH_MEMORY :: USB0_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_CLOCK_DISABLE - Disable VEC_AIO_TOP's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: DISABLE_VEC_ITU656_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE_STATUS :: DISABLE_VEC_ITU656_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE_STATUS :: DISABLE_VEC_DACADC_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_CLOCK_ENABLE - Vec aio top clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_AIO_ALTERNATE2_216_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_AIO_ALTERNATE2_216_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_AIO_ALTERNATE2_216_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_AIO_ALTERNATE2_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_CLOCK_ENABLE_AIO - Vec aio top clock enable aio |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_AIO :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_AIO :: AIO_SCB_CLOCK_ENABLE_AIO [01:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_SCB_CLOCK_ENABLE_AIO_MASK 0x00000002 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_SCB_CLOCK_ENABLE_AIO_SHIFT 1 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_SCB_CLOCK_ENABLE_AIO_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_AIO :: AIO_108_CLOCK_ENABLE_AIO [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_108_CLOCK_ENABLE_AIO_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_108_CLOCK_ENABLE_AIO_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_108_CLOCK_ENABLE_AIO_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_CLOCK_ENABLE_AIO_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_AIO_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_AIO_STATUS :: AIO_SCB_CLOCK_ENABLE_AIO_STATUS [01:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_STATUS_AIO_SCB_CLOCK_ENABLE_AIO_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_STATUS_AIO_SCB_CLOCK_ENABLE_AIO_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_AIO_STATUS :: AIO_108_CLOCK_ENABLE_AIO_STATUS [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_STATUS_AIO_108_CLOCK_ENABLE_AIO_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_STATUS_AIO_108_CLOCK_ENABLE_AIO_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_STATUS :: VEC_AIO_ALTERNATE2_216_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_STATUS_VEC_AIO_ALTERNATE2_216_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_STATUS_VEC_AIO_ALTERNATE2_216_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_CLOCK_ENABLE_VEC - Vec aio top clock enable vec |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC :: VEC_SCB_CLOCK_ENABLE_VEC [03:03] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_MASK 0x00000008 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_SHIFT 3 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC :: VEC_216_CLOCK_ENABLE_VEC [02:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_MASK 0x00000004 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_SHIFT 2 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC :: VEC_108_CLOCK_ENABLE_VEC [01:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_MASK 0x00000002 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_SHIFT 1 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC :: QDAC_216_CLOCK_ENABLE_VEC [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_QDAC_216_CLOCK_ENABLE_VEC_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_QDAC_216_CLOCK_ENABLE_VEC_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_QDAC_216_CLOCK_ENABLE_VEC_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS :: VEC_SCB_CLOCK_ENABLE_VEC_STATUS [03:03] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS_VEC_SCB_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS_VEC_SCB_CLOCK_ENABLE_VEC_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS :: VEC_216_CLOCK_ENABLE_VEC_STATUS [02:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS_VEC_216_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS_VEC_216_CLOCK_ENABLE_VEC_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS :: VEC_108_CLOCK_ENABLE_VEC_STATUS [01:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS_VEC_108_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS_VEC_108_CLOCK_ENABLE_VEC_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS :: QDAC_216_CLOCK_ENABLE_VEC_STATUS [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS_QDAC_216_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS_QDAC_216_CLOCK_ENABLE_VEC_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO - Vec aio top memory standby enable aio |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO :: AIO_MEMORY_STANDBY_ENABLE_AIO [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC - Vec aio top memory standby enable vec |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC :: VEC_MEMORY_STANDBY_ENABLE_VEC [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_OBSERVE_CLOCK - Vec aio top observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_ENABLE_OBSERVE_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: AIO_ENABLE_OBSERVE_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_OBSERVE_CLOCK_AIO - Vec aio top observe clock aio |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK_AIO :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK_AIO :: AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_AIO [04:04] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_AIO_MASK 0x00000010 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_AIO_SHIFT 4 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_AIO_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK_AIO :: AIO_CONTROL_OBSERVE_CLOCK_AIO [03:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_AIO_CONTROL_OBSERVE_CLOCK_AIO_MASK 0x0000000f |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_AIO_CONTROL_OBSERVE_CLOCK_AIO_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_AIO_CONTROL_OBSERVE_CLOCK_AIO_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_OBSERVE_CLOCK_VEC - Vec aio top observe clock vec |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK_VEC :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK_VEC :: VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_VEC [04:04] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_VEC_MASK 0x00000010 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_VEC_SHIFT 4 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_VEC_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK_VEC :: VEC_CONTROL_OBSERVE_CLOCK_VEC [03:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_VEC_CONTROL_OBSERVE_CLOCK_VEC_MASK 0x0000000f |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_VEC_CONTROL_OBSERVE_CLOCK_VEC_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_VEC_CONTROL_OBSERVE_CLOCK_VEC_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO - Vec aio top power switch memory aio |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO :: AIO_POWER_SWITCH_MEMORY_AIO [01:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_MASK 0x00000003 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC - Vec aio top power switch memory vec |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC :: VEC_POWER_SWITCH_MEMORY_VEC [01:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_MASK 0x00000003 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_TS_CTRL - TS_CTRL |
| ***************************************************************************/ |
| /* CLKGEN :: TM_TS_CTRL :: RSVD [31:00] */ |
| #define BCHP_CLKGEN_TM_TS_CTRL_RSVD_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_TS_CTRL_RSVD_SHIFT 0 |
| #define BCHP_CLKGEN_TM_TS_CTRL_RSVD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_MEM_CTRL - MEM_CTRL |
| ***************************************************************************/ |
| /* CLKGEN :: TM_MEM_CTRL :: RSVD_0 [31:12] */ |
| #define BCHP_CLKGEN_TM_MEM_CTRL_RSVD_0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_TM_MEM_CTRL_RSVD_0_SHIFT 12 |
| #define BCHP_CLKGEN_TM_MEM_CTRL_RSVD_0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: TM_MEM_CTRL :: RAM_STBY_DS3 [11:11] */ |
| #define BCHP_CLKGEN_TM_MEM_CTRL_RAM_STBY_DS3_MASK 0x00000800 |
| #define BCHP_CLKGEN_TM_MEM_CTRL_RAM_STBY_DS3_SHIFT 11 |
| #define BCHP_CLKGEN_TM_MEM_CTRL_RAM_STBY_DS3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: TM_MEM_CTRL :: PSM_DS3 [10:09] */ |
| #define BCHP_CLKGEN_TM_MEM_CTRL_PSM_DS3_MASK 0x00000600 |
| #define BCHP_CLKGEN_TM_MEM_CTRL_PSM_DS3_SHIFT 9 |
| #define BCHP_CLKGEN_TM_MEM_CTRL_PSM_DS3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: TM_MEM_CTRL :: RAM_STBY_DS2 [08:08] */ |
| #define BCHP_CLKGEN_TM_MEM_CTRL_RAM_STBY_DS2_MASK 0x00000100 |
| #define BCHP_CLKGEN_TM_MEM_CTRL_RAM_STBY_DS2_SHIFT 8 |
| #define BCHP_CLKGEN_TM_MEM_CTRL_RAM_STBY_DS2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: TM_MEM_CTRL :: PSM_DS2 [07:06] */ |
| #define BCHP_CLKGEN_TM_MEM_CTRL_PSM_DS2_MASK 0x000000c0 |
| #define BCHP_CLKGEN_TM_MEM_CTRL_PSM_DS2_SHIFT 6 |
| #define BCHP_CLKGEN_TM_MEM_CTRL_PSM_DS2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: TM_MEM_CTRL :: RAM_STBY_DS1 [05:05] */ |
| #define BCHP_CLKGEN_TM_MEM_CTRL_RAM_STBY_DS1_MASK 0x00000020 |
| #define BCHP_CLKGEN_TM_MEM_CTRL_RAM_STBY_DS1_SHIFT 5 |
| #define BCHP_CLKGEN_TM_MEM_CTRL_RAM_STBY_DS1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: TM_MEM_CTRL :: PSM_DS1 [04:03] */ |
| #define BCHP_CLKGEN_TM_MEM_CTRL_PSM_DS1_MASK 0x00000018 |
| #define BCHP_CLKGEN_TM_MEM_CTRL_PSM_DS1_SHIFT 3 |
| #define BCHP_CLKGEN_TM_MEM_CTRL_PSM_DS1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: TM_MEM_CTRL :: RAM_STBY_DS0 [02:02] */ |
| #define BCHP_CLKGEN_TM_MEM_CTRL_RAM_STBY_DS0_MASK 0x00000004 |
| #define BCHP_CLKGEN_TM_MEM_CTRL_RAM_STBY_DS0_SHIFT 2 |
| #define BCHP_CLKGEN_TM_MEM_CTRL_RAM_STBY_DS0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: TM_MEM_CTRL :: PSM_DS0 [01:00] */ |
| #define BCHP_CLKGEN_TM_MEM_CTRL_PSM_DS0_MASK 0x00000003 |
| #define BCHP_CLKGEN_TM_MEM_CTRL_PSM_DS0_SHIFT 0 |
| #define BCHP_CLKGEN_TM_MEM_CTRL_PSM_DS0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_MEM_CTRL2 - MEM_CTRL2 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_MEM_CTRL2 :: RSVD [31:00] */ |
| #define BCHP_CLKGEN_TM_MEM_CTRL2_RSVD_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_MEM_CTRL2_RSVD_SHIFT 0 |
| #define BCHP_CLKGEN_TM_MEM_CTRL2_RSVD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_PWRDN - PWRDN |
| ***************************************************************************/ |
| /* CLKGEN :: TM_PWRDN :: RSVD [31:00] */ |
| #define BCHP_CLKGEN_TM_PWRDN_RSVD_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_PWRDN_RSVD_SHIFT 0 |
| #define BCHP_CLKGEN_TM_PWRDN_RSVD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_SFT_RST - SFT_RST |
| ***************************************************************************/ |
| /* CLKGEN :: TM_SFT_RST :: RSVD [31:02] */ |
| #define BCHP_CLKGEN_TM_SFT_RST_RSVD_MASK 0xfffffffc |
| #define BCHP_CLKGEN_TM_SFT_RST_RSVD_SHIFT 2 |
| #define BCHP_CLKGEN_TM_SFT_RST_RSVD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: TM_SFT_RST :: DS_TOPA [01:01] */ |
| #define BCHP_CLKGEN_TM_SFT_RST_DS_TOPA_MASK 0x00000002 |
| #define BCHP_CLKGEN_TM_SFT_RST_DS_TOPA_SHIFT 1 |
| #define BCHP_CLKGEN_TM_SFT_RST_DS_TOPA_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: TM_SFT_RST :: WFE [00:00] */ |
| #define BCHP_CLKGEN_TM_SFT_RST_WFE_MASK 0x00000001 |
| #define BCHP_CLKGEN_TM_SFT_RST_WFE_SHIFT 0 |
| #define BCHP_CLKGEN_TM_SFT_RST_WFE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_SYS_PLL_STATUS - SYS_PLL_STATUS |
| ***************************************************************************/ |
| /* CLKGEN :: TM_SYS_PLL_STATUS :: RSVD [31:17] */ |
| #define BCHP_CLKGEN_TM_SYS_PLL_STATUS_RSVD_MASK 0xfffe0000 |
| #define BCHP_CLKGEN_TM_SYS_PLL_STATUS_RSVD_SHIFT 17 |
| #define BCHP_CLKGEN_TM_SYS_PLL_STATUS_RSVD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: TM_SYS_PLL_STATUS :: LOCK [16:16] */ |
| #define BCHP_CLKGEN_TM_SYS_PLL_STATUS_LOCK_MASK 0x00010000 |
| #define BCHP_CLKGEN_TM_SYS_PLL_STATUS_LOCK_SHIFT 16 |
| #define BCHP_CLKGEN_TM_SYS_PLL_STATUS_LOCK_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: TM_SYS_PLL_STATUS :: STAT_OUT [15:00] */ |
| #define BCHP_CLKGEN_TM_SYS_PLL_STATUS_STAT_OUT_MASK 0x0000ffff |
| #define BCHP_CLKGEN_TM_SYS_PLL_STATUS_STAT_OUT_SHIFT 0 |
| #define BCHP_CLKGEN_TM_SYS_PLL_STATUS_STAT_OUT_DEFAULT 0x00000102 |
| |
| /*************************************************************************** |
| *TM_SYS_PLL_RST - SYS_PLL_RST |
| ***************************************************************************/ |
| /* CLKGEN :: TM_SYS_PLL_RST :: RSVD [31:00] */ |
| #define BCHP_CLKGEN_TM_SYS_PLL_RST_RSVD_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_SYS_PLL_RST_RSVD_SHIFT 0 |
| #define BCHP_CLKGEN_TM_SYS_PLL_RST_RSVD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_SYS_PLL_CLK_216 - SYS_PLL_CLK_216 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_SYS_PLL_CLK_216 :: RSVD [31:00] */ |
| #define BCHP_CLKGEN_TM_SYS_PLL_CLK_216_RSVD_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_SYS_PLL_CLK_216_RSVD_SHIFT 0 |
| #define BCHP_CLKGEN_TM_SYS_PLL_CLK_216_RSVD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_SYS_PLL_CLK_T2B - SYS_PLL_CLK_T2B |
| ***************************************************************************/ |
| /* CLKGEN :: TM_SYS_PLL_CLK_T2B :: RSVD [31:00] */ |
| #define BCHP_CLKGEN_TM_SYS_PLL_CLK_T2B_RSVD_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_SYS_PLL_CLK_T2B_RSVD_SHIFT 0 |
| #define BCHP_CLKGEN_TM_SYS_PLL_CLK_T2B_RSVD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_SYS_CLK_EN - SYS_CLK_EN |
| ***************************************************************************/ |
| /* CLKGEN :: TM_SYS_CLK_EN :: RSVD_1 [31:16] */ |
| #define BCHP_CLKGEN_TM_SYS_CLK_EN_RSVD_1_MASK 0xffff0000 |
| #define BCHP_CLKGEN_TM_SYS_CLK_EN_RSVD_1_SHIFT 16 |
| #define BCHP_CLKGEN_TM_SYS_CLK_EN_RSVD_1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: TM_SYS_CLK_EN :: RSVD_0 [15:05] */ |
| #define BCHP_CLKGEN_TM_SYS_CLK_EN_RSVD_0_MASK 0x0000ffe0 |
| #define BCHP_CLKGEN_TM_SYS_CLK_EN_RSVD_0_SHIFT 5 |
| #define BCHP_CLKGEN_TM_SYS_CLK_EN_RSVD_0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: TM_SYS_CLK_EN :: LEAP_27 [04:04] */ |
| #define BCHP_CLKGEN_TM_SYS_CLK_EN_LEAP_27_MASK 0x00000010 |
| #define BCHP_CLKGEN_TM_SYS_CLK_EN_LEAP_27_SHIFT 4 |
| #define BCHP_CLKGEN_TM_SYS_CLK_EN_LEAP_27_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: TM_SYS_CLK_EN :: RSVD_2 [03:00] */ |
| #define BCHP_CLKGEN_TM_SYS_CLK_EN_RSVD_2_MASK 0x0000000f |
| #define BCHP_CLKGEN_TM_SYS_CLK_EN_RSVD_2_SHIFT 0 |
| #define BCHP_CLKGEN_TM_SYS_CLK_EN_RSVD_2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_SYS_REV_ID - SYS_REV_ID |
| ***************************************************************************/ |
| /* CLKGEN :: TM_SYS_REV_ID :: RSVD [31:00] */ |
| #define BCHP_CLKGEN_TM_SYS_REV_ID_RSVD_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_SYS_REV_ID_RSVD_SHIFT 0 |
| #define BCHP_CLKGEN_TM_SYS_REV_ID_RSVD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_OSC_CLK_EN - OSC_CLK_EN |
| ***************************************************************************/ |
| /* CLKGEN :: TM_OSC_CLK_EN :: RSVD [31:00] */ |
| #define BCHP_CLKGEN_TM_OSC_CLK_EN_RSVD_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_OSC_CLK_EN_RSVD_SHIFT 0 |
| #define BCHP_CLKGEN_TM_OSC_CLK_EN_RSVD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_SYS_PLL_PDIV - SYS_PLL_PDIV |
| ***************************************************************************/ |
| /* CLKGEN :: TM_SYS_PLL_PDIV :: RSVD [31:00] */ |
| #define BCHP_CLKGEN_TM_SYS_PLL_PDIV_RSVD_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_SYS_PLL_PDIV_RSVD_SHIFT 0 |
| #define BCHP_CLKGEN_TM_SYS_PLL_PDIV_RSVD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_SYS_PLL_NDIV_INT - SYS_PLL_NDIV_INT |
| ***************************************************************************/ |
| /* CLKGEN :: TM_SYS_PLL_NDIV_INT :: RSVD [31:00] */ |
| #define BCHP_CLKGEN_TM_SYS_PLL_NDIV_INT_RSVD_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_SYS_PLL_NDIV_INT_RSVD_SHIFT 0 |
| #define BCHP_CLKGEN_TM_SYS_PLL_NDIV_INT_RSVD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_SFT0 - SFT0 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_SFT0 :: RSVD [31:00] */ |
| #define BCHP_CLKGEN_TM_SFT0_RSVD_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_SFT0_RSVD_SHIFT 0 |
| #define BCHP_CLKGEN_TM_SFT0_RSVD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_SFT1 - SFT1 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_SFT1 :: RSVD [31:00] */ |
| #define BCHP_CLKGEN_TM_SFT1_RSVD_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_SFT1_RSVD_SHIFT 0 |
| #define BCHP_CLKGEN_TM_SFT1_RSVD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_SFT2 - SFT2 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_SFT2 :: RSVD [31:00] */ |
| #define BCHP_CLKGEN_TM_SFT2_RSVD_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_SFT2_RSVD_SHIFT 0 |
| #define BCHP_CLKGEN_TM_SFT2_RSVD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_SFT3 - SFT3 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_SFT3 :: RSVD [31:00] */ |
| #define BCHP_CLKGEN_TM_SFT3_RSVD_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_SFT3_RSVD_SHIFT 0 |
| #define BCHP_CLKGEN_TM_SFT3_RSVD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_SFT4 - SFT4 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_SFT4 :: RSVD [31:00] */ |
| #define BCHP_CLKGEN_TM_SFT4_RSVD_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_SFT4_RSVD_SHIFT 0 |
| #define BCHP_CLKGEN_TM_SFT4_RSVD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_SFT5 - SFT5 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_SFT5 :: RSVD [31:00] */ |
| #define BCHP_CLKGEN_TM_SFT5_RSVD_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_SFT5_RSVD_SHIFT 0 |
| #define BCHP_CLKGEN_TM_SFT5_RSVD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_SFT6 - SFT6 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_SFT6 :: RSVD [31:00] */ |
| #define BCHP_CLKGEN_TM_SFT6_RSVD_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_SFT6_RSVD_SHIFT 0 |
| #define BCHP_CLKGEN_TM_SFT6_RSVD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_SFT7 - SFT7 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_SFT7 :: RSVD [31:00] */ |
| #define BCHP_CLKGEN_TM_SFT7_RSVD_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_SFT7_RSVD_SHIFT 0 |
| #define BCHP_CLKGEN_TM_SFT7_RSVD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_CM0 - CM0 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_CM0 :: RSVD [31:00] */ |
| #define BCHP_CLKGEN_TM_CM0_RSVD_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_CM0_RSVD_SHIFT 0 |
| #define BCHP_CLKGEN_TM_CM0_RSVD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_CM1 - CM1 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_CM1 :: RSVD [31:00] */ |
| #define BCHP_CLKGEN_TM_CM1_RSVD_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_CM1_RSVD_SHIFT 0 |
| #define BCHP_CLKGEN_TM_CM1_RSVD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_CM2 - CM2 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_CM2 :: RSVD [31:00] */ |
| #define BCHP_CLKGEN_TM_CM2_RSVD_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_CM2_RSVD_SHIFT 0 |
| #define BCHP_CLKGEN_TM_CM2_RSVD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TM_CM3 - CM3 |
| ***************************************************************************/ |
| /* CLKGEN :: TM_CM3 :: RSVD [31:00] */ |
| #define BCHP_CLKGEN_TM_CM3_RSVD_MASK 0xffffffff |
| #define BCHP_CLKGEN_TM_CM3_RSVD_SHIFT 0 |
| #define BCHP_CLKGEN_TM_CM3_RSVD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BSPI_CLOCK_SELECT - BSPI CLOCK SELECT - spi clock control |
| ***************************************************************************/ |
| /* CLKGEN :: BSPI_CLOCK_SELECT :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: BSPI_CLOCK_SELECT :: spi_clock_freq_sel [02:01] */ |
| #define BCHP_CLKGEN_BSPI_CLOCK_SELECT_spi_clock_freq_sel_MASK 0x00000006 |
| #define BCHP_CLKGEN_BSPI_CLOCK_SELECT_spi_clock_freq_sel_SHIFT 1 |
| #define BCHP_CLKGEN_BSPI_CLOCK_SELECT_spi_clock_freq_sel_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: BSPI_CLOCK_SELECT :: spi_clock_override_strap [00:00] */ |
| #define BCHP_CLKGEN_BSPI_CLOCK_SELECT_spi_clock_override_strap_MASK 0x00000001 |
| #define BCHP_CLKGEN_BSPI_CLOCK_SELECT_spi_clock_override_strap_SHIFT 0 |
| #define BCHP_CLKGEN_BSPI_CLOCK_SELECT_spi_clock_override_strap_DEFAULT 0x00000000 |
| |
| #endif /* #ifndef BCHP_CLKGEN_H__ */ |
| |
| /* End of File */ |
