| /*************************************************************************** |
| * Copyright (c) 1999-2011, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Mon Apr 11 12:23:07 2011 |
| * MD5 Checksum 8cf142ad25caa9f873c54e8bb2bb1755 |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: /magnum/basemodules/chp/7425/rdb/b0/bchp_ddr40_phy_word_lane_0_1.h $ |
| * |
| * Hydra_Software_Devel/2 4/11/11 11:57p vanessah |
| * SW7425-112: Update rdb files for 7425 B0. |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_DDR40_PHY_WORD_LANE_0_1_H__ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_H__ |
| |
| /*************************************************************************** |
| *DDR40_PHY_WORD_LANE_0_1 - DDR40 DDR40 word lane #0 control registers 1 |
| ***************************************************************************/ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN 0x003c6200 /* Read Enable Byte VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W 0x003c6204 /* Write Byte VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P 0x003c6208 /* Read Byte DQSP VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N 0x003c620c /* Read Byte DQSN VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W 0x003c6210 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W 0x003c6214 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W 0x003c6218 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W 0x003c621c /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W 0x003c6220 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W 0x003c6224 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W 0x003c6228 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W 0x003c622c /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W 0x003c6230 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003c6234 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003c6238 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003c623c /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003c6240 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003c6244 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003c6248 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003c624c /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003c6250 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003c6254 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003c6258 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003c625c /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003c6260 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003c6264 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003c6268 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003c626c /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003c6270 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003c6274 /* Read Enable Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W 0x003c62a4 /* Write Byte VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P 0x003c62a8 /* Read Byte DQSP VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N 0x003c62ac /* Read Byte DQSN VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W 0x003c62b0 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W 0x003c62b4 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W 0x003c62b8 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W 0x003c62bc /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W 0x003c62c0 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W 0x003c62c4 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W 0x003c62c8 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W 0x003c62cc /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W 0x003c62d0 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003c62d4 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003c62d8 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003c62dc /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003c62e0 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003c62e4 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003c62e8 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003c62ec /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003c62f0 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003c62f4 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003c62f8 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003c62fc /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003c6300 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003c6304 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003c6308 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003c630c /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003c6310 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003c6314 /* Read Enable Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_P 0x003c6328 /* Read DQSP VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_N 0x003c632c /* Read DQSN VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003c6330 /* Read DQ-P VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003c6334 /* Read DQ-N VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_W 0x003c6338 /* Write DQ Byte VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003c633c /* Write DQ Bit VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_P 0x003c6348 /* Read DQSP VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_N 0x003c634c /* Read DQSN VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003c6350 /* Read DQ-P VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003c6354 /* Read DQ-N VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_W 0x003c6358 /* Write DQ Byte VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003c635c /* Write DQ Bit VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_DATA_DLY 0x003c6360 /* Word Lane read channel control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_CONTROL 0x003c6364 /* Word Lane read channel control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_0 0x003c6370 /* Read fifo data register, first data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_1 0x003c6374 /* Read fifo data register, second data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_2 0x003c6378 /* Read fifo data register, third data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_3 0x003c637c /* Read fifo data register, fourth data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_0 0x003c6380 /* Read fifo data register, first data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_1 0x003c6384 /* Read fifo data register, second data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_2 0x003c6388 /* Read fifo data register, third data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_3 0x003c638c /* Read fifo data register, fourth data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_STATUS 0x003c6390 /* Read fifo status register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_CLEAR 0x003c6394 /* Read fifo status clear register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL 0x003c63a0 /* Idle mode SSTL pad control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL 0x003c63a4 /* SSTL pad drive characteristics control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_CLOCK_PAD_DISABLE 0x003c63a8 /* Clock pad disable register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_WR_PREAMBLE_MODE 0x003c63ac /* Write cycle preamble control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_0_1_PHYBIST_VDL_ADJ 0x003c63b0 /* PHYBIST mode VDL step select adjustment register */ |
| |
| #endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_0_1_H__ */ |
| |
| /* End of File */ |
