| /*************************************************************************** |
| * Copyright (c) 1999-2011, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Tue Dec 6 18:45:27 2011 |
| * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_clkgen.h $ |
| * |
| * Hydra_Software_Devel/2 12/7/11 1:58p mward |
| * SW7435-3: Synced up with central rdb. |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_CLKGEN_H__ |
| #define BCHP_CLKGEN_H__ |
| |
| /*************************************************************************** |
| *CLKGEN - clkgen registers |
| ***************************************************************************/ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL 0x00430000 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV 0x00430004 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN 0x00430008 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS 0x0043000c /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN 0x00430010 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET 0x00430014 /* Resets */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x00430018 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x0043001c /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS 0x00430020 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL 0x00430024 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV 0x00430028 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN 0x0043002c /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS 0x00430030 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN 0x00430034 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET 0x00430038 /* Resets */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x0043003c /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x00430040 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS 0x00430044 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL 0x00430048 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV 0x0043004c /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN 0x00430050 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS 0x00430054 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN 0x00430058 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET 0x0043005c /* Resets */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH 0x00430060 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW 0x00430064 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS 0x00430068 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 0x0043006c /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 0x00430070 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 0x00430074 /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 0x00430078 /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4 0x0043007c /* PLL CHANNEL control CH 4 */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL 0x00430080 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_DIV 0x00430084 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN 0x00430088 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_LDO_PWRDN 0x0043008c /* LDO Powerdowns */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS 0x00430090 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC 0x00430094 /* Miscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2 0x00430098 /* Miscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN 0x0043009c /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_RESET 0x004300a0 /* Resets */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH 0x004300a4 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW 0x004300a8 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_STATUS 0x004300ac /* Test Status */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0 0x004300b0 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL 0x004300b4 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_DIV 0x004300b8 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_FRAC 0x004300bc /* Fractional */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_GAIN 0x004300c0 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_LOCK_STATUS 0x004300c4 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC 0x004300c8 /* Miscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN 0x004300cc /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_RESET 0x004300d0 /* Resets */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_STATUS 0x004300d4 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN 0x004300d8 /* Cml buffer Tristate enable */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 0x004300dc /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 0x004300e0 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL 0x004300e4 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV 0x004300e8 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_FRAC 0x004300ec /* Fractional */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN 0x004300f0 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LDO_PWRDN 0x004300f4 /* LDO Powerdowns */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS 0x004300f8 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC 0x004300fc /* Miscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2 0x00430100 /* Miscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN 0x00430104 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET 0x00430108 /* Resets */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH 0x0043010c /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW 0x00430110 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS 0x00430114 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 0x00430118 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 0x0043011c /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 0x00430120 /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 0x00430124 /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 0x00430128 /* PLL CHANNEL control CH 4 */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL 0x0043012c /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV 0x00430130 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN 0x00430134 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRDN 0x00430138 /* LDO Powerdowns */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS 0x0043013c /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC 0x00430140 /* Miscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2 0x00430144 /* Miscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN 0x00430148 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET 0x0043014c /* Resets */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH 0x00430150 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW 0x00430154 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS 0x00430158 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 0x0043015c /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 0x00430160 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 0x00430164 /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3 0x00430168 /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL 0x0043016c /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV 0x00430170 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN 0x00430174 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRDN 0x00430178 /* LDO Powerdowns */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS 0x0043017c /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC 0x00430180 /* Miscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2 0x00430184 /* Miscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN 0x00430188 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET 0x0043018c /* Resets */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH 0x00430190 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW 0x00430194 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS 0x00430198 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 0x0043019c /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 0x004301a0 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL 0x004301a4 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV 0x004301a8 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN 0x004301ac /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRDN 0x004301b0 /* LDO Powerdowns */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS 0x004301b4 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC 0x004301b8 /* Miscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2 0x004301bc /* Miscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN 0x004301c0 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET 0x004301c4 /* Resets */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH 0x004301c8 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW 0x004301cc /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS 0x004301d0 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0 0x004301d4 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CONTROL 0x004301d8 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_DIV 0x004301dc /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_FRAC 0x004301e0 /* Fractional */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN 0x004301e4 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS 0x004301e8 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC 0x004301ec /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_PWRDN 0x004301f0 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET 0x004301f4 /* Resets */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH 0x004301f8 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW 0x004301fc /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_STATUS 0x00430200 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0 0x00430204 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CONTROL 0x00430208 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_DIV 0x0043020c /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_FRAC 0x00430210 /* Fractional */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN 0x00430214 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS 0x00430218 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC 0x0043021c /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_PWRDN 0x00430220 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET 0x00430224 /* Resets */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH 0x00430228 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW 0x0043022c /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_STATUS 0x00430230 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x00430234 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x00430238 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x0043023c /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x00430240 /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL 0x00430244 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV 0x00430248 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN 0x0043024c /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRDN 0x00430250 /* LDO Powerdowns */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS 0x00430254 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC 0x00430258 /* Miscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2 0x0043025c /* Miscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN 0x00430260 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_RESET 0x00430264 /* Resets */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x00430268 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x0043026c /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS 0x00430270 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 0x00430274 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 0x00430278 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 0x0043027c /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL 0x00430280 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV 0x00430284 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC 0x00430288 /* Fractional */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN 0x0043028c /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS 0x00430290 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC 0x00430294 /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN 0x00430298 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET 0x0043029c /* Resets */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH 0x004302a0 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW 0x004302a4 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS 0x004302a8 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 0x004302ac /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 0x004302b0 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 0x004302b4 /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL 0x004302b8 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV 0x004302bc /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC 0x004302c0 /* Fractional */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN 0x004302c4 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS 0x004302c8 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC 0x004302cc /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN 0x004302d0 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET 0x004302d4 /* Resets */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH 0x004302d8 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW 0x004302dc /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS 0x004302e0 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 0x004302e4 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 0x004302e8 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 0x004302ec /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL 0x004302f0 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV 0x004302f4 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC 0x004302f8 /* Fractional */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN 0x004302fc /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS 0x00430300 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC 0x00430304 /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN 0x00430308 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET 0x0043030c /* Resets */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH 0x00430310 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW 0x00430314 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS 0x00430318 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0 0x0043031c /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1 0x00430320 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2 0x00430324 /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3 0x00430328 /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CONTROL 0x0043032c /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_DIV 0x00430330 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN 0x00430334 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRDN 0x00430338 /* LDO Powerdowns */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS 0x0043033c /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC 0x00430340 /* Miscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC2 0x00430344 /* Miscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_PWRDN 0x00430348 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_RESET 0x0043034c /* Resets */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH 0x00430350 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW 0x00430354 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_STATUS 0x00430358 /* Test Status */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE 0x0043035c /* Avd0 top inst clock enable */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_SID 0x00430360 /* Avd0 top inst clock enable sid */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_SID_STATUS 0x00430364 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_STATUS 0x00430368 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_MEMORY_STANDBY_ENABLE 0x0043036c /* Avd0 top inst memory standby enable */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK 0x00430370 /* Avd0 top inst observe clock */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_POWER_SWITCH_MEMORY 0x00430374 /* Avd0 top inst power switch memory */ |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE 0x00430378 /* Bvn mvp top inst clock enable */ |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS 0x0043037c /* Clock Enable Status */ |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_MEMORY_STANDBY_ENABLE 0x00430380 /* Bvn mvp top inst memory standby enable */ |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_POWER_SWITCH_MEMORY 0x00430384 /* Bvn mvp top inst power switch memory */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE 0x00430388 /* Bvn top inst clock enable */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS 0x0043038c /* Clock Enable Status */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE 0x00430390 /* Bvn top inst memory standby enable */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY 0x00430394 /* Bvn top inst power switch memory */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE 0x00430398 /* Disable CLKGEN's clocks */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS 0x0043039c /* Clock Disable Status */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL 0x004303a0 /* Clock Monitor Control */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT 0x004303a4 /* Clock Monitor Max Reference Count */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER 0x004303a8 /* Clock Monitor Reference Counter */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE 0x004303ac /* Clock Monitor Reference Counter */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER 0x004303b0 /* Clock Monitor View Counter */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE 0x004303b4 /* Disable CORE_XPT_INST's clocks */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS 0x004303b8 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE 0x004303bc /* Core xpt inst clock enable */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS 0x004303c0 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE 0x004303c4 /* Core xpt inst memory standby enable */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK 0x004303c8 /* Core xpt inst observe clock */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY 0x004303cc /* Core xpt inst power switch memory */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE 0x004303d0 /* Disable DUAL_GENET_TOP_DUAL_RGMII_INST's clocks */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS 0x004303d4 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE 0x004303d8 /* Dual genet top dual rgmii inst clock enable */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 0x004303dc /* Dual genet top dual rgmii inst clock enable genet0 */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS 0x004303e0 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 0x004303e4 /* Dual genet top dual rgmii inst clock enable genet1 */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS 0x004303e8 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS 0x004303ec /* Clock Enable Status */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0 0x004303f0 /* Dual genet top dual rgmii inst clock select genet0 */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1 0x004303f4 /* Dual genet top dual rgmii inst clock select genet1 */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK 0x004303f8 /* Dual genet top dual rgmii inst observe clock */ |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE 0x004303fc /* Disable DVP_HR_INST's clocks */ |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS 0x00430400 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE 0x00430404 /* Dvp hr inst clock enable */ |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS 0x00430408 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE 0x0043040c /* Dvp hr inst memory standby enable */ |
| #define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK 0x00430410 /* Dvp hr inst observe clock */ |
| #define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY 0x00430414 /* Dvp hr inst power switch memory */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE 0x00430418 /* Disable DVP_HT_INST's clocks */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS 0x0043041c /* Clock Disable Status */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE 0x00430420 /* Dvp ht inst clock enable */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS 0x00430424 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_DVP_HT_INST_ENABLE 0x00430428 /* Dvp ht inst enable */ |
| #define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE 0x0043042c /* Dvp ht inst memory standby enable */ |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK 0x00430430 /* Dvp ht inst observe clock */ |
| #define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY 0x00430434 /* Dvp ht inst power switch memory */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE 0x00430438 /* Graphics inst clock enable */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0 0x0043043c /* Graphics inst clock enable m2mc0 */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS 0x00430440 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1 0x00430444 /* Graphics inst clock enable m2mc1 */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS 0x00430448 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS 0x0043044c /* Clock Enable Status */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC0 0x00430450 /* Graphics inst memory standby enable m2mc0 */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC1 0x00430454 /* Graphics inst memory standby enable m2mc1 */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK 0x00430458 /* Graphics inst observe clock */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC0 0x0043045c /* Graphics inst power switch memory m2mc0 */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC1 0x00430460 /* Graphics inst power switch memory m2mc1 */ |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE 0x00430464 /* Disable HIF_INST's clocks */ |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS 0x00430468 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE 0x0043046c /* Hif inst memory standby enable */ |
| #define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK 0x00430470 /* Hif inst observe clock */ |
| #define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH 0x00430474 /* Hif inst pll hif ssc mode control high */ |
| #define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW 0x00430478 /* Hif inst pll hif ssc mode control low */ |
| #define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY 0x0043047c /* Hif inst power switch memory */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT 0x00430480 /* Mux selects for Internal clocks */ |
| #define BCHP_CLKGEN_ITU656_0_MUX_SELECT 0x00430484 /* Mux selects for itu656_0 clocks */ |
| #define BCHP_CLKGEN_ITU656_1_MUX_SELECT 0x00430488 /* Mux selects for itu656_1 clocks */ |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE 0x0043048c /* Memsys 32 0 inst clock enable */ |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS 0x00430490 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE 0x00430494 /* Memsys 32 0 inst memory standby enable */ |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK 0x00430498 /* Memsys 32 0 inst observe clock */ |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY 0x0043049c /* Memsys 32 0 inst power switch memory */ |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS 0x004304a0 /* Memsys 32 0 inst status */ |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE 0x004304a4 /* Memsys 32 1 inst clock enable */ |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS 0x004304a8 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE 0x004304ac /* Memsys 32 1 inst memory standby enable */ |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK 0x004304b0 /* Memsys 32 1 inst observe clock */ |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY 0x004304b4 /* Memsys 32 1 inst power switch memory */ |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_STATUS 0x004304b8 /* Memsys 32 1 inst status */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE 0x004304bc /* Moca top inst clock enable */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_STATUS 0x004304c0 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE 0x004304c4 /* Moca top inst memory standby enable */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK 0x004304c8 /* Moca top inst observe clock */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY 0x004304cc /* Moca top inst power switch memory */ |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION 0x004304d0 /* Select observation clk */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE 0x004304d4 /* Disable PAD's clocks */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS 0x004304d8 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION 0x004304dc /* Select observation clk */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT 0x004304e0 /* Mux selects for Pad clocks */ |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION 0x004304e4 /* Select observation clk */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS 0x004304e8 /* PLL_AUDIO0 Reset Status */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS 0x004304ec /* PLL_AUDIO1 Reset Status */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS 0x004304f0 /* PLL_AUDIO2 Reset Status */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS 0x004304f4 /* PLL_AVD1 Reset Status */ |
| #define BCHP_CLKGEN_PLL_AVD1_RDB_MACRO_CTRL 0x004304f8 /* PLL RDB Macro Disable */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS 0x004304fc /* PLL_HIF Reset Status */ |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST 0x00430500 /* PLL_MIPS Glitchless Clock Switching */ |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS 0x00430504 /* PLL_MIPS Glitchless Switching */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS 0x00430508 /* PLL_MIPS Reset Status */ |
| #define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL 0x0043050c /* PLL RDB Macro Disable */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS 0x00430510 /* PLL_MOCA Reset Status */ |
| #define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL 0x00430514 /* PLL RDB Macro Disable */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS 0x00430518 /* PLL_NETWORK Reset Status */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS 0x0043051c /* PLL_RAAGA Reset Status */ |
| #define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL 0x00430520 /* PLL RDB Macro Disable */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS 0x00430524 /* PLL_SC0 Reset Status */ |
| #define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL 0x00430528 /* PLL RDB Macro Disable */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS 0x0043052c /* PLL_SC1 Reset Status */ |
| #define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL 0x00430530 /* PLL RDB Macro Disable */ |
| #define BCHP_CLKGEN_PLL_STRAP_OVERRIDE 0x00430534 /* Disable */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS 0x00430538 /* PLL_VCXO0 Reset Status */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS 0x0043053c /* PLL_VCXO1 Reset Status */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS 0x00430540 /* PLL_VCXO2 Reset Status */ |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL 0x00430544 /* Select clocks that can stay alive during power management standby mode. */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL 0x00430548 /* PLL Alive in Standby Mode */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP 0x0043054c /* Power management LDO PLL */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM 0x00430550 /* Power management LDO PLL state machine */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0 0x00430554 /* Raaga dsp top wrap inst clock enable0 */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_STATUS 0x00430558 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1 0x0043055c /* Raaga dsp top wrap inst clock enable1 */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_STATUS 0x00430560 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_MEMORY_STANDBY_ENABLE0 0x00430564 /* Raaga dsp top wrap inst memory standby enable0 */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_MEMORY_STANDBY_ENABLE1 0x00430568 /* Raaga dsp top wrap inst memory standby enable1 */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK0 0x0043056c /* Raaga dsp top wrap inst observe clock0 */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK1 0x00430570 /* Raaga dsp top wrap inst observe clock1 */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_POWER_SWITCH_MEMORY0 0x00430574 /* Raaga dsp top wrap inst power switch memory0 */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_POWER_SWITCH_MEMORY1 0x00430578 /* Raaga dsp top wrap inst power switch memory1 */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE 0x0043057c /* Disable SATA3_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS 0x00430580 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE 0x00430584 /* Sata3 top inst clock enable */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS 0x00430588 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT 0x0043058c /* Sata3 top inst clock select */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE 0x00430590 /* Sata3 top inst memory standby enable */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK 0x00430594 /* Sata3 top inst observe clock */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY 0x00430598 /* Sata3 top inst power switch memory */ |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA 0x0043059c /* Sectop inst clock enable m2mdma */ |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_STATUS 0x004305a0 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE 0x004305a4 /* Sectop inst memory standby enable */ |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK 0x004305a8 /* Sectop inst observe clock */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT 0x004305ac /* Mux selects for Smartcard clocks */ |
| #define BCHP_CLKGEN_SPARE 0x004305b0 /* Spares */ |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE 0x004305b4 /* Svd0 top inst clock enable */ |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS 0x004305b8 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE 0x004305bc /* Svd0 top inst memory standby enable */ |
| #define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY 0x004305c0 /* Svd0 top inst power switch memory */ |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK 0x004305c4 /* Sys aon inst observe clock */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE 0x004305c8 /* Disable SYS_CTRL_INST's clocks */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS 0x004305cc /* Clock Disable Status */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE 0x004305d0 /* Sys ctrl inst memory standby enable */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK 0x004305d4 /* Sys ctrl inst observe clock */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY 0x004305d8 /* Sys ctrl inst power switch memory */ |
| #define BCHP_CLKGEN_TESTPORT 0x004305dc /* Special Testport Controls */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE 0x004305e0 /* Disable UHFR_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_STATUS 0x004305e4 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE 0x004305e8 /* Uhfr top inst clock enable */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_STATUS 0x004305ec /* Clock Enable Status */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE 0x004305f0 /* Uhfr top inst memory standby enable */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK 0x004305f4 /* Uhfr top inst observe clock */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY 0x004305f8 /* Uhfr top inst power switch memory */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE 0x004305fc /* Disable USB0_INST's clocks */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_STATUS 0x00430600 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE 0x00430604 /* Usb0 inst clock enable */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_STATUS 0x00430608 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE 0x0043060c /* Usb0 inst memory standby enable */ |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK 0x00430610 /* Usb0 inst observe clock */ |
| #define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY 0x00430614 /* Usb0 inst power switch memory */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE 0x00430618 /* Disable USB1_INST's clocks */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_STATUS 0x0043061c /* Clock Disable Status */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE 0x00430620 /* Usb1 inst clock enable */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_STATUS 0x00430624 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE 0x00430628 /* Usb1 inst memory standby enable */ |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK 0x0043062c /* Usb1 inst observe clock */ |
| #define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY 0x00430630 /* Usb1 inst power switch memory */ |
| #define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE 0x00430634 /* V3d top inst clock enable */ |
| #define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS 0x00430638 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE 0x0043063c /* V3d top inst memory standby enable */ |
| #define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY 0x00430640 /* V3d top inst power switch memory */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE 0x00430644 /* Disable VEC_AIO_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS 0x00430648 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO 0x0043064c /* Vec aio top inst clock enable aio */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS 0x00430650 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC 0x00430654 /* Vec aio top inst clock enable vec */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS 0x00430658 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO 0x0043065c /* Vec aio top inst memory standby enable aio */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC 0x00430660 /* Vec aio top inst memory standby enable vec */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK 0x00430664 /* Vec aio top inst observe clock */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO 0x00430668 /* Vec aio top inst power switch memory aio */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC 0x0043066c /* Vec aio top inst power switch memory vec */ |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE 0x00430670 /* Vice2 1 inst clock enable */ |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS 0x00430674 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_VICE2_1_INST_MEMORY_STANDBY_ENABLE 0x00430678 /* Vice2 1 inst memory standby enable */ |
| #define BCHP_CLKGEN_VICE2_1_INST_POWER_SWITCH_MEMORY 0x0043067c /* Vice2 1 inst power switch memory */ |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE 0x00430680 /* Vice2 inst clock enable */ |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_STATUS 0x00430684 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE 0x00430688 /* Vice2 inst memory standby enable */ |
| #define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY 0x0043068c /* Vice2 inst power switch memory */ |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_DISABLE 0x00430690 /* Disable ZCPU_DUAL_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_STATUS 0x00430694 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE 0x00430698 /* Zcpu dual top inst clock enable */ |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS 0x0043069c /* Clock Enable Status */ |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK 0x004306a0 /* Zcpu dual top inst observe clock */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS 0x004306a4 /* Bypass GENET_TOP_DUAL_RGMII_INST's clocks */ |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [02:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [02:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO2_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO2_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO2_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO2_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO2_PLL_DIV :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PLL_AUDIO2_PLL_DIV :: PDIV [02:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_PDIV_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_PDIV_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_PDIV_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_AUDIO2_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007 |
| |
| /* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO2_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO2_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO2_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO2_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO2_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO2_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO2_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO2_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AUDIO2_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO2_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO2_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO2_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_AUDIO2_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000007 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000009 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000007 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD1_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x0000007b |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD1_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD1_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD1_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD1_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_DIV :: PDIV [12:10] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_PDIV_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_PDIV_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_NDIV_INT_DEFAULT 0x000000a4 |
| |
| /*************************************************************************** |
| *PLL_AVD1_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD1_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000006 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD1_PLL_LDO_PWRDN - LDO Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD1_PLL_LDO_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_LDO_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_LDO_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_LDO_PWRDN :: LDO_PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_LDO_PWRDN_LDO_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_LDO_PWRDN_LDO_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_LDO_PWRDN_LDO_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD1_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD1_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AVD1_PLL_MISC - Miscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD1_PLL_MISC :: reserved0 [31:31] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_reserved0_MASK 0x80000000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_reserved0_SHIFT 31 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_MISC :: VCO_DLY [30:29] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCO_DLY_MASK 0x60000000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCO_DLY_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCO_DLY_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_MISC :: VCODIV2 [28:28] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCODIV2_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCODIV2_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCODIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_MISC :: STAT_UPDATE [27:27] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_UPDATE_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_UPDATE_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_MISC :: STAT_SELECT [26:24] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_SELECT_MASK 0x07000000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_SELECT_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_MISC :: STAT_RESET_ [23:23] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_RESET__MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_RESET__SHIFT 23 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_MISC :: STAT_MODE [22:21] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_MODE_MASK 0x00600000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_MODE_SHIFT 21 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_MISC :: REFCLKOUT [20:20] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_REFCLKOUT_MASK 0x00100000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_REFCLKOUT_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_MISC :: PWM_RATE [19:18] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_PWM_RATE_MASK 0x000c0000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_PWM_RATE_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_PWM_RATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_MISC :: POR_BYPASS [17:17] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_POR_BYPASS_MASK 0x00020000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_POR_BYPASS_SHIFT 17 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_POR_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_MISC :: NDIV_RELOCK [16:16] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_NDIV_RELOCK_MASK 0x00010000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_NDIV_RELOCK_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_MISC :: LDO_REF_SEL [15:15] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_LDO_REF_SEL_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_LDO_REF_SEL_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_LDO_REF_SEL_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_MISC :: FAST_LOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_FAST_LOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_FAST_LOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD1_PLL_MISC2 - Miscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD1_PLL_MISC2 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_MISC2 :: SPARE [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2_SPARE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2_SPARE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2_SPARE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD1_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD1_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD1_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD1_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AVD1_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD1_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_HIF_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:15] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffff8000 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 15 |
| |
| /* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [14:14] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [12:10] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [09:02] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000003fc |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000001b |
| |
| /* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: CML_CLOCK_EN_CH0 [01:01] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CML_CLOCK_EN_CH0_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CML_CLOCK_EN_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CML_CLOCK_EN_CH0_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_HIF_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_HIF_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_HIF_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_HIF_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_HIF_PLL_DIV :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_DIV_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_DIV_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_HIF_PLL_DIV :: PDIV [10:08] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_DIV_PDIV_MASK 0x00000700 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_DIV_PDIV_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_DIV_PDIV_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_HIF_PLL_DIV :: NDIV_INT [07:00] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_DIV_NDIV_INT_MASK 0x000000ff |
| #define BCHP_CLKGEN_PLL_HIF_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_DIV_NDIV_INT_DEFAULT 0x00000032 |
| |
| /*************************************************************************** |
| *PLL_HIF_PLL_FRAC - Fractional |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_HIF_PLL_FRAC :: reserved0 [31:20] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_FRAC_reserved0_MASK 0xfff00000 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_FRAC_reserved0_SHIFT 20 |
| |
| /* CLKGEN :: PLL_HIF_PLL_FRAC :: FRAC_CONTROL [19:00] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff |
| #define BCHP_CLKGEN_PLL_HIF_PLL_FRAC_FRAC_CONTROL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_HIF_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_HIF_PLL_GAIN :: reserved0 [31:10] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_reserved0_MASK 0xfffffc00 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_reserved0_SHIFT 10 |
| |
| /* CLKGEN :: PLL_HIF_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008 |
| |
| /* CLKGEN :: PLL_HIF_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: PLL_HIF_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003 |
| |
| /*************************************************************************** |
| *PLL_HIF_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_HIF_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_HIF_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_HIF_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_HIF_PLL_MISC - Miscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_HIF_PLL_MISC :: reserved0 [31:28] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_reserved0_MASK 0xf0000000 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_reserved0_SHIFT 28 |
| |
| /* CLKGEN :: PLL_HIF_PLL_MISC :: VCODIV2 [27:27] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_VCODIV2_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_VCODIV2_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_VCODIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_HIF_PLL_MISC :: STAT_UPDATE [26:26] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_UPDATE_MASK 0x04000000 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_UPDATE_SHIFT 26 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_HIF_PLL_MISC :: STAT_SELECT [25:23] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_SELECT_MASK 0x03800000 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_SELECT_SHIFT 23 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_HIF_PLL_MISC :: STAT_RESET_ [22:22] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_RESET__MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_RESET__SHIFT 22 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_HIF_PLL_MISC :: REFCLKOUT [21:21] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_REFCLKOUT_MASK 0x00200000 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_REFCLKOUT_SHIFT 21 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_HIF_PLL_MISC :: LDO_CONTROL [20:19] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_LDO_CONTROL_MASK 0x00180000 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_LDO_CONTROL_SHIFT 19 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_LDO_CONTROL_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_HIF_PLL_MISC :: HYST_EN [18:18] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_HYST_EN_MASK 0x00040000 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_HYST_EN_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_HYST_EN_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_HIF_PLL_MISC :: DIGITAL_LDO_CONTROL [17:16] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DIGITAL_LDO_CONTROL_MASK 0x00030000 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DIGITAL_LDO_CONTROL_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DIGITAL_LDO_CONTROL_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_HIF_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [15:15] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_HIF_PLL_MISC :: DCO_CTRL_BYPASS [14:03] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00007ff8 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_HIF_PLL_MISC :: AUX_CTRL [02:02] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_AUX_CTRL_MASK 0x00000004 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_AUX_CTRL_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_HIF_PLL_MISC :: ANALOG_LDO_CONTROL [01:00] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_ANALOG_LDO_CONTROL_MASK 0x00000003 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_ANALOG_LDO_CONTROL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_MISC_ANALOG_LDO_CONTROL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_HIF_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_HIF_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_HIF_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_HIF_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_HIF_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_HIF_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_HIF_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_HIF_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_HIF_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_HIF_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_HIF_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_HIF_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_HIF_PLL_TRI_EN - Cml buffer Tristate enable |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_HIF_PLL_TRI_EN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_HIF_PLL_TRI_EN :: TRI_EN [00:00] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN_TRI_EN_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN_TRI_EN_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN_TRI_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000064 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_DIV :: PDIV [12:10] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_DEFAULT 0x00000068 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_FRAC - Fractional |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_FRAC :: reserved0 [31:20] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_FRAC_reserved0_MASK 0xfff00000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_FRAC_reserved0_SHIFT 20 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_FRAC :: FRAC_CONTROL [19:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_FRAC_FRAC_CONTROL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_LDO_PWRDN - LDO Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_LDO_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LDO_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LDO_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_LDO_PWRDN :: LDO_PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LDO_PWRDN_LDO_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LDO_PWRDN_LDO_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LDO_PWRDN_LDO_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_MISC - Miscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: reserved0 [31:31] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_MASK 0x80000000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_SHIFT 31 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: VCO_DLY [30:29] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_MASK 0x60000000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: VCODIV2 [28:28] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_UPDATE [27:27] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_SELECT [26:24] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_MASK 0x07000000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_RESET_ [23:23] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__SHIFT 23 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_MODE [22:21] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_MASK 0x00600000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_SHIFT 21 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: REFCLKOUT [20:20] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_MASK 0x00100000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: PWM_RATE [19:18] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_MASK 0x000c0000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: POR_BYPASS [17:17] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_MASK 0x00020000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_SHIFT 17 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: NDIV_RELOCK [16:16] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_MASK 0x00010000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: LDO_REF_SEL [15:15] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: FAST_LOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_MISC2 - Miscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_MISC2 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC2 :: SPARE [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000c |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000024 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000009 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000009 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_DIV :: PDIV [12:10] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_DEFAULT 0x000000c8 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_LDO_PWRDN - LDO Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_LDO_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_LDO_PWRDN :: LDO_PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRDN_LDO_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRDN_LDO_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRDN_LDO_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_MISC - Miscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: reserved0 [31:31] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_reserved0_MASK 0x80000000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_reserved0_SHIFT 31 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_DLY [30:29] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_MASK 0x60000000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: VCODIV2 [28:28] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_UPDATE [27:27] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_SELECT [26:24] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_MASK 0x07000000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_RESET_ [23:23] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__SHIFT 23 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_MODE [22:21] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_MASK 0x00600000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_SHIFT 21 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: REFCLKOUT [20:20] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_MASK 0x00100000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: PWM_RATE [19:18] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_MASK 0x000c0000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: POR_BYPASS [17:17] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_MASK 0x00020000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_SHIFT 17 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: NDIV_RELOCK [16:16] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_MASK 0x00010000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: LDO_REF_SEL [15:15] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: FAST_LOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_MISC2 - Miscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_MISC2 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC2 :: SPARE [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000012 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000005a |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000001c |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_NETWORK_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_NETWORK_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_NETWORK_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_NETWORK_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_DIV :: PDIV [12:10] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_PDIV_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_PDIV_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_NDIV_INT_DEFAULT 0x0000007d |
| |
| /*************************************************************************** |
| *PLL_NETWORK_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_NETWORK_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000006 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_NETWORK_PLL_LDO_PWRDN - LDO Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_NETWORK_PLL_LDO_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_LDO_PWRDN :: LDO_PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRDN_LDO_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRDN_LDO_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRDN_LDO_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_NETWORK_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_NETWORK_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_NETWORK_PLL_MISC - Miscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_NETWORK_PLL_MISC :: reserved0 [31:31] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_reserved0_MASK 0x80000000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_reserved0_SHIFT 31 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_MISC :: VCO_DLY [30:29] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_DLY_MASK 0x60000000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_DLY_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_DLY_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_MISC :: VCODIV2 [28:28] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCODIV2_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCODIV2_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCODIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_UPDATE [27:27] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_UPDATE_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_UPDATE_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_SELECT [26:24] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_SELECT_MASK 0x07000000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_SELECT_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_RESET_ [23:23] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_RESET__MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_RESET__SHIFT 23 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_MODE [22:21] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_MODE_MASK 0x00600000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_MODE_SHIFT 21 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_MISC :: REFCLKOUT [20:20] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_REFCLKOUT_MASK 0x00100000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_REFCLKOUT_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_MISC :: PWM_RATE [19:18] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PWM_RATE_MASK 0x000c0000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PWM_RATE_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PWM_RATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_MISC :: POR_BYPASS [17:17] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_POR_BYPASS_MASK 0x00020000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_POR_BYPASS_SHIFT 17 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_POR_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_MISC :: NDIV_RELOCK [16:16] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_NDIV_RELOCK_MASK 0x00010000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_NDIV_RELOCK_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_MISC :: LDO_REF_SEL [15:15] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_LDO_REF_SEL_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_LDO_REF_SEL_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_LDO_REF_SEL_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_MISC :: FAST_LOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_FAST_LOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_FAST_LOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_NETWORK_PLL_MISC2 - Miscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_NETWORK_PLL_MISC2 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_MISC2 :: SPARE [00:00] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_SPARE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_SPARE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_SPARE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_NETWORK_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_NETWORK_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_NETWORK_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_NETWORK_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_NETWORK_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_NETWORK_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000007 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000007 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_DIV :: PDIV [12:10] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_DEFAULT 0x0000008f |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000009 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_LDO_PWRDN - LDO Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_LDO_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_LDO_PWRDN :: LDO_PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRDN_LDO_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRDN_LDO_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRDN_LDO_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_MISC - Miscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: reserved0 [31:31] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_reserved0_MASK 0x80000000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_reserved0_SHIFT 31 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCO_DLY [30:29] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_MASK 0x60000000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCODIV2 [28:28] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_UPDATE [27:27] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_SELECT [26:24] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_MASK 0x07000000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_RESET_ [23:23] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__SHIFT 23 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_MODE [22:21] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_MASK 0x00600000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_SHIFT 21 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: REFCLKOUT [20:20] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_MASK 0x00100000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: PWM_RATE [19:18] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_MASK 0x000c0000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: POR_BYPASS [17:17] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_MASK 0x00020000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_SHIFT 17 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: NDIV_RELOCK [16:16] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_MASK 0x00010000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: LDO_REF_SEL [15:15] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: FAST_LOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_MISC2 - Miscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: SPARE [00:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000030 |
| |
| /* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC0_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_SC0_PLL_DIV :: PDIV [12:10] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_SC0_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_FRAC - Fractional |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_FRAC :: reserved0 [31:20] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_reserved0_MASK 0xfff00000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_reserved0_SHIFT 20 |
| |
| /* CLKGEN :: PLL_SC0_PLL_FRAC :: FRAC_CONTROL [19:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff |
| #define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_SC0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008 |
| |
| /* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_SC0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: reserved0 [31:30] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_reserved0_MASK 0xc0000000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_reserved0_SHIFT 30 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: VCO_DLY [29:28] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_DLY_MASK 0x30000000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_DLY_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_DLY_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: VCODIV2_POST [27:27] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCODIV2_POST_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCODIV2_POST_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCODIV2_POST_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: VCODIV2 [26:26] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCODIV2_MASK 0x04000000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCODIV2_SHIFT 26 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCODIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_UPDATE [25:25] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_MASK 0x02000000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_SHIFT 25 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_SELECT [24:22] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_MASK 0x01c00000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_RESET_ [21:21] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET__MASK 0x00200000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET__SHIFT 21 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_MODE [20:19] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_MASK 0x00180000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_SHIFT 19 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: REFCLKOUT [18:18] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_REFCLKOUT_MASK 0x00040000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_REFCLKOUT_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: PWM_RATE [17:16] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_MASK 0x00030000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: MDIV_RELOCK [15:15] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_MDIV_RELOCK_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_MDIV_RELOCK_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_MDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: FAST_LOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SC0_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC0_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SC0_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_SC0_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000030 |
| |
| /* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC1_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_SC1_PLL_DIV :: PDIV [12:10] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_SC1_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_FRAC - Fractional |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_FRAC :: reserved0 [31:20] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_reserved0_MASK 0xfff00000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_reserved0_SHIFT 20 |
| |
| /* CLKGEN :: PLL_SC1_PLL_FRAC :: FRAC_CONTROL [19:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff |
| #define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_SC1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008 |
| |
| /* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_SC1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: reserved0 [31:30] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_reserved0_MASK 0xc0000000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_reserved0_SHIFT 30 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: VCO_DLY [29:28] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_DLY_MASK 0x30000000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_DLY_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_DLY_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: VCODIV2_POST [27:27] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCODIV2_POST_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCODIV2_POST_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCODIV2_POST_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: VCODIV2 [26:26] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCODIV2_MASK 0x04000000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCODIV2_SHIFT 26 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCODIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_UPDATE [25:25] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_MASK 0x02000000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_SHIFT 25 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_SELECT [24:22] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_MASK 0x01c00000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_RESET_ [21:21] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET__MASK 0x00200000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET__SHIFT 21 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_MODE [20:19] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_MASK 0x00180000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_SHIFT 19 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: REFCLKOUT [18:18] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_REFCLKOUT_MASK 0x00040000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_REFCLKOUT_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: PWM_RATE [17:16] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_MASK 0x00030000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: MDIV_RELOCK [15:15] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_MDIV_RELOCK_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_MDIV_RELOCK_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_MDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: FAST_LOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SC1_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC1_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SC1_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_SC1_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000012 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000c |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x000000a2 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000e |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [12:10] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT 0x00000048 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x0000000a |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_LDO_PWRDN - LDO Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_LDO_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_LDO_PWRDN :: LDO_PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRDN_LDO_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRDN_LDO_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRDN_LDO_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_MISC - Miscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: reserved0 [31:31] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_MASK 0x80000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_SHIFT 31 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DLY [30:29] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_MASK 0x60000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: VCODIV2 [28:28] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [27:27] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [26:24] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK 0x07000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET_ [23:23] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__SHIFT 23 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [22:21] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK 0x00600000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT 21 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: REFCLKOUT [20:20] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_MASK 0x00100000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [19:18] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK 0x000c0000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: POR_BYPASS [17:17] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_MASK 0x00020000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_SHIFT 17 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK 0x00010000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: LDO_REF_SEL [15:15] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_MISC2 - Miscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_MISC2 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC2 :: SPARE [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_RESET :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_RESET :: RESETD [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000004b |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO0_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO0_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO0_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO0_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_DIV :: PDIV [12:10] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_DEFAULT 0x00000040 |
| |
| /*************************************************************************** |
| *PLL_VCXO0_PLL_FRAC - Fractional |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO0_PLL_FRAC :: reserved0 [31:20] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_reserved0_MASK 0xfff00000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_reserved0_SHIFT 20 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_FRAC :: FRAC_CONTROL [19:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO0_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO0_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO0_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO0_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO0_PLL_MISC :: reserved0 [31:30] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_reserved0_MASK 0xc0000000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_reserved0_SHIFT 30 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCO_DLY [29:28] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DLY_MASK 0x30000000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DLY_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DLY_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCODIV2_POST [27:27] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_POST_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_POST_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_POST_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCODIV2 [26:26] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_MASK 0x04000000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_SHIFT 26 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_UPDATE [25:25] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_MASK 0x02000000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_SHIFT 25 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_SELECT [24:22] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_MASK 0x01c00000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_RESET_ [21:21] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET__MASK 0x00200000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET__SHIFT 21 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_MODE [20:19] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_MASK 0x00180000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_SHIFT 19 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_MISC :: REFCLKOUT [18:18] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REFCLKOUT_MASK 0x00040000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REFCLKOUT_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_MISC :: PWM_RATE [17:16] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_MASK 0x00030000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_MISC :: MDIV_RELOCK [15:15] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_MDIV_RELOCK_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_MDIV_RELOCK_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_MDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_MISC :: FAST_LOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO0_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO0_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO0_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO0_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO0_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO0_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000004b |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO1_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO1_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO1_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO1_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_DIV :: PDIV [12:10] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_DEFAULT 0x00000040 |
| |
| /*************************************************************************** |
| *PLL_VCXO1_PLL_FRAC - Fractional |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO1_PLL_FRAC :: reserved0 [31:20] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_reserved0_MASK 0xfff00000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_reserved0_SHIFT 20 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_FRAC :: FRAC_CONTROL [19:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO1_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO1_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO1_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO1_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO1_PLL_MISC :: reserved0 [31:30] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_reserved0_MASK 0xc0000000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_reserved0_SHIFT 30 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCO_DLY [29:28] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DLY_MASK 0x30000000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DLY_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DLY_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCODIV2_POST [27:27] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_POST_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_POST_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_POST_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCODIV2 [26:26] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_MASK 0x04000000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_SHIFT 26 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_UPDATE [25:25] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_MASK 0x02000000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_SHIFT 25 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_SELECT [24:22] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_MASK 0x01c00000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_RESET_ [21:21] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET__MASK 0x00200000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET__SHIFT 21 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_MODE [20:19] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_MASK 0x00180000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_SHIFT 19 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_MISC :: REFCLKOUT [18:18] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REFCLKOUT_MASK 0x00040000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REFCLKOUT_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_MISC :: PWM_RATE [17:16] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_MASK 0x00030000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_MISC :: MDIV_RELOCK [15:15] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_MDIV_RELOCK_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_MDIV_RELOCK_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_MDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_MISC :: FAST_LOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO1_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO1_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO1_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO1_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO1_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO1_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000004b |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO2_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO2_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO2_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO2_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_DIV :: PDIV [12:10] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_DEFAULT 0x00000040 |
| |
| /*************************************************************************** |
| *PLL_VCXO2_PLL_FRAC - Fractional |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO2_PLL_FRAC :: reserved0 [31:20] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_reserved0_MASK 0xfff00000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_reserved0_SHIFT 20 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_FRAC :: FRAC_CONTROL [19:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO2_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO2_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO2_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO2_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO2_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO2_PLL_MISC :: reserved0 [31:30] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_reserved0_MASK 0xc0000000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_reserved0_SHIFT 30 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCO_DLY [29:28] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DLY_MASK 0x30000000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DLY_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DLY_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCODIV2_POST [27:27] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_POST_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_POST_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_POST_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCODIV2 [26:26] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_MASK 0x04000000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_SHIFT 26 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_UPDATE [25:25] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_MASK 0x02000000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_SHIFT 25 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_SELECT [24:22] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_MASK 0x01c00000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_RESET_ [21:21] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET__MASK 0x00200000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET__SHIFT 21 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_MODE [20:19] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_MASK 0x00180000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_SHIFT 19 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_MISC :: REFCLKOUT [18:18] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REFCLKOUT_MASK 0x00040000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REFCLKOUT_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_MISC :: PWM_RATE [17:16] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_MASK 0x00030000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_MISC :: MDIV_RELOCK [15:15] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_MDIV_RELOCK_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_MDIV_RELOCK_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_MDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_MISC :: FAST_LOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO2_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO2_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO2_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO2_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO2_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO2_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000000d |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000a |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000000a |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000d |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_XPT_PLL_DIV :: PDIV [12:10] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_MASK 0x00001c00 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_XPT_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_DEFAULT 0x00000082 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_XPT_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000009 |
| |
| /* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x000000e0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004 |
| |
| /* CLKGEN :: PLL_XPT_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_LDO_PWRDN - LDO Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_LDO_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_XPT_PLL_LDO_PWRDN :: LDO_PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRDN_LDO_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRDN_LDO_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRDN_LDO_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1 |
| |
| /* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_MISC - Miscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: reserved0 [31:31] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_reserved0_MASK 0x80000000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_reserved0_SHIFT 31 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: VCO_DLY [30:29] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_DLY_MASK 0x60000000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_DLY_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_DLY_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: VCODIV2 [28:28] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCODIV2_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCODIV2_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCODIV2_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_UPDATE [27:27] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_SELECT [26:24] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_MASK 0x07000000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_RESET_ [23:23] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET__MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET__SHIFT 23 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET__DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_MODE [22:21] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_MASK 0x00600000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_SHIFT 21 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: REFCLKOUT [20:20] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_REFCLKOUT_MASK 0x00100000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_REFCLKOUT_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_REFCLKOUT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: PWM_RATE [19:18] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_MASK 0x000c0000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: POR_BYPASS [17:17] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POR_BYPASS_MASK 0x00020000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POR_BYPASS_SHIFT 17 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POR_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: NDIV_RELOCK [16:16] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_MASK 0x00010000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: LDO_REF_SEL [15:15] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_LDO_REF_SEL_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_LDO_REF_SEL_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_LDO_REF_SEL_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: FAST_LOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_MISC2 - Miscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_MISC2 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC2 :: SPARE [00:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_SPARE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_SPARE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_SPARE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_XPT_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_XPT_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_PWRDN_PWRDN_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_RESET :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_RESET_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_XPT_PLL_RESET_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_XPT_PLL_RESET :: RESETD [00:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_XPT_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *AVD0_TOP_INST_CLOCK_ENABLE - Avd0 top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE :: AVD1_SCB_CLOCK_ENABLE [03:03] */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_SCB_CLOCK_ENABLE_MASK 0x00000008 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_SCB_CLOCK_ENABLE_SHIFT 3 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE :: AVD1_CPU_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_CPU_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_CPU_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_CPU_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE :: AVD1_CORE_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_CORE_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_CORE_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_CORE_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE :: AVD1_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *AVD0_TOP_INST_CLOCK_ENABLE_SID - Avd0 top inst clock enable sid |
| ***************************************************************************/ |
| /* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE_SID :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_SID_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_SID_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE_SID :: SID_216_CLOCK_ENABLE_SID [00:00] */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_SID_SID_216_CLOCK_ENABLE_SID_MASK 0x00000001 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_SID_SID_216_CLOCK_ENABLE_SID_SHIFT 0 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_SID_SID_216_CLOCK_ENABLE_SID_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *AVD0_TOP_INST_CLOCK_ENABLE_SID_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE_SID_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_SID_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_SID_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE_SID_STATUS :: SID_216_CLOCK_ENABLE_SID_STATUS [00:00] */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_SID_STATUS_SID_216_CLOCK_ENABLE_SID_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_SID_STATUS_SID_216_CLOCK_ENABLE_SID_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *AVD0_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE_STATUS :: AVD1_SCB_CLOCK_ENABLE_STATUS [03:03] */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_STATUS_AVD1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_STATUS_AVD1_SCB_CLOCK_ENABLE_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE_STATUS :: AVD1_CPU_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_STATUS_AVD1_CPU_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_STATUS_AVD1_CPU_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE_STATUS :: AVD1_CORE_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_STATUS_AVD1_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_STATUS_AVD1_CORE_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE_STATUS :: AVD1_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_STATUS_AVD1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_STATUS_AVD1_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *AVD0_TOP_INST_MEMORY_STANDBY_ENABLE - Avd0 top inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: AVD0_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_AVD0_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: AVD0_TOP_INST_MEMORY_STANDBY_ENABLE :: AVD1_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_MEMORY_STANDBY_ENABLE_AVD1_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_MEMORY_STANDBY_ENABLE_AVD1_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_MEMORY_STANDBY_ENABLE_AVD1_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *AVD0_TOP_INST_OBSERVE_CLOCK - Avd0 top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: AVD0_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: AVD0_TOP_INST_OBSERVE_CLOCK :: AVD1_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: AVD0_TOP_INST_OBSERVE_CLOCK :: AVD1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: AVD0_TOP_INST_OBSERVE_CLOCK :: AVD1_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK_AVD1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK_AVD1_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK_AVD1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *AVD0_TOP_INST_POWER_SWITCH_MEMORY - Avd0 top inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: AVD0_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_AVD0_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: AVD0_TOP_INST_POWER_SWITCH_MEMORY :: AVD1_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_AVD0_TOP_INST_POWER_SWITCH_MEMORY_AVD1_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_POWER_SWITCH_MEMORY_AVD1_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_AVD0_TOP_INST_POWER_SWITCH_MEMORY_AVD1_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BVN_MVP_TOP_INST_CLOCK_ENABLE - Bvn mvp top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_SCB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_216_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_216_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_216_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_SCB_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_SCB_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_216_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_216_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_216_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *BVN_MVP_TOP_INST_MEMORY_STANDBY_ENABLE - Bvn mvp top inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: BVN_MVP_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: BVN_MVP_TOP_INST_MEMORY_STANDBY_ENABLE :: BVND_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_MEMORY_STANDBY_ENABLE_BVND_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_MEMORY_STANDBY_ENABLE_BVND_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_MEMORY_STANDBY_ENABLE_BVND_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BVN_MVP_TOP_INST_POWER_SWITCH_MEMORY - Bvn mvp top inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: BVN_MVP_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: BVN_MVP_TOP_INST_POWER_SWITCH_MEMORY :: BVND_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_POWER_SWITCH_MEMORY_BVND_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_POWER_SWITCH_MEMORY_BVND_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_BVN_MVP_TOP_INST_POWER_SWITCH_MEMORY_BVND_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BVN_TOP_INST_CLOCK_ENABLE - Bvn top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_SCB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_216_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *BVN_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_SCB_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_SCB_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_216_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_216_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_216_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *BVN_TOP_INST_MEMORY_STANDBY_ENABLE - Bvn top inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: BVN_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: BVN_TOP_INST_MEMORY_STANDBY_ENABLE :: BVN_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BVN_TOP_INST_POWER_SWITCH_MEMORY - Bvn top inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: BVN_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: BVN_TOP_INST_POWER_SWITCH_MEMORY :: BVN_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_OSC_DIGITAL_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_AVS_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CLKGEN_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: DISABLE_OSC_DIGITAL_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_OSC_DIGITAL_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_OSC_DIGITAL_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: DISABLE_AVS_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_AVS_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_AVS_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_CONTROL - Clock Monitor Control |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK 0x00000008 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT 3 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK 0x00000004 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT 2 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK 0x00000002 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT 1 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff |
| #define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 0xffffffff |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK 0xffffffff |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK 0x00000001 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT 0 |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff |
| #define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *CORE_XPT_INST_CLOCK_DISABLE - Disable CORE_XPT_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CORE_XPT_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_81_CLOCK_STATUS [04:04] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_81_CLOCK_STATUS_MASK 0x00000010 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_81_CLOCK_STATUS_SHIFT 4 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_54_CLOCK_STATUS [03:03] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_54_CLOCK_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_54_CLOCK_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_40P5_CLOCK_STATUS [02:02] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_40P5_CLOCK_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_40P5_CLOCK_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_27_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_27_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_27_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_20P25_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_20P25_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_20P25_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *CORE_XPT_INST_CLOCK_ENABLE - Core xpt inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [03:03] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000008 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 3 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_CORE_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_216_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *CORE_XPT_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_SCB_CLOCK_ENABLE_STATUS [03:03] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_SCB_CLOCK_ENABLE_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_CORE_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_CORE_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_216_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_216_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_216_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *CORE_XPT_INST_MEMORY_STANDBY_ENABLE - Core xpt inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: CORE_XPT_INST_MEMORY_STANDBY_ENABLE :: XPT_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CORE_XPT_INST_OBSERVE_CLOCK - Core xpt inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CORE_XPT_INST_POWER_SWITCH_MEMORY - Core xpt inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: CORE_XPT_INST_POWER_SWITCH_MEMORY :: XPT_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE - Disable DUAL_GENET_TOP_DUAL_RGMII_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET_PLL_CLOCK [08:08] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_PLL_CLOCK_MASK 0x00000100 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_PLL_CLOCK_SHIFT 8 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_PLL_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK [07:07] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_MASK 0x00000080 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_SHIFT 7 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_PM_CLOCK [06:06] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_MASK 0x00000040 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_SHIFT 6 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_FAST_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_ALWAYSON_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_ALWAYSON_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_ALWAYSON_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_ALWAYSON_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [03:03] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000008 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 3 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_FAST_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_ALWAYSON_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_ALWAYSON_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_ALWAYSON_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_ALWAYSON_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET_PLL_CLOCK_STATUS [08:08] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET_PLL_CLOCK_STATUS_MASK 0x00000100 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET_PLL_CLOCK_STATUS_SHIFT 8 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK_STATUS [07:07] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_STATUS_MASK 0x00000080 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_STATUS_SHIFT 7 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_SYSTEM_PM_CLOCK_STATUS [06:06] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_PM_CLOCK_STATUS_MASK 0x00000040 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_PM_CLOCK_STATUS_SHIFT 6 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_SYSTEM_FAST_CLOCK_STATUS [05:05] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_FAST_CLOCK_STATUS_MASK 0x00000020 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_FAST_CLOCK_STATUS_SHIFT 5 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_ALWAYSON_CLOCK_STATUS [04:04] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_ALWAYSON_CLOCK_STATUS_MASK 0x00000010 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_ALWAYSON_CLOCK_STATUS_SHIFT 4 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS [03:03] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS [02:02] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_ALWAYSON_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_ALWAYSON_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_ALWAYSON_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE - Dual genet top dual rgmii inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 - Dual genet top dual rgmii inst clock enable genet0 |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0 [08:08] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_MASK 0x00000100 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_SHIFT 8 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0 [07:07] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_MASK 0x00000080 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_SHIFT 7 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_SCB_CLOCK_ENABLE_GENET0 [06:06] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_SCB_CLOCK_ENABLE_GENET0_MASK 0x00000040 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_SCB_CLOCK_ENABLE_GENET0_SHIFT 6 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_SCB_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_L2INTR_CLOCK_ENABLE_GENET0 [05:05] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_L2INTR_CLOCK_ENABLE_GENET0_MASK 0x00000020 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_L2INTR_CLOCK_ENABLE_GENET0_SHIFT 5 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_L2INTR_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_HFB_CLOCK_ENABLE_GENET0 [04:04] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_HFB_CLOCK_ENABLE_GENET0_MASK 0x00000010 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_HFB_CLOCK_ENABLE_GENET0_SHIFT 4 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_HFB_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_GMII_CLOCK_ENABLE_GENET0 [03:03] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GMII_CLOCK_ENABLE_GENET0_MASK 0x00000008 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GMII_CLOCK_ENABLE_GENET0_SHIFT 3 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GMII_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_EEE_CLOCK_ENABLE_GENET0 [02:02] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_EEE_CLOCK_ENABLE_GENET0_MASK 0x00000004 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_EEE_CLOCK_ENABLE_GENET0_SHIFT 2 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_EEE_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_CLK_250_CLOCK_ENABLE_GENET0 [01:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_CLK_250_CLOCK_ENABLE_GENET0_MASK 0x00000002 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_CLK_250_CLOCK_ENABLE_GENET0_SHIFT 1 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_CLK_250_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_108_CLOCK_ENABLE_GENET0 [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_108_CLOCK_ENABLE_GENET0_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_108_CLOCK_ENABLE_GENET0_SHIFT 0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_108_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_STATUS [08:08] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000100 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_STATUS_SHIFT 8 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_STATUS [07:07] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000080 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_STATUS_SHIFT 7 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_SCB_CLOCK_ENABLE_GENET0_STATUS [06:06] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_SCB_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000040 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_SCB_CLOCK_ENABLE_GENET0_STATUS_SHIFT 6 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_L2INTR_CLOCK_ENABLE_GENET0_STATUS [05:05] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_L2INTR_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000020 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_L2INTR_CLOCK_ENABLE_GENET0_STATUS_SHIFT 5 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_HFB_CLOCK_ENABLE_GENET0_STATUS [04:04] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_HFB_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000010 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_HFB_CLOCK_ENABLE_GENET0_STATUS_SHIFT 4 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_GMII_CLOCK_ENABLE_GENET0_STATUS [03:03] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_GMII_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_GMII_CLOCK_ENABLE_GENET0_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_EEE_CLOCK_ENABLE_GENET0_STATUS [02:02] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_EEE_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_EEE_CLOCK_ENABLE_GENET0_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_CLK_250_CLOCK_ENABLE_GENET0_STATUS [01:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_CLK_250_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_CLK_250_CLOCK_ENABLE_GENET0_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_108_CLOCK_ENABLE_GENET0_STATUS [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_108_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_108_CLOCK_ENABLE_GENET0_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 - Dual genet top dual rgmii inst clock enable genet1 |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1 [08:08] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_MASK 0x00000100 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_SHIFT 8 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1 [07:07] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_MASK 0x00000080 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_SHIFT 7 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_SCB_CLOCK_ENABLE_GENET1 [06:06] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_SCB_CLOCK_ENABLE_GENET1_MASK 0x00000040 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_SCB_CLOCK_ENABLE_GENET1_SHIFT 6 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_SCB_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_L2INTR_CLOCK_ENABLE_GENET1 [05:05] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_L2INTR_CLOCK_ENABLE_GENET1_MASK 0x00000020 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_L2INTR_CLOCK_ENABLE_GENET1_SHIFT 5 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_L2INTR_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_HFB_CLOCK_ENABLE_GENET1 [04:04] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_HFB_CLOCK_ENABLE_GENET1_MASK 0x00000010 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_HFB_CLOCK_ENABLE_GENET1_SHIFT 4 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_HFB_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_GMII_CLOCK_ENABLE_GENET1 [03:03] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GMII_CLOCK_ENABLE_GENET1_MASK 0x00000008 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GMII_CLOCK_ENABLE_GENET1_SHIFT 3 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GMII_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_EEE_CLOCK_ENABLE_GENET1 [02:02] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_EEE_CLOCK_ENABLE_GENET1_MASK 0x00000004 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_EEE_CLOCK_ENABLE_GENET1_SHIFT 2 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_EEE_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_CLK_250_CLOCK_ENABLE_GENET1 [01:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_CLK_250_CLOCK_ENABLE_GENET1_MASK 0x00000002 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_CLK_250_CLOCK_ENABLE_GENET1_SHIFT 1 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_CLK_250_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_108_CLOCK_ENABLE_GENET1 [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_108_CLOCK_ENABLE_GENET1_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_108_CLOCK_ENABLE_GENET1_SHIFT 0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_108_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_STATUS [08:08] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000100 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_STATUS_SHIFT 8 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_STATUS [07:07] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000080 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_STATUS_SHIFT 7 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_SCB_CLOCK_ENABLE_GENET1_STATUS [06:06] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_SCB_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000040 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_SCB_CLOCK_ENABLE_GENET1_STATUS_SHIFT 6 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_L2INTR_CLOCK_ENABLE_GENET1_STATUS [05:05] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_L2INTR_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000020 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_L2INTR_CLOCK_ENABLE_GENET1_STATUS_SHIFT 5 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_HFB_CLOCK_ENABLE_GENET1_STATUS [04:04] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_HFB_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000010 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_HFB_CLOCK_ENABLE_GENET1_STATUS_SHIFT 4 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_GMII_CLOCK_ENABLE_GENET1_STATUS [03:03] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_GMII_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_GMII_CLOCK_ENABLE_GENET1_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_EEE_CLOCK_ENABLE_GENET1_STATUS [02:02] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_EEE_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_EEE_CLOCK_ENABLE_GENET1_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_CLK_250_CLOCK_ENABLE_GENET1_STATUS [01:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_CLK_250_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_CLK_250_CLOCK_ENABLE_GENET1_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_108_CLOCK_ENABLE_GENET1_STATUS [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_108_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_108_CLOCK_ENABLE_GENET1_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS :: GENET_SCB_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS_GENET_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS_GENET_SCB_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0 - Dual genet top dual rgmii inst clock select genet0 |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0 :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0 :: GENET0_GMII_CLOCK_SELECT_GENET0 [01:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_GMII_CLOCK_SELECT_GENET0_MASK 0x00000002 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_GMII_CLOCK_SELECT_GENET0_SHIFT 1 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_GMII_CLOCK_SELECT_GENET0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0 :: GENET0_CLOCK_SELECT_GENET0 [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_CLOCK_SELECT_GENET0_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_CLOCK_SELECT_GENET0_SHIFT 0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_CLOCK_SELECT_GENET0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1 - Dual genet top dual rgmii inst clock select genet1 |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1 :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1 :: GENET1_GMII_CLOCK_SELECT_GENET1 [01:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_GMII_CLOCK_SELECT_GENET1_MASK 0x00000002 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_GMII_CLOCK_SELECT_GENET1_SHIFT 1 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_GMII_CLOCK_SELECT_GENET1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1 :: GENET1_CLOCK_SELECT_GENET1 [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_CLOCK_SELECT_GENET1_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_CLOCK_SELECT_GENET1_SHIFT 0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_CLOCK_SELECT_GENET1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK - Dual genet top dual rgmii inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DVP_HR_INST_CLOCK_DISABLE - Disable DVP_HR_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE :: DISABLE_DVPHR_ALWAYSON_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DVP_HR_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE_STATUS :: DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DVP_HR_INST_CLOCK_ENABLE - Dvp hr inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_ALTERNATE_216_CLOCK_ENABLE [04:04] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000010 |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE_216_CLOCK_ENABLE_SHIFT 4 |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_ALTERNATE2_108_CLOCK_ENABLE [03:03] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE2_108_CLOCK_ENABLE_MASK 0x00000008 |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE2_108_CLOCK_ENABLE_SHIFT 3 |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE2_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_324_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_324_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_324_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_324_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_216_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_216_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_216_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DVP_HR_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_ALTERNATE_216_CLOCK_ENABLE_STATUS [04:04] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_ALTERNATE_216_CLOCK_ENABLE_STATUS_MASK 0x00000010 |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_ALTERNATE_216_CLOCK_ENABLE_STATUS_SHIFT 4 |
| |
| /* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_ALTERNATE2_108_CLOCK_ENABLE_STATUS [03:03] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_ALTERNATE2_108_CLOCK_ENABLE_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_ALTERNATE2_108_CLOCK_ENABLE_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_324_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_324_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_324_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_216_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_216_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_216_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DVP_HR_INST_MEMORY_STANDBY_ENABLE - Dvp hr inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HR_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DVP_HR_INST_MEMORY_STANDBY_ENABLE :: DVPHR_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_DVPHR_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_DVPHR_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_DVPHR_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DVP_HR_INST_OBSERVE_CLOCK - Dvp hr inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DVP_HR_INST_POWER_SWITCH_MEMORY - Dvp hr inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HR_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: DVP_HR_INST_POWER_SWITCH_MEMORY :: DVPHR_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_DVPHR_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_DVPHR_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_DVPHR_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DVP_HT_INST_CLOCK_DISABLE - Disable DVP_HT_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DVP_HT_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE_STATUS :: DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DVP_HT_INST_CLOCK_ENABLE - Dvp ht inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_ALTERNATE_216_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_216_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DVP_HT_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: DVPHT_ALTERNATE_216_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_ALTERNATE_216_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_ALTERNATE_216_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: DVPHT_216_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_216_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_216_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: DVPHT_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DVP_HT_INST_ENABLE - Dvp ht inst enable |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_INST_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_DVP_HT_INST_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: DVP_HT_INST_ENABLE :: DVPHT_CLK_VEC_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_ENABLE_DVPHT_CLK_VEC_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_DVP_HT_INST_ENABLE_DVPHT_CLK_VEC_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_DVP_HT_INST_ENABLE_DVPHT_CLK_VEC_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DVP_HT_INST_ENABLE :: DVPHT_CLK_MAX_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_ENABLE_DVPHT_CLK_MAX_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HT_INST_ENABLE_DVPHT_CLK_MAX_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HT_INST_ENABLE_DVPHT_CLK_MAX_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DVP_HT_INST_MEMORY_STANDBY_ENABLE - Dvp ht inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DVP_HT_INST_MEMORY_STANDBY_ENABLE :: DVPHT_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DVP_HT_INST_OBSERVE_CLOCK - Dvp ht inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DVP_HT_INST_POWER_SWITCH_MEMORY - Dvp ht inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: DVP_HT_INST_POWER_SWITCH_MEMORY :: DVPHT_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GRAPHICS_INST_CLOCK_ENABLE - Graphics inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_SCB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *GRAPHICS_INST_CLOCK_ENABLE_M2MC0 - Graphics inst clock enable m2mc0 |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0 :: GFX_M2MC0_CLOCK_ENABLE_M2MC0 [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_CLOCK_ENABLE_M2MC0_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_CLOCK_ENABLE_M2MC0_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_CLOCK_ENABLE_M2MC0_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS :: GFX_M2MC0_CLOCK_ENABLE_M2MC0_STATUS [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_GFX_M2MC0_CLOCK_ENABLE_M2MC0_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_GFX_M2MC0_CLOCK_ENABLE_M2MC0_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *GRAPHICS_INST_CLOCK_ENABLE_M2MC1 - Graphics inst clock enable m2mc1 |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1 :: GFX_M2MC1_CLOCK_ENABLE_M2MC1 [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_CLOCK_ENABLE_M2MC1_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_CLOCK_ENABLE_M2MC1_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_CLOCK_ENABLE_M2MC1_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS :: GFX_M2MC1_CLOCK_ENABLE_M2MC1_STATUS [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_M2MC1_CLOCK_ENABLE_M2MC1_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_M2MC1_CLOCK_ENABLE_M2MC1_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *GRAPHICS_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_STATUS :: GFX_SCB_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_GFX_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_GFX_SCB_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_STATUS :: GFX_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_GFX_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_GFX_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC0 - Graphics inst memory standby enable m2mc0 |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC0 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC0_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC0_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC0 :: GFX_M2MC0_MEMORY_STANDBY_ENABLE_M2MC0 [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC0_GFX_M2MC0_MEMORY_STANDBY_ENABLE_M2MC0_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC0_GFX_M2MC0_MEMORY_STANDBY_ENABLE_M2MC0_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC0_GFX_M2MC0_MEMORY_STANDBY_ENABLE_M2MC0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC1 - Graphics inst memory standby enable m2mc1 |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC1 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC1_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC1_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC1 :: GFX_M2MC1_MEMORY_STANDBY_ENABLE_M2MC1 [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC1_GFX_M2MC1_MEMORY_STANDBY_ENABLE_M2MC1_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC1_GFX_M2MC1_MEMORY_STANDBY_ENABLE_M2MC1_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC1_GFX_M2MC1_MEMORY_STANDBY_ENABLE_M2MC1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GRAPHICS_INST_OBSERVE_CLOCK - Graphics inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC0 - Graphics inst power switch memory m2mc0 |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC0 :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC0_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC0_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC0 :: GFX_M2MC0_POWER_SWITCH_MEMORY_M2MC0 [01:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC0_GFX_M2MC0_POWER_SWITCH_MEMORY_M2MC0_MASK 0x00000003 |
| #define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC0_GFX_M2MC0_POWER_SWITCH_MEMORY_M2MC0_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC0_GFX_M2MC0_POWER_SWITCH_MEMORY_M2MC0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC1 - Graphics inst power switch memory m2mc1 |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC1 :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC1_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC1_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC1 :: GFX_M2MC1_POWER_SWITCH_MEMORY_M2MC1 [01:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC1_GFX_M2MC1_POWER_SWITCH_MEMORY_M2MC1_MASK 0x00000003 |
| #define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC1_GFX_M2MC1_POWER_SWITCH_MEMORY_M2MC1_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC1_GFX_M2MC1_POWER_SWITCH_MEMORY_M2MC1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *HIF_INST_CLOCK_DISABLE - Disable HIF_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_INST_CLOCK_DISABLE :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_EBI_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [03:03] */ |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK 0x00000008 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT 3 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_EMMC_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CARD_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_ALWAYSON_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *HIF_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_EBI_CLOCK_STATUS [04:04] */ |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_EBI_CLOCK_STATUS_MASK 0x00000010 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_EBI_CLOCK_STATUS_SHIFT 4 |
| |
| /* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SPI_CLOCK_STATUS [03:03] */ |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS [02:02] */ |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SDIO_CARD_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_ALWAYSON_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_ALWAYSON_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_ALWAYSON_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *HIF_INST_MEMORY_STANDBY_ENABLE - Hif inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: HIF_INST_MEMORY_STANDBY_ENABLE :: HIF_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *HIF_INST_OBSERVE_CLOCK - Hif inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH - Hif inst pll hif ssc mode control high |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH :: reserved0 [31:20] */ |
| #define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xfff00000 |
| #define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 20 |
| |
| /* CLKGEN :: HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH :: SSC_STEP_PLL_HIF_SSC_MODE_CONTROL_HIGH [19:04] */ |
| #define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH_SSC_STEP_PLL_HIF_SSC_MODE_CONTROL_HIGH_MASK 0x000ffff0 |
| #define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH_SSC_STEP_PLL_HIF_SSC_MODE_CONTROL_HIGH_SHIFT 4 |
| #define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH_SSC_STEP_PLL_HIF_SSC_MODE_CONTROL_HIGH_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH :: SSC_CLK_DIV_PLL_HIF_SSC_MODE_CONTROL_HIGH [03:00] */ |
| #define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH_SSC_CLK_DIV_PLL_HIF_SSC_MODE_CONTROL_HIGH_MASK 0x0000000f |
| #define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH_SSC_CLK_DIV_PLL_HIF_SSC_MODE_CONTROL_HIGH_SHIFT 0 |
| #define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH_SSC_CLK_DIV_PLL_HIF_SSC_MODE_CONTROL_HIGH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW - Hif inst pll hif ssc mode control low |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW :: reserved0 [31:21] */ |
| #define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xffe00000 |
| #define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 21 |
| |
| /* CLKGEN :: HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW :: SSC_MODE_PLL_HIF_SSC_MODE_CONTROL_LOW [20:20] */ |
| #define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW_SSC_MODE_PLL_HIF_SSC_MODE_CONTROL_LOW_MASK 0x00100000 |
| #define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW_SSC_MODE_PLL_HIF_SSC_MODE_CONTROL_LOW_SHIFT 20 |
| #define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW_SSC_MODE_PLL_HIF_SSC_MODE_CONTROL_LOW_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW :: SSC_LIMIT_PLL_HIF_SSC_MODE_CONTROL_LOW [19:00] */ |
| #define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW_SSC_LIMIT_PLL_HIF_SSC_MODE_CONTROL_LOW_MASK 0x000fffff |
| #define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW_SSC_LIMIT_PLL_HIF_SSC_MODE_CONTROL_LOW_SHIFT 0 |
| #define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW_SSC_LIMIT_PLL_HIF_SSC_MODE_CONTROL_LOW_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *HIF_INST_POWER_SWITCH_MEMORY - Hif inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: HIF_INST_POWER_SWITCH_MEMORY :: HIF_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *INTERNAL_MUX_SELECT - Mux selects for Internal clocks |
| ***************************************************************************/ |
| /* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO2_REFERENCE_CLOCK [05:04] */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_MASK 0x00000030 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [03:02] */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x0000000c |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [01:00] */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000003 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ITU656_0_MUX_SELECT - Mux selects for itu656_0 clocks |
| ***************************************************************************/ |
| /* CLKGEN :: ITU656_0_MUX_SELECT :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_ITU656_0_MUX_SELECT_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_ITU656_0_MUX_SELECT_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: ITU656_0_MUX_SELECT :: VEC_ITU656_0_CLOCK [02:01] */ |
| #define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_MASK 0x00000006 |
| #define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: ITU656_0_MUX_SELECT :: ENABLE_INVERT_VEC_ITU656_0_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ITU656_1_MUX_SELECT - Mux selects for itu656_1 clocks |
| ***************************************************************************/ |
| /* CLKGEN :: ITU656_1_MUX_SELECT :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_ITU656_1_MUX_SELECT_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_ITU656_1_MUX_SELECT_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: ITU656_1_MUX_SELECT :: VEC_ITU656_1_CLOCK [02:01] */ |
| #define BCHP_CLKGEN_ITU656_1_MUX_SELECT_VEC_ITU656_1_CLOCK_MASK 0x00000006 |
| #define BCHP_CLKGEN_ITU656_1_MUX_SELECT_VEC_ITU656_1_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_ITU656_1_MUX_SELECT_VEC_ITU656_1_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: ITU656_1_MUX_SELECT :: ENABLE_INVERT_VEC_ITU656_1_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_ITU656_1_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_1_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_ITU656_1_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_1_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_ITU656_1_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_1_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEMSYS_32_0_INST_CLOCK_ENABLE - Memsys 32 0 inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: DDR0_SCB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_SCB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_SCB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: DDR0_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS :: DDR0_SCB_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_DDR0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_DDR0_SCB_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS :: DDR0_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_DDR0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_DDR0_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE - Memsys 32 0 inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE :: DDR0_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE_DDR0_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE_DDR0_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE_DDR0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEMSYS_32_0_INST_OBSERVE_CLOCK - Memsys 32 0 inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: DDR0_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: DDR0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: DDR0_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEMSYS_32_0_INST_POWER_SWITCH_MEMORY - Memsys 32 0 inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_32_0_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: MEMSYS_32_0_INST_POWER_SWITCH_MEMORY :: DDR0_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY_DDR0_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY_DDR0_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY_DDR0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEMSYS_32_0_INST_STATUS - Memsys 32 0 inst status |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_32_0_INST_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: MEMSYS_32_0_INST_STATUS :: DDR0_PLL_LOCKED_STATUS [00:00] */ |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS_DDR0_PLL_LOCKED_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS_DDR0_PLL_LOCKED_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *MEMSYS_32_1_INST_CLOCK_ENABLE - Memsys 32 1 inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE :: DDR1_SCB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE :: DDR1_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS :: DDR1_SCB_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_DDR1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_DDR1_SCB_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS :: DDR1_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_DDR1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_DDR1_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE - Memsys 32 1 inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE :: DDR1_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEMSYS_32_1_INST_OBSERVE_CLOCK - Memsys 32 1 inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: DDR1_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: DDR1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: DDR1_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEMSYS_32_1_INST_POWER_SWITCH_MEMORY - Memsys 32 1 inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_32_1_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: MEMSYS_32_1_INST_POWER_SWITCH_MEMORY :: DDR1_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEMSYS_32_1_INST_STATUS - Memsys 32 1 inst status |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_32_1_INST_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: MEMSYS_32_1_INST_STATUS :: DDR1_PLL_LOCKED_STATUS [00:00] */ |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_STATUS_DDR1_PLL_LOCKED_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMSYS_32_1_INST_STATUS_DDR1_PLL_LOCKED_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *MOCA_TOP_INST_CLOCK_ENABLE - Moca top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: MOCA_SCB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: MOCA_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *MOCA_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE_STATUS :: MOCA_SCB_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_STATUS_MOCA_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_STATUS_MOCA_SCB_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE_STATUS :: MOCA_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_STATUS_MOCA_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_STATUS_MOCA_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *MOCA_TOP_INST_MEMORY_STANDBY_ENABLE - Moca top inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: MOCA_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: MOCA_TOP_INST_MEMORY_STANDBY_ENABLE :: MOCA_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MOCA_TOP_INST_OBSERVE_CLOCK - Moca top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MOCA_TOP_INST_POWER_SWITCH_MEMORY - Moca top inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: MOCA_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: MOCA_TOP_INST_POWER_SWITCH_MEMORY :: MOCA_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PAD_CLK27_OBSERVATION - Select observation clk |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CLK27_OBSERVATION :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: PAD_CLK27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */ |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100 |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8 |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */ |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PAD_CLOCK_DISABLE - Disable PAD's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_VCXO27_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_SC_CLOCK [03:03] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_MASK 0x00000008 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_SHIFT 3 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLKBT_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKBT_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKBT_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKBT_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK27_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PAD_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_VCXO27_CLOCK_STATUS [04:04] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_STATUS_MASK 0x00000010 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_STATUS_SHIFT 4 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_SC_CLOCK_STATUS [03:03] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_SC_CLOCK_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_SC_CLOCK_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_STATUS [02:02] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CLKBT_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLKBT_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLKBT_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CLK27_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK27_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK27_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PAD_CODEC_MCLK_OBSERVATION - Select observation clk |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */ |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100 |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8 |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */ |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PAD_MUX_SELECT - Mux selects for Pad clocks |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_VCXO27_CLOCK [04:02] */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_MASK 0x0000001c |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_SC_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_MUX_SELECT :: ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PAD_VCXO27_OBSERVATION - Select observation clk |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_VCXO27_OBSERVATION :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: PAD_VCXO27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */ |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100 |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8 |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */ |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_RESET_STATUS - PLL_AUDIO0 Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_RESET_STATUS - PLL_AUDIO1 Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO2_PLL_RESET_STATUS - PLL_AUDIO2 Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO2_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AUDIO2_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO2_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AVD1_PLL_RESET_STATUS - PLL_AVD1 Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD1_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AVD1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AVD1_RDB_MACRO_CTRL - PLL RDB Macro Disable |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD1_RDB_MACRO_CTRL :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_PLL_AVD1_RDB_MACRO_CTRL_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_PLL_AVD1_RDB_MACRO_CTRL_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: PLL_AVD1_RDB_MACRO_CTRL :: PLL_AVD1_OPTIONS_DISABLE_RDB_MACRO [03:03] */ |
| #define BCHP_CLKGEN_PLL_AVD1_RDB_MACRO_CTRL_PLL_AVD1_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008 |
| #define BCHP_CLKGEN_PLL_AVD1_RDB_MACRO_CTRL_PLL_AVD1_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_AVD1_RDB_MACRO_CTRL_PLL_AVD1_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_AVD1_RDB_MACRO_CTRL :: OPTIONS [02:00] */ |
| #define BCHP_CLKGEN_PLL_AVD1_RDB_MACRO_CTRL_OPTIONS_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_AVD1_RDB_MACRO_CTRL_OPTIONS_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD1_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_HIF_PLL_RESET_STATUS - PLL_HIF Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_HIF_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_HIF_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_HIF_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MIPS_GLITCHLESS_SWITCH_REQUEST - PLL_MIPS Glitchless Clock Switching |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: TRANSACTION_WAIT [08:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_DEFAULT 0x0000001f |
| |
| /* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: PLL_BYPASS_REQUEST [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MIPS_GLITCHLESS_SWITCH_STATUS - PLL_MIPS Glitchless Switching |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_STATUS :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_STATUS :: PLL_BYPASS_STATUS [03:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_MASK 0x0000000f |
| #define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_RESET_STATUS - PLL_MIPS Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MIPS_RDB_MACRO_CTRL - PLL RDB Macro Disable |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_RDB_MACRO_CTRL :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: PLL_MIPS_RDB_MACRO_CTRL :: PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO [03:03] */ |
| #define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008 |
| #define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MIPS_RDB_MACRO_CTRL :: OPTIONS [02:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_OPTIONS_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_OPTIONS_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_RESET_STATUS - PLL_MOCA Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_RDB_MACRO_CTRL - PLL RDB Macro Disable |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO [02:02] */ |
| #define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000004 |
| #define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: OPTIONS [01:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_MASK 0x00000003 |
| #define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_NETWORK_PLL_RESET_STATUS - PLL_NETWORK Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_NETWORK_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_NETWORK_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_RESET_STATUS - PLL_RAAGA Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_RDB_MACRO_CTRL - PLL RDB Macro Disable |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO [03:03] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008 |
| #define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: OPTIONS [02:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_RESET_STATUS - PLL_SC0 Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SC0_RDB_MACRO_CTRL - PLL RDB Macro Disable |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: PLL_SC0_OPTIONS_DISABLE_RDB_MACRO [04:04] */ |
| #define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: OPTIONS [03:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_MASK 0x0000000f |
| #define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_RESET_STATUS - PLL_SC1 Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SC1_RDB_MACRO_CTRL - PLL RDB Macro Disable |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: PLL_SC1_OPTIONS_DISABLE_RDB_MACRO [04:04] */ |
| #define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: OPTIONS [03:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_MASK 0x0000000f |
| #define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_STRAP_OVERRIDE - Disable |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_STRAP_OVERRIDE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_STRAP_OVERRIDE :: STRAP_HIFSPI_DISABLE [01:01] */ |
| #define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_HIFSPI_DISABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_HIFSPI_DISABLE_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_HIFSPI_DISABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_STRAP_OVERRIDE :: STRAP_FREQ_PLLMIPS_DISABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_VCXO0_PLL_RESET_STATUS - PLL_VCXO0 Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO1_PLL_RESET_STATUS - PLL_VCXO1 Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO2_PLL_RESET_STATUS - PLL_VCXO2 Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PM_CLOCK_216_ALIVE_SEL - Select clocks that can stay alive during power management standby mode. |
| ***************************************************************************/ |
| /* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */ |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_MASK 0x00000001 |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT 0 |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode |
| ***************************************************************************/ |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys1_PLL [04:04] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys1_PLL_MASK 0x00000010 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys1_PLL_SHIFT 4 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys1_PLL_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys0_PLL [03:03] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys0_PLL_MASK 0x00000008 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys0_PLL_SHIFT 3 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys0_PLL_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_XPT [02:02] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_MASK 0x00000004 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_SHIFT 2 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [01:01] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK 0x00000002 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT 1 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_MIPS [00:00] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_SHIFT 0 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PM_PLL_LDO_POWERUP - Power management LDO PLL |
| ***************************************************************************/ |
| /* CLKGEN :: PM_PLL_LDO_POWERUP :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_RAAGA [04:04] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_MASK 0x00000010 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_SHIFT 4 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_NETWORK [03:03] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_NETWORK_MASK 0x00000008 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_NETWORK_SHIFT 3 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_NETWORK_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_MOCA [02:02] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_MASK 0x00000004 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_SHIFT 2 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_HIF [01:01] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_HIF_MASK 0x00000002 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_HIF_SHIFT 1 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_HIF_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_AVD1 [00:00] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD1_SHIFT 0 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD1_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PM_PLL_LDO_POWERUP_SM - Power management LDO PLL state machine |
| ***************************************************************************/ |
| /* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: reserved0 [31:27] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_MASK 0xf8000000 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_SHIFT 27 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_POWERUP_WAIT_TIME [26:14] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_MASK 0x07ffc000 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_SHIFT 14 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_DEFAULT 0x00001518 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_CLK_STOP_WAIT_TIME [13:01] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_MASK 0x00003ffe |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_SHIFT 1 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_DEFAULT 0x000000c8 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: GISB_OVERRIDE_SM [00:00] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_MASK 0x00000001 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_SHIFT 0 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0 - Raaga dsp top wrap inst clock enable0 |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0 :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0 :: RAAGA_SCB_CLOCK_ENABLE0 [02:02] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_RAAGA_SCB_CLOCK_ENABLE0_MASK 0x00000004 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_RAAGA_SCB_CLOCK_ENABLE0_SHIFT 2 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_RAAGA_SCB_CLOCK_ENABLE0_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0 :: RAAGA_DSP_CLOCK_ENABLE0 [01:01] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_RAAGA_DSP_CLOCK_ENABLE0_MASK 0x00000002 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_RAAGA_DSP_CLOCK_ENABLE0_SHIFT 1 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_RAAGA_DSP_CLOCK_ENABLE0_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0 :: RAAGA_108_CLOCK_ENABLE0 [00:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_RAAGA_108_CLOCK_ENABLE0_MASK 0x00000001 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_RAAGA_108_CLOCK_ENABLE0_SHIFT 0 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_RAAGA_108_CLOCK_ENABLE0_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_STATUS :: RAAGA_SCB_CLOCK_ENABLE0_STATUS [02:02] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_STATUS_RAAGA_SCB_CLOCK_ENABLE0_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_STATUS_RAAGA_SCB_CLOCK_ENABLE0_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_STATUS :: RAAGA_DSP_CLOCK_ENABLE0_STATUS [01:01] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_STATUS_RAAGA_DSP_CLOCK_ENABLE0_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_STATUS_RAAGA_DSP_CLOCK_ENABLE0_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_STATUS :: RAAGA_108_CLOCK_ENABLE0_STATUS [00:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_STATUS_RAAGA_108_CLOCK_ENABLE0_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE0_STATUS_RAAGA_108_CLOCK_ENABLE0_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1 - Raaga dsp top wrap inst clock enable1 |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1 :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1 :: RAAGA_SCB_CLOCK_ENABLE1 [02:02] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_RAAGA_SCB_CLOCK_ENABLE1_MASK 0x00000004 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_RAAGA_SCB_CLOCK_ENABLE1_SHIFT 2 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_RAAGA_SCB_CLOCK_ENABLE1_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1 :: RAAGA_DSP_CLOCK_ENABLE1 [01:01] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_RAAGA_DSP_CLOCK_ENABLE1_MASK 0x00000002 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_RAAGA_DSP_CLOCK_ENABLE1_SHIFT 1 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_RAAGA_DSP_CLOCK_ENABLE1_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1 :: RAAGA_108_CLOCK_ENABLE1 [00:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_RAAGA_108_CLOCK_ENABLE1_MASK 0x00000001 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_RAAGA_108_CLOCK_ENABLE1_SHIFT 0 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_RAAGA_108_CLOCK_ENABLE1_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_STATUS :: RAAGA_SCB_CLOCK_ENABLE1_STATUS [02:02] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_STATUS_RAAGA_SCB_CLOCK_ENABLE1_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_STATUS_RAAGA_SCB_CLOCK_ENABLE1_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_STATUS :: RAAGA_DSP_CLOCK_ENABLE1_STATUS [01:01] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_STATUS_RAAGA_DSP_CLOCK_ENABLE1_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_STATUS_RAAGA_DSP_CLOCK_ENABLE1_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_STATUS :: RAAGA_108_CLOCK_ENABLE1_STATUS [00:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_STATUS_RAAGA_108_CLOCK_ENABLE1_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_CLOCK_ENABLE1_STATUS_RAAGA_108_CLOCK_ENABLE1_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_WRAP_INST_MEMORY_STANDBY_ENABLE0 - Raaga dsp top wrap inst memory standby enable0 |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_MEMORY_STANDBY_ENABLE0 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_MEMORY_STANDBY_ENABLE0_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_MEMORY_STANDBY_ENABLE0_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_MEMORY_STANDBY_ENABLE0 :: RAAGA_MEMORY_STANDBY_ENABLE0 [00:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_MEMORY_STANDBY_ENABLE0_RAAGA_MEMORY_STANDBY_ENABLE0_MASK 0x00000001 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_MEMORY_STANDBY_ENABLE0_RAAGA_MEMORY_STANDBY_ENABLE0_SHIFT 0 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_MEMORY_STANDBY_ENABLE0_RAAGA_MEMORY_STANDBY_ENABLE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_WRAP_INST_MEMORY_STANDBY_ENABLE1 - Raaga dsp top wrap inst memory standby enable1 |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_MEMORY_STANDBY_ENABLE1 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_MEMORY_STANDBY_ENABLE1_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_MEMORY_STANDBY_ENABLE1_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_MEMORY_STANDBY_ENABLE1 :: RAAGA_MEMORY_STANDBY_ENABLE1 [00:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_MEMORY_STANDBY_ENABLE1_RAAGA_MEMORY_STANDBY_ENABLE1_MASK 0x00000001 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_MEMORY_STANDBY_ENABLE1_RAAGA_MEMORY_STANDBY_ENABLE1_SHIFT 0 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_MEMORY_STANDBY_ENABLE1_RAAGA_MEMORY_STANDBY_ENABLE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK0 - Raaga dsp top wrap inst observe clock0 |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK0 :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK0_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK0_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK0 :: RAAGA_ENABLE_OBSERVE_CLOCK0 [01:01] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK0_RAAGA_ENABLE_OBSERVE_CLOCK0_MASK 0x00000002 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK0_RAAGA_ENABLE_OBSERVE_CLOCK0_SHIFT 1 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK0_RAAGA_ENABLE_OBSERVE_CLOCK0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK0 :: RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK0 [00:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK0_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK0_MASK 0x00000001 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK0_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK0_SHIFT 0 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK0_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK1 - Raaga dsp top wrap inst observe clock1 |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK1 :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK1_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK1_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK1 :: RAAGA_ENABLE_OBSERVE_CLOCK1 [01:01] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK1_RAAGA_ENABLE_OBSERVE_CLOCK1_MASK 0x00000002 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK1_RAAGA_ENABLE_OBSERVE_CLOCK1_SHIFT 1 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK1_RAAGA_ENABLE_OBSERVE_CLOCK1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK1 :: RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK1 [00:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK1_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK1_MASK 0x00000001 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK1_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK1_SHIFT 0 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_OBSERVE_CLOCK1_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_WRAP_INST_POWER_SWITCH_MEMORY0 - Raaga dsp top wrap inst power switch memory0 |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_POWER_SWITCH_MEMORY0 :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_POWER_SWITCH_MEMORY0_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_POWER_SWITCH_MEMORY0_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_POWER_SWITCH_MEMORY0 :: RAAGA_POWER_SWITCH_MEMORY0 [01:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_POWER_SWITCH_MEMORY0_RAAGA_POWER_SWITCH_MEMORY0_MASK 0x00000003 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_POWER_SWITCH_MEMORY0_RAAGA_POWER_SWITCH_MEMORY0_SHIFT 0 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_POWER_SWITCH_MEMORY0_RAAGA_POWER_SWITCH_MEMORY0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_WRAP_INST_POWER_SWITCH_MEMORY1 - Raaga dsp top wrap inst power switch memory1 |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_POWER_SWITCH_MEMORY1 :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_POWER_SWITCH_MEMORY1_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_POWER_SWITCH_MEMORY1_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_WRAP_INST_POWER_SWITCH_MEMORY1 :: RAAGA_POWER_SWITCH_MEMORY1 [01:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_POWER_SWITCH_MEMORY1_RAAGA_POWER_SWITCH_MEMORY1_MASK 0x00000003 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_POWER_SWITCH_MEMORY1_RAAGA_POWER_SWITCH_MEMORY1_SHIFT 0 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_WRAP_INST_POWER_SWITCH_MEMORY1_RAAGA_POWER_SWITCH_MEMORY1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SATA3_TOP_INST_CLOCK_DISABLE - Disable SATA3_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE :: DISABLE_SATA3_AT_SPEED_SCAN_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SATA3_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *SATA3_TOP_INST_CLOCK_ENABLE - Sata3 top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_SCB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SATA3_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: SATA3_SCB_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_SCB_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: SATA3_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *SATA3_TOP_INST_CLOCK_SELECT - Sata3 top inst clock select |
| ***************************************************************************/ |
| /* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: SATA3_REF_CLOCK_SELECT [00:00] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_MASK 0x00000001 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_SHIFT 0 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SATA3_TOP_INST_MEMORY_STANDBY_ENABLE - Sata3 top inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: SATA3_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SATA3_TOP_INST_MEMORY_STANDBY_ENABLE :: SATA3_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SATA3_TOP_INST_OBSERVE_CLOCK - Sata3 top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SATA3_TOP_INST_POWER_SWITCH_MEMORY - Sata3 top inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: SATA3_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SATA3_TOP_INST_POWER_SWITCH_MEMORY :: SATA3_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SECTOP_INST_CLOCK_ENABLE_M2MDMA - Sectop inst clock enable m2mdma |
| ***************************************************************************/ |
| /* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA :: M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA [00:00] */ |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_MASK 0x00000001 |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_SHIFT 0 |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SECTOP_INST_CLOCK_ENABLE_M2MDMA_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA_STATUS :: M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_STATUS [00:00] */ |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_STATUS_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_STATUS_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *SECTOP_INST_MEMORY_STANDBY_ENABLE - Sectop inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: SECTOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SECTOP_INST_MEMORY_STANDBY_ENABLE :: SEC_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks |
| ***************************************************************************/ |
| /* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SPARE - Spares |
| ***************************************************************************/ |
| /* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */ |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK 0xfffff000 |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT 12 |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */ |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK 0x00000fff |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT 0 |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SVD0_TOP_INST_CLOCK_ENABLE - Svd0 top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD0_SCB_CLOCK_ENABLE [03:03] */ |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_SCB_CLOCK_ENABLE_MASK 0x00000008 |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_SCB_CLOCK_ENABLE_SHIFT 3 |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD0_CPU_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CPU_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CPU_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CPU_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD0_CORE_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CORE_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CORE_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CORE_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD0_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SVD0_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE_STATUS :: SVD0_SCB_CLOCK_ENABLE_STATUS [03:03] */ |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD0_SCB_CLOCK_ENABLE_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE_STATUS :: SVD0_CPU_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD0_CPU_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD0_CPU_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE_STATUS :: SVD0_CORE_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD0_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD0_CORE_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE_STATUS :: SVD0_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD0_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *SVD0_TOP_INST_MEMORY_STANDBY_ENABLE - Svd0 top inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: SVD0_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SVD0_TOP_INST_MEMORY_STANDBY_ENABLE :: SVD0_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD0_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD0_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SVD0_TOP_INST_POWER_SWITCH_MEMORY - Svd0 top inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: SVD0_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SVD0_TOP_INST_POWER_SWITCH_MEMORY :: SVD0_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD0_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD0_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SYS_AON_INST_OBSERVE_CLOCK - Sys aon inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SYS_CTRL_INST_CLOCK_DISABLE - Disable SYS_CTRL_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [03:03] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000008 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 3 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SYS_CTRL_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSCTRL_UPG_CLOCK_STATUS [03:03] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK_STATUS [02:02] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SC1_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SC0_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *SYS_CTRL_INST_MEMORY_STANDBY_ENABLE - Sys ctrl inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SYS_CTRL_INST_MEMORY_STANDBY_ENABLE :: SYS_CTRL_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SYS_CTRL_INST_OBSERVE_CLOCK - Sys ctrl inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SYS_CTRL_INST_POWER_SWITCH_MEMORY - Sys ctrl inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SYS_CTRL_INST_POWER_SWITCH_MEMORY :: SYS_CTRL_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TESTPORT - Special Testport Controls |
| ***************************************************************************/ |
| /* CLKGEN :: TESTPORT :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_TESTPORT_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [03:00] */ |
| #define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK 0x0000000f |
| #define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT 0 |
| #define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UHFR_TOP_INST_CLOCK_DISABLE - Disable UHFR_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE :: DISABLE_UHFR_ALWAYSON_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UHFR_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_UHFR_ALWAYSON_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UHFR_ALWAYSON_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UHFR_ALWAYSON_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *UHFR_TOP_INST_CLOCK_ENABLE - Uhfr top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE :: UHFR_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *UHFR_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE_STATUS :: UHFR_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_STATUS_UHFR_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_STATUS_UHFR_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *UHFR_TOP_INST_MEMORY_STANDBY_ENABLE - Uhfr top inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: UHFR_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: UHFR_TOP_INST_MEMORY_STANDBY_ENABLE :: UHFR_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UHFR_TOP_INST_OBSERVE_CLOCK - Uhfr top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UHFR_TOP_INST_POWER_SWITCH_MEMORY - Uhfr top inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: UHFR_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: UHFR_TOP_INST_POWER_SWITCH_MEMORY :: UHFR_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *USB0_INST_CLOCK_DISABLE - Disable USB0_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: USB0_INST_CLOCK_DISABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB0_INST_CLOCK_DISABLE :: DISABLE_USB0_FREERUN_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: USB0_INST_CLOCK_DISABLE :: DISABLE_USB0_54_MDIO_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *USB0_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: USB0_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB0_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB0_FREERUN_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_FREERUN_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_FREERUN_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: USB0_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB0_54_MDIO_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_54_MDIO_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_54_MDIO_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *USB0_INST_CLOCK_ENABLE - Usb0 inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: USB0_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB0_INST_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: USB0_INST_CLOCK_ENABLE :: USB0_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *USB0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: USB0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB0_INST_CLOCK_ENABLE_STATUS :: USB0_SCB_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: USB0_INST_CLOCK_ENABLE_STATUS :: USB0_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_STATUS_USB0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_STATUS_USB0_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *USB0_INST_MEMORY_STANDBY_ENABLE - Usb0 inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: USB0_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: USB0_INST_MEMORY_STANDBY_ENABLE :: USB0_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *USB0_INST_OBSERVE_CLOCK - Usb0 inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *USB0_INST_POWER_SWITCH_MEMORY - Usb0 inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: USB0_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB0_INST_POWER_SWITCH_MEMORY :: USB0_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *USB1_INST_CLOCK_DISABLE - Disable USB1_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: USB1_INST_CLOCK_DISABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB1_INST_CLOCK_DISABLE :: DISABLE_USB1_FREERUN_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_FREERUN_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_FREERUN_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_FREERUN_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: USB1_INST_CLOCK_DISABLE :: DISABLE_USB1_54_MDIO_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *USB1_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: USB1_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB1_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB1_FREERUN_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_STATUS_DISABLE_USB1_FREERUN_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_STATUS_DISABLE_USB1_FREERUN_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: USB1_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB1_54_MDIO_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_STATUS_DISABLE_USB1_54_MDIO_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_STATUS_DISABLE_USB1_54_MDIO_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *USB1_INST_CLOCK_ENABLE - Usb1 inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: USB1_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB1_INST_CLOCK_ENABLE :: USB1_SCB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: USB1_INST_CLOCK_ENABLE :: USB1_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *USB1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: USB1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB1_INST_CLOCK_ENABLE_STATUS :: USB1_SCB_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_STATUS_USB1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_STATUS_USB1_SCB_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: USB1_INST_CLOCK_ENABLE_STATUS :: USB1_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_STATUS_USB1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_STATUS_USB1_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *USB1_INST_MEMORY_STANDBY_ENABLE - Usb1 inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: USB1_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: USB1_INST_MEMORY_STANDBY_ENABLE :: USB1_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *USB1_INST_OBSERVE_CLOCK - Usb1 inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *USB1_INST_POWER_SWITCH_MEMORY - Usb1 inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: USB1_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB1_INST_POWER_SWITCH_MEMORY :: USB1_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *V3D_TOP_INST_CLOCK_ENABLE - V3d top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_SCB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_108_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_108_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_108_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: GFX_V3D_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *V3D_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_SCB_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_SCB_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_108_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_108_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_108_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: GFX_V3D_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_GFX_V3D_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_GFX_V3D_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *V3D_TOP_INST_MEMORY_STANDBY_ENABLE - V3d top inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: V3D_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: V3D_TOP_INST_MEMORY_STANDBY_ENABLE :: V3D_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE_V3D_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE_V3D_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE_V3D_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *V3D_TOP_INST_POWER_SWITCH_MEMORY - V3d top inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: V3D_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: V3D_TOP_INST_POWER_SWITCH_MEMORY :: V3D_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY_V3D_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY_V3D_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY_V3D_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_INST_CLOCK_DISABLE - Disable VEC_AIO_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_ITU656_1_CLOCK [03:03] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_1_CLOCK_MASK 0x00000008 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_1_CLOCK_SHIFT 3 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_1_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_ITU656_0_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_AIO_CLEAN_216_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AIO_CLEAN_216_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AIO_CLEAN_216_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AIO_CLEAN_216_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_VEC_ITU656_1_CLOCK_STATUS [03:03] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_1_CLOCK_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_1_CLOCK_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_VEC_ITU656_0_CLOCK_STATUS [02:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_0_CLOCK_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_0_CLOCK_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_VEC_DACADC_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_AIO_CLEAN_216_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AIO_CLEAN_216_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AIO_CLEAN_216_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO - Vec aio top inst clock enable aio |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO [02:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_MASK 0x00000004 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_SHIFT 2 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO [01:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_MASK 0x00000002 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_SHIFT 1 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_108_CLOCK_ENABLE_AIO [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_108_CLOCK_ENABLE_AIO_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_108_CLOCK_ENABLE_AIO_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_108_CLOCK_ENABLE_AIO_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_STATUS [02:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_STATUS [01:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: AIO_108_CLOCK_ENABLE_AIO_STATUS [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_108_CLOCK_ENABLE_AIO_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_108_CLOCK_ENABLE_AIO_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC - Vec aio top inst clock enable vec |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_SCB_CLOCK_ENABLE_VEC [05:05] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_MASK 0x00000020 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_SHIFT 5 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_ALTERNATE_216_CLOCK_ENABLE_VEC [04:04] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_MASK 0x00000010 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_SHIFT 4 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_ALTERNATE2_108_CLOCK_ENABLE_VEC [03:03] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE2_108_CLOCK_ENABLE_VEC_MASK 0x00000008 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE2_108_CLOCK_ENABLE_VEC_SHIFT 3 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE2_108_CLOCK_ENABLE_VEC_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_324_CLOCK_ENABLE_VEC [02:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_324_CLOCK_ENABLE_VEC_MASK 0x00000004 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_324_CLOCK_ENABLE_VEC_SHIFT 2 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_324_CLOCK_ENABLE_VEC_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_216_CLOCK_ENABLE_VEC [01:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_MASK 0x00000002 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_SHIFT 1 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: QDAC_216_CLOCK_ENABLE_VEC [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_216_CLOCK_ENABLE_VEC_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_216_CLOCK_ENABLE_VEC_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_216_CLOCK_ENABLE_VEC_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_SCB_CLOCK_ENABLE_VEC_STATUS [05:05] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_SCB_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000020 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_SCB_CLOCK_ENABLE_VEC_STATUS_SHIFT 5 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_STATUS [04:04] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000010 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_STATUS_SHIFT 4 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_ALTERNATE2_108_CLOCK_ENABLE_VEC_STATUS [03:03] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_ALTERNATE2_108_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_ALTERNATE2_108_CLOCK_ENABLE_VEC_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_324_CLOCK_ENABLE_VEC_STATUS [02:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_324_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_324_CLOCK_ENABLE_VEC_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_216_CLOCK_ENABLE_VEC_STATUS [01:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_216_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_216_CLOCK_ENABLE_VEC_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: QDAC_216_CLOCK_ENABLE_VEC_STATUS [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_QDAC_216_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_QDAC_216_CLOCK_ENABLE_VEC_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO - Vec aio top inst memory standby enable aio |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO :: AIO_MEMORY_STANDBY_ENABLE_AIO [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC - Vec aio top inst memory standby enable vec |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC :: VEC_MEMORY_STANDBY_ENABLE_VEC [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_INST_OBSERVE_CLOCK - Vec aio top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO - Vec aio top inst power switch memory aio |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO :: AIO_POWER_SWITCH_MEMORY_AIO [01:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_MASK 0x00000003 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC - Vec aio top inst power switch memory vec |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC :: VEC_POWER_SWITCH_MEMORY_VEC [01:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_MASK 0x00000003 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VICE2_1_INST_CLOCK_ENABLE - Vice2 1 inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE1_SCB_CLOCK_ENABLE [03:03] */ |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_SCB_CLOCK_ENABLE_MASK 0x00000008 |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_SCB_CLOCK_ENABLE_SHIFT 3 |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE1_CORE_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_CORE_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_CORE_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_CORE_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE1_216_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_216_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_216_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE1_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *VICE2_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE1_SCB_CLOCK_ENABLE_STATUS [03:03] */ |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE1_SCB_CLOCK_ENABLE_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE1_CORE_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE1_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE1_CORE_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE1_216_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE1_216_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE1_216_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE1_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE1_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *VICE2_1_INST_MEMORY_STANDBY_ENABLE - Vice2 1 inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: VICE2_1_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_VICE2_1_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_VICE2_1_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: VICE2_1_INST_MEMORY_STANDBY_ENABLE :: VICE1_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_VICE2_1_INST_MEMORY_STANDBY_ENABLE_VICE1_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_VICE2_1_INST_MEMORY_STANDBY_ENABLE_VICE1_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_VICE2_1_INST_MEMORY_STANDBY_ENABLE_VICE1_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VICE2_1_INST_POWER_SWITCH_MEMORY - Vice2 1 inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: VICE2_1_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_VICE2_1_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_VICE2_1_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: VICE2_1_INST_POWER_SWITCH_MEMORY :: VICE1_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_VICE2_1_INST_POWER_SWITCH_MEMORY_VICE1_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_VICE2_1_INST_POWER_SWITCH_MEMORY_VICE1_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_VICE2_1_INST_POWER_SWITCH_MEMORY_VICE1_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VICE2_INST_CLOCK_ENABLE - Vice2 inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: VICE2_INST_CLOCK_ENABLE :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: VICE2_INST_CLOCK_ENABLE :: VICE_SCB_CLOCK_ENABLE [03:03] */ |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_SCB_CLOCK_ENABLE_MASK 0x00000008 |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_SCB_CLOCK_ENABLE_SHIFT 3 |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: VICE2_INST_CLOCK_ENABLE :: VICE_CORE_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_CORE_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_CORE_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_CORE_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: VICE2_INST_CLOCK_ENABLE :: VICE_216_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_216_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_216_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: VICE2_INST_CLOCK_ENABLE :: VICE_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *VICE2_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: VICE2_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: VICE2_INST_CLOCK_ENABLE_STATUS :: VICE_SCB_CLOCK_ENABLE_STATUS [03:03] */ |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_STATUS_VICE_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_STATUS_VICE_SCB_CLOCK_ENABLE_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: VICE2_INST_CLOCK_ENABLE_STATUS :: VICE_CORE_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_STATUS_VICE_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_STATUS_VICE_CORE_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: VICE2_INST_CLOCK_ENABLE_STATUS :: VICE_216_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_STATUS_VICE_216_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_STATUS_VICE_216_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: VICE2_INST_CLOCK_ENABLE_STATUS :: VICE_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_STATUS_VICE_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_STATUS_VICE_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *VICE2_INST_MEMORY_STANDBY_ENABLE - Vice2 inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: VICE2_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: VICE2_INST_MEMORY_STANDBY_ENABLE :: VICE_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE_VICE_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE_VICE_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE_VICE_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VICE2_INST_POWER_SWITCH_MEMORY - Vice2 inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: VICE2_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: VICE2_INST_POWER_SWITCH_MEMORY :: VICE_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY_VICE_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY_VICE_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY_VICE_POWER_SWITCH_MEMORY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ZCPU_DUAL_TOP_INST_CLOCK_DISABLE - Disable ZCPU_DUAL_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_DISABLE :: DISABLE_ZMIPS_SLOWMIPS_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_SLOWMIPS_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_SLOWMIPS_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_SLOWMIPS_CLOCK_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_ZMIPS_SLOWMIPS_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_ZMIPS_SLOWMIPS_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_ZMIPS_SLOWMIPS_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *ZCPU_DUAL_TOP_INST_CLOCK_ENABLE - Zcpu dual top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_ENABLE :: ZMIPS_SCB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_ENABLE :: ZMIPS_216_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_ZMIPS_216_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_ZMIPS_216_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_ZMIPS_216_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_ENABLE :: ZMIPS_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_ZMIPS_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_ZMIPS_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_ZMIPS_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS :: ZMIPS_SCB_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS_ZMIPS_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS_ZMIPS_SCB_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS :: ZMIPS_216_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS_ZMIPS_216_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS_ZMIPS_216_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS :: ZMIPS_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS_ZMIPS_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS_ZMIPS_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK - Zcpu dual top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK :: ZMIPS_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK :: ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK :: ZMIPS_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS - Bypass GENET_TOP_DUAL_RGMII_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS :: EEE_25_CLOCK_BYPASS [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_SHIFT 0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_DEFAULT 0x00000000 |
| |
| #endif /* #ifndef BCHP_CLKGEN_H__ */ |
| |
| /* End of File */ |
