| /*************************************************************************** |
| * Copyright (c) 1999-2011, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Mon Aug 8 20:14:25 2011 |
| * MD5 Checksum bdb30c5d18c5d13008bcd4430a6d3384 |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_sun_top_ctrl.h $ |
| * |
| * Hydra_Software_Devel/3 8/9/11 11:21a pntruong |
| * SW7344-144: Synced with central RDB. |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_SUN_TOP_CTRL_H__ |
| #define BCHP_SUN_TOP_CTRL_H__ |
| |
| /*************************************************************************** |
| *SUN_TOP_CTRL - Top Control registers |
| ***************************************************************************/ |
| #define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID 0x00404000 /* Chip family ID */ |
| #define BCHP_SUN_TOP_CTRL_PRODUCT_ID 0x00404004 /* Product Revision ID */ |
| #define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0 0x0040401c /* Strapping values */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1 0x00404020 /* Strapping values */ |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS 0x00404024 /* Bond option value register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0 0x00404028 /* OTP option test register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1 0x0040402c /* OTP option test register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0 0x00404030 /* OTP option status register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1 0x00404034 /* OTP option status register */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0 0x00404038 /* Semaphore channel 0 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1 0x0040403c /* Semaphore channel 1 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2 0x00404040 /* Semaphore channel 2 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3 0x00404044 /* Semaphore channel 3 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4 0x00404048 /* Semaphore channel 4 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5 0x0040404c /* Semaphore channel 5 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6 0x00404050 /* Semaphore channel 6 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7 0x00404054 /* Semaphore channel 7 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8 0x00404058 /* Semaphore channel 8 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9 0x0040405c /* Semaphore channel 9 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10 0x00404060 /* Semaphore channel 10 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11 0x00404064 /* Semaphore channel 11 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12 0x00404068 /* Semaphore channel 12 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13 0x0040406c /* Semaphore channel 13 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14 0x00404070 /* Semaphore channel 14 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15 0x00404074 /* Semaphore channel 15 */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0 0x00404078 /* General watchdog timer 0 */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1 0x0040407c /* General watchdog timer 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0 0x00404080 /* General control register 0 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1 0x00404084 /* General control register 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2 0x00404088 /* General control register 2 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3 0x0040408c /* General control register 3 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4 0x00404090 /* General control register 4 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5 0x00404094 /* General control register 5 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0 0x00404098 /* General status register 0 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1 0x0040409c /* General status register 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2 0x004040a0 /* General status register 2 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0 0x00404100 /* Pinmux control register 0 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1 0x00404104 /* Pinmux control register 1 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2 0x00404108 /* Pinmux control register 2 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3 0x0040410c /* Pinmux control register 3 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4 0x00404110 /* Pinmux control register 4 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5 0x00404114 /* Pinmux control register 5 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6 0x00404118 /* Pinmux control register 6 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7 0x0040411c /* Pinmux control register 7 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8 0x00404120 /* Pinmux control register 8 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9 0x00404124 /* Pinmux control register 9 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10 0x00404128 /* Pinmux control register 10 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11 0x0040412c /* Pinmux control register 11 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12 0x00404130 /* Pinmux control register 12 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13 0x00404134 /* Pinmux control register 13 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14 0x00404138 /* Pinmux control register 14 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15 0x0040413c /* Pinmux control register 15 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16 0x00404140 /* Pinmux control register 16 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17 0x00404144 /* Pinmux control register 17 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18 0x00404148 /* Pinmux control register 18 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0 0x0040414c /* Pad pull-up/pull-down control register 0 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1 0x00404150 /* Pad pull-up/pull-down control register 1 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2 0x00404154 /* Pad pull-up/pull-down control register 2 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3 0x00404158 /* Pad pull-up/pull-down control register 3 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4 0x0040415c /* Pad pull-up/pull-down control register 4 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5 0x00404160 /* Pad pull-up/pull-down control register 5 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6 0x00404164 /* Pad pull-up/pull-down control register 6 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7 0x00404168 /* Pad pull-up/pull-down control register 7 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8 0x0040416c /* Pad pull-up/pull-down control register 8 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9 0x00404170 /* Pad pull-up/pull-down control register 9 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10 0x00404174 /* Pad pull-up/pull-down control register 10 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11 0x00404178 /* Pad pull-up/pull-down control register 11 */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0 0x0040417c /* Bypass clock unselect register 0 */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL 0x00404300 /* Reset control */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE 0x00404304 /* Reset source enable */ |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET 0x00404308 /* Software master reset */ |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION 0x0040430c /* Hardware reset extension */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR 0x00404310 /* Reset Monitor */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY 0x00404314 /* Reset history */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET 0x00404318 /* Software init 0 set */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR 0x0040431c /* Software init 0 clear */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS 0x00404320 /* Software init 0 status */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR 0x00404324 /* Security software init 0 monitor */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET 0x00404330 /* Software init 1 set */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR 0x00404334 /* Software init 1 clear */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS 0x00404338 /* Software init 1 status */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR 0x0040433c /* Security software init 1 monitor */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */ |
| #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH 0x00404364 /* Scratch register */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL 0x00404368 /* Spare control bits reserved for future use */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL 0x00404380 /* Test port control */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK 0x00404384 /* Testport peek register */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE 0x00404388 /* Testport poke register */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK 0x0040438c /* Testport peek register */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE 0x00404390 /* Testport poke register */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN 0x00404394 /* EJTAG input bus enables */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL 0x00404398 /* EJTAG output select */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL 0x0040439c /* UART Router select */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL 0x004043a0 /* VTRAP Control */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS 0x004043a4 /* VTRAP Status */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG 0x00404400 /* Serial Slave Port configuration register */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV 0x00404420 /* SERS Revision Register */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG 0x00404424 /* SERS Configuration Register */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL 0x00404514 /* Block select for RO testmode */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION 0x00404518 /* Test configuration */ |
| |
| /*************************************************************************** |
| *CHIP_FAMILY_ID - Chip family ID |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT 1933836304 |
| |
| /*************************************************************************** |
| *PRODUCT_ID - Product Revision ID |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT 1933836304 |
| |
| /*************************************************************************** |
| *BSP_FEATURE_TABLE_ADDR - BSP feature table address |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0 |
| |
| /*************************************************************************** |
| *STRAP_VALUE_0 - Strapping values |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:11] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK 0xfffff800 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_reset_outb_def_val [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [09:06] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK 0x000003c0 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT 10 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_mips_freq [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_mips_freq_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_mips_freq_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_mips_freq_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd [02:00] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_MASK 0x00000007 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_DEFAULT 0 |
| |
| /*************************************************************************** |
| *STRAP_VALUE_1 - Strapping values |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:05] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK 0xffffffe0 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias [04:02] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_MASK 0x0000001c |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_DEFAULT 2 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xtal_enable_ext_cml [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xtal_enable_ext_cml_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xtal_enable_ext_cml_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xtal_enable_ext_cml_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT 1 |
| |
| /*************************************************************************** |
| *BOND_STATUS - Bond option value register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */ |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT 0 |
| |
| /*************************************************************************** |
| *OTP_OPTION_TEST_0 - OTP option test register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_1 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_0 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_freq_pllmips [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_freq_pllmips_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_freq_pllmips_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_freq_pllmips_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_genet1_disable [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet1_disable_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet1_disable_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet1_disable_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_temp_sensor_disable [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_svc_disable [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_directv_disable [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_pvtmon_disable [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pvtmon_disable_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pvtmon_disable_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pvtmon_disable_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_moca_disable [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sds0_tuner_disable [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hd_display_disable [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ephy_disable [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_tfec_disable [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ldpc_disable [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_adjust_voltage [14:10] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_adjust_voltage_MASK 0x00007c00 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_adjust_voltage_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_adjust_voltage_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK 0x00000060 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 3 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0 |
| |
| /*************************************************************************** |
| *OTP_OPTION_TEST_1 - OTP option test register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_30 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_29 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_28 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_27 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_26 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_25 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_24 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_23 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_22 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_21 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_20 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_19 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_18 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_17 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_16 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_15 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_14 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_13 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_0 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rv9_disable [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_DEFAULT 0 |
| |
| /*************************************************************************** |
| *OTP_OPTION_STATUS_0 - OTP option status register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_1 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_0 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_freq_pllmips [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_freq_pllmips_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_freq_pllmips_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_genet1_disable [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet1_disable_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet1_disable_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_temp_sensor_disable [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_temp_sensor_disable_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_temp_sensor_disable_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_svc_disable [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_svc_disable_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_svc_disable_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_directv_disable [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_pvtmon_disable [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pvtmon_disable_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pvtmon_disable_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_moca_disable [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sds0_tuner_disable [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sds0_tuner_disable_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sds0_tuner_disable_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hd_display_disable [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ephy_disable [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_tfec_disable [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec_disable_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec_disable_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ldpc_disable [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc_disable_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc_disable_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_adjust_voltage [14:10] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_adjust_voltage_MASK 0x00007c00 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_adjust_voltage_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0 |
| |
| /*************************************************************************** |
| *OTP_OPTION_STATUS_1 - OTP option status register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_30 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_30_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_30_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_29 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_28 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_27 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_26 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_25 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_24 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_23 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_22 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_21 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_20 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_19 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_18 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_17 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_16 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_15 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_14 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_13 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_0 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rv9_disable [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_SHIFT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_0 - Semaphore channel 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_1 - Semaphore channel 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_2 - Semaphore channel 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_3 - Semaphore channel 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_4 - Semaphore channel 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_5 - Semaphore channel 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_6 - Semaphore channel 6 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_7 - Semaphore channel 7 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_8 - Semaphore channel 8 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_9 - Semaphore channel 9 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_10 - Semaphore channel 10 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_11 - Semaphore channel 11 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_12 - Semaphore channel 12 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_13 - Semaphore channel 13 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_14 - Semaphore channel 14 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_15 - Semaphore channel 15 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT 0 |
| |
| /*************************************************************************** |
| *GEN_WATCHDOG_0 - General watchdog timer 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0 |
| |
| /*************************************************************************** |
| *GEN_WATCHDOG_1 - General watchdog timer 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_0 - General control register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: mii_genet_mac_select [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_genet_mac_select_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_genet_mac_select_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_genet_mac_select_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_1 - General control register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_DEFAULT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_2 - General control register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_DEFAULT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_3 - General control register 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_4 - General control register 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_5 - General control register 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT 0 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_0 - General status register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_1 - General status register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_2 - General status register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_amp_en [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_sel [06:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_MASK 0x00000060 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_GMII_CMOS_3P3V 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_RGMII_CMOS_2P5V 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_HSTL_CLASS1_1P5V 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_HSTL_CLASS1_1P8V 3 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_rx_pad_amp_en [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_rx_pad_amp_en_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_rx_pad_amp_en_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_rx_pad_amp_en_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_tx_pad_amp_en [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_tx_pad_amp_en_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_tx_pad_amp_en_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_tx_pad_amp_en_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_slew [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_slew_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_slew_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_slew_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_sel [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_GMII_CMOS_3P3V 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_RGMII_CMOS_2P5V 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_HSTL_CLASS1_1P5V 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_HSTL_CLASS1_1P8V 3 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_31 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_31_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_31_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_31_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_30_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_29 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_29_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_29_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_29_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_28 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_28_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_28_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_28_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_27 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_27_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_27_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_27_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_26 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_26_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_26_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_26_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_25_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_25_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_24 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_24_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_24_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_24_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_23_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_22_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_21 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_21_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_21_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_21_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_20_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_19 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_19_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_19_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_19_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_18 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_18_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_18_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_18_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_17_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_16 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_16_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_16_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_16_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_15 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_15_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_15_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_15_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_vregcntl [14:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_MASK 0x00007ffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_pwrdn [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_vregcntl_en [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_DEFAULT 1 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:24] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK 0xff000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: mii_drive_src_0 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: mii_drive_sel_0 [22:20] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_MASK 0x00700000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DEFAULT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_4 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_4_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_4_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_4_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_4 [18:16] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_MASK 0x00070000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DEFAULT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_3 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_3_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_3_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_3_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_3 [14:12] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_MASK 0x00007000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DEFAULT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_2 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_2_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_2_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_2_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_2 [10:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_MASK 0x00000700 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DEFAULT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_1 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_1_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_1_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_1_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_1 [06:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_MASK 0x00000070 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DEFAULT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_0 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_0_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_0_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_0_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_0 [02:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_MASK 0x00000007 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DEFAULT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_16MA 7 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_51 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_51_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_51_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_51_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_50 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_50_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_50_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_50_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_49 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_49_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_49_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_49_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_48 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_48_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_48_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_48_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_47 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_47_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_47_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_47_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_46 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_46_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_46_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_46_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_45 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_45_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_45_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_45_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_44 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_44_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_44_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_44_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_19 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_19_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_19_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_19_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_18 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_18_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_18_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_18_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_17_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_16 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_16_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_16_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_16_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_15 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_15_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_15_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_15_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_14 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_14_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_14_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_14_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_13_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_12_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_12_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_11_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_10 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_10_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_10_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_10_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_09 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_09_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_09_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_09_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_08 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_08_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_08_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_08_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_07 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_07_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_07_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_07_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_06 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_06_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_06_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_06_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_05 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_05_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_05_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_05_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_04 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_04_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_04_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_04_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_03 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_03_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_03_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_03_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_02 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_02_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_02_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_02_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_01 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_01_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_01_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_01_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_00 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_00_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_00_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_00_DEFAULT 1 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_DEFAULT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_0 - Pinmux control register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_75 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_GPIO_75 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_VO_656_7 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_SDIO_CMD 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_SDS0_DEMOD_ERROR 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_SDS0_BERT_ERROR 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_PM_GPIO_75 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_74 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_GPIO_74 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_VO_656_6 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_SDIO_WPROT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_SDS0_DEMOD_VALID 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_SDS0_BERT_VALID 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_PM_GPIO_74 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_73 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_GPIO_73 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_VO_656_5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_SDIO_PRES 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_SDS0_DEMOD_SYNC 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_SDS0_BERT_SYNC 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_PM_GPIO_73 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_72 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_GPIO_72 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_VO_656_4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_SDIO_PWR0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_SDS0_DEMOD_DATA 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_SDS0_BERT_DATA 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_PM_GPIO_72 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_71 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_GPIO_71 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_VO_656_3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_SDIO_DATA3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_SDS0_DEMOD_CLK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_SDS0_BERT_CLK 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_PM_GPIO_71 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_70 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_GPIO_70 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_VO_656_2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_EXT_IRQB_15 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_SDIO_DATA2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_PM_GPIO_70 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_69 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_GPIO_69 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_VO_656_1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_EXT_IRQB_14 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_SDIO_DATA1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_PM_GPIO_69 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_68 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_GPIO_68 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_VO_656_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_EXT_IRQB_13 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_SDIO_DATA0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_PM_GPIO_68 4 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_1 - Pinmux control register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data1 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data1_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data1_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data1_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data1_EBI_DATA1 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data1_ALT_TP_IN_01 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data0 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_EBI_DATA0 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_ALT_TP_IN_00 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: clk_acc [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_clk_acc_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_clk_acc_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_clk_acc_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_clk_acc_CLK_ACC 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_clk_acc_EXT_SC_CLK 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: usb0_pwron [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_usb0_pwron_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_usb0_pwron_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_usb0_pwron_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_usb0_pwron_USB0_PWRON 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_usb0_pwron_TP_IN_20 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: aud_spdif [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_aud_spdif_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_aud_spdif_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_aud_spdif_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_aud_spdif_AUD_SPDIF 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_aud_spdif_RO_TEST_OUT 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_78 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_78_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_78_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_78_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_78_GPIO_78 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_78_TTX_DATA 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_78_EXT_IRQB_15 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_78_PM_GPIO_78 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_77 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_77_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_77_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_77_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_77_GPIO_77 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_77_TTX_REQ 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_77_SDIO_LED 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_77_PM_GPIO_77 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_76 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_76_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_76_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_76_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_76_GPIO_76 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_76_VO_656_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_76_SDIO_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_76_PM_GPIO_76 3 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_2 - Pinmux control register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data9 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data9_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data9_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data9_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data9_EBI_DATA9 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data9_ALT_TP_IN_09 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data8 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_EBI_DATA8 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_ALT_TP_IN_08 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data7 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_EBI_DATA7 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_ALT_TP_IN_07 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data6 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_EBI_DATA6 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_ALT_TP_IN_06 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data5 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_EBI_DATA5 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_ALT_TP_IN_05 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data4 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_EBI_DATA4 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_ALT_TP_IN_04 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data3 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_EBI_DATA3 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_ALT_TP_IN_03 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data2 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_EBI_DATA2 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_ALT_TP_IN_02 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_3 - Pinmux control register 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr1 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr1_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr1_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr1_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr1_EBI_ADDR1 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr1_ALT_TP_IN_17 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr0 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_EBI_ADDR0 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_ALT_TP_IN_16 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data15 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_EBI_DATA15 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_ALT_TP_IN_15 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data14 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_EBI_DATA14 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_ALT_TP_IN_14 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data13 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_EBI_DATA13 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_ALT_TP_IN_13 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data12 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_EBI_DATA12 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_ALT_TP_IN_12 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data11 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_EBI_DATA11 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_ALT_TP_IN_11 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data10 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_EBI_DATA10 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_ALT_TP_IN_10 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_4 - Pinmux control register 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr9 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr9_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr9_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr9_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr9_EBI_ADDR9 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr9_ALT_TP_IN_25 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr8 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_EBI_ADDR8 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_ALT_TP_OUT_24 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr7 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_EBI_ADDR7 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_ALT_TP_IN_23 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr6 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_EBI_ADDR6 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_ALT_TP_IN_22 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr5 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_EBI_ADDR5 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_ALT_TP_IN_21 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr4 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_EBI_ADDR4 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_ALT_TP_IN_20 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr3 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_EBI_ADDR3 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_ALT_TP_IN_19 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr2 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_EBI_ADDR2 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_ALT_TP_IN_18 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_5 - Pinmux control register 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_82 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_82_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_82_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_82_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_82_GPIO_82 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_82_USB2_PWRFLT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_82_PM_GPIO_82 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_81 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_81_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_81_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_81_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_81_GPIO_81 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_81_USB2_PWRON 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_81_PM_GPIO_81 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr15 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_EBI_ADDR15 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_ALT_TP_IN_31 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr14 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_EBI_ADDR14 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_ALT_TP_IN_30 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr13 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_EBI_ADDR13 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_ALT_TP_IN_29 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr12 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_EBI_ADDR12 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_ALT_TP_OUT_28 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr11 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_EBI_ADDR11 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_ALT_TP_IN_27 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr10 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_EBI_ADDR10 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_ALT_TP_IN_26 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_6 - Pinmux control register 6 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_05 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_GPIO_05 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_CHIP2CI_MDO_5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_PPKT_O_DATA_5 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_SDS0_O_DATA_5 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_I2S_BIDIR_CLK_IN 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_I2S_BIDIR_CLK_OUT 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_TP_OUT_09 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_PM_GPIO_05 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_04 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_GPIO_04 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_CHIP2CI_MDO_4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_PPKT_O_DATA_4 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_SDS0_O_DATA_4 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_I2S_BIDIR_SYNC_IN 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_I2S_BIDIR_SYNC_OUT 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_TP_OUT_08 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_PM_GPIO_04 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_03 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_GPIO_03 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_CHIP2CI_MDO_3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_PPKT_O_DATA_3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_SDS0_O_DATA_3 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_I2S_BIDIR_DATA_IN 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_I2S_BIDIR_DATA_OUT 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_TP_OUT_07 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_PM_GPIO_03 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_02 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_GPIO_02 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_CHIP2CI_MDO_2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_PPKT_O_DATA_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_SDS0_O_DATA_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_TP_OUT_06 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_PM_GPIO_02 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_01 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_GPIO_01 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_CHIP2CI_MDO_1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_PPKT_O_DATA_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_SDS0_O_DATA_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_TP_OUT_05 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_PM_GPIO_01 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_00 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_GPIO_00 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_CHIP2CI_MDO_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_PPKT_O_DATA_0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_SDS0_O_DATA_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_TP_OUT_04 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_PM_GPIO_00 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_84 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_84_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_84_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_84_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_84_GPIO_84 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_84_USB3_PWRFLT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_84_PM_GPIO_84 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_83 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_83_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_83_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_83_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_83_GPIO_83 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_83_USB3_PWRON 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_83_PM_GPIO_83 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_7 - Pinmux control register 7 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_13 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_GPIO_13 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_CI2CHIP_MIVAL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_PPKT_I_VALID 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_TP_OUT_17 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_PM_GPIO_13 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_12 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_GPIO_12 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_CI2CHIP_MISTRT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_PPKT_I_SYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_TP_OUT_16 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_PM_GPIO_12 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_11 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_GPIO_11 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_CHIP2CI_MOCLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_PPKT_O_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_SDS0_O_CLK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_CHIP2CI_MCLKO 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_TP_OUT_15 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_PM_GPIO_11 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_10 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_GPIO_10 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_CHIP2CI_MCLKO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_PPKT_O_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_SDS0_O_ERROR 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_CHIP2CI_MOCLK 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_TP_OUT_14 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_PM_GPIO_10 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_09 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_GPIO_09 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_CHIP2CI_MOVAL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_PPKT_O_VALID 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_SDS0_O_VALID 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_TP_OUT_13 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_PM_GPIO_09 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_08 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_GPIO_08 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_CHIP2CI_MOSTRT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_PPKT_O_SYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_SDS0_O_SYNC 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_TP_OUT_12 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_PM_GPIO_08 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_07 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_GPIO_07 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_CHIP2CI_MDO_7 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_PPKT_O_DATA_7 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_SDS0_O_DATA_7 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_TP_OUT_11 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_PM_GPIO_07 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_06 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_GPIO_06 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_CHIP2CI_MDO_6 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_PPKT_O_DATA_6 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_SDS0_O_DATA_6 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_TP_OUT_10 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_PM_GPIO_06 5 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_8 - Pinmux control register 8 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_24 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_GPIO_24 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_MII_RGMII_RXD_02 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_VEC_VSYNC_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_TP_IN_01 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_PM_GPIO_24 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_23 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_GPIO_23 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_MII_RGMII_RXD_03 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_VEC_VSYNC_0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_TP_IN_00 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_PM_GPIO_23 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_19 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_GPIO_19 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_SPI_S_MISO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_PWM_3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_EXT_SC_CLK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_AIO_EXTMCLK1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_CHIP2CC_SCTL 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_TP_OUT_23 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_PM_GPIO_19 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_18 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_GPIO_18 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_SPI_S_SS0B 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_PWM_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_AIO_EXTMCLK0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_CHIP2CC_SCLK 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_TP_OUT_22 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_PM_GPIO_18 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_17 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_GPIO_17 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_I2S_O_SYNC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_RMX_VALID0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_CHIP2CC_SDO 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_TP_OUT_21 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_PM_GPIO_17 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_16 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_GPIO_16 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_I2S_O_DATA 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_RMX_PAUSE0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_CC2CHIP_SDI 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_TP_OUT_20 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_PM_GPIO_16 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_15 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_GPIO_15 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_CI2CHIP_MICLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_PPKT_I_ERROR 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_CI2CHIP_MCLKI 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_TP_OUT_19 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_PM_GPIO_15 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_14 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_GPIO_14 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_CI2CHIP_MCLKI 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_PPKT_I_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_CI2CHIP_MICLK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_TP_OUT_18 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_PM_GPIO_14 5 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_9 - Pinmux control register 9 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_34 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_GPIO_34 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_MII_RGMII_TX_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_FSK_UART_MAN_DATA 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_TP_IN_11 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_PM_GPIO_34 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_31 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_31_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_31_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_31_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_31_GPIO_31 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_31_MII_RGMII_RX_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_31_TP_IN_08 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_31_PM_GPIO_31 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_30 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_30_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_30_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_30_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_30_GPIO_30 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_30_MII_COL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_30_TP_IN_07 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_30_PM_GPIO_30 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_29 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_29_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_29_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_29_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_29_GPIO_29 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_29_MII_CRS 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_29_TP_IN_06 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_29_PM_GPIO_29 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_28 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_28_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_28_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_28_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_28_GPIO_28 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_28_MII_RXDV_RGMII_RXCTL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_28_TP_IN_05 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_28_PM_GPIO_28 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_27 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_27_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_27_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_27_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_27_GPIO_27 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_27_MII_RX_ER 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_27_TP_IN_04 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_27_PM_GPIO_27 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_26 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_GPIO_26 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_MII_RGMII_RXD_00 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_VEC_HSYNC_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_TP_IN_03 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_PM_GPIO_26 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_25 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_GPIO_25 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_MII_RGMII_RXD_01 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_VEC_HSYNC_0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_TP_IN_02 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_PM_GPIO_25 4 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_10 - Pinmux control register 10 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_33 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_GPIO_33 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_MII_MDC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_EXT_IRQB_12 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_TP_IN_10 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_PM_GPIO_33 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_32 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_GPIO_32 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_MII_MDIO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_EXT_IRQB_11 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_TP_IN_09 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_PM_GPIO_32 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_40 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_40_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_40_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_40_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_40_GPIO_40 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_40_MII_RGMII_TXD_00 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_40_TP_IN_17 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_40_PM_GPIO_40 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_39 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_39_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_39_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_39_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_39_GPIO_39 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_39_MII_RGMII_TXD_01 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_39_TP_IN_16 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_39_PM_GPIO_39 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_38 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_38_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_38_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_38_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_38_GPIO_38 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_38_MII_RGMII_TXD_02 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_38_TP_IN_15 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_38_PM_GPIO_38 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_37 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_37_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_37_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_37_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_37_GPIO_37 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_37_MII_RGMII_TXD_03 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_37_TP_IN_14 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_37_PM_GPIO_37 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_36 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_36_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_36_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_36_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_36_GPIO_36 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_36_MII_TXER 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_36_TP_IN_13 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_36_PM_GPIO_36 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_35 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_GPIO_35 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_MII_TXEN_RGMII_TXCTL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_FSK_RX_DATA_BYP 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_TP_IN_12 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_PM_GPIO_35 4 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_11 - Pinmux control register 11 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_49 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_GPIO_49 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_SC0_IO_AUX1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_CI2CHIP_MDI_5 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_PPKT_I_DATA_5 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_TP_IN_26 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_PM_GPIO_49 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_48 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_GPIO_48 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_SC0_VCC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_CI2CHIP_MDI_4 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_PPKT_I_DATA_4 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_TP_IN_25 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_PM_GPIO_48 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_47 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_GPIO_47 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_SC0_PRES 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_CI2CHIP_MDI_3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_PPKT_I_DATA_3 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_TP_IN_24 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_PM_GPIO_47 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_46 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_GPIO_46 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_SC0_RST 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_CI2CHIP_MDI_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_PPKT_I_DATA_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_TP_IN_23 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_PM_GPIO_46 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_45 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_GPIO_45 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_SC0_CLK_OUT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_CI2CHIP_MDI_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_PPKT_I_DATA_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_TP_IN_22 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_PM_GPIO_45 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_44 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_GPIO_44 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_SC0_IO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_CI2CHIP_MDI_0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_PPKT_I_DATA_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_TP_IN_21 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_PM_GPIO_44 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_42 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_42_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_42_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_42_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_42_GPIO_42 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_42_PWM_1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_42_TP_IN_19 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_42_PM_GPIO_42 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_41 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_GPIO_41 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_PWM_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_PVTMON_DATA_FREQ 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_TP_IN_18 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_PM_GPIO_41 4 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_12 - Pinmux control register 12 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_20 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_20_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_20_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_20_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_20_GPIO_20 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_20_SC1_IO_AUX1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_20_PM_GPIO_20 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_56 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_56_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_56_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_56_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_56_GPIO_56 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_56_SC1_VCC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_56_ALT_TP_OUT_01 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_56_PM_GPIO_56 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_55 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_55_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_55_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_55_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_55_GPIO_55 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_55_SC1_PRES 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_55_ALT_TP_OUT_00 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_55_PM_GPIO_55 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_54 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_54_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_54_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_54_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_54_GPIO_54 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_54_SC1_RST 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_54_TP_IN_31 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_54_PM_GPIO_54 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_53 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_53_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_53_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_53_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_53_GPIO_53 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_53_SC1_CLK_OUT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_53_TP_IN_30 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_53_PM_GPIO_53 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_52 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_52_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_52_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_52_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_52_GPIO_52 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_52_SC1_IO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_52_TP_IN_29 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_52_PM_GPIO_52 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_51 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_GPIO_51 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_SC0_VPP 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_CI2CHIP_MDI_7 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_PPKT_I_DATA_7 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_TP_IN_28 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_PM_GPIO_51 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_50 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_GPIO_50 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_SC0_IO_AUX2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_CI2CHIP_MDI_6 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_PPKT_I_DATA_6 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_TP_IN_27 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_PM_GPIO_50 5 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_13 - Pinmux control register 13 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: rmx_clk0 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_rmx_clk0_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_rmx_clk0_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_rmx_clk0_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_rmx_clk0_RMX_CLK0 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_rmx_clk0_ALT_TP_OUT_15 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: pkt_error0 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_PKT_ERROR0 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_SDS0_DEMOD_ERROR 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_SDS0_BERT_ERROR 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_MTSIF_RX_DATA_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_PM_PKT_ERROR0 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: pkt_valid0 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_PKT_VALID0 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_SDS0_DEMOD_VALID 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_SDS0_BERT_VALID 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_MTSIF_RX_DATA_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_PM_PKT_VALID0 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: pkt_sync0 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_PKT_SYNC0 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_SDS0_DEMOD_SYNC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_SDS0_BERT_SYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_MTSIF_RX_SYNC 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_PM_PKT_SYNC0 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: pkt_data0 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_PKT_DATA0 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_SDS0_DEMOD_DATA 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_SDS0_BERT_DATA 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_MTSIF_RX_DATA_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_PM_PKT_DATA0 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: pkt_clk0 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_PKT_CLK0 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_SDS0_DEMOD_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_SDS0_BERT_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_MTSIF_RX_CLK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_PM_PKT_CLK0 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_22 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_22_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_22_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_22_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_22_GPIO_22 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_22_SC1_VPP 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_22_PM_GPIO_22 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_21 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_21_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_21_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_21_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_21_GPIO_21 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_21_SC1_IO_AUX2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_21_PM_GPIO_21 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_14 - Pinmux control register 14 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_62 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_GPIO_62 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_PKT_CLK2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_MTSIF_RX_DATA_7 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_ALT_TP_OUT_07 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_PM_GPIO_62 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_61 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_GPIO_61 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_PKT_ERROR1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_SDS0_DEMOD_ERROR 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_I2S_O_CLK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_PM_GPIO_61 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_60 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_GPIO_60 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_PKT_VALID1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_SDS0_DEMOD_VALID 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_MTSIF_RX_DATA_6 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_PM_GPIO_60 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_59 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_GPIO_59 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_PKT_SYNC1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_SDS0_DEMOD_SYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_MTSIF_RX_DATA_5 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_PM_GPIO_59 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_58 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_GPIO_58 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_PKT_DATA1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_SDS0_DEMOD_DATA 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_MTSIF_RX_DATA_4 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_PM_GPIO_58 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_57 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_GPIO_57 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_PKT_CLK1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_SDS0_DEMOD_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_MTSIF_RX_DATA_3 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_PM_GPIO_57 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: rmx_sync0 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_sync0_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_sync0_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_sync0_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_sync0_RMX_SYNC0 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_sync0_ALT_TP_OUT_17 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: rmx_data0 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_data0_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_data0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_data0_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_data0_RMX_DATA0 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_data0_ALT_TP_OUT_16 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_15 - Pinmux control register 15 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_80 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_80_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_80_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_80_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_80_GPIO_80 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_80_MOCA_ACTIVITY_N 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_80_EXT_IRQB_20 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_80_PM_GPIO_80 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_79 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_79_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_79_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_79_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_79_GPIO_79 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_79_MOCA_LINK_N 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_79_EXT_IRQB_19 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_79_PM_GPIO_79 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_66 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_GPIO_66 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_ENET_ACTIVITY 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_MOCA_ACTIVE_N 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_ALT_TP_OUT_14 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_PM_GPIO_66 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_43 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_GPIO_43 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_ENET_LINK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_MOCA_LINK_N 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_ALT_TP_OUT_13 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_PM_GPIO_43 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_67 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_GPIO_67 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_PKT_ERROR2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_MTSIC_ATS_RESET 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_ALT_TP_OUT_12 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_PM_GPIO_67 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_65 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_GPIO_65 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_PKT_VALID2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_MTSIF_ATS_INC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_ALT_TP_OUT_11 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_PM_GPIO_65 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_64 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_GPIO_64 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_PKT_SYNC2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_EXT_IRQB_18 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_ALT_TP_OUT_10 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_PM_GPIO_64 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_63 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_GPIO_63 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_PKT_DATA2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_EXT_IRQB_17 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_ALT_TP_OUT_09 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_PM_GPIO_63 4 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_16 - Pinmux control register 16 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: codec_sdi [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sdi_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sdi_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sdi_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sdi_CODEC_SDI 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sdi_ALT_TP_OUT_21 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sdi_PM_CODEC_SDI 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: codec_sclk [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sclk_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sclk_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sclk_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sclk_CODEC_SCLK 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sclk_I2S_O_SYNC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sclk_ALT_TP_OUT_20 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sclk_PM_CODEC_SCLK 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: codec_mclk [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_CODEC_MCLK 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_I2S_O_DATA 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_ALT_TP_OUT_19 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_PM_CODEC_MCLK 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: ir_out [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_ir_out_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_ir_out_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_ir_out_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_ir_out_IR_OUT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_ir_out_ALT_TP_OUT_18 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_ir_out_PM_IR_OUT 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_05 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_05_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_05_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_05_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_05_SGPIO_05 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_05_BSC_M3_SDA 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_04 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_SGPIO_04 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_BSC_M3_SCL 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_03 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_SGPIO_03 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_BSC_M1_SDA 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_02 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_SGPIO_02 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_BSC_M1_SCL 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_17 - Pinmux control register 17 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: uart_txdb [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txdb_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txdb_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txdb_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txdb_UART_TXDB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txdb_ALT_TP_OUT_29 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: uart_rxdb [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxdb_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxdb_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxdb_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxdb_UART_RXDB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxdb_ALT_TP_IN_28 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: uart_rtsab [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rtsab_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rtsab_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rtsab_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rtsab_UART_RTSAB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rtsab_ALT_TP_OUT_27 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: uart_ctsab [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_ctsab_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_ctsab_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_ctsab_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_ctsab_UART_CTSAB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_ctsab_ALT_TP_OUT_26 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: uart_txda [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txda_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txda_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txda_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txda_UART_TXDA 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txda_ALT_TP_OUT_25 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: uart_rxda [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxda_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxda_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxda_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxda_UART_RXDA 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxda_ALT_TP_IN_24 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: codec_fsync [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_CODEC_FSYNC 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_ALT_TP_OUT_23 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_PM_CODEC_FSYNC 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: codec_sdo [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_CODEC_SDO 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_I2S_O_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_ALT_TP_OUT_22 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_PM_CODEC_SDO 3 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_18 - Pinmux control register 18 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: uart_rtsbb [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rtsbb_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rtsbb_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rtsbb_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rtsbb_UART_RTSBB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rtsbb_ALT_TP_OUT_31 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: uart_ctsbb [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_ctsbb_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_ctsbb_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_ctsbb_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_ctsbb_UART_CTSBB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_ctsbb_ALT_TP_OUT_30 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [29:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK 0x3f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_78_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_78_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_78_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_78_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_78_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_78_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_78_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_77_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_77_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_77_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_77_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_77_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_77_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_77_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_76_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_76_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_76_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_76_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_76_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_76_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_76_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_75_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_75_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_75_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_75_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_75_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_75_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_75_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_74_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_74_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_74_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_74_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_74_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_74_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_74_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_73_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_73_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_73_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_73_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_73_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_73_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_73_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_72_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_72_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_72_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_72_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_72_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_72_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_72_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_71_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_71_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_71_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_71_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_71_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_71_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_71_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_70_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_70_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_70_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_70_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_70_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_70_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_70_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_69_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_69_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_69_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_69_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_69_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_69_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_69_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_68_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_68_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_68_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_68_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_68_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_68_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_68_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved1 [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK 0x3fffffff |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [29:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK 0x3fffffff |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: reserved0 [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved0_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved0_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_addr23_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr23_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr23_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr23_pad_ctrl_DEFAULT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr23_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr23_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr23_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: reserved1 [25:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved1_MASK 0x03ffffff |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved1_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_84_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_84_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_84_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_84_pad_ctrl_DEFAULT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_84_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_84_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_84_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_83_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_83_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_83_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_83_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_83_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_83_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_83_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_82_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_82_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_82_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_82_pad_ctrl_DEFAULT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_82_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_82_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_82_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_81_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_81_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_81_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_81_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_81_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_81_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_81_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved0 [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_dsb_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_dsb_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_dsb_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_dsb_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_dsb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_dsb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_dsb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_tsb_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsb_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsb_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsb_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved1 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved1_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved1_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_addr27_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_DEFAULT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_addr26_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_DEFAULT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_addr25_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_DEFAULT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_addr24_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_DEFAULT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved2 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved2_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved2_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_14_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_14_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_14_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_14_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_14_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_14_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_14_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_13_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_13_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_13_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_13_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_13_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_13_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_13_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_12_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_12_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_12_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_12_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_12_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_12_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_12_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_11_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_11_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_11_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_11_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_11_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_11_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_11_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_10_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_10_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_10_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_10_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_10_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_10_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_10_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_09_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_09_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_09_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_09_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_09_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_09_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_09_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_08_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_08_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_08_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_08_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_08_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_08_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_08_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_07_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_07_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_07_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_07_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_07_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_07_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_07_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_06_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_06_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_06_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_06_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_06_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_06_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_06_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_05_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_05_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_05_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_05_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_05_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_05_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_05_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_04_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_04_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_04_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_04_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_04_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_04_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_04_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_03_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_03_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_03_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_03_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_03_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_03_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_03_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_02_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_02_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_02_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_02_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_02_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_02_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_02_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_01_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_01_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_01_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_01_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_01_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_01_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_01_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_00_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_00_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_00_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_00_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_00_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_00_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_00_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_34_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_34_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_34_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_34_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_34_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_34_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_34_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_31_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_31_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_31_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_31_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_31_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_31_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_31_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_30_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_30_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_30_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_30_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_30_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_30_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_30_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_29_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_29_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_29_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_29_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_29_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_29_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_29_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_28_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_28_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_28_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_28_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_28_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_28_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_28_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_27_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_27_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_27_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_27_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_27_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_27_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_27_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_26_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_26_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_26_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_26_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_26_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_26_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_26_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_25_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_25_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_25_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_25_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_25_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_25_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_25_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_24_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_24_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_24_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_24_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_24_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_24_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_24_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_23_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_23_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_23_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_23_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_23_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_23_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_23_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_19_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_19_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_19_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_19_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_19_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_19_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_19_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_18_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_18_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_18_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_18_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_18_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_18_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_18_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_17_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_17_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_17_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_17_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_17_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_17_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_17_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_16_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_16_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_16_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_16_pad_ctrl_DEFAULT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_16_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_16_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_16_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_15_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_15_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_15_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_15_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_15_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_15_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_15_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_48_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_48_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_48_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_48_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_48_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_48_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_48_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_47_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_47_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_47_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_47_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_47_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_47_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_47_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_46_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_46_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_46_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_46_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_46_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_46_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_46_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_45_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_45_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_45_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_45_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_45_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_45_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_45_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_44_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_44_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_44_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_44_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_44_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_44_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_44_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_42_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_42_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_42_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_42_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_42_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_42_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_42_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_41_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_41_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_41_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_41_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_41_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_41_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_41_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_33_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_33_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_33_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_33_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_33_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_33_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_33_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_32_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_32_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_32_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_32_pad_ctrl_DEFAULT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_32_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_32_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_32_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_40_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_40_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_40_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_40_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_40_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_40_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_40_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_39_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_39_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_39_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_39_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_39_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_39_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_39_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_38_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_38_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_38_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_38_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_38_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_38_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_38_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_37_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_37_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_37_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_37_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_37_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_37_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_37_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_36_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_36_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_36_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_36_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_36_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_36_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_36_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_35_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_35_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_35_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_35_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_35_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_35_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_35_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved0 [29:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_MASK 0x3fc00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_22_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_22_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_22_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_22_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_22_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_22_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_22_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_21_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_21_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_21_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_21_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_21_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_21_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_21_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_20_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_20_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_20_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_20_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_20_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_20_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_20_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_56_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_56_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_56_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_56_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_56_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_56_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_56_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_55_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_55_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_55_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_55_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_55_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_55_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_55_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_54_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_54_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_54_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_54_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_54_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_54_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_54_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_53_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_53_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_53_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_53_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_53_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_53_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_53_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_52_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_52_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_52_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_52_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_52_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_52_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_52_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_51_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_51_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_51_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_51_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_51_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_51_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_51_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_50_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_50_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_50_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_50_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_50_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_50_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_50_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_49_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_49_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_49_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_49_pad_ctrl_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_49_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_49_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_49_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_9 - Pad pull-up/pull-down control register 9 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: spare_pad_ctrl_9 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_43_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_43_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_43_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_43_pad_ctrl_DEFAULT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_43_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_43_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_43_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_67_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_67_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_67_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_67_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_67_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_67_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_67_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_65_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_65_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_65_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_65_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_65_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_65_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_65_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_64_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_64_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_64_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_64_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_64_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_64_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_64_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_63_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_63_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_63_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_63_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_63_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_63_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_63_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_62_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_62_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_62_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_62_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_62_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_62_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_62_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_61_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_61_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_61_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_61_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_61_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_61_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_61_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_60_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_60_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_60_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_60_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_60_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_60_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_60_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_59_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_59_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_59_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_59_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_59_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_59_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_59_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_58_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_58_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_58_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_58_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_58_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_58_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_58_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_57_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_57_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_57_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_57_pad_ctrl_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_57_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_57_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_57_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: reserved0 [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved0_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_10 - Pad pull-up/pull-down control register 10 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: spare_pad_ctrl_10 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: reserved0 [29:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_reserved0_MASK 0x3fffffc0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_reserved0_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_80_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_80_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_80_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_80_pad_ctrl_DEFAULT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_80_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_80_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_80_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_79_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_79_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_79_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_79_pad_ctrl_DEFAULT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_79_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_79_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_79_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_66_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_66_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_66_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_66_pad_ctrl_DEFAULT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_66_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_66_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_66_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_11 - Pad pull-up/pull-down control register 11 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: reserved0 [31:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved0_MASK 0xffff0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved0_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: spare_pad_ctrl_11 [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: reserved1 [13:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved1_MASK 0x00003fff |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved1_SHIFT 0 |
| |
| /*************************************************************************** |
| *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:21] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK 0xffe00000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_79 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_79_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_79_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_79_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_59 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_59_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_59_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_59_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_58 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_58_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_58_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_58_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_57 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_57_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_57_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_57_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_pkt_valid0 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pkt_valid0_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pkt_valid0_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pkt_valid0_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_pkt_clk0 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pkt_clk0_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pkt_clk0_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pkt_clk0_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_cs3b [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs3b_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs3b_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs3b_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_nand_rbb [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_nand_rbb_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_nand_rbb_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_nand_rbb_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_cs5b [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs5b_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs5b_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs5b_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_cs4b [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs4b_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs4b_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs4b_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_cpu_clk [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_cpu_clk_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_cpu_clk_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_cpu_clk_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_moca_clk [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_moca_clk_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_moca_clk_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_moca_clk_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_clk_acc [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_clk_acc_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_clk_acc_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_clk_acc_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_vcxo27 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_vcxo27_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_vcxo27_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_vcxo27_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_usb1_pwrflt [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_usb1_pwrflt_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_usb1_pwrflt_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_usb1_pwrflt_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_usb0_pwrflt [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_usb0_pwrflt_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_usb0_pwrflt_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_usb0_pwrflt_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_76 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_76_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_76_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_76_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_72 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_72_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_72_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_72_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_71 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_71_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_71_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_71_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_69 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_69_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_69_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_69_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_68 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_68_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_68_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_68_DEFAULT 0 |
| |
| /*************************************************************************** |
| *RESET_CTRL - Reset control |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK 0xfffffffe |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT 0 |
| |
| /*************************************************************************** |
| *RESET_SOURCE_ENABLE - Reset source enable |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK 0xfffffc00 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SW_MASTER_RESET - Software master reset |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK 0xfffffffe |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0 |
| |
| /*************************************************************************** |
| *HW_RESET_EXTENSION - Hardware reset extension |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */ |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0 |
| |
| /*************************************************************************** |
| *RESET_MONITOR - Reset Monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0 |
| |
| /*************************************************************************** |
| *RESET_HISTORY - Reset history |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:17] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK 0xfffe0000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_reset [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_reset [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: security_dl_sw_reset [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT 0 |
| |
| /*************************************************************************** |
| *SW_INIT_0_SET - Software init 0 set |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: reserved0 [31:29] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved0_MASK 0xe0000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved0_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: svd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SW_INIT_0_CLEAR - Software init 0 clear |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: reserved0 [31:29] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved0_MASK 0xe0000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved0_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: svd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SW_INIT_0_STATUS - Software init 0 status |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: reserved0 [31:29] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved0_MASK 0xe0000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved0_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: svd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: reserved0 [31:29] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved0_MASK 0xe0000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved0_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_svd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: reserved0 [31:29] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved0_MASK 0xe0000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved0_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_svd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: reserved0 [31:29] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved0_MASK 0xe0000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved0_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_svd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *SW_INIT_1_SET - Software init 1 set |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK 0xffffff80 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_a_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_top_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_2 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: ftm_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: uhfr_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_uhfr_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_uhfr_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_uhfr_sw_init_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SW_INIT_1_CLEAR - Software init 1 clear |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK 0xffffff80 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_a_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_top_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_2 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: ftm_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: uhfr_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_uhfr_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_uhfr_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_uhfr_sw_init_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SW_INIT_1_STATUS - Software init 1 status |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK 0xffffff80 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_a_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_top_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_2 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: ftm_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: uhfr_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_uhfr_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_uhfr_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_uhfr_sw_init_DEFAULT 1 |
| |
| /*************************************************************************** |
| *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:07] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK 0xffffff80 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_a_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_top_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: ftm_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: uhfr_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_uhfr_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_uhfr_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:07] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xffffff80 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_a_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_top_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: ftm_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: uhfr_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_uhfr_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_uhfr_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:07] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK 0xffffff80 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_a_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_top_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: ftm_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: uhfr_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_uhfr_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_uhfr_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0 |
| |
| /*************************************************************************** |
| *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0 |
| |
| /*************************************************************************** |
| *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: reserved0 [31:29] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved0_MASK 0xe0000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved0_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: svd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0 |
| |
| /*************************************************************************** |
| *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:07] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xffffff80 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_a_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_top_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_2 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: ftm_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: uhfr_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_uhfr_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_uhfr_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_uhfr_sw_init_DEFAULT 0 |
| |
| /*************************************************************************** |
| *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0 |
| |
| /*************************************************************************** |
| *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: reserved0 [31:29] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved0_MASK 0xe0000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved0_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: svd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0 |
| |
| /*************************************************************************** |
| *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:07] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xffffff80 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_a_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_top_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_2 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: ftm_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: uhfr_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_uhfr_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_uhfr_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_uhfr_sw_init_DEFAULT 0 |
| |
| /*************************************************************************** |
| *UNCLEARED_SCRATCH - Scratch register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SPARE_CTRL - Spare control bits reserved for future use |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT 0 |
| |
| /*************************************************************************** |
| *TEST_PORT_CTRL - Test port control |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SOFT_MODEM_TP 9 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_14 14 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK 0x0ffffc00 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK 0x00000180 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK 0x0000007f |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 127 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET1 1 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU 2 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_R 4 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_A 5 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_T 6 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS 16 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK 17 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON 18 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF 20 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP 21 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNE 22 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNM 23 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC 25 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DVP_HT 26 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SVD0 27 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GFX 29 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO 30 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA 31 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT 33 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0 35 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0 45 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB1 46 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MOCA 47 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_UHFR 50 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_FTM 51 |
| |
| /*************************************************************************** |
| *TEST_PORT_OUT_PEEK - Testport peek register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_PORT_OUT_POKE - Testport poke register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0 |
| |
| /*************************************************************************** |
| *TEST_PORT_IN_PEEK - Testport peek register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_PORT_IN_POKE - Testport poke register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0 |
| |
| /*************************************************************************** |
| *EJTAG_INPUT_EN - EJTAG input bus enables |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:04] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK 0xfffffff0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 2 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_MIPS_CPU_ONE_HOT 2 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA_CPU_ONE_HOT 4 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 8 |
| |
| /*************************************************************************** |
| *EJTAG_OUTPUT_SEL - EJTAG output select |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:03] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK 0xfffffff8 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [02:00] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK 0x00000007 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_MIPS_CPU 1 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA_CPU 2 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 3 |
| |
| /*************************************************************************** |
| *UART_ROUTER_SEL - UART Router select |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AUDIO_FP 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_BL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SID 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_06 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_09 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_12 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_14 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_15 15 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AUDIO_FP 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_BL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SID 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_06 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_09 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_12 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_14 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_15 15 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AUDIO_FP 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_BL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SID 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_06 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_09 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_12 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_14 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_15 15 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AUDIO_FP 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_BL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SID 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_06 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_09 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_12 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_14 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_15 15 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AUDIO_FP 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_BL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SID 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_06 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_09 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_12 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_14 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_15 15 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_FP 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_BL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SID 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_06 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_09 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_FP 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_BL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SID 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_06 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_09 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_FP 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_BL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SID 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_06 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_09 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15 |
| |
| /*************************************************************************** |
| *VTRAP_CTRL - VTRAP Control |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:12] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK 0xfffff000 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_threshold [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_threshold [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_threshold [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [08:03] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x000001f8 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 24 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_status_clear [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_status_clear [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_status_clear [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_DEFAULT 0 |
| |
| /*************************************************************************** |
| *VTRAP_STATUS - VTRAP Status |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:03] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_status [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_status [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_status [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SSP_CONFIG - Serial Slave Port configuration register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK 0xfffff800 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK 0x00000780 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT 4 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK 0x00000078 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT 1 |
| |
| /*************************************************************************** |
| *SERS_REV - SERS Revision Register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK 0xffff0000 |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK 0x0000ff00 |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SERS_CFG - SERS Configuration Register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK 0xe0000000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode 1 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT 0 |
| |
| /* union - case mapped_buffer_mode [26:08] */ |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0 |
| |
| /* union - case cmd_fifo_mode [26:08] */ |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK 0x07c00000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK 0x003e0000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 31 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 16 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 1 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK 0x000000fe |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT 0 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SERS_CMD_BUF_%i - Host Serial Write Command Buffer |
| ***************************************************************************/ |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE 0x00404428 |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END 7 |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE 32 |
| |
| /*************************************************************************** |
| *SERS_CMD_BUF_%i - Host Serial Write Command Buffer |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT 0 |
| |
| |
| /*************************************************************************** |
| *SERS_STAT_BUF_%i - Host Serial Read Status Buffer |
| ***************************************************************************/ |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE 0x00404448 |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END 1 |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE 32 |
| |
| /*************************************************************************** |
| *SERS_STAT_BUF_%i - Host Serial Read Status Buffer |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT 0 |
| |
| |
| /*************************************************************************** |
| *RO_TEST_BLOCK_SEL - Block select for RO testmode |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK 0xffffffe0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_pwenb [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DEFAULT 1 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_ENABLED 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DISABLED 1 |
| |
| /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MIN_LOAD 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MED_LOAD 1 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MAX_LOAD 2 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SVT_MIN_LOAD 3 |
| |
| /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3 |
| |
| /*************************************************************************** |
| *TEST_CONFIGURATION - Test configuration |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK 0xfffffff0 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0 |
| |
| #endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */ |
| |
| /* End of File */ |
