| /*************************************************************************** |
| * Copyright (c) 1999-2009, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Wed Nov 18 01:15:44 2009 |
| * MD5 Checksum 8e4822e2d8c445f841e653dc06da5e41 |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: /magnum/basemodules/chp/7340/rdb/b0/bchp_vcxo_ctl_misc.h $ |
| * |
| * Hydra_Software_Devel/1 11/18/09 10:47a albertl |
| * SW7340-102: Initial revision. |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_VCXO_CTL_MISC_H__ |
| #define BCHP_VCXO_CTL_MISC_H__ |
| |
| /*************************************************************************** |
| *VCXO_CTL_MISC - VCXO Core Registers |
| ***************************************************************************/ |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL 0x00041200 /* VCXO 0 PLL reset, ndiv_mode, powerdown */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_CLOCK_ENA_1 0x00041204 /* VCXO 0 clock outputs enable */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_1 0x00041208 /* VCXO 0 channel 1 powerdown post divider */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_2 0x0004120c /* VCXO 0 channel 2 powerdown post divider */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_3 0x00041210 /* VCXO 0 channel 3 powerdown post divider */ |
| #define BCHP_VCXO_CTL_MISC_VC1_CTRL 0x00041214 /* VCXO 1 PLL reset, ndiv_mode, powerdown */ |
| #define BCHP_VCXO_CTL_MISC_VC1_PM_CLOCK_ENA_1 0x00041218 /* VCXO 1 clock outputs enable */ |
| #define BCHP_VCXO_CTL_MISC_VC1_PM_DIS_CHL_1 0x0004121c /* VCXO 1 channel 1 powerdown post divider */ |
| #define BCHP_VCXO_CTL_MISC_VC1_PM_DIS_CHL_2 0x00041220 /* VCXO 1 channel 2 powerdown post divider */ |
| #define BCHP_VCXO_CTL_MISC_VC1_PM_DIS_CHL_3 0x00041224 /* VCXO 1 channel 3 powerdown post divider */ |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL 0x00041228 /* Audio PLL 0 reset, ndiv_mode and powerdown */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_CLOCK_ENA_1 0x0004122c /* Audio PLL 0 clock outputs enable */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_1 0x00041230 /* Audio PLL 0 channel 1 powerdown post divider */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_2 0x00041234 /* Audio PLL 0 channel 2 powerdown post divider */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_3 0x00041238 /* Audio PLL 0 channel 3 powerdown post divider */ |
| #define BCHP_VCXO_CTL_MISC_AC1_CTRL 0x0004123c /* Audio PLL 1 reset, ndiv_mode and powerdown */ |
| #define BCHP_VCXO_CTL_MISC_AC1_PM_CLOCK_ENA_1 0x00041240 /* Audio PLL 1 clock outputs enable */ |
| #define BCHP_VCXO_CTL_MISC_AC1_PM_DIS_CHL_1 0x00041244 /* Audio PLL 1 channel 1 powerdown post divider */ |
| #define BCHP_VCXO_CTL_MISC_AC1_PM_DIS_CHL_2 0x00041248 /* Audio PLL 1 channel 2 powerdown post divider */ |
| #define BCHP_VCXO_CTL_MISC_AC1_PM_DIS_CHL_3 0x0004124c /* Audio PLL 1 channel 3 powerdown post divider */ |
| #define BCHP_VCXO_CTL_MISC_AC2_CTRL 0x00041250 /* Audio PLL 2 reset, ndiv_mode and powerdown */ |
| #define BCHP_VCXO_CTL_MISC_AC2_PM_CLOCK_ENA_1 0x00041254 /* Audio PLL 2 clock outputs enable */ |
| #define BCHP_VCXO_CTL_MISC_AC2_PM_DIS_CHL_1 0x00041258 /* Audio PLL 2 channel 1 powerdown post divider */ |
| #define BCHP_VCXO_CTL_MISC_AC2_PM_DIS_CHL_2 0x0004125c /* Audio PLL 2 channel 2 powerdown post divider */ |
| #define BCHP_VCXO_CTL_MISC_AC2_PM_DIS_CHL_3 0x00041260 /* Audio PLL 2 channel 3 powerdown post divider */ |
| #define BCHP_VCXO_CTL_MISC_SC_CTRL 0x00041264 /* smart card PLL reset, ndiv_mode and powerdown */ |
| #define BCHP_VCXO_CTL_MISC_SC_PM_CLOCK_ENA_1 0x00041268 /* smart card PLL clock outputs enable */ |
| #define BCHP_VCXO_CTL_MISC_SC_PM_DIS_CHL_1 0x0004126c /* smart card PLL channel 1 powerdown post divider */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL 0x00041270 /* RAP_AVD PLL reset */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1 0x00041274 /* RAP_AVD_PLL channel 1: 250 MHz raptor DSP clock, PLL source post divider powerdown, channel gate on/off and cml buffer enable */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6 0x00041278 /* RAP_AVD_PLL channel 6: 250 MHz AVD clock, PLL source post divider powerdown, channel gate on/off and cml buffer enable */ |
| #define BCHP_VCXO_CTL_MISC_LOCK 0x0004127c /* VCXO core lock status */ |
| #define BCHP_VCXO_CTL_MISC_VC0_DIV 0x00041280 /* VCXO 0 PLL divider settings */ |
| #define BCHP_VCXO_CTL_MISC_VC1_DIV 0x00041284 /* VCXO 1 PLL divider settings */ |
| #define BCHP_VCXO_CTL_MISC_AVD_RAP_DIV 0x00041288 /* AVD RAP PLL divider settings */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET 0x0004128c /* VCXO Lock Counter Reset */ |
| #define BCHP_VCXO_CTL_MISC_VC0_LOCK_CNT 0x00041290 /* VCXO 0 PLL Lock Counter */ |
| #define BCHP_VCXO_CTL_MISC_VC1_LOCK_CNT 0x00041294 /* VCXO 1 PLL Lock Counter */ |
| #define BCHP_VCXO_CTL_MISC_AC0_LOCK_CNT 0x00041298 /* Audio PLL 0 Lock Counter */ |
| #define BCHP_VCXO_CTL_MISC_AC1_LOCK_CNT 0x0004129c /* Audio PLL 1 Lock Counter */ |
| #define BCHP_VCXO_CTL_MISC_AC2_LOCK_CNT 0x000412a0 /* Audio PLL 2 Lock Counter */ |
| #define BCHP_VCXO_CTL_MISC_SC_LOCK_CNT 0x000412a4 /* Smart Card PLL Lock Counter */ |
| #define BCHP_VCXO_CTL_MISC_AUDDSP_LOCK_CNT 0x000412a8 /* Audio DSP PLL Lock Counter */ |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL 0x000412ac /* TOP LEVEL PLLs (except MIPS, RAPAVD and NETWORK PLL) test select */ |
| #define BCHP_VCXO_CTL_MISC_MIPS_RAPAVD_PLL_TEST_SEL 0x000412b0 /* MIPS and RAPAVD PLL test select */ |
| #define BCHP_VCXO_CTL_MISC_NETWORK_PLL_TEST_SEL 0x000412b4 /* NETWORK PLL test select */ |
| |
| /*************************************************************************** |
| *VC0_CTRL - VCXO 0 PLL reset, ndiv_mode, powerdown |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: VC0_CTRL :: reserved0 [31:07] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_reserved0_MASK 0xffffff80 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_reserved0_SHIFT 7 |
| |
| /* VCXO_CTL_MISC :: VC0_CTRL :: NDIV_MODE [06:04] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_NDIV_MODE_MASK 0x00000070 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_NDIV_MODE_SHIFT 4 |
| |
| /* VCXO_CTL_MISC :: VC0_CTRL :: POWERDOWN [03:03] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_POWERDOWN_MASK 0x00000008 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_POWERDOWN_SHIFT 3 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_POWERDOWN_Powerdown 1 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_POWERDOWN_Normal 0 |
| |
| /* VCXO_CTL_MISC :: VC0_CTRL :: RESERVED [02:02] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_RESERVED_MASK 0x00000004 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_RESERVED_SHIFT 2 |
| |
| /* VCXO_CTL_MISC :: VC0_CTRL :: DRESET [01:01] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_DRESET_MASK 0x00000002 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_DRESET_SHIFT 1 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_DRESET_Reset 1 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_DRESET_Normal 0 |
| |
| /* VCXO_CTL_MISC :: VC0_CTRL :: ARESET [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_ARESET_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_ARESET_SHIFT 0 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_ARESET_Reset 1 |
| #define BCHP_VCXO_CTL_MISC_VC0_CTRL_ARESET_Normal 0 |
| |
| /*************************************************************************** |
| *VC0_PM_CLOCK_ENA_1 - VCXO 0 clock outputs enable |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: VC0_PM_CLOCK_ENA_1 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_CLOCK_ENA_1_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_CLOCK_ENA_1_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: VC0_PM_CLOCK_ENA_1 :: CLOCK_ENA [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_CLOCK_ENA_1_CLOCK_ENA_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_CLOCK_ENA_1_CLOCK_ENA_SHIFT 0 |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_CLOCK_ENA_1_CLOCK_ENA_Enable 1 |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_CLOCK_ENA_1_CLOCK_ENA_Disable 0 |
| |
| /*************************************************************************** |
| *VC0_PM_DIS_CHL_1 - VCXO 0 channel 1 powerdown post divider |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: VC0_PM_DIS_CHL_1 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_1_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_1_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: VC0_PM_DIS_CHL_1 :: DIS_CH [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_1_DIS_CH_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_1_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *VC0_PM_DIS_CHL_2 - VCXO 0 channel 2 powerdown post divider |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: VC0_PM_DIS_CHL_2 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_2_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_2_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: VC0_PM_DIS_CHL_2 :: DIS_CH [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_2_DIS_CH_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_2_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *VC0_PM_DIS_CHL_3 - VCXO 0 channel 3 powerdown post divider |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: VC0_PM_DIS_CHL_3 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_3_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_3_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: VC0_PM_DIS_CHL_3 :: DIS_CH [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_3_DIS_CH_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_3_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *VC1_CTRL - VCXO 1 PLL reset, ndiv_mode, powerdown |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: VC1_CTRL :: reserved0 [31:07] */ |
| #define BCHP_VCXO_CTL_MISC_VC1_CTRL_reserved0_MASK 0xffffff80 |
| #define BCHP_VCXO_CTL_MISC_VC1_CTRL_reserved0_SHIFT 7 |
| |
| /* VCXO_CTL_MISC :: VC1_CTRL :: NDIV_MODE [06:04] */ |
| #define BCHP_VCXO_CTL_MISC_VC1_CTRL_NDIV_MODE_MASK 0x00000070 |
| #define BCHP_VCXO_CTL_MISC_VC1_CTRL_NDIV_MODE_SHIFT 4 |
| |
| /* VCXO_CTL_MISC :: VC1_CTRL :: POWERDOWN [03:03] */ |
| #define BCHP_VCXO_CTL_MISC_VC1_CTRL_POWERDOWN_MASK 0x00000008 |
| #define BCHP_VCXO_CTL_MISC_VC1_CTRL_POWERDOWN_SHIFT 3 |
| #define BCHP_VCXO_CTL_MISC_VC1_CTRL_POWERDOWN_Powerdown 1 |
| #define BCHP_VCXO_CTL_MISC_VC1_CTRL_POWERDOWN_Normal 0 |
| |
| /* VCXO_CTL_MISC :: VC1_CTRL :: RESERVED [02:02] */ |
| #define BCHP_VCXO_CTL_MISC_VC1_CTRL_RESERVED_MASK 0x00000004 |
| #define BCHP_VCXO_CTL_MISC_VC1_CTRL_RESERVED_SHIFT 2 |
| |
| /* VCXO_CTL_MISC :: VC1_CTRL :: DRESET [01:01] */ |
| #define BCHP_VCXO_CTL_MISC_VC1_CTRL_DRESET_MASK 0x00000002 |
| #define BCHP_VCXO_CTL_MISC_VC1_CTRL_DRESET_SHIFT 1 |
| #define BCHP_VCXO_CTL_MISC_VC1_CTRL_DRESET_Reset 1 |
| #define BCHP_VCXO_CTL_MISC_VC1_CTRL_DRESET_Normal 0 |
| |
| /* VCXO_CTL_MISC :: VC1_CTRL :: ARESET [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_VC1_CTRL_ARESET_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_VC1_CTRL_ARESET_SHIFT 0 |
| #define BCHP_VCXO_CTL_MISC_VC1_CTRL_ARESET_Reset 1 |
| #define BCHP_VCXO_CTL_MISC_VC1_CTRL_ARESET_Normal 0 |
| |
| /*************************************************************************** |
| *VC1_PM_CLOCK_ENA_1 - VCXO 1 clock outputs enable |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: VC1_PM_CLOCK_ENA_1 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_VC1_PM_CLOCK_ENA_1_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_VC1_PM_CLOCK_ENA_1_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: VC1_PM_CLOCK_ENA_1 :: CLOCK_ENA [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_VC1_PM_CLOCK_ENA_1_CLOCK_ENA_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_VC1_PM_CLOCK_ENA_1_CLOCK_ENA_SHIFT 0 |
| #define BCHP_VCXO_CTL_MISC_VC1_PM_CLOCK_ENA_1_CLOCK_ENA_Enable 1 |
| #define BCHP_VCXO_CTL_MISC_VC1_PM_CLOCK_ENA_1_CLOCK_ENA_Disable 0 |
| |
| /*************************************************************************** |
| *VC1_PM_DIS_CHL_1 - VCXO 1 channel 1 powerdown post divider |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: VC1_PM_DIS_CHL_1 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_VC1_PM_DIS_CHL_1_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_VC1_PM_DIS_CHL_1_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: VC1_PM_DIS_CHL_1 :: DIS_CH [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_VC1_PM_DIS_CHL_1_DIS_CH_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_VC1_PM_DIS_CHL_1_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *VC1_PM_DIS_CHL_2 - VCXO 1 channel 2 powerdown post divider |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: VC1_PM_DIS_CHL_2 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_VC1_PM_DIS_CHL_2_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_VC1_PM_DIS_CHL_2_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: VC1_PM_DIS_CHL_2 :: DIS_CH [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_VC1_PM_DIS_CHL_2_DIS_CH_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_VC1_PM_DIS_CHL_2_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *VC1_PM_DIS_CHL_3 - VCXO 1 channel 3 powerdown post divider |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: VC1_PM_DIS_CHL_3 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_VC1_PM_DIS_CHL_3_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_VC1_PM_DIS_CHL_3_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: VC1_PM_DIS_CHL_3 :: DIS_CH [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_VC1_PM_DIS_CHL_3_DIS_CH_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_VC1_PM_DIS_CHL_3_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC0_CTRL - Audio PLL 0 reset, ndiv_mode and powerdown |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC0_CTRL :: reserved0 [31:03] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_reserved0_SHIFT 3 |
| |
| /* VCXO_CTL_MISC :: AC0_CTRL :: POWERDOWN [02:02] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_POWERDOWN_MASK 0x00000004 |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_POWERDOWN_SHIFT 2 |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_POWERDOWN_Powerdown 1 |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_POWERDOWN_Normal 0 |
| |
| /* VCXO_CTL_MISC :: AC0_CTRL :: RESET [01:01] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_RESET_MASK 0x00000002 |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_RESET_SHIFT 1 |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_RESET_Reset 1 |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_RESET_Normal 0 |
| |
| /* VCXO_CTL_MISC :: AC0_CTRL :: RESERVED [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_RESERVED_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_AC0_CTRL_RESERVED_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC0_PM_CLOCK_ENA_1 - Audio PLL 0 clock outputs enable |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC0_PM_CLOCK_ENA_1 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_CLOCK_ENA_1_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_CLOCK_ENA_1_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: AC0_PM_CLOCK_ENA_1 :: CLOCK_ENA [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_CLOCK_ENA_1_CLOCK_ENA_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_CLOCK_ENA_1_CLOCK_ENA_SHIFT 0 |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_CLOCK_ENA_1_CLOCK_ENA_Enable 1 |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_CLOCK_ENA_1_CLOCK_ENA_Disable 0 |
| |
| /*************************************************************************** |
| *AC0_PM_DIS_CHL_1 - Audio PLL 0 channel 1 powerdown post divider |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC0_PM_DIS_CHL_1 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_1_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_1_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: AC0_PM_DIS_CHL_1 :: DIS_CH [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_1_DIS_CH_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_1_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC0_PM_DIS_CHL_2 - Audio PLL 0 channel 2 powerdown post divider |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC0_PM_DIS_CHL_2 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_2_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_2_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: AC0_PM_DIS_CHL_2 :: DIS_CH [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_2_DIS_CH_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_2_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC0_PM_DIS_CHL_3 - Audio PLL 0 channel 3 powerdown post divider |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC0_PM_DIS_CHL_3 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_3_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_3_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: AC0_PM_DIS_CHL_3 :: DIS_CH [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_3_DIS_CH_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_3_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC1_CTRL - Audio PLL 1 reset, ndiv_mode and powerdown |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC1_CTRL :: reserved0 [31:03] */ |
| #define BCHP_VCXO_CTL_MISC_AC1_CTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_VCXO_CTL_MISC_AC1_CTRL_reserved0_SHIFT 3 |
| |
| /* VCXO_CTL_MISC :: AC1_CTRL :: POWERDOWN [02:02] */ |
| #define BCHP_VCXO_CTL_MISC_AC1_CTRL_POWERDOWN_MASK 0x00000004 |
| #define BCHP_VCXO_CTL_MISC_AC1_CTRL_POWERDOWN_SHIFT 2 |
| #define BCHP_VCXO_CTL_MISC_AC1_CTRL_POWERDOWN_Powerdown 1 |
| #define BCHP_VCXO_CTL_MISC_AC1_CTRL_POWERDOWN_Normal 0 |
| |
| /* VCXO_CTL_MISC :: AC1_CTRL :: RESET [01:01] */ |
| #define BCHP_VCXO_CTL_MISC_AC1_CTRL_RESET_MASK 0x00000002 |
| #define BCHP_VCXO_CTL_MISC_AC1_CTRL_RESET_SHIFT 1 |
| #define BCHP_VCXO_CTL_MISC_AC1_CTRL_RESET_Reset 1 |
| #define BCHP_VCXO_CTL_MISC_AC1_CTRL_RESET_Normal 0 |
| |
| /* VCXO_CTL_MISC :: AC1_CTRL :: RESERVED [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC1_CTRL_RESERVED_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_AC1_CTRL_RESERVED_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC1_PM_CLOCK_ENA_1 - Audio PLL 1 clock outputs enable |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC1_PM_CLOCK_ENA_1 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_AC1_PM_CLOCK_ENA_1_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_AC1_PM_CLOCK_ENA_1_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: AC1_PM_CLOCK_ENA_1 :: CLOCK_ENA [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC1_PM_CLOCK_ENA_1_CLOCK_ENA_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_AC1_PM_CLOCK_ENA_1_CLOCK_ENA_SHIFT 0 |
| #define BCHP_VCXO_CTL_MISC_AC1_PM_CLOCK_ENA_1_CLOCK_ENA_Enable 1 |
| #define BCHP_VCXO_CTL_MISC_AC1_PM_CLOCK_ENA_1_CLOCK_ENA_Disable 0 |
| |
| /*************************************************************************** |
| *AC1_PM_DIS_CHL_1 - Audio PLL 1 channel 1 powerdown post divider |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC1_PM_DIS_CHL_1 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_AC1_PM_DIS_CHL_1_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_AC1_PM_DIS_CHL_1_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: AC1_PM_DIS_CHL_1 :: DIS_CH [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC1_PM_DIS_CHL_1_DIS_CH_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_AC1_PM_DIS_CHL_1_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC1_PM_DIS_CHL_2 - Audio PLL 1 channel 2 powerdown post divider |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC1_PM_DIS_CHL_2 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_AC1_PM_DIS_CHL_2_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_AC1_PM_DIS_CHL_2_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: AC1_PM_DIS_CHL_2 :: DIS_CH [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC1_PM_DIS_CHL_2_DIS_CH_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_AC1_PM_DIS_CHL_2_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC1_PM_DIS_CHL_3 - Audio PLL 1 channel 3 powerdown post divider |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC1_PM_DIS_CHL_3 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_AC1_PM_DIS_CHL_3_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_AC1_PM_DIS_CHL_3_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: AC1_PM_DIS_CHL_3 :: DIS_CH [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC1_PM_DIS_CHL_3_DIS_CH_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_AC1_PM_DIS_CHL_3_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC2_CTRL - Audio PLL 2 reset, ndiv_mode and powerdown |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC2_CTRL :: reserved0 [31:03] */ |
| #define BCHP_VCXO_CTL_MISC_AC2_CTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_VCXO_CTL_MISC_AC2_CTRL_reserved0_SHIFT 3 |
| |
| /* VCXO_CTL_MISC :: AC2_CTRL :: POWERDOWN [02:02] */ |
| #define BCHP_VCXO_CTL_MISC_AC2_CTRL_POWERDOWN_MASK 0x00000004 |
| #define BCHP_VCXO_CTL_MISC_AC2_CTRL_POWERDOWN_SHIFT 2 |
| #define BCHP_VCXO_CTL_MISC_AC2_CTRL_POWERDOWN_Powerdown 1 |
| #define BCHP_VCXO_CTL_MISC_AC2_CTRL_POWERDOWN_Normal 0 |
| |
| /* VCXO_CTL_MISC :: AC2_CTRL :: RESET [01:01] */ |
| #define BCHP_VCXO_CTL_MISC_AC2_CTRL_RESET_MASK 0x00000002 |
| #define BCHP_VCXO_CTL_MISC_AC2_CTRL_RESET_SHIFT 1 |
| #define BCHP_VCXO_CTL_MISC_AC2_CTRL_RESET_Reset 1 |
| #define BCHP_VCXO_CTL_MISC_AC2_CTRL_RESET_Normal 0 |
| |
| /* VCXO_CTL_MISC :: AC2_CTRL :: RESERVED [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC2_CTRL_RESERVED_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_AC2_CTRL_RESERVED_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC2_PM_CLOCK_ENA_1 - Audio PLL 2 clock outputs enable |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC2_PM_CLOCK_ENA_1 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_AC2_PM_CLOCK_ENA_1_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_AC2_PM_CLOCK_ENA_1_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: AC2_PM_CLOCK_ENA_1 :: CLOCK_ENA [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC2_PM_CLOCK_ENA_1_CLOCK_ENA_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_AC2_PM_CLOCK_ENA_1_CLOCK_ENA_SHIFT 0 |
| #define BCHP_VCXO_CTL_MISC_AC2_PM_CLOCK_ENA_1_CLOCK_ENA_Enable 1 |
| #define BCHP_VCXO_CTL_MISC_AC2_PM_CLOCK_ENA_1_CLOCK_ENA_Disable 0 |
| |
| /*************************************************************************** |
| *AC2_PM_DIS_CHL_1 - Audio PLL 2 channel 1 powerdown post divider |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC2_PM_DIS_CHL_1 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_AC2_PM_DIS_CHL_1_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_AC2_PM_DIS_CHL_1_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: AC2_PM_DIS_CHL_1 :: DIS_CH [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC2_PM_DIS_CHL_1_DIS_CH_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_AC2_PM_DIS_CHL_1_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC2_PM_DIS_CHL_2 - Audio PLL 2 channel 2 powerdown post divider |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC2_PM_DIS_CHL_2 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_AC2_PM_DIS_CHL_2_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_AC2_PM_DIS_CHL_2_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: AC2_PM_DIS_CHL_2 :: DIS_CH [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC2_PM_DIS_CHL_2_DIS_CH_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_AC2_PM_DIS_CHL_2_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC2_PM_DIS_CHL_3 - Audio PLL 2 channel 3 powerdown post divider |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC2_PM_DIS_CHL_3 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_AC2_PM_DIS_CHL_3_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_AC2_PM_DIS_CHL_3_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: AC2_PM_DIS_CHL_3 :: DIS_CH [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC2_PM_DIS_CHL_3_DIS_CH_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_AC2_PM_DIS_CHL_3_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *SC_CTRL - smart card PLL reset, ndiv_mode and powerdown |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: SC_CTRL :: reserved0 [31:03] */ |
| #define BCHP_VCXO_CTL_MISC_SC_CTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_VCXO_CTL_MISC_SC_CTRL_reserved0_SHIFT 3 |
| |
| /* VCXO_CTL_MISC :: SC_CTRL :: POWERDOWN [02:02] */ |
| #define BCHP_VCXO_CTL_MISC_SC_CTRL_POWERDOWN_MASK 0x00000004 |
| #define BCHP_VCXO_CTL_MISC_SC_CTRL_POWERDOWN_SHIFT 2 |
| #define BCHP_VCXO_CTL_MISC_SC_CTRL_POWERDOWN_Powerdown 1 |
| #define BCHP_VCXO_CTL_MISC_SC_CTRL_POWERDOWN_Normal 0 |
| |
| /* VCXO_CTL_MISC :: SC_CTRL :: RESET [01:01] */ |
| #define BCHP_VCXO_CTL_MISC_SC_CTRL_RESET_MASK 0x00000002 |
| #define BCHP_VCXO_CTL_MISC_SC_CTRL_RESET_SHIFT 1 |
| #define BCHP_VCXO_CTL_MISC_SC_CTRL_RESET_Reset 1 |
| #define BCHP_VCXO_CTL_MISC_SC_CTRL_RESET_Normal 0 |
| |
| /* VCXO_CTL_MISC :: SC_CTRL :: RESERVED [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_SC_CTRL_RESERVED_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_SC_CTRL_RESERVED_SHIFT 0 |
| |
| /*************************************************************************** |
| *SC_PM_CLOCK_ENA_1 - smart card PLL clock outputs enable |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: SC_PM_CLOCK_ENA_1 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_SC_PM_CLOCK_ENA_1_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_SC_PM_CLOCK_ENA_1_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: SC_PM_CLOCK_ENA_1 :: CLOCK_ENA [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_SC_PM_CLOCK_ENA_1_CLOCK_ENA_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_SC_PM_CLOCK_ENA_1_CLOCK_ENA_SHIFT 0 |
| #define BCHP_VCXO_CTL_MISC_SC_PM_CLOCK_ENA_1_CLOCK_ENA_Enable 1 |
| #define BCHP_VCXO_CTL_MISC_SC_PM_CLOCK_ENA_1_CLOCK_ENA_Disable 0 |
| |
| /*************************************************************************** |
| *SC_PM_DIS_CHL_1 - smart card PLL channel 1 powerdown post divider |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: SC_PM_DIS_CHL_1 :: reserved0 [31:01] */ |
| #define BCHP_VCXO_CTL_MISC_SC_PM_DIS_CHL_1_reserved0_MASK 0xfffffffe |
| #define BCHP_VCXO_CTL_MISC_SC_PM_DIS_CHL_1_reserved0_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: SC_PM_DIS_CHL_1 :: DIS_CH [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_SC_PM_DIS_CHL_1_DIS_CH_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_SC_PM_DIS_CHL_1_DIS_CH_SHIFT 0 |
| |
| /*************************************************************************** |
| *RAP_AVD_PLL_CTRL - RAP_AVD PLL reset |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CTRL :: LDO_CTRL [31:30] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_LDO_CTRL_MASK 0xc0000000 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_LDO_CTRL_SHIFT 30 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CTRL :: reserved0 [29:08] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_reserved0_MASK 0x3fffff00 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_reserved0_SHIFT 8 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CTRL :: POWERDOWN [07:07] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_POWERDOWN_MASK 0x00000080 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_POWERDOWN_SHIFT 7 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_POWERDOWN_Powerdown 1 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_POWERDOWN_Normal 0 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CTRL :: reserved1 [06:01] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_reserved1_MASK 0x0000007e |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_reserved1_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CTRL :: RESET [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_RESET_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_RESET_SHIFT 0 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_RESET_Reset 1 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_RESET_Normal 0 |
| |
| /*************************************************************************** |
| *RAP_AVD_PLL_CHL_1 - RAP_AVD_PLL channel 1: 250 MHz raptor DSP clock, PLL source post divider powerdown, channel gate on/off and cml buffer enable |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_1 :: reserved0 [31:03] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_reserved0_MASK 0xfffffff8 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_reserved0_SHIFT 3 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_1 :: DIS_CH [02:02] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_DIS_CH_MASK 0x00000004 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_DIS_CH_SHIFT 2 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_1 :: CLOCK_ENA [01:01] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_CLOCK_ENA_MASK 0x00000002 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_CLOCK_ENA_SHIFT 1 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_CLOCK_ENA_Enable 1 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_CLOCK_ENA_Disable 0 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_1 :: EN_CMLBUF [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_EN_CMLBUF_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_EN_CMLBUF_SHIFT 0 |
| |
| /*************************************************************************** |
| *RAP_AVD_PLL_CHL_6 - RAP_AVD_PLL channel 6: 250 MHz AVD clock, PLL source post divider powerdown, channel gate on/off and cml buffer enable |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_6 :: reserved0 [31:03] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_reserved0_MASK 0xfffffff8 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_reserved0_SHIFT 3 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_6 :: DIS_CH [02:02] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_DIS_CH_MASK 0x00000004 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_DIS_CH_SHIFT 2 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_6 :: CLOCK_ENA [01:01] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_CLOCK_ENA_MASK 0x00000002 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_CLOCK_ENA_SHIFT 1 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_CLOCK_ENA_Enable 1 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_CLOCK_ENA_Disable 0 |
| |
| /* VCXO_CTL_MISC :: RAP_AVD_PLL_CHL_6 :: EN_CMLBUF [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_EN_CMLBUF_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_EN_CMLBUF_SHIFT 0 |
| |
| /*************************************************************************** |
| *LOCK - VCXO core lock status |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: LOCK :: reserved0 [31:07] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_reserved0_MASK 0xffffff80 |
| #define BCHP_VCXO_CTL_MISC_LOCK_reserved0_SHIFT 7 |
| |
| /* VCXO_CTL_MISC :: LOCK :: AUDDSP [06:06] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_AUDDSP_MASK 0x00000040 |
| #define BCHP_VCXO_CTL_MISC_LOCK_AUDDSP_SHIFT 6 |
| |
| /* VCXO_CTL_MISC :: LOCK :: SC [05:05] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_SC_MASK 0x00000020 |
| #define BCHP_VCXO_CTL_MISC_LOCK_SC_SHIFT 5 |
| |
| /* VCXO_CTL_MISC :: LOCK :: AC2 [04:04] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_AC2_MASK 0x00000010 |
| #define BCHP_VCXO_CTL_MISC_LOCK_AC2_SHIFT 4 |
| |
| /* VCXO_CTL_MISC :: LOCK :: AC1 [03:03] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_AC1_MASK 0x00000008 |
| #define BCHP_VCXO_CTL_MISC_LOCK_AC1_SHIFT 3 |
| |
| /* VCXO_CTL_MISC :: LOCK :: AC0 [02:02] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_AC0_MASK 0x00000004 |
| #define BCHP_VCXO_CTL_MISC_LOCK_AC0_SHIFT 2 |
| |
| /* VCXO_CTL_MISC :: LOCK :: VC1 [01:01] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_VC1_MASK 0x00000002 |
| #define BCHP_VCXO_CTL_MISC_LOCK_VC1_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: LOCK :: VC0 [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_VC0_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_LOCK_VC0_SHIFT 0 |
| |
| /*************************************************************************** |
| *VC0_DIV - VCXO 0 PLL divider settings |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: VC0_DIV :: reserved0 [31:26] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_DIV_reserved0_MASK 0xfc000000 |
| #define BCHP_VCXO_CTL_MISC_VC0_DIV_reserved0_SHIFT 26 |
| |
| /* VCXO_CTL_MISC :: VC0_DIV :: VCORNG [25:24] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_DIV_VCORNG_MASK 0x03000000 |
| #define BCHP_VCXO_CTL_MISC_VC0_DIV_VCORNG_SHIFT 24 |
| |
| /* VCXO_CTL_MISC :: VC0_DIV :: M3DIV [23:16] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_DIV_M3DIV_MASK 0x00ff0000 |
| #define BCHP_VCXO_CTL_MISC_VC0_DIV_M3DIV_SHIFT 16 |
| |
| /* VCXO_CTL_MISC :: VC0_DIV :: M2DIV [15:08] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_DIV_M2DIV_MASK 0x0000ff00 |
| #define BCHP_VCXO_CTL_MISC_VC0_DIV_M2DIV_SHIFT 8 |
| |
| /* VCXO_CTL_MISC :: VC0_DIV :: M1DIV [07:00] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_DIV_M1DIV_MASK 0x000000ff |
| #define BCHP_VCXO_CTL_MISC_VC0_DIV_M1DIV_SHIFT 0 |
| |
| /*************************************************************************** |
| *VC1_DIV - VCXO 1 PLL divider settings |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: VC1_DIV :: reserved0 [31:26] */ |
| #define BCHP_VCXO_CTL_MISC_VC1_DIV_reserved0_MASK 0xfc000000 |
| #define BCHP_VCXO_CTL_MISC_VC1_DIV_reserved0_SHIFT 26 |
| |
| /* VCXO_CTL_MISC :: VC1_DIV :: VCORNG [25:24] */ |
| #define BCHP_VCXO_CTL_MISC_VC1_DIV_VCORNG_MASK 0x03000000 |
| #define BCHP_VCXO_CTL_MISC_VC1_DIV_VCORNG_SHIFT 24 |
| |
| /* VCXO_CTL_MISC :: VC1_DIV :: M3DIV [23:16] */ |
| #define BCHP_VCXO_CTL_MISC_VC1_DIV_M3DIV_MASK 0x00ff0000 |
| #define BCHP_VCXO_CTL_MISC_VC1_DIV_M3DIV_SHIFT 16 |
| |
| /* VCXO_CTL_MISC :: VC1_DIV :: M2DIV [15:08] */ |
| #define BCHP_VCXO_CTL_MISC_VC1_DIV_M2DIV_MASK 0x0000ff00 |
| #define BCHP_VCXO_CTL_MISC_VC1_DIV_M2DIV_SHIFT 8 |
| |
| /* VCXO_CTL_MISC :: VC1_DIV :: M1DIV [07:00] */ |
| #define BCHP_VCXO_CTL_MISC_VC1_DIV_M1DIV_MASK 0x000000ff |
| #define BCHP_VCXO_CTL_MISC_VC1_DIV_M1DIV_SHIFT 0 |
| |
| /*************************************************************************** |
| *AVD_RAP_DIV - AVD RAP PLL divider settings |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AVD_RAP_DIV :: reserved0 [31:27] */ |
| #define BCHP_VCXO_CTL_MISC_AVD_RAP_DIV_reserved0_MASK 0xf8000000 |
| #define BCHP_VCXO_CTL_MISC_AVD_RAP_DIV_reserved0_SHIFT 27 |
| |
| /* VCXO_CTL_MISC :: AVD_RAP_DIV :: VCORNG [26:25] */ |
| #define BCHP_VCXO_CTL_MISC_AVD_RAP_DIV_VCORNG_MASK 0x06000000 |
| #define BCHP_VCXO_CTL_MISC_AVD_RAP_DIV_VCORNG_SHIFT 25 |
| |
| /* VCXO_CTL_MISC :: AVD_RAP_DIV :: NDIV_INT [24:16] */ |
| #define BCHP_VCXO_CTL_MISC_AVD_RAP_DIV_NDIV_INT_MASK 0x01ff0000 |
| #define BCHP_VCXO_CTL_MISC_AVD_RAP_DIV_NDIV_INT_SHIFT 16 |
| |
| /* VCXO_CTL_MISC :: AVD_RAP_DIV :: M6DIV [15:08] */ |
| #define BCHP_VCXO_CTL_MISC_AVD_RAP_DIV_M6DIV_MASK 0x0000ff00 |
| #define BCHP_VCXO_CTL_MISC_AVD_RAP_DIV_M6DIV_SHIFT 8 |
| |
| /* VCXO_CTL_MISC :: AVD_RAP_DIV :: M1DIV [07:00] */ |
| #define BCHP_VCXO_CTL_MISC_AVD_RAP_DIV_M1DIV_MASK 0x000000ff |
| #define BCHP_VCXO_CTL_MISC_AVD_RAP_DIV_M1DIV_SHIFT 0 |
| |
| /*************************************************************************** |
| *LOCK_CNTR_RESET - VCXO Lock Counter Reset |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: LOCK_CNTR_RESET :: reserved0 [31:07] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_reserved0_MASK 0xffffff80 |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_reserved0_SHIFT 7 |
| |
| /* VCXO_CTL_MISC :: LOCK_CNTR_RESET :: AUDDSP [06:06] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_AUDDSP_MASK 0x00000040 |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_AUDDSP_SHIFT 6 |
| |
| /* VCXO_CTL_MISC :: LOCK_CNTR_RESET :: SC [05:05] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_SC_MASK 0x00000020 |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_SC_SHIFT 5 |
| |
| /* VCXO_CTL_MISC :: LOCK_CNTR_RESET :: AC2 [04:04] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_AC2_MASK 0x00000010 |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_AC2_SHIFT 4 |
| |
| /* VCXO_CTL_MISC :: LOCK_CNTR_RESET :: AC1 [03:03] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_AC1_MASK 0x00000008 |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_AC1_SHIFT 3 |
| |
| /* VCXO_CTL_MISC :: LOCK_CNTR_RESET :: AC0 [02:02] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_AC0_MASK 0x00000004 |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_AC0_SHIFT 2 |
| |
| /* VCXO_CTL_MISC :: LOCK_CNTR_RESET :: VC1 [01:01] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_VC1_MASK 0x00000002 |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_VC1_SHIFT 1 |
| |
| /* VCXO_CTL_MISC :: LOCK_CNTR_RESET :: VC0 [00:00] */ |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_VC0_MASK 0x00000001 |
| #define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_VC0_SHIFT 0 |
| |
| /*************************************************************************** |
| *VC0_LOCK_CNT - VCXO 0 PLL Lock Counter |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: VC0_LOCK_CNT :: reserved0 [31:12] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_LOCK_CNT_reserved0_MASK 0xfffff000 |
| #define BCHP_VCXO_CTL_MISC_VC0_LOCK_CNT_reserved0_SHIFT 12 |
| |
| /* VCXO_CTL_MISC :: VC0_LOCK_CNT :: COUNT [11:00] */ |
| #define BCHP_VCXO_CTL_MISC_VC0_LOCK_CNT_COUNT_MASK 0x00000fff |
| #define BCHP_VCXO_CTL_MISC_VC0_LOCK_CNT_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *VC1_LOCK_CNT - VCXO 1 PLL Lock Counter |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: VC1_LOCK_CNT :: reserved0 [31:12] */ |
| #define BCHP_VCXO_CTL_MISC_VC1_LOCK_CNT_reserved0_MASK 0xfffff000 |
| #define BCHP_VCXO_CTL_MISC_VC1_LOCK_CNT_reserved0_SHIFT 12 |
| |
| /* VCXO_CTL_MISC :: VC1_LOCK_CNT :: COUNT [11:00] */ |
| #define BCHP_VCXO_CTL_MISC_VC1_LOCK_CNT_COUNT_MASK 0x00000fff |
| #define BCHP_VCXO_CTL_MISC_VC1_LOCK_CNT_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC0_LOCK_CNT - Audio PLL 0 Lock Counter |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC0_LOCK_CNT :: reserved0 [31:12] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_LOCK_CNT_reserved0_MASK 0xfffff000 |
| #define BCHP_VCXO_CTL_MISC_AC0_LOCK_CNT_reserved0_SHIFT 12 |
| |
| /* VCXO_CTL_MISC :: AC0_LOCK_CNT :: COUNT [11:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC0_LOCK_CNT_COUNT_MASK 0x00000fff |
| #define BCHP_VCXO_CTL_MISC_AC0_LOCK_CNT_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC1_LOCK_CNT - Audio PLL 1 Lock Counter |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC1_LOCK_CNT :: reserved0 [31:12] */ |
| #define BCHP_VCXO_CTL_MISC_AC1_LOCK_CNT_reserved0_MASK 0xfffff000 |
| #define BCHP_VCXO_CTL_MISC_AC1_LOCK_CNT_reserved0_SHIFT 12 |
| |
| /* VCXO_CTL_MISC :: AC1_LOCK_CNT :: COUNT [11:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC1_LOCK_CNT_COUNT_MASK 0x00000fff |
| #define BCHP_VCXO_CTL_MISC_AC1_LOCK_CNT_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC2_LOCK_CNT - Audio PLL 2 Lock Counter |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AC2_LOCK_CNT :: reserved0 [31:12] */ |
| #define BCHP_VCXO_CTL_MISC_AC2_LOCK_CNT_reserved0_MASK 0xfffff000 |
| #define BCHP_VCXO_CTL_MISC_AC2_LOCK_CNT_reserved0_SHIFT 12 |
| |
| /* VCXO_CTL_MISC :: AC2_LOCK_CNT :: COUNT [11:00] */ |
| #define BCHP_VCXO_CTL_MISC_AC2_LOCK_CNT_COUNT_MASK 0x00000fff |
| #define BCHP_VCXO_CTL_MISC_AC2_LOCK_CNT_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *SC_LOCK_CNT - Smart Card PLL Lock Counter |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: SC_LOCK_CNT :: reserved0 [31:12] */ |
| #define BCHP_VCXO_CTL_MISC_SC_LOCK_CNT_reserved0_MASK 0xfffff000 |
| #define BCHP_VCXO_CTL_MISC_SC_LOCK_CNT_reserved0_SHIFT 12 |
| |
| /* VCXO_CTL_MISC :: SC_LOCK_CNT :: COUNT [11:00] */ |
| #define BCHP_VCXO_CTL_MISC_SC_LOCK_CNT_COUNT_MASK 0x00000fff |
| #define BCHP_VCXO_CTL_MISC_SC_LOCK_CNT_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *AUDDSP_LOCK_CNT - Audio DSP PLL Lock Counter |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: AUDDSP_LOCK_CNT :: reserved0 [31:12] */ |
| #define BCHP_VCXO_CTL_MISC_AUDDSP_LOCK_CNT_reserved0_MASK 0xfffff000 |
| #define BCHP_VCXO_CTL_MISC_AUDDSP_LOCK_CNT_reserved0_SHIFT 12 |
| |
| /* VCXO_CTL_MISC :: AUDDSP_LOCK_CNT :: COUNT [11:00] */ |
| #define BCHP_VCXO_CTL_MISC_AUDDSP_LOCK_CNT_COUNT_MASK 0x00000fff |
| #define BCHP_VCXO_CTL_MISC_AUDDSP_LOCK_CNT_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_SEL - TOP LEVEL PLLs (except MIPS, RAPAVD and NETWORK PLL) test select |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: TEST_SEL :: reserved0 [31:12] */ |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_reserved0_MASK 0xfffff000 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_reserved0_SHIFT 12 |
| |
| /* VCXO_CTL_MISC :: TEST_SEL :: reserved_for_eco1 [11:08] */ |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_reserved_for_eco1_MASK 0x00000f00 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_reserved_for_eco1_SHIFT 8 |
| |
| /* VCXO_CTL_MISC :: TEST_SEL :: PLL_SEL [07:04] */ |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_PLL_SEL_MASK 0x000000f0 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_PLL_SEL_SHIFT 4 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_PLL_SEL_Reserved_6 15 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_PLL_SEL_Reserved_5 14 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_PLL_SEL_Reserved_4 13 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_PLL_SEL_Reserved_3 12 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_PLL_SEL_Reserved_2 11 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_PLL_SEL_Reserved_1 10 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_PLL_SEL_SC_PLL 9 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_PLL_SEL_AC2_PLL 8 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_PLL_SEL_AC1_PLL 7 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_PLL_SEL_AC0_PLL 6 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_PLL_SEL_Reserved_0 5 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_PLL_SEL_VC1_PLL 4 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_PLL_SEL_VC0_PLL 3 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_PLL_SEL_SYSTEM_PLL1 2 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_PLL_SEL_SYSTEM_PLL0 1 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_PLL_SEL_None 0 |
| |
| /* VCXO_CTL_MISC :: TEST_SEL :: SUB_SEL [03:00] */ |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_SUB_SEL_MASK 0x0000000f |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_SUB_SEL_SHIFT 0 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_SUB_SEL_VCO_Vcontrol 0 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_SUB_SEL_VCO_divid_BY_8_clock 1 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_SUB_SEL_frefi 2 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_SUB_SEL_fdbki 3 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_SUB_SEL_watchdog_timer_reset_output 4 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_SUB_SEL_clkout1 5 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_SUB_SEL_clkout2 6 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_SUB_SEL_clkout3 7 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_SUB_SEL_clkout4 8 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_SUB_SEL_clkout5 9 |
| #define BCHP_VCXO_CTL_MISC_TEST_SEL_SUB_SEL_clkout6 10 |
| |
| /*************************************************************************** |
| *MIPS_RAPAVD_PLL_TEST_SEL - MIPS and RAPAVD PLL test select |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: MIPS_RAPAVD_PLL_TEST_SEL :: reserved0 [31:05] */ |
| #define BCHP_VCXO_CTL_MISC_MIPS_RAPAVD_PLL_TEST_SEL_reserved0_MASK 0xffffffe0 |
| #define BCHP_VCXO_CTL_MISC_MIPS_RAPAVD_PLL_TEST_SEL_reserved0_SHIFT 5 |
| |
| /* VCXO_CTL_MISC :: MIPS_RAPAVD_PLL_TEST_SEL :: PLL_SEL [04:03] */ |
| #define BCHP_VCXO_CTL_MISC_MIPS_RAPAVD_PLL_TEST_SEL_PLL_SEL_MASK 0x00000018 |
| #define BCHP_VCXO_CTL_MISC_MIPS_RAPAVD_PLL_TEST_SEL_PLL_SEL_SHIFT 3 |
| #define BCHP_VCXO_CTL_MISC_MIPS_RAPAVD_PLL_TEST_SEL_PLL_SEL_Reserved_0 3 |
| #define BCHP_VCXO_CTL_MISC_MIPS_RAPAVD_PLL_TEST_SEL_PLL_SEL_RAPAVD_PLL 2 |
| #define BCHP_VCXO_CTL_MISC_MIPS_RAPAVD_PLL_TEST_SEL_PLL_SEL_MIPS_PLL 1 |
| #define BCHP_VCXO_CTL_MISC_MIPS_RAPAVD_PLL_TEST_SEL_PLL_SEL_None 0 |
| |
| /* VCXO_CTL_MISC :: MIPS_RAPAVD_PLL_TEST_SEL :: SUB_SEL [02:00] */ |
| #define BCHP_VCXO_CTL_MISC_MIPS_RAPAVD_PLL_TEST_SEL_SUB_SEL_MASK 0x00000007 |
| #define BCHP_VCXO_CTL_MISC_MIPS_RAPAVD_PLL_TEST_SEL_SUB_SEL_SHIFT 0 |
| |
| /*************************************************************************** |
| *NETWORK_PLL_TEST_SEL - NETWORK PLL test select |
| ***************************************************************************/ |
| /* VCXO_CTL_MISC :: NETWORK_PLL_TEST_SEL :: reserved0 [31:04] */ |
| #define BCHP_VCXO_CTL_MISC_NETWORK_PLL_TEST_SEL_reserved0_MASK 0xfffffff0 |
| #define BCHP_VCXO_CTL_MISC_NETWORK_PLL_TEST_SEL_reserved0_SHIFT 4 |
| |
| /* VCXO_CTL_MISC :: NETWORK_PLL_TEST_SEL :: PLL_SEL [03:03] */ |
| #define BCHP_VCXO_CTL_MISC_NETWORK_PLL_TEST_SEL_PLL_SEL_MASK 0x00000008 |
| #define BCHP_VCXO_CTL_MISC_NETWORK_PLL_TEST_SEL_PLL_SEL_SHIFT 3 |
| #define BCHP_VCXO_CTL_MISC_NETWORK_PLL_TEST_SEL_PLL_SEL_NETWORK_PLL 1 |
| #define BCHP_VCXO_CTL_MISC_NETWORK_PLL_TEST_SEL_PLL_SEL_None 0 |
| |
| /* VCXO_CTL_MISC :: NETWORK_PLL_TEST_SEL :: SUB_SEL [02:00] */ |
| #define BCHP_VCXO_CTL_MISC_NETWORK_PLL_TEST_SEL_SUB_SEL_MASK 0x00000007 |
| #define BCHP_VCXO_CTL_MISC_NETWORK_PLL_TEST_SEL_SUB_SEL_SHIFT 0 |
| |
| #endif /* #ifndef BCHP_VCXO_CTL_MISC_H__ */ |
| |
| /* End of File */ |
