| /*************************************************************************** |
| * Copyright (c) 1999-2014, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Wed Sep 3 11:52:56 2014 |
| * Full Compile MD5 Checksum 4a20c0e31b928020bbfa96c583b9e661 |
| * (minus title and desc) |
| * MD5 Checksum 077c6f684bcabb645ae9da4069fea8e4 |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008005 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: $ |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_HIF_CPUBIUCTRL_H__ |
| #define BCHP_HIF_CPUBIUCTRL_H__ |
| |
| /*************************************************************************** |
| *HIF_CPUBIUCTRL - CPU BIU Control registers |
| ***************************************************************************/ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0 0x003e2400 /* CPU Address Range0 Upper Limit Mapping Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0 0x003e2404 /* CPU Address Range0 Lower Limit Mapping Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1 0x003e2408 /* CPU Address Range1 Upper Limit Mapping Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1 0x003e240c /* CPU Address Range1 Lower Limit Mapping Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2 0x003e2410 /* CPU Address Range2 Upper Limit Mapping Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2 0x003e2414 /* CPU Address Range2 Lower Limit Mapping Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3 0x003e2418 /* CPU Address Range3 Upper Limit Mapping Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3 0x003e241c /* CPU Address Range3 Lower Limit Mapping Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4 0x003e2420 /* CPU Address Range4 Upper Limit Mapping Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4 0x003e2424 /* CPU Address Range4 Lower Limit Mapping Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5 0x003e2428 /* CPU Address Range5 Upper Limit Mapping Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5 0x003e242c /* CPU Address Range5 Lower Limit Mapping Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6 0x003e2430 /* CPU Address Range6 Upper Limit Mapping Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6 0x003e2434 /* CPU Address Range6 Lower Limit Mapping Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7 0x003e2438 /* CPU Address Range7 Upper Limit Mapping Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7 0x003e243c /* CPU Address Range7 Lower Limit Mapping Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8 0x003e2440 /* CPU Address Range8 Upper Limit Mapping Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8 0x003e2444 /* CPU Address Range8 Lower Limit Mapping Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9 0x003e2448 /* CPU Address Range9 Upper Limit Mapping Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9 0x003e244c /* CPU Address Range9 Lower Limit Mapping Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10 0x003e2450 /* CPU Address Range10 Upper Limit Mapping Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10 0x003e2454 /* CPU Address Range10 Lower Limit Mapping Register */ |
| #define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG 0x003e2458 /* CPU Secure Soft Reset Handshake Register */ |
| #define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG 0x003e245c /* CPU Secure Soft Reset Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR0 0x003e2460 /* STB CPU Access Rights Violation Address0 Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0 0x003e2464 /* STB CPU Access Rights Violation Upper Address0 Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 0x003e2468 /* STB CPU Access Rights Violation Transaction Detail0 Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR1 0x003e246c /* WEB CPU Access Rights Violation Address1 Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1 0x003e2470 /* WEB CPU Access Rights Violation Upper Address1 Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 0x003e2474 /* WEB CPU Access Rights Violation Transaction Detail1 Register */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG 0x003e2478 /* Read Ahead Cache Configuration0 Register */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG 0x003e247c /* Read Ahead Cache Configuration1 Register */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG 0x003e2480 /* Read Ahead Cache Flush Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG 0x003e2484 /* CPU Power Configuration Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG 0x003e2488 /* CPU0 Power Zone Control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG 0x003e248c /* CPU1 Power Zone Control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG 0x003e2490 /* CPU2 Power Zone Control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG 0x003e2494 /* CPU3 Power Zone Control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG 0x003e2498 /* L2 and BIU Power Zone Control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG 0x003e249c /* CPU0 Power Zone Config1 Registers */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG 0x003e24a0 /* CPU0 Power Zone Config2 Registers */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG 0x003e24a4 /* CPU1 Power Zone Config1 Registers */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG 0x003e24a8 /* CPU1 Power Zone Config2 Registers */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG 0x003e24ac /* CPU2 Power Zone Config1 Registers */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG 0x003e24b0 /* CPU2 Power Zone Config2 Registers */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG 0x003e24b4 /* CPU3 Power Zone Config1 Registers */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG 0x003e24b8 /* CPU3 Power Zone Config2 Registers */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG 0x003e24bc /* L2/BIU Power Zone Config1 Registers */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG 0x003e24c0 /* L2/BIU Power Zone Config2 Registers */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG 0x003e24c4 /* CPU0 BPCM Frequency Scalar Control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG 0x003e24c8 /* CPU1 BPCM Frequency Scalar Control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG 0x003e24cc /* CPU2 BPCM Frequency Scalar Control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG 0x003e24d0 /* CPU3 BPCM Frequency Scalar Control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG 0x003e24d4 /* L2/BIU BPCM Frequency Scalar Control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID 0x003e24d8 /* CPU0 BPCM ID Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CAPABILITY 0x003e24dc /* CPU0 BPCM Capability Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CONTROL 0x003e24e0 /* CPU0 BPCM Control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_STATUS 0x003e24e4 /* CPU0 BPCM Status Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL 0x003e24e8 /* CPU0 Ring Oscillator Control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD 0x003e24ec /* CPU0 Event Counter Threshold Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT 0x003e24f0 /* CPU0 Event Counter Count Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL 0x003e24f4 /* CPU0 PWD control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID 0x003e24f8 /* CPU1 BPCM ID Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CAPABILITY 0x003e24fc /* CPU1 BPCM Capability Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CONTROL 0x003e2500 /* CPU1 BPCM Control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_STATUS 0x003e2504 /* CPU1 BPCM Status Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL 0x003e2508 /* CPU1 Ring Oscillator Control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD 0x003e250c /* CPU1 Event Counter Threshold Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT 0x003e2510 /* CPU1 Event Counter Count Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL 0x003e2514 /* CPU1 PWD control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID 0x003e2518 /* CPU2 BPCM ID Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CAPABILITY 0x003e251c /* CPU2 BPCM Capability Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CONTROL 0x003e2520 /* CPU2 BPCM Control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_STATUS 0x003e2524 /* CPU2 BPCM Status Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL 0x003e2528 /* CPU2 Ring Oscillator Control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD 0x003e252c /* CPU2 Event Counter Threshold Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT 0x003e2530 /* CPU2 Event Counter Count Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL 0x003e2534 /* CPU2 PWD control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID 0x003e2538 /* CPU3 BPCM ID Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CAPABILITY 0x003e253c /* CPU3 BPCM Capability Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CONTROL 0x003e2540 /* CPU3 BPCM Control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_STATUS 0x003e2544 /* CPU3 BPCM Status Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL 0x003e2548 /* CPU3 Ring Oscillator Control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD 0x003e254c /* CPU3 Event Counter Threshold Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT 0x003e2550 /* CPU3 Event Counter Count Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL 0x003e2554 /* CPU3 PWD control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID 0x003e2558 /* L2BIU BPCM ID Register */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CAPABILITY 0x003e255c /* L2BIU BPCM Capability Register */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CONTROL 0x003e2560 /* L2BIU BPCM Control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_STATUS 0x003e2564 /* L2BIU BPCM Status Register */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL 0x003e2568 /* L2BIU Ring Oscillator Control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD 0x003e256c /* L2BIU Event Counter Threshold Register */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT 0x003e2570 /* L2BIU Event Counter Count Register */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL 0x003e2574 /* L2BIU PWD control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG 0x003e2578 /* CPU Reset Configuration Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG 0x003e257c /* CPU Clock Configuration Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG 0x003e2580 /* CPU Miscellaneous Configuration Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG 0x003e2584 /* CPU Request Credit Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG 0x003e2588 /* CPU Thermal Throttling IRQ Config Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG 0x003e258c /* CPU Thermal Throttling IRQ Config Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_HIGH_REG 0x003e2590 /* CPU Thermal Throttling IRQ High Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_LOW_REG 0x003e2594 /* CPU Thermal Throttling IRQ Low Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG 0x003e2598 /* CPU Thermal Throttling Misc Threshold Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_MISC_REG 0x003e259c /* CPU Thermal Throttling Misc IRQ Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG 0x003e25a0 /* CPU Defeature Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_KEY_REG 0x003e25a4 /* CPU Defeature Key Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG 0x003e25a8 /* CPU Debug ROM Address Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG 0x003e25ac /* CPU Debug SELF Address Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG 0x003e25b0 /* CPU Debug Trace Control Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG 0x003e25b4 /* CPU AXI Config Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG 0x003e25b8 /* CPU Revision Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW0 0x003e25bc /* UBUS CFG Window0 Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW1 0x003e25c0 /* UBUS CFG Window1 Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW2 0x003e25c4 /* UBUS CFG Window2 Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW3 0x003e25c8 /* UBUS CFG Window3 Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW4 0x003e25cc /* UBUS CFG Window4 Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW5 0x003e25d0 /* UBUS CFG Window5 Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW6 0x003e25d4 /* UBUS CFG Window6 Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW7 0x003e25d8 /* UBUS CFG Window7 Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG 0x003e25dc /* UBUS Configuration Register */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_SCRATCH_REG 0x003e27fc /* Scratch Register */ |
| |
| /*************************************************************************** |
| *CPU_BUS_RANGE_ULIMT0 - CPU Address Range0 Upper Limit Mapping Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT0 :: ULIMIT [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_ULIMIT_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_ULIMIT_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_ULIMIT_DEFAULT 0x000fffff |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT0 :: BUSNUM [03:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_BUSNUM_MASK 0x0000000f |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_BUSNUM_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_BUSNUM_DEFAULT 0x00000002 |
| |
| /*************************************************************************** |
| *CPU_BUS_RANGE_LLIMT0 - CPU Address Range0 Lower Limit Mapping Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT0 :: LLIMIT [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_LLIMIT_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_LLIMIT_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_LLIMIT_DEFAULT 0x000ffe00 |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT0 :: reserved0 [03:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_reserved0_MASK 0x0000000e |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_reserved0_SHIFT 1 |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT0 :: UBUSCDBIT [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_UBUSCDBIT_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_UBUSCDBIT_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_UBUSCDBIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_BUS_RANGE_ULIMT1 - CPU Address Range1 Upper Limit Mapping Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT1 :: ULIMIT [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_ULIMIT_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_ULIMIT_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_ULIMIT_DEFAULT 0x000f1fff |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT1 :: BUSNUM [03:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_BUSNUM_MASK 0x0000000f |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_BUSNUM_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_BUSNUM_DEFAULT 0x00000002 |
| |
| /*************************************************************************** |
| *CPU_BUS_RANGE_LLIMT1 - CPU Address Range1 Lower Limit Mapping Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT1 :: LLIMIT [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_LLIMIT_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_LLIMIT_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_LLIMIT_DEFAULT 0x000c0000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT1 :: reserved0 [03:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_reserved0_MASK 0x0000000e |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_reserved0_SHIFT 1 |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT1 :: UBUSCDBIT [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_UBUSCDBIT_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_UBUSCDBIT_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_UBUSCDBIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_BUS_RANGE_ULIMT2 - CPU Address Range2 Upper Limit Mapping Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT2 :: ULIMIT [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_ULIMIT_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_ULIMIT_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_ULIMIT_DEFAULT 0x00bfffff |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT2 :: BUSNUM [03:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_BUSNUM_MASK 0x0000000f |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_BUSNUM_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_BUSNUM_DEFAULT 0x00000002 |
| |
| /*************************************************************************** |
| *CPU_BUS_RANGE_LLIMT2 - CPU Address Range2 Lower Limit Mapping Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT2 :: LLIMIT [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_LLIMIT_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_LLIMIT_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_LLIMIT_DEFAULT 0x00600000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT2 :: reserved0 [03:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_reserved0_MASK 0x0000000e |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_reserved0_SHIFT 1 |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT2 :: UBUSCDBIT [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_UBUSCDBIT_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_UBUSCDBIT_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_UBUSCDBIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_BUS_RANGE_ULIMT3 - CPU Address Range3 Upper Limit Mapping Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT3 :: ULIMIT [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_ULIMIT_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_ULIMIT_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_ULIMIT_DEFAULT 0x0003ffff |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT3 :: BUSNUM [03:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_BUSNUM_MASK 0x0000000f |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_BUSNUM_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_BUSNUM_DEFAULT 0x00000004 |
| |
| /*************************************************************************** |
| *CPU_BUS_RANGE_LLIMT3 - CPU Address Range3 Lower Limit Mapping Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT3 :: LLIMIT [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_LLIMIT_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_LLIMIT_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_LLIMIT_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT3 :: reserved0 [03:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_reserved0_MASK 0x0000000e |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_reserved0_SHIFT 1 |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT3 :: UBUSCDBIT [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_UBUSCDBIT_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_UBUSCDBIT_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_UBUSCDBIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_BUS_RANGE_ULIMT4 - CPU Address Range4 Upper Limit Mapping Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT4 :: ULIMIT [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_ULIMIT_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_ULIMIT_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_ULIMIT_DEFAULT 0x001bffff |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT4 :: BUSNUM [03:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_BUSNUM_MASK 0x0000000f |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_BUSNUM_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_BUSNUM_DEFAULT 0x00000004 |
| |
| /*************************************************************************** |
| *CPU_BUS_RANGE_LLIMT4 - CPU Address Range4 Lower Limit Mapping Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT4 :: LLIMIT [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_LLIMIT_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_LLIMIT_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_LLIMIT_DEFAULT 0x00100000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT4 :: reserved0 [03:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_reserved0_MASK 0x0000000e |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_reserved0_SHIFT 1 |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT4 :: UBUSCDBIT [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_UBUSCDBIT_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_UBUSCDBIT_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_UBUSCDBIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_BUS_RANGE_ULIMT5 - CPU Address Range5 Upper Limit Mapping Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT5 :: ULIMIT [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_ULIMIT_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_ULIMIT_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_ULIMIT_DEFAULT 0x0007ffff |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT5 :: BUSNUM [03:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_BUSNUM_MASK 0x0000000f |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_BUSNUM_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_BUSNUM_DEFAULT 0x00000005 |
| |
| /*************************************************************************** |
| *CPU_BUS_RANGE_LLIMT5 - CPU Address Range5 Lower Limit Mapping Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT5 :: LLIMIT [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_LLIMIT_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_LLIMIT_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_LLIMIT_DEFAULT 0x00040000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT5 :: reserved0 [03:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_reserved0_MASK 0x0000000e |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_reserved0_SHIFT 1 |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT5 :: UBUSCDBIT [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_UBUSCDBIT_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_UBUSCDBIT_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_UBUSCDBIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_BUS_RANGE_ULIMT6 - CPU Address Range6 Upper Limit Mapping Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT6 :: ULIMIT [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_ULIMIT_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_ULIMIT_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_ULIMIT_DEFAULT 0x003bffff |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT6 :: BUSNUM [03:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_BUSNUM_MASK 0x0000000f |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_BUSNUM_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_BUSNUM_DEFAULT 0x00000005 |
| |
| /*************************************************************************** |
| *CPU_BUS_RANGE_LLIMT6 - CPU Address Range6 Lower Limit Mapping Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT6 :: LLIMIT [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_LLIMIT_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_LLIMIT_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_LLIMIT_DEFAULT 0x00300000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT6 :: reserved0 [03:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_reserved0_MASK 0x0000000e |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_reserved0_SHIFT 1 |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT6 :: UBUSCDBIT [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_UBUSCDBIT_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_UBUSCDBIT_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_UBUSCDBIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_BUS_RANGE_ULIMT7 - CPU Address Range7 Upper Limit Mapping Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT7 :: ULIMIT [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_ULIMIT_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_ULIMIT_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_ULIMIT_DEFAULT 0x000bffff |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT7 :: BUSNUM [03:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_BUSNUM_MASK 0x0000000f |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_BUSNUM_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_BUSNUM_DEFAULT 0x00000006 |
| |
| /*************************************************************************** |
| *CPU_BUS_RANGE_LLIMT7 - CPU Address Range7 Lower Limit Mapping Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT7 :: LLIMIT [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_LLIMIT_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_LLIMIT_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_LLIMIT_DEFAULT 0x00080000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT7 :: reserved0 [03:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_reserved0_MASK 0x0000000e |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_reserved0_SHIFT 1 |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT7 :: UBUSCDBIT [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_UBUSCDBIT_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_UBUSCDBIT_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_UBUSCDBIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_BUS_RANGE_ULIMT8 - CPU Address Range8 Upper Limit Mapping Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT8 :: ULIMIT [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_ULIMIT_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_ULIMIT_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_ULIMIT_DEFAULT 0x00cbffff |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT8 :: BUSNUM [03:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_BUSNUM_MASK 0x0000000f |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_BUSNUM_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_BUSNUM_DEFAULT 0x00000006 |
| |
| /*************************************************************************** |
| *CPU_BUS_RANGE_LLIMT8 - CPU Address Range8 Lower Limit Mapping Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT8 :: LLIMIT [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_LLIMIT_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_LLIMIT_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_LLIMIT_DEFAULT 0x00c00000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT8 :: reserved0 [03:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_reserved0_MASK 0x0000000e |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_reserved0_SHIFT 1 |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT8 :: UBUSCDBIT [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_UBUSCDBIT_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_UBUSCDBIT_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_UBUSCDBIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_BUS_RANGE_ULIMT9 - CPU Address Range9 Upper Limit Mapping Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT9 :: ULIMIT [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_ULIMIT_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_ULIMIT_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_ULIMIT_DEFAULT 0x00dfffff |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT9 :: BUSNUM [03:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_BUSNUM_MASK 0x0000000f |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_BUSNUM_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_BUSNUM_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_BUS_RANGE_LLIMT9 - CPU Address Range9 Lower Limit Mapping Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT9 :: LLIMIT [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_LLIMIT_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_LLIMIT_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_LLIMIT_DEFAULT 0x00d00000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT9 :: reserved0 [03:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_reserved0_MASK 0x0000000e |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_reserved0_SHIFT 1 |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT9 :: UBUSCDBIT [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_UBUSCDBIT_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_UBUSCDBIT_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_UBUSCDBIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_BUS_RANGE_ULIMT10 - CPU Address Range10 Upper Limit Mapping Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT10 :: ULIMIT [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_ULIMIT_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_ULIMIT_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_ULIMIT_DEFAULT 0x00efffff |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT10 :: BUSNUM [03:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_BUSNUM_MASK 0x0000000f |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_BUSNUM_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_BUSNUM_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_BUS_RANGE_LLIMT10 - CPU Address Range10 Lower Limit Mapping Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT10 :: LLIMIT [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_LLIMIT_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_LLIMIT_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_LLIMIT_DEFAULT 0x00e00000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT10 :: reserved0 [03:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_reserved0_MASK 0x0000000e |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_reserved0_SHIFT 1 |
| |
| /* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT10 :: UBUSCDBIT [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_UBUSCDBIT_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_UBUSCDBIT_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_UBUSCDBIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SECURE_RESET_HNDSHAKE_REG - CPU Secure Soft Reset Handshake Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: SECURE_RESET_HNDSHAKE_REG :: START [31:31] */ |
| #define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_START_MASK 0x80000000 |
| #define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_START_SHIFT 31 |
| #define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_START_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: SECURE_RESET_HNDSHAKE_REG :: SW_DONE [30:30] */ |
| #define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_SW_DONE_MASK 0x40000000 |
| #define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_SW_DONE_SHIFT 30 |
| #define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_SW_DONE_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: SECURE_RESET_HNDSHAKE_REG :: HW_DONE [29:29] */ |
| #define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_HW_DONE_MASK 0x20000000 |
| #define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_HW_DONE_SHIFT 29 |
| |
| /* HIF_CPUBIUCTRL :: SECURE_RESET_HNDSHAKE_REG :: reserved0 [28:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_reserved0_MASK 0x1fffffff |
| #define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *SECURE_SOFT_RESET_REG - CPU Secure Soft Reset Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: SECURE_SOFT_RESET_REG :: WEBCORES_SOFT_RESET [31:31] */ |
| #define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG_WEBCORES_SOFT_RESET_MASK 0x80000000 |
| #define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG_WEBCORES_SOFT_RESET_SHIFT 31 |
| #define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG_WEBCORES_SOFT_RESET_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: SECURE_SOFT_RESET_REG :: reserved0 [30:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG_reserved0_MASK 0x7fffffff |
| #define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU_ACCESS_RIGHT_VIOL_ADDR0 - STB CPU Access Rights Violation Address0 Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_ADDR0 :: VIOL_ADDR [31:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR0_VIOL_ADDR_MASK 0xffffffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR0_VIOL_ADDR_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR0_VIOL_ADDR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0 - STB CPU Access Rights Violation Upper Address0 Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0 :: reserved0 [31:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0_reserved0_MASK 0xffffff00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0_reserved0_SHIFT 8 |
| |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0 :: VIOL_UPPER_ADDR [07:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0_VIOL_UPPER_ADDR_MASK 0x000000ff |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0_VIOL_UPPER_ADDR_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0_VIOL_UPPER_ADDR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 - STB CPU Access Rights Violation Transaction Detail0 Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: ERROR_VLD [31:31] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_ERROR_VLD_MASK 0x80000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_ERROR_VLD_SHIFT 31 |
| |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: reserved0 [30:30] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved0_MASK 0x40000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved0_SHIFT 30 |
| |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: CLUSTER_ID [29:26] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_CLUSTER_ID_MASK 0x3c000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_CLUSTER_ID_SHIFT 26 |
| |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: PROCESSOR_ID [25:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_PROCESSOR_ID_MASK 0x03000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_PROCESSOR_ID_SHIFT 24 |
| |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: reserved1 [23:23] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved1_MASK 0x00800000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved1_SHIFT 23 |
| |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: INSTRUCTION_ACCESS [22:22] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_INSTRUCTION_ACCESS_MASK 0x00400000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_INSTRUCTION_ACCESS_SHIFT 22 |
| |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: reserved2 [21:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved2_MASK 0x003f0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved2_SHIFT 16 |
| |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: REQUEST_SIZE [15:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_REQUEST_SIZE_MASK 0x0000f000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_REQUEST_SIZE_SHIFT 12 |
| |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: UPPER_VIOL_ADDR [11:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_UPPER_VIOL_ADDR_MASK 0x00000ff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_UPPER_VIOL_ADDR_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_UPPER_VIOL_ADDR_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: REQUEST_TYPE [03:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_REQUEST_TYPE_MASK 0x0000000f |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_REQUEST_TYPE_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU_ACCESS_RIGHT_VIOL_ADDR1 - WEB CPU Access Rights Violation Address1 Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_ADDR1 :: VIOL_ADDR [31:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR1_VIOL_ADDR_MASK 0xffffffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR1_VIOL_ADDR_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR1_VIOL_ADDR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1 - WEB CPU Access Rights Violation Upper Address1 Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1 :: reserved0 [31:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1_reserved0_MASK 0xffffff00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1_reserved0_SHIFT 8 |
| |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1 :: VIOL_UPPER_ADDR [07:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1_VIOL_UPPER_ADDR_MASK 0x000000ff |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1_VIOL_UPPER_ADDR_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1_VIOL_UPPER_ADDR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 - WEB CPU Access Rights Violation Transaction Detail1 Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: ERROR_VLD [31:31] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_ERROR_VLD_MASK 0x80000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_ERROR_VLD_SHIFT 31 |
| |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: reserved0 [30:30] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved0_MASK 0x40000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved0_SHIFT 30 |
| |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: CLUSTER_ID [29:26] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_CLUSTER_ID_MASK 0x3c000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_CLUSTER_ID_SHIFT 26 |
| |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: PROCESSOR_ID [25:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_PROCESSOR_ID_MASK 0x03000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_PROCESSOR_ID_SHIFT 24 |
| |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: reserved1 [23:23] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved1_MASK 0x00800000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved1_SHIFT 23 |
| |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: INSTRUCTION_ACCESS [22:22] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_INSTRUCTION_ACCESS_MASK 0x00400000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_INSTRUCTION_ACCESS_SHIFT 22 |
| |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: reserved2 [21:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved2_MASK 0x003f0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved2_SHIFT 16 |
| |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: REQUEST_SIZE [15:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_REQUEST_SIZE_MASK 0x0000f000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_REQUEST_SIZE_SHIFT 12 |
| |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: UPPER_VIOL_ADDR [11:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_UPPER_VIOL_ADDR_MASK 0x00000ff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_UPPER_VIOL_ADDR_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_UPPER_VIOL_ADDR_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: REQUEST_TYPE [03:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_REQUEST_TYPE_MASK 0x0000000f |
| #define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_REQUEST_TYPE_SHIFT 0 |
| |
| /*************************************************************************** |
| *RAC_CONFIG0_REG - Read Ahead Cache Configuration0 Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENDATA3 [31:30] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA3_MASK 0xc0000000 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA3_SHIFT 30 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA3_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFDATA3 [29:28] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA3_MASK 0x30000000 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA3_SHIFT 28 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA3_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENINST3 [27:26] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST3_MASK 0x0c000000 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST3_SHIFT 26 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST3_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFINST3 [25:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST3_MASK 0x03000000 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST3_SHIFT 24 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST3_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENDATA2 [23:22] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA2_MASK 0x00c00000 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA2_SHIFT 22 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA2_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFDATA2 [21:20] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA2_MASK 0x00300000 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA2_SHIFT 20 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA2_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENINST2 [19:18] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST2_MASK 0x000c0000 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST2_SHIFT 18 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST2_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFINST2 [17:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST2_MASK 0x00030000 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST2_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST2_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENDATA1 [15:14] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA1_MASK 0x0000c000 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA1_SHIFT 14 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA1_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFDATA1 [13:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA1_MASK 0x00003000 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA1_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA1_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENINST1 [11:10] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST1_MASK 0x00000c00 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST1_SHIFT 10 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST1_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFINST1 [09:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST1_MASK 0x00000300 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST1_SHIFT 8 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST1_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENDATA0 [07:06] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA0_MASK 0x000000c0 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA0_SHIFT 6 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA0_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFDATA0 [05:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA0_MASK 0x00000030 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA0_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA0_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENINST0 [03:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST0_MASK 0x0000000c |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST0_SHIFT 2 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST0_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFINST0 [01:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST0_MASK 0x00000003 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST0_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RAC_CONFIG1_REG - Read Ahead Cache Configuration1 Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: reserved0 [31:09] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_reserved0_MASK 0xfffffe00 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_reserved0_SHIFT 9 |
| |
| /* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: RAC_TBD_CTRL8 [08:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL8_MASK 0x00000100 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL8_SHIFT 8 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL8_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: RAC_TBD_CTRL7to6 [07:06] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL7to6_MASK 0x000000c0 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL7to6_SHIFT 6 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL7to6_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: RAC_FIFO_CTRL [05:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_FIFO_CTRL_MASK 0x00000030 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_FIFO_CTRL_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_FIFO_CTRL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: RAC_TBD_CTRL3to1 [03:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL3to1_MASK 0x0000000e |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL3to1_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL3to1_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: UBUS_RAC_EN [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_UBUS_RAC_EN_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_UBUS_RAC_EN_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_UBUS_RAC_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RAC_FLUSH_REG - Read Ahead Cache Flush Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: RAC_FLUSH_REG :: reserved0 [31:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG_reserved0_MASK 0xfffffffe |
| #define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG_reserved0_SHIFT 1 |
| |
| /* HIF_CPUBIUCTRL :: RAC_FLUSH_REG :: FLUSH_RAC [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG_FLUSH_RAC_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG_FLUSH_RAC_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG_FLUSH_RAC_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_POWER_CONFIG_REG - CPU Power Configuration Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: reserved0 [31:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_reserved0_MASK 0xffffff00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_reserved0_SHIFT 8 |
| |
| /* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU3_BPCM_INIT_ON [07:07] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_INIT_ON_MASK 0x00000080 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_INIT_ON_SHIFT 7 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_INIT_ON_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU2_BPCM_INIT_ON [06:06] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_INIT_ON_MASK 0x00000040 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_INIT_ON_SHIFT 6 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_INIT_ON_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU1_BPCM_INIT_ON [05:05] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_INIT_ON_MASK 0x00000020 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_INIT_ON_SHIFT 5 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_INIT_ON_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU0_BPCM_INIT_ON [04:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_INIT_ON_MASK 0x00000010 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_INIT_ON_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_INIT_ON_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU3_BPCM_DIS [03:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_DIS_MASK 0x00000008 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_DIS_SHIFT 3 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_DIS_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU2_BPCM_DIS [02:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_DIS_MASK 0x00000004 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_DIS_SHIFT 2 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_DIS_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU1_BPCM_DIS [01:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_DIS_MASK 0x00000002 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_DIS_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_DIS_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU0_BPCM_DIS [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_DIS_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_DIS_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_DIS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU0_PWR_ZONE_CNTRL_REG - CPU0 Power Zone Control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_RESET_STATE [31:31] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_MASK 0x80000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_SHIFT 31 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_ISO_STATE [30:30] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_MASK 0x40000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_SHIFT 30 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_STATE [29:29] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_MASK 0x20000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_SHIFT 29 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_DPG_PWR_STATE [28:28] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_MASK 0x10000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_SHIFT 28 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_POWER_GOOD [27:27] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_MASK 0x08000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_SHIFT 27 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_PWR_ON_STATE [26:26] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_MASK 0x04000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_SHIFT 26 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_PWR_OFF_STATE [25:25] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_MASK 0x02000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_SHIFT 25 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: FREQ_SCALAR_DYNAMIC_SEL [24:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_MASK 0x01000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_SHIFT 24 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_PWR_CNTL_STATE [23:19] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_MASK 0x00f80000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_SHIFT 19 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: reserved0 [18:14] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_reserved0_MASK 0x0007c000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_reserved0_SHIFT 14 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MEM_STBY [13:13] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_MASK 0x00002000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_SHIFT 13 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_BLK_RST_ASSERT [12:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_MASK 0x00001000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_CNTL_EN [11:11] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_MASK 0x00000800 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_SHIFT 11 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_PWR_UP_REQ [10:10] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_MASK 0x00000400 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_SHIFT 10 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_PWR_DN_REQ [09:09] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_MASK 0x00000200 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_SHIFT 9 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CNTL_EN [08:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_MASK 0x00000100 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_SHIFT 8 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MANUAL_CONTROL [07:07] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_MASK 0x00000080 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_SHIFT 7 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MAN_ISO_CNTL [06:06] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_MASK 0x00000040 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_SHIFT 6 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: reserved1 [05:05] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_reserved1_MASK 0x00000020 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_reserved1_SHIFT 5 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MAN_MEM_PWR [04:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_MASK 0x00000010 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CAPABLE [03:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_MASK 0x00000008 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_SHIFT 3 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_FREQ_SCALE_USED [02:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_MASK 0x00000004 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_SHIFT 2 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MAN_RESET_CNTL [01:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_MASK 0x00000002 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MAN_CLKEN [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU1_PWR_ZONE_CNTRL_REG - CPU1 Power Zone Control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_RESET_STATE [31:31] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_MASK 0x80000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_SHIFT 31 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_ISO_STATE [30:30] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_MASK 0x40000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_SHIFT 30 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_STATE [29:29] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_MASK 0x20000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_SHIFT 29 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_DPG_PWR_STATE [28:28] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_MASK 0x10000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_SHIFT 28 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_POWER_GOOD [27:27] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_MASK 0x08000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_SHIFT 27 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_PWR_ON_STATE [26:26] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_MASK 0x04000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_SHIFT 26 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_PWR_OFF_STATE [25:25] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_MASK 0x02000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_SHIFT 25 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: FREQ_SCALAR_DYNAMIC_SEL [24:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_MASK 0x01000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_SHIFT 24 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_PWR_CNTL_STATE [23:19] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_MASK 0x00f80000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_SHIFT 19 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: reserved0 [18:14] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_reserved0_MASK 0x0007c000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_reserved0_SHIFT 14 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MEM_STBY [13:13] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_MASK 0x00002000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_SHIFT 13 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_BLK_RST_ASSERT [12:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_MASK 0x00001000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_CNTL_EN [11:11] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_MASK 0x00000800 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_SHIFT 11 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_PWR_UP_REQ [10:10] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_MASK 0x00000400 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_SHIFT 10 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_PWR_DN_REQ [09:09] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_MASK 0x00000200 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_SHIFT 9 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CNTL_EN [08:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_MASK 0x00000100 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_SHIFT 8 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MANUAL_CONTROL [07:07] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_MASK 0x00000080 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_SHIFT 7 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MAN_ISO_CNTL [06:06] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_MASK 0x00000040 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_SHIFT 6 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: reserved1 [05:05] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_reserved1_MASK 0x00000020 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_reserved1_SHIFT 5 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MAN_MEM_PWR [04:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_MASK 0x00000010 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CAPABLE [03:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_MASK 0x00000008 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_SHIFT 3 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_FREQ_SCALE_USED [02:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_MASK 0x00000004 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_SHIFT 2 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MAN_RESET_CNTL [01:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_MASK 0x00000002 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MAN_CLKEN [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU2_PWR_ZONE_CNTRL_REG - CPU2 Power Zone Control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_RESET_STATE [31:31] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_MASK 0x80000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_SHIFT 31 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_ISO_STATE [30:30] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_MASK 0x40000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_SHIFT 30 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_STATE [29:29] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_MASK 0x20000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_SHIFT 29 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_DPG_PWR_STATE [28:28] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_MASK 0x10000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_SHIFT 28 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_POWER_GOOD [27:27] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_MASK 0x08000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_SHIFT 27 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_PWR_ON_STATE [26:26] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_MASK 0x04000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_SHIFT 26 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_PWR_OFF_STATE [25:25] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_MASK 0x02000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_SHIFT 25 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: FREQ_SCALAR_DYNAMIC_SEL [24:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_MASK 0x01000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_SHIFT 24 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_PWR_CNTL_STATE [23:19] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_MASK 0x00f80000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_SHIFT 19 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: reserved0 [18:14] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_reserved0_MASK 0x0007c000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_reserved0_SHIFT 14 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MEM_STBY [13:13] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_MASK 0x00002000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_SHIFT 13 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_BLK_RST_ASSERT [12:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_MASK 0x00001000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_CNTL_EN [11:11] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_MASK 0x00000800 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_SHIFT 11 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_PWR_UP_REQ [10:10] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_MASK 0x00000400 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_SHIFT 10 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_PWR_DN_REQ [09:09] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_MASK 0x00000200 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_SHIFT 9 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CNTL_EN [08:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_MASK 0x00000100 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_SHIFT 8 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MANUAL_CONTROL [07:07] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_MASK 0x00000080 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_SHIFT 7 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MAN_ISO_CNTL [06:06] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_MASK 0x00000040 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_SHIFT 6 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: reserved1 [05:05] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_reserved1_MASK 0x00000020 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_reserved1_SHIFT 5 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MAN_MEM_PWR [04:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_MASK 0x00000010 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CAPABLE [03:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_MASK 0x00000008 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_SHIFT 3 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_FREQ_SCALE_USED [02:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_MASK 0x00000004 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_SHIFT 2 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MAN_RESET_CNTL [01:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_MASK 0x00000002 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MAN_CLKEN [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU3_PWR_ZONE_CNTRL_REG - CPU3 Power Zone Control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_RESET_STATE [31:31] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_MASK 0x80000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_SHIFT 31 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_ISO_STATE [30:30] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_MASK 0x40000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_SHIFT 30 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_STATE [29:29] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_MASK 0x20000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_SHIFT 29 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_DPG_PWR_STATE [28:28] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_MASK 0x10000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_SHIFT 28 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_POWER_GOOD [27:27] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_MASK 0x08000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_SHIFT 27 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_PWR_ON_STATE [26:26] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_MASK 0x04000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_SHIFT 26 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_PWR_OFF_STATE [25:25] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_MASK 0x02000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_SHIFT 25 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: FREQ_SCALAR_DYNAMIC_SEL [24:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_MASK 0x01000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_SHIFT 24 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_PWR_CNTL_STATE [23:19] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_MASK 0x00f80000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_SHIFT 19 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: reserved0 [18:14] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_reserved0_MASK 0x0007c000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_reserved0_SHIFT 14 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MEM_STBY [13:13] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_MASK 0x00002000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_SHIFT 13 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_BLK_RST_ASSERT [12:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_MASK 0x00001000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_CNTL_EN [11:11] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_MASK 0x00000800 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_SHIFT 11 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_PWR_UP_REQ [10:10] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_MASK 0x00000400 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_SHIFT 10 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_PWR_DN_REQ [09:09] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_MASK 0x00000200 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_SHIFT 9 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CNTL_EN [08:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_MASK 0x00000100 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_SHIFT 8 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MANUAL_CONTROL [07:07] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_MASK 0x00000080 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_SHIFT 7 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MAN_ISO_CNTL [06:06] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_MASK 0x00000040 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_SHIFT 6 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: reserved1 [05:05] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_reserved1_MASK 0x00000020 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_reserved1_SHIFT 5 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MAN_MEM_PWR [04:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_MASK 0x00000010 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CAPABLE [03:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_MASK 0x00000008 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_SHIFT 3 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_FREQ_SCALE_USED [02:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_MASK 0x00000004 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_SHIFT 2 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MAN_RESET_CNTL [01:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_MASK 0x00000002 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MAN_CLKEN [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *L2BIU_PWR_ZONE_CNTRL_REG - L2 and BIU Power Zone Control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_RESET_STATE [31:31] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_MASK 0x80000000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_SHIFT 31 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_ISO_STATE [30:30] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_MASK 0x40000000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_SHIFT 30 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_STATE [29:29] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_MASK 0x20000000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_SHIFT 29 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_DPG_PWR_STATE [28:28] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_MASK 0x10000000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_SHIFT 28 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_POWER_GOOD [27:27] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_MASK 0x08000000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_SHIFT 27 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_PWR_ON_STATE [26:26] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_MASK 0x04000000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_SHIFT 26 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_PWR_OFF_STATE [25:25] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_MASK 0x02000000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_SHIFT 25 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: FREQ_SCALAR_DYNAMIC_SEL [24:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_MASK 0x01000000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_SHIFT 24 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_PWR_CNTL_STATE [23:19] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_MASK 0x00f80000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_SHIFT 19 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: reserved0 [18:14] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_reserved0_MASK 0x0007c000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_reserved0_SHIFT 14 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MEM_STBY [13:13] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_MASK 0x00002000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_SHIFT 13 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_BLK_RST_ASSERT [12:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_MASK 0x00001000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_CNTL_EN [11:11] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_MASK 0x00000800 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_SHIFT 11 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_PWR_UP_REQ [10:10] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_MASK 0x00000400 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_SHIFT 10 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_PWR_DN_REQ [09:09] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_MASK 0x00000200 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_SHIFT 9 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CNTL_EN [08:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_MASK 0x00000100 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_SHIFT 8 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MANUAL_CONTROL [07:07] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_MASK 0x00000080 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_SHIFT 7 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MAN_ISO_CNTL [06:06] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_MASK 0x00000040 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_SHIFT 6 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: reserved1 [05:05] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_reserved1_MASK 0x00000020 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_reserved1_SHIFT 5 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MAN_MEM_PWR [04:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_MASK 0x00000010 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CAPABLE [03:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_MASK 0x00000008 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_SHIFT 3 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_FREQ_SCALE_USED [02:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_MASK 0x00000004 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_SHIFT 2 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MAN_RESET_CNTL [01:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_MASK 0x00000002 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MAN_CLKEN [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU0_PWR_ZONE_CONFIG1_REG - CPU0 Power Zone Config1 Registers |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: RST_OFF_DLY [31:28] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_MASK 0xf0000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_SHIFT 28 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: RST_ON_DLY [27:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_MASK 0x0f000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_SHIFT 24 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: CLK_OFF_DLY [23:20] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_MASK 0x00f00000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_SHIFT 20 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: CLK_ON_DLY [19:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_MASK 0x000f0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: ISO_OFF_DLY [15:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_MASK 0x0000f000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: ISO_ON_DLY [11:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_MASK 0x00000f00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_SHIFT 8 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: reserved0 [07:05] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_reserved0_MASK 0x000000e0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_reserved0_SHIFT 5 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: PWROK_TRESH [04:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_MASK 0x00000018 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_SHIFT 3 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: PWROK_DELAY_SEL [02:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_MASK 0x00000007 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU0_PWR_ZONE_CONFIG2_REG - CPU0 Power Zone Config2 Registers |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: MEM_OFF_DLY [31:28] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_MASK 0xf0000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_SHIFT 28 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: MEM_ON_DLY [27:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_MASK 0x0f000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_SHIFT 24 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: DPG_OFF_DLY [23:20] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_MASK 0x00f00000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_SHIFT 20 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: DPG1_ON_DLY [19:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_MASK 0x000f0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_DEFAULT 0x00000003 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: DPGN_ON_DLY [15:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_MASK 0x0000f000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: reserved0 [11:06] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_reserved0_MASK 0x00000fc0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_reserved0_SHIFT 6 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: SLEW_PRESCALE_SEL [05:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_MASK 0x00000038 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_SHIFT 3 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_DEFAULT 0x00000002 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: DELAY_PRESCALE_SEL [02:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_MASK 0x00000007 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_DEFAULT 0x00000002 |
| |
| /*************************************************************************** |
| *CPU1_PWR_ZONE_CONFIG1_REG - CPU1 Power Zone Config1 Registers |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: RST_OFF_DLY [31:28] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_MASK 0xf0000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_SHIFT 28 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: RST_ON_DLY [27:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_MASK 0x0f000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_SHIFT 24 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: CLK_OFF_DLY [23:20] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_MASK 0x00f00000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_SHIFT 20 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: CLK_ON_DLY [19:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_MASK 0x000f0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: ISO_OFF_DLY [15:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_MASK 0x0000f000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: ISO_ON_DLY [11:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_MASK 0x00000f00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_SHIFT 8 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: reserved0 [07:05] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_reserved0_MASK 0x000000e0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_reserved0_SHIFT 5 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: PWROK_TRESH [04:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_MASK 0x00000018 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_SHIFT 3 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: PWROK_DELAY_SEL [02:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_MASK 0x00000007 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU1_PWR_ZONE_CONFIG2_REG - CPU1 Power Zone Config2 Registers |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: MEM_OFF_DLY [31:28] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_MASK 0xf0000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_SHIFT 28 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: MEM_ON_DLY [27:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_MASK 0x0f000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_SHIFT 24 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: DPG_OFF_DLY [23:20] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_MASK 0x00f00000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_SHIFT 20 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: DPG1_ON_DLY [19:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_MASK 0x000f0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_DEFAULT 0x00000003 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: DPGN_ON_DLY [15:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_MASK 0x0000f000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: reserved0 [11:06] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_reserved0_MASK 0x00000fc0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_reserved0_SHIFT 6 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: SLEW_PRESCALE_SEL [05:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_MASK 0x00000038 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_SHIFT 3 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_DEFAULT 0x00000002 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: DELAY_PRESCALE_SEL [02:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_MASK 0x00000007 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_DEFAULT 0x00000002 |
| |
| /*************************************************************************** |
| *CPU2_PWR_ZONE_CONFIG1_REG - CPU2 Power Zone Config1 Registers |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: RST_OFF_DLY [31:28] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_MASK 0xf0000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_SHIFT 28 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: RST_ON_DLY [27:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_MASK 0x0f000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_SHIFT 24 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: CLK_OFF_DLY [23:20] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_MASK 0x00f00000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_SHIFT 20 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: CLK_ON_DLY [19:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_MASK 0x000f0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: ISO_OFF_DLY [15:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_MASK 0x0000f000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: ISO_ON_DLY [11:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_MASK 0x00000f00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_SHIFT 8 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: reserved0 [07:05] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_reserved0_MASK 0x000000e0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_reserved0_SHIFT 5 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: PWROK_TRESH [04:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_MASK 0x00000018 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_SHIFT 3 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: PWROK_DELAY_SEL [02:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_MASK 0x00000007 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU2_PWR_ZONE_CONFIG2_REG - CPU2 Power Zone Config2 Registers |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: MEM_OFF_DLY [31:28] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_MASK 0xf0000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_SHIFT 28 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: MEM_ON_DLY [27:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_MASK 0x0f000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_SHIFT 24 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: DPG_OFF_DLY [23:20] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_MASK 0x00f00000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_SHIFT 20 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: DPG1_ON_DLY [19:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_MASK 0x000f0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_DEFAULT 0x00000003 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: DPGN_ON_DLY [15:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_MASK 0x0000f000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: reserved0 [11:06] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_reserved0_MASK 0x00000fc0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_reserved0_SHIFT 6 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: SLEW_PRESCALE_SEL [05:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_MASK 0x00000038 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_SHIFT 3 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_DEFAULT 0x00000002 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: DELAY_PRESCALE_SEL [02:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_MASK 0x00000007 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_DEFAULT 0x00000002 |
| |
| /*************************************************************************** |
| *CPU3_PWR_ZONE_CONFIG1_REG - CPU3 Power Zone Config1 Registers |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: RST_OFF_DLY [31:28] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_MASK 0xf0000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_SHIFT 28 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: RST_ON_DLY [27:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_MASK 0x0f000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_SHIFT 24 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: CLK_OFF_DLY [23:20] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_MASK 0x00f00000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_SHIFT 20 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: CLK_ON_DLY [19:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_MASK 0x000f0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: ISO_OFF_DLY [15:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_MASK 0x0000f000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: ISO_ON_DLY [11:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_MASK 0x00000f00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_SHIFT 8 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: reserved0 [07:05] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_reserved0_MASK 0x000000e0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_reserved0_SHIFT 5 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: PWROK_TRESH [04:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_MASK 0x00000018 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_SHIFT 3 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: PWROK_DELAY_SEL [02:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_MASK 0x00000007 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU3_PWR_ZONE_CONFIG2_REG - CPU3 Power Zone Config2 Registers |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: MEM_OFF_DLY [31:28] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_MASK 0xf0000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_SHIFT 28 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: MEM_ON_DLY [27:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_MASK 0x0f000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_SHIFT 24 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: DPG_OFF_DLY [23:20] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_MASK 0x00f00000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_SHIFT 20 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: DPG1_ON_DLY [19:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_MASK 0x000f0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_DEFAULT 0x00000003 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: DPGN_ON_DLY [15:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_MASK 0x0000f000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: reserved0 [11:06] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_reserved0_MASK 0x00000fc0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_reserved0_SHIFT 6 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: SLEW_PRESCALE_SEL [05:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_MASK 0x00000038 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_SHIFT 3 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_DEFAULT 0x00000002 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: DELAY_PRESCALE_SEL [02:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_MASK 0x00000007 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_DEFAULT 0x00000002 |
| |
| /*************************************************************************** |
| *L2BIU_PWR_ZONE_CONFIG1_REG - L2/BIU Power Zone Config1 Registers |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: RST_OFF_DLY [31:28] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_MASK 0xf0000000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_SHIFT 28 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: RST_ON_DLY [27:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_MASK 0x0f000000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_SHIFT 24 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: CLK_OFF_DLY [23:20] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_MASK 0x00f00000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_SHIFT 20 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: CLK_ON_DLY [19:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_MASK 0x000f0000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: ISO_OFF_DLY [15:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_MASK 0x0000f000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: ISO_ON_DLY [11:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_MASK 0x00000f00 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_SHIFT 8 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: reserved0 [07:05] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_reserved0_MASK 0x000000e0 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_reserved0_SHIFT 5 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: PWROK_TRESH [04:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_MASK 0x00000018 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_SHIFT 3 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: PWROK_DELAY_SEL [02:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_MASK 0x00000007 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *L2BIU_PWR_ZONE_CONFIG2_REG - L2/BIU Power Zone Config2 Registers |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: MEM_OFF_DLY [31:28] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_MASK 0xf0000000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_SHIFT 28 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: MEM_ON_DLY [27:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_MASK 0x0f000000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_SHIFT 24 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: DPG_OFF_DLY [23:20] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_MASK 0x00f00000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_SHIFT 20 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: DPG1_ON_DLY [19:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_MASK 0x000f0000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_DEFAULT 0x00000003 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: DPGN_ON_DLY [15:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_MASK 0x0000f000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: reserved0 [11:06] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_reserved0_MASK 0x00000fc0 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_reserved0_SHIFT 6 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: SLEW_PRESCALE_SEL [05:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_MASK 0x00000038 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_SHIFT 3 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_DEFAULT 0x00000002 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: DELAY_PRESCALE_SEL [02:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_MASK 0x00000007 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_DEFAULT 0x00000002 |
| |
| /*************************************************************************** |
| *CPU0_PWR_FREQ_SCALAR_CTRL_REG - CPU0 BPCM Frequency Scalar Control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: reserved0 [31:10] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_reserved0_MASK 0xfffffc00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_reserved0_SHIFT 10 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: HIGH_GEAR_DIV [09:07] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_MASK 0x00000380 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_SHIFT 7 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: LOW_GEAR_DIV [06:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_MASK 0x00000070 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: reserved1 [03:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_reserved1_MASK 0x00000008 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_reserved1_SHIFT 3 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: USE_DYN_GEAR_SEL [02:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_MASK 0x00000004 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_SHIFT 2 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: GEAR_SELECT [01:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_MASK 0x00000002 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: FS_BYPASS_EN [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU1_PWR_FREQ_SCALAR_CTRL_REG - CPU1 BPCM Frequency Scalar Control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: reserved0 [31:10] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_reserved0_MASK 0xfffffc00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_reserved0_SHIFT 10 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: HIGH_GEAR_DIV [09:07] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_MASK 0x00000380 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_SHIFT 7 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: LOW_GEAR_DIV [06:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_MASK 0x00000070 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: reserved1 [03:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_reserved1_MASK 0x00000008 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_reserved1_SHIFT 3 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: USE_DYN_GEAR_SEL [02:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_MASK 0x00000004 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_SHIFT 2 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: GEAR_SELECT [01:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_MASK 0x00000002 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: FS_BYPASS_EN [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU2_PWR_FREQ_SCALAR_CTRL_REG - CPU2 BPCM Frequency Scalar Control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: reserved0 [31:10] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_reserved0_MASK 0xfffffc00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_reserved0_SHIFT 10 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: HIGH_GEAR_DIV [09:07] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_MASK 0x00000380 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_SHIFT 7 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: LOW_GEAR_DIV [06:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_MASK 0x00000070 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: reserved1 [03:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_reserved1_MASK 0x00000008 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_reserved1_SHIFT 3 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: USE_DYN_GEAR_SEL [02:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_MASK 0x00000004 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_SHIFT 2 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: GEAR_SELECT [01:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_MASK 0x00000002 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: FS_BYPASS_EN [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU3_PWR_FREQ_SCALAR_CTRL_REG - CPU3 BPCM Frequency Scalar Control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: reserved0 [31:10] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_reserved0_MASK 0xfffffc00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_reserved0_SHIFT 10 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: HIGH_GEAR_DIV [09:07] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_MASK 0x00000380 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_SHIFT 7 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: LOW_GEAR_DIV [06:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_MASK 0x00000070 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: reserved1 [03:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_reserved1_MASK 0x00000008 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_reserved1_SHIFT 3 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: USE_DYN_GEAR_SEL [02:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_MASK 0x00000004 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_SHIFT 2 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: GEAR_SELECT [01:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_MASK 0x00000002 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: FS_BYPASS_EN [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *L2BIU_PWR_FREQ_SCALAR_CTRL_REG - L2/BIU BPCM Frequency Scalar Control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: reserved0 [31:10] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_reserved0_MASK 0xfffffc00 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_reserved0_SHIFT 10 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: HIGH_GEAR_DIV [09:07] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_MASK 0x00000380 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_SHIFT 7 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: LOW_GEAR_DIV [06:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_MASK 0x00000070 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: reserved1 [03:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_reserved1_MASK 0x00000008 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_reserved1_SHIFT 3 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: USE_DYN_GEAR_SEL [02:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_MASK 0x00000004 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_SHIFT 2 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: GEAR_SELECT [01:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_MASK 0x00000002 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: FS_BYPASS_EN [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU0_BPCM_ID - CPU0 BPCM ID Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU0_BPCM_ID :: SW_strap [31:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_SW_strap_MASK 0xffff0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_SW_strap_SHIFT 16 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_BPCM_ID :: HW_revision [15:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_HW_revision_MASK 0x0000ff00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_HW_revision_SHIFT 8 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_BPCM_ID :: PMB_ADDR [07:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_PMB_ADDR_MASK 0x000000ff |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_PMB_ADDR_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU0_BPCM_CAPABILITY - CPU0 BPCM Capability Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU0_BPCM_CAPABILITY :: reserved0 [31:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CAPABILITY_reserved0_MASK 0xffffff00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CAPABILITY_reserved0_SHIFT 8 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_BPCM_CAPABILITY :: Number_of_zones [07:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CAPABILITY_Number_of_zones_MASK 0x000000ff |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CAPABILITY_Number_of_zones_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU0_BPCM_CONTROL - CPU0 BPCM Control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU0_BPCM_CONTROL :: TbdField [31:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CONTROL_TbdField_MASK 0xffffffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CONTROL_TbdField_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU0_BPCM_STATUS - CPU0 BPCM Status Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU0_BPCM_STATUS :: reserved0 [31:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_STATUS_reserved0_SHIFT 1 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_BPCM_STATUS :: PWD_Alert [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_STATUS_PWD_Alert_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_STATUS_PWD_Alert_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU0_AVS_ROSC_CONTROL - CPU0 Ring Oscillator Control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: Test_interval [31:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_Test_interval_MASK 0xffff0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_Test_interval_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_Test_interval_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: ALERT_H [15:15] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_H_MASK 0x00008000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_H_SHIFT 15 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: VALID_H [14:14] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_H_MASK 0x00004000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_H_SHIFT 14 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: ALERT_S [13:13] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_S_MASK 0x00002000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_S_SHIFT 13 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: VALID_S [12:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_S_MASK 0x00001000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_S_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: reserved0 [11:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_reserved0_MASK 0x00000f00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_reserved0_SHIFT 8 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: CONTINUOUS_H [07:07] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_H_MASK 0x00000080 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_H_SHIFT 7 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: CONTINUOUS_S [06:06] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_S_MASK 0x00000040 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_S_SHIFT 6 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: THRSH_EN_H [05:05] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_H_MASK 0x00000020 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_H_SHIFT 5 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: THRSH_EN_S [04:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_S_MASK 0x00000010 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_S_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: ECTR_EN_H [03:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_H_MASK 0x00000008 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_H_SHIFT 3 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: ECTR_EN_S [02:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_S_MASK 0x00000004 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_S_SHIFT 2 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: RO_EN_H [01:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_H_MASK 0x00000002 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_H_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: RO_EN_S [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_S_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_S_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_S_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU0_AVS_ROSC_THRESHOLD - CPU0 Event Counter Threshold Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_THRESHOLD :: THRESH_HI [31:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_HI_MASK 0xffff0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_HI_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_HI_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_THRESHOLD :: THRESH_LO [15:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_LO_MASK 0x0000ffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_LO_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_LO_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU0_AVS_ROSC_COUNT - CPU0 Event Counter Count Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_COUNT :: COUNT_H [31:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_H_MASK 0xffff0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_H_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_COUNT :: COUNT_S [15:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_S_MASK 0x0000ffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_S_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_S_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU0_AVS_PWD_CONTROL - CPU0 PWD control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: reserved0 [31:30] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_reserved0_MASK 0xc0000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_reserved0_SHIFT 30 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: CLRCFG [29:27] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CLRCFG_MASK 0x38000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CLRCFG_SHIFT 27 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CLRCFG_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: RSEL [26:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_RSEL_MASK 0x07000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_RSEL_SHIFT 24 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_RSEL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: CGFG [23:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CGFG_MASK 0x00ff0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CGFG_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CGFG_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: ALERT [15:15] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_ALERT_MASK 0x00008000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_ALERT_SHIFT 15 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_ALERT_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: reserved1 [14:09] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_reserved1_MASK 0x00007e00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_reserved1_SHIFT 9 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: PWD_TM_EN [08:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_TM_EN_MASK 0x00000100 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_TM_EN_SHIFT 8 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_TM_EN_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: START [07:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_START_MASK 0x000000fc |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_START_SHIFT 2 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_START_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: PWD_ALERT_SEL [01:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_ALERT_SEL_MASK 0x00000002 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_ALERT_SEL_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_ALERT_SEL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: PWD_EN [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_EN_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_EN_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU1_BPCM_ID - CPU1 BPCM ID Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU1_BPCM_ID :: SW_strap [31:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_SW_strap_MASK 0xffff0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_SW_strap_SHIFT 16 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_BPCM_ID :: HW_revision [15:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_HW_revision_MASK 0x0000ff00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_HW_revision_SHIFT 8 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_BPCM_ID :: PMB_ADDR [07:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_PMB_ADDR_MASK 0x000000ff |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_PMB_ADDR_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU1_BPCM_CAPABILITY - CPU1 BPCM Capability Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU1_BPCM_CAPABILITY :: reserved0 [31:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CAPABILITY_reserved0_MASK 0xffffff00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CAPABILITY_reserved0_SHIFT 8 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_BPCM_CAPABILITY :: Number_of_zones [07:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CAPABILITY_Number_of_zones_MASK 0x000000ff |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CAPABILITY_Number_of_zones_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU1_BPCM_CONTROL - CPU1 BPCM Control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU1_BPCM_CONTROL :: TbdField [31:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CONTROL_TbdField_MASK 0xffffffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CONTROL_TbdField_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU1_BPCM_STATUS - CPU1 BPCM Status Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU1_BPCM_STATUS :: reserved0 [31:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_STATUS_reserved0_SHIFT 1 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_BPCM_STATUS :: PWD_Alert [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_STATUS_PWD_Alert_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_STATUS_PWD_Alert_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU1_AVS_ROSC_CONTROL - CPU1 Ring Oscillator Control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: Test_interval [31:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_Test_interval_MASK 0xffff0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_Test_interval_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_Test_interval_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: ALERT_H [15:15] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_H_MASK 0x00008000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_H_SHIFT 15 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: VALID_H [14:14] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_H_MASK 0x00004000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_H_SHIFT 14 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: ALERT_S [13:13] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_S_MASK 0x00002000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_S_SHIFT 13 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: VALID_S [12:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_S_MASK 0x00001000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_S_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: reserved0 [11:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_reserved0_MASK 0x00000f00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_reserved0_SHIFT 8 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: CONTINUOUS_H [07:07] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_H_MASK 0x00000080 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_H_SHIFT 7 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: CONTINUOUS_S [06:06] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_S_MASK 0x00000040 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_S_SHIFT 6 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: THRSH_EN_H [05:05] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_H_MASK 0x00000020 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_H_SHIFT 5 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: THRSH_EN_S [04:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_S_MASK 0x00000010 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_S_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: ECTR_EN_H [03:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_H_MASK 0x00000008 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_H_SHIFT 3 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: ECTR_EN_S [02:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_S_MASK 0x00000004 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_S_SHIFT 2 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: RO_EN_H [01:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_H_MASK 0x00000002 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_H_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: RO_EN_S [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_S_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_S_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_S_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU1_AVS_ROSC_THRESHOLD - CPU1 Event Counter Threshold Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_THRESHOLD :: THRESH_HI [31:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_HI_MASK 0xffff0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_HI_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_HI_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_THRESHOLD :: THRESH_LO [15:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_LO_MASK 0x0000ffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_LO_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_LO_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU1_AVS_ROSC_COUNT - CPU1 Event Counter Count Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_COUNT :: COUNT_H [31:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_H_MASK 0xffff0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_H_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_COUNT :: COUNT_S [15:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_S_MASK 0x0000ffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_S_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_S_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU1_AVS_PWD_CONTROL - CPU1 PWD control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: reserved0 [31:30] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_reserved0_MASK 0xc0000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_reserved0_SHIFT 30 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: CLRCFG [29:27] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CLRCFG_MASK 0x38000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CLRCFG_SHIFT 27 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CLRCFG_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: RSEL [26:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_RSEL_MASK 0x07000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_RSEL_SHIFT 24 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_RSEL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: CGFG [23:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CGFG_MASK 0x00ff0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CGFG_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CGFG_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: ALERT [15:15] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_ALERT_MASK 0x00008000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_ALERT_SHIFT 15 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_ALERT_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: reserved1 [14:09] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_reserved1_MASK 0x00007e00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_reserved1_SHIFT 9 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: PWD_TM_EN [08:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_TM_EN_MASK 0x00000100 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_TM_EN_SHIFT 8 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_TM_EN_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: START [07:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_START_MASK 0x000000fc |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_START_SHIFT 2 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_START_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: PWD_ALERT_SEL [01:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_ALERT_SEL_MASK 0x00000002 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_ALERT_SEL_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_ALERT_SEL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: PWD_EN [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_EN_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_EN_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU2_BPCM_ID - CPU2 BPCM ID Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU2_BPCM_ID :: SW_strap [31:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_SW_strap_MASK 0xffff0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_SW_strap_SHIFT 16 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_BPCM_ID :: HW_revision [15:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_HW_revision_MASK 0x0000ff00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_HW_revision_SHIFT 8 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_BPCM_ID :: PMB_ADDR [07:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_PMB_ADDR_MASK 0x000000ff |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_PMB_ADDR_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU2_BPCM_CAPABILITY - CPU2 BPCM Capability Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU2_BPCM_CAPABILITY :: reserved0 [31:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CAPABILITY_reserved0_MASK 0xffffff00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CAPABILITY_reserved0_SHIFT 8 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_BPCM_CAPABILITY :: Number_of_zones [07:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CAPABILITY_Number_of_zones_MASK 0x000000ff |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CAPABILITY_Number_of_zones_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU2_BPCM_CONTROL - CPU2 BPCM Control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU2_BPCM_CONTROL :: TbdField [31:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CONTROL_TbdField_MASK 0xffffffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CONTROL_TbdField_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU2_BPCM_STATUS - CPU2 BPCM Status Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU2_BPCM_STATUS :: reserved0 [31:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_STATUS_reserved0_SHIFT 1 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_BPCM_STATUS :: PWD_Alert [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_STATUS_PWD_Alert_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_STATUS_PWD_Alert_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU2_AVS_ROSC_CONTROL - CPU2 Ring Oscillator Control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: Test_interval [31:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_Test_interval_MASK 0xffff0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_Test_interval_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_Test_interval_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: ALERT_H [15:15] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_H_MASK 0x00008000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_H_SHIFT 15 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: VALID_H [14:14] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_H_MASK 0x00004000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_H_SHIFT 14 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: ALERT_S [13:13] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_S_MASK 0x00002000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_S_SHIFT 13 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: VALID_S [12:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_S_MASK 0x00001000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_S_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: reserved0 [11:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_reserved0_MASK 0x00000f00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_reserved0_SHIFT 8 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: CONTINUOUS_H [07:07] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_H_MASK 0x00000080 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_H_SHIFT 7 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: CONTINUOUS_S [06:06] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_S_MASK 0x00000040 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_S_SHIFT 6 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: THRSH_EN_H [05:05] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_H_MASK 0x00000020 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_H_SHIFT 5 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: THRSH_EN_S [04:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_S_MASK 0x00000010 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_S_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: ECTR_EN_H [03:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_H_MASK 0x00000008 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_H_SHIFT 3 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: ECTR_EN_S [02:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_S_MASK 0x00000004 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_S_SHIFT 2 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: RO_EN_H [01:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_H_MASK 0x00000002 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_H_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: RO_EN_S [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_S_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_S_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_S_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU2_AVS_ROSC_THRESHOLD - CPU2 Event Counter Threshold Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_THRESHOLD :: THRESH_HI [31:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_HI_MASK 0xffff0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_HI_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_HI_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_THRESHOLD :: THRESH_LO [15:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_LO_MASK 0x0000ffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_LO_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_LO_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU2_AVS_ROSC_COUNT - CPU2 Event Counter Count Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_COUNT :: COUNT_H [31:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_H_MASK 0xffff0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_H_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_COUNT :: COUNT_S [15:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_S_MASK 0x0000ffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_S_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_S_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU2_AVS_PWD_CONTROL - CPU2 PWD control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: reserved0 [31:30] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_reserved0_MASK 0xc0000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_reserved0_SHIFT 30 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: CLRCFG [29:27] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CLRCFG_MASK 0x38000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CLRCFG_SHIFT 27 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CLRCFG_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: RSEL [26:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_RSEL_MASK 0x07000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_RSEL_SHIFT 24 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_RSEL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: CGFG [23:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CGFG_MASK 0x00ff0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CGFG_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CGFG_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: ALERT [15:15] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_ALERT_MASK 0x00008000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_ALERT_SHIFT 15 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_ALERT_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: reserved1 [14:09] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_reserved1_MASK 0x00007e00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_reserved1_SHIFT 9 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: PWD_TM_EN [08:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_TM_EN_MASK 0x00000100 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_TM_EN_SHIFT 8 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_TM_EN_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: START [07:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_START_MASK 0x000000fc |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_START_SHIFT 2 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_START_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: PWD_ALERT_SEL [01:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_ALERT_SEL_MASK 0x00000002 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_ALERT_SEL_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_ALERT_SEL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: PWD_EN [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_EN_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_EN_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU3_BPCM_ID - CPU3 BPCM ID Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU3_BPCM_ID :: SW_strap [31:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_SW_strap_MASK 0xffff0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_SW_strap_SHIFT 16 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_BPCM_ID :: HW_revision [15:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_HW_revision_MASK 0x0000ff00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_HW_revision_SHIFT 8 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_BPCM_ID :: PMB_ADDR [07:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_PMB_ADDR_MASK 0x000000ff |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_PMB_ADDR_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU3_BPCM_CAPABILITY - CPU3 BPCM Capability Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU3_BPCM_CAPABILITY :: reserved0 [31:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CAPABILITY_reserved0_MASK 0xffffff00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CAPABILITY_reserved0_SHIFT 8 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_BPCM_CAPABILITY :: Number_of_zones [07:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CAPABILITY_Number_of_zones_MASK 0x000000ff |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CAPABILITY_Number_of_zones_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU3_BPCM_CONTROL - CPU3 BPCM Control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU3_BPCM_CONTROL :: TbdField [31:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CONTROL_TbdField_MASK 0xffffffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CONTROL_TbdField_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU3_BPCM_STATUS - CPU3 BPCM Status Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU3_BPCM_STATUS :: reserved0 [31:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_STATUS_reserved0_SHIFT 1 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_BPCM_STATUS :: PWD_Alert [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_STATUS_PWD_Alert_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_STATUS_PWD_Alert_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU3_AVS_ROSC_CONTROL - CPU3 Ring Oscillator Control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: Test_interval [31:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_Test_interval_MASK 0xffff0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_Test_interval_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_Test_interval_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: ALERT_H [15:15] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_H_MASK 0x00008000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_H_SHIFT 15 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: VALID_H [14:14] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_H_MASK 0x00004000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_H_SHIFT 14 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: ALERT_S [13:13] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_S_MASK 0x00002000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_S_SHIFT 13 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: VALID_S [12:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_S_MASK 0x00001000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_S_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: reserved0 [11:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_reserved0_MASK 0x00000f00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_reserved0_SHIFT 8 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: CONTINUOUS_H [07:07] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_H_MASK 0x00000080 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_H_SHIFT 7 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: CONTINUOUS_S [06:06] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_S_MASK 0x00000040 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_S_SHIFT 6 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: THRSH_EN_H [05:05] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_H_MASK 0x00000020 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_H_SHIFT 5 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: THRSH_EN_S [04:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_S_MASK 0x00000010 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_S_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: ECTR_EN_H [03:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_H_MASK 0x00000008 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_H_SHIFT 3 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: ECTR_EN_S [02:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_S_MASK 0x00000004 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_S_SHIFT 2 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: RO_EN_H [01:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_H_MASK 0x00000002 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_H_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: RO_EN_S [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_S_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_S_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_S_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU3_AVS_ROSC_THRESHOLD - CPU3 Event Counter Threshold Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_THRESHOLD :: THRESH_HI [31:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_HI_MASK 0xffff0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_HI_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_HI_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_THRESHOLD :: THRESH_LO [15:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_LO_MASK 0x0000ffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_LO_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_LO_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU3_AVS_ROSC_COUNT - CPU3 Event Counter Count Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_COUNT :: COUNT_H [31:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_H_MASK 0xffff0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_H_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_COUNT :: COUNT_S [15:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_S_MASK 0x0000ffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_S_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_S_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU3_AVS_PWD_CONTROL - CPU3 PWD control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: reserved0 [31:30] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_reserved0_MASK 0xc0000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_reserved0_SHIFT 30 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: CLRCFG [29:27] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CLRCFG_MASK 0x38000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CLRCFG_SHIFT 27 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CLRCFG_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: RSEL [26:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_RSEL_MASK 0x07000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_RSEL_SHIFT 24 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_RSEL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: CGFG [23:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CGFG_MASK 0x00ff0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CGFG_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CGFG_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: ALERT [15:15] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_ALERT_MASK 0x00008000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_ALERT_SHIFT 15 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_ALERT_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: reserved1 [14:09] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_reserved1_MASK 0x00007e00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_reserved1_SHIFT 9 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: PWD_TM_EN [08:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_TM_EN_MASK 0x00000100 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_TM_EN_SHIFT 8 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_TM_EN_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: START [07:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_START_MASK 0x000000fc |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_START_SHIFT 2 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_START_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: PWD_ALERT_SEL [01:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_ALERT_SEL_MASK 0x00000002 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_ALERT_SEL_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_ALERT_SEL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: PWD_EN [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_EN_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_EN_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *L2BIU_BPCM_ID - L2BIU BPCM ID Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: L2BIU_BPCM_ID :: SW_strap [31:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_SW_strap_MASK 0xffff0000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_SW_strap_SHIFT 16 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_BPCM_ID :: HW_revision [15:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_HW_revision_MASK 0x0000ff00 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_HW_revision_SHIFT 8 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_BPCM_ID :: PMB_ADDR [07:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_PMB_ADDR_MASK 0x000000ff |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_PMB_ADDR_SHIFT 0 |
| |
| /*************************************************************************** |
| *L2BIU_BPCM_CAPABILITY - L2BIU BPCM Capability Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: L2BIU_BPCM_CAPABILITY :: reserved0 [31:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CAPABILITY_reserved0_MASK 0xffffff00 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CAPABILITY_reserved0_SHIFT 8 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_BPCM_CAPABILITY :: Number_of_zones [07:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CAPABILITY_Number_of_zones_MASK 0x000000ff |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CAPABILITY_Number_of_zones_SHIFT 0 |
| |
| /*************************************************************************** |
| *L2BIU_BPCM_CONTROL - L2BIU BPCM Control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: L2BIU_BPCM_CONTROL :: TbdField [31:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CONTROL_TbdField_MASK 0xffffffff |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CONTROL_TbdField_SHIFT 0 |
| |
| /*************************************************************************** |
| *L2BIU_BPCM_STATUS - L2BIU BPCM Status Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: L2BIU_BPCM_STATUS :: reserved0 [31:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_STATUS_reserved0_SHIFT 1 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_BPCM_STATUS :: PWD_Alert [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_STATUS_PWD_Alert_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_STATUS_PWD_Alert_SHIFT 0 |
| |
| /*************************************************************************** |
| *L2BIU_AVS_ROSC_CONTROL - L2BIU Ring Oscillator Control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: Test_interval [31:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_Test_interval_MASK 0xffff0000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_Test_interval_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_Test_interval_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: ALERT_H [15:15] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_H_MASK 0x00008000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_H_SHIFT 15 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: VALID_H [14:14] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_H_MASK 0x00004000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_H_SHIFT 14 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: ALERT_S [13:13] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_S_MASK 0x00002000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_S_SHIFT 13 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: VALID_S [12:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_S_MASK 0x00001000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_S_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: reserved0 [11:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_reserved0_MASK 0x00000f00 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_reserved0_SHIFT 8 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: CONTINUOUS_H [07:07] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_H_MASK 0x00000080 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_H_SHIFT 7 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: CONTINUOUS_S [06:06] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_S_MASK 0x00000040 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_S_SHIFT 6 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: THRSH_EN_H [05:05] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_H_MASK 0x00000020 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_H_SHIFT 5 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: THRSH_EN_S [04:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_S_MASK 0x00000010 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_S_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: ECTR_EN_H [03:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_H_MASK 0x00000008 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_H_SHIFT 3 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: ECTR_EN_S [02:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_S_MASK 0x00000004 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_S_SHIFT 2 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_S_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: RO_EN_H [01:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_H_MASK 0x00000002 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_H_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: RO_EN_S [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_S_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_S_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_S_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *L2BIU_AVS_ROSC_THRESHOLD - L2BIU Event Counter Threshold Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_THRESHOLD :: THRESH_HI [31:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_HI_MASK 0xffff0000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_HI_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_HI_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_THRESHOLD :: THRESH_LO [15:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_LO_MASK 0x0000ffff |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_LO_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_LO_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *L2BIU_AVS_ROSC_COUNT - L2BIU Event Counter Count Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_COUNT :: COUNT_H [31:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_H_MASK 0xffff0000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_H_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_H_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_COUNT :: COUNT_S [15:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_S_MASK 0x0000ffff |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_S_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_S_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *L2BIU_AVS_PWD_CONTROL - L2BIU PWD control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: reserved0 [31:30] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_reserved0_MASK 0xc0000000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_reserved0_SHIFT 30 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: CLRCFG [29:27] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CLRCFG_MASK 0x38000000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CLRCFG_SHIFT 27 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CLRCFG_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: RSEL [26:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_RSEL_MASK 0x07000000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_RSEL_SHIFT 24 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_RSEL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: CGFG [23:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CGFG_MASK 0x00ff0000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CGFG_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CGFG_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: ALERT [15:15] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_ALERT_MASK 0x00008000 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_ALERT_SHIFT 15 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_ALERT_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: reserved1 [14:09] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_reserved1_MASK 0x00007e00 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_reserved1_SHIFT 9 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: PWD_TM_EN [08:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_TM_EN_MASK 0x00000100 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_TM_EN_SHIFT 8 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_TM_EN_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: START [07:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_START_MASK 0x000000fc |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_START_SHIFT 2 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_START_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: PWD_ALERT_SEL [01:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_ALERT_SEL_MASK 0x00000002 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_ALERT_SEL_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_ALERT_SEL_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: PWD_EN [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_EN_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_EN_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_RESET_CONFIG_REG - CPU Reset Configuration Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_RESET_CONFIG_REG :: reserved0 [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_reserved0_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_reserved0_SHIFT 4 |
| |
| /* HIF_CPUBIUCTRL :: CPU_RESET_CONFIG_REG :: CPU3_RESET [03:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU3_RESET_MASK 0x00000008 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU3_RESET_SHIFT 3 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU3_RESET_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU_RESET_CONFIG_REG :: CPU2_RESET [02:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU2_RESET_MASK 0x00000004 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU2_RESET_SHIFT 2 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU2_RESET_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU_RESET_CONFIG_REG :: CPU1_RESET [01:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU1_RESET_MASK 0x00000002 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU1_RESET_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU1_RESET_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU_RESET_CONFIG_REG :: CPU0_RESET [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU0_RESET_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU0_RESET_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU0_RESET_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_CLOCK_CONFIG_REG - CPU Clock Configuration Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_CLOCK_CONFIG_REG :: reserved0 [31:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_reserved0_MASK 0xfffff000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_reserved0_SHIFT 12 |
| |
| /* HIF_CPUBIUCTRL :: CPU_CLOCK_CONFIG_REG :: GIC_CLK_RATIO [11:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_GIC_CLK_RATIO_MASK 0x00000f00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_GIC_CLK_RATIO_SHIFT 8 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_GIC_CLK_RATIO_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_CLOCK_CONFIG_REG :: reserved1 [07:06] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_reserved1_MASK 0x000000c0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_reserved1_SHIFT 6 |
| |
| /* HIF_CPUBIUCTRL :: CPU_CLOCK_CONFIG_REG :: UBUS_CLK_EN [05:05] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_UBUS_CLK_EN_MASK 0x00000020 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_UBUS_CLK_EN_SHIFT 5 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_UBUS_CLK_EN_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_CLOCK_CONFIG_REG :: SAFE_CLK_MODE [04:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_SAFE_CLK_MODE_MASK 0x00000010 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_SAFE_CLK_MODE_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_SAFE_CLK_MODE_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU_CLOCK_CONFIG_REG :: CLK_RATIO [03:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_CLK_RATIO_MASK 0x0000000f |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_CLK_RATIO_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_CLK_RATIO_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *CPU_MISC_CONFIG_REG - CPU Miscellaneous Configuration Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_MISC_CONFIG_REG :: MiscCommands [31:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_MiscCommands_MASK 0xffffff00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_MiscCommands_SHIFT 8 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_MiscCommands_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_MISC_CONFIG_REG :: ENABLE_PMUIRQ [07:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_ENABLE_PMUIRQ_MASK 0x000000f0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_ENABLE_PMUIRQ_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_ENABLE_PMUIRQ_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_MISC_CONFIG_REG :: VINITHI [03:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_VINITHI_MASK 0x0000000f |
| #define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_VINITHI_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_VINITHI_DEFAULT 0x0000000f |
| |
| /*************************************************************************** |
| *CPU_CREDIT_REG - CPU Request Credit Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: reserved0 [31:31] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_reserved0_MASK 0x80000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_reserved0_SHIFT 31 |
| |
| /* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP2_WR_PAIRING_EN [30:30] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_WR_PAIRING_EN_MASK 0x40000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_WR_PAIRING_EN_SHIFT 30 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_WR_PAIRING_EN_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP1_WR_PAIRING_EN [29:29] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_WR_PAIRING_EN_MASK 0x20000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_WR_PAIRING_EN_SHIFT 29 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_WR_PAIRING_EN_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP0_WR_PAIRING_EN [28:28] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_WR_PAIRING_EN_MASK 0x10000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_WR_PAIRING_EN_SHIFT 28 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_WR_PAIRING_EN_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: reserved1 [27:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_reserved1_MASK 0x0f000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_reserved1_SHIFT 24 |
| |
| /* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP2_WRITE_CRED [23:20] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_WRITE_CRED_MASK 0x00f00000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_WRITE_CRED_SHIFT 20 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_WRITE_CRED_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP2_READ_CRED [19:16] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_READ_CRED_MASK 0x000f0000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_READ_CRED_SHIFT 16 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_READ_CRED_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP1_WRITE_CRED [15:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_WRITE_CRED_MASK 0x0000f000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_WRITE_CRED_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_WRITE_CRED_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP1_READ_CRED [11:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_READ_CRED_MASK 0x00000f00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_READ_CRED_SHIFT 8 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_READ_CRED_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP0_WRITE_CRED [07:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_WRITE_CRED_MASK 0x000000f0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_WRITE_CRED_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_WRITE_CRED_DEFAULT 0x00000004 |
| |
| /* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP0_READ_CRED [03:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_READ_CRED_MASK 0x0000000f |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_READ_CRED_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_READ_CRED_DEFAULT 0x00000004 |
| |
| /*************************************************************************** |
| *CPU_THERM_THROTTLE_TEMP_REG - CPU Thermal Throttling IRQ Config Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_TEMP_REG :: Valid [31:31] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_Valid_MASK 0x80000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_Valid_SHIFT 31 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_Valid_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_TEMP_REG :: reserved0 [30:10] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_reserved0_MASK 0x7ffffc00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_reserved0_SHIFT 10 |
| |
| /* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_TEMP_REG :: Temp [09:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_Temp_MASK 0x000003ff |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_Temp_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_Temp_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_THERM_THROTTLE_IRQ_CONFIG_REG - CPU Thermal Throttling IRQ Config Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_IRQ_CONFIG_REG :: reserved0 [31:27] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_reserved0_MASK 0xf8000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_reserved0_SHIFT 27 |
| |
| /* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_IRQ_CONFIG_REG :: ThermCtl [26:24] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_ThermCtl_MASK 0x07000000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_ThermCtl_SHIFT 24 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_ThermCtl_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_IRQ_CONFIG_REG :: Irq_Enable_Low [23:23] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Irq_Enable_Low_MASK 0x00800000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Irq_Enable_Low_SHIFT 23 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Irq_Enable_Low_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_IRQ_CONFIG_REG :: Irq_Enable_High [22:22] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Irq_Enable_High_MASK 0x00400000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Irq_Enable_High_SHIFT 22 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Irq_Enable_High_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_IRQ_CONFIG_REG :: Temp_Threshold_Low [21:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Temp_Threshold_Low_MASK 0x003ff000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Temp_Threshold_Low_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Temp_Threshold_Low_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_IRQ_CONFIG_REG :: reserved1 [11:10] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_reserved1_MASK 0x00000c00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_reserved1_SHIFT 10 |
| |
| /* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_IRQ_CONFIG_REG :: Temp_Threshold_High [09:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Temp_Threshold_High_MASK 0x000003ff |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Temp_Threshold_High_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Temp_Threshold_High_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_THERM_IRQ_HIGH_REG - CPU Thermal Throttling IRQ High Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_THERM_IRQ_HIGH_REG :: reserved0 [31:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_HIGH_REG_reserved0_MASK 0xfffffffe |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_HIGH_REG_reserved0_SHIFT 1 |
| |
| /* HIF_CPUBIUCTRL :: CPU_THERM_IRQ_HIGH_REG :: Therm_Irq_High [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_HIGH_REG_Therm_Irq_High_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_HIGH_REG_Therm_Irq_High_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_HIGH_REG_Therm_Irq_High_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_THERM_IRQ_LOW_REG - CPU Thermal Throttling IRQ Low Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_THERM_IRQ_LOW_REG :: reserved0 [31:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_LOW_REG_reserved0_MASK 0xfffffffe |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_LOW_REG_reserved0_SHIFT 1 |
| |
| /* HIF_CPUBIUCTRL :: CPU_THERM_IRQ_LOW_REG :: Therm_Irq_Low [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_LOW_REG_Therm_Irq_Low_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_LOW_REG_Therm_Irq_Low_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_LOW_REG_Therm_Irq_Low_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_THERM_MISC_THRESHOLD_REG - CPU Thermal Throttling Misc Threshold Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_THERM_MISC_THRESHOLD_REG :: reserved0 [31:23] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_reserved0_MASK 0xff800000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_reserved0_SHIFT 23 |
| |
| /* HIF_CPUBIUCTRL :: CPU_THERM_MISC_THRESHOLD_REG :: Misc_Irq_Enable [22:22] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Misc_Irq_Enable_MASK 0x00400000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Misc_Irq_Enable_SHIFT 22 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Misc_Irq_Enable_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_THERM_MISC_THRESHOLD_REG :: Temp_Threshold_Low [21:12] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Temp_Threshold_Low_MASK 0x003ff000 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Temp_Threshold_Low_SHIFT 12 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Temp_Threshold_Low_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_THERM_MISC_THRESHOLD_REG :: reserved1 [11:10] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_reserved1_MASK 0x00000c00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_reserved1_SHIFT 10 |
| |
| /* HIF_CPUBIUCTRL :: CPU_THERM_MISC_THRESHOLD_REG :: Temp_Threshold_High [09:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Temp_Threshold_High_MASK 0x000003ff |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Temp_Threshold_High_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Temp_Threshold_High_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_THERM_IRQ_MISC_REG - CPU Thermal Throttling Misc IRQ Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_THERM_IRQ_MISC_REG :: reserved0 [31:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_MISC_REG_reserved0_MASK 0xfffffffe |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_MISC_REG_reserved0_SHIFT 1 |
| |
| /* HIF_CPUBIUCTRL :: CPU_THERM_IRQ_MISC_REG :: Therm_Irq_Misc [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_MISC_REG_Therm_Irq_Misc_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_MISC_REG_Therm_Irq_Misc_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU_DEFEATURE_REG - CPU Defeature Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_DEFEATURE_REG :: TBD_field [31:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_TBD_field_MASK 0xffffff00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_TBD_field_SHIFT 8 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_TBD_field_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_DEFEATURE_REG :: RAC_DEBUG [07:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEBUG_MASK 0x000000f0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEBUG_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEBUG_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_DEFEATURE_REG :: RAC_DEFEATURE [03:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEFEATURE_MASK 0x0000000f |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEFEATURE_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEFEATURE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_DEFEATURE_KEY_REG - CPU Defeature Key Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_DEFEATURE_KEY_REG :: KEY [31:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_KEY_REG_KEY_MASK 0xffffffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_KEY_REG_KEY_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_KEY_REG_KEY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_DEBUGROMADDR_REG - CPU Debug ROM Address Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_DEBUGROMADDR_REG :: DBGROMADDR [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDR_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDR_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDR_DEFAULT 0x01200000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_DEBUGROMADDR_REG :: reserved0 [03:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_reserved0_MASK 0x0000000e |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_reserved0_SHIFT 1 |
| |
| /* HIF_CPUBIUCTRL :: CPU_DEBUGROMADDR_REG :: DBGROMADDRV [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDRV_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDRV_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDRV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_DEBUGSELFADDR_REG - CPU Debug SELF Address Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_DEBUGSELFADDR_REG :: DBGSELFADDR [31:11] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDR_MASK 0xfffff800 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDR_SHIFT 11 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDR_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU_DEBUGSELFADDR_REG :: reserved0 [10:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_reserved0_MASK 0x000007fe |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_reserved0_SHIFT 1 |
| |
| /* HIF_CPUBIUCTRL :: CPU_DEBUGSELFADDR_REG :: DBGSELFADDRV [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDRV_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDRV_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDRV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_DEBUG_TRACECTRL_REG - CPU Debug Trace Control Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_DEBUG_TRACECTRL_REG :: reserved0 [31:05] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG_reserved0_MASK 0xffffffe0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG_reserved0_SHIFT 5 |
| |
| /* HIF_CPUBIUCTRL :: CPU_DEBUG_TRACECTRL_REG :: TPMAXDATASIZE [04:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG_TPMAXDATASIZE_MASK 0x0000001f |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG_TPMAXDATASIZE_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG_TPMAXDATASIZE_DEFAULT 0x00000003 |
| |
| /*************************************************************************** |
| *CPU_AXICONFIG_REG - CPU AXI Config Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_AXICONFIG_REG :: reserved0 [31:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_reserved0_MASK 0xfffffff0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_reserved0_SHIFT 4 |
| |
| /* HIF_CPUBIUCTRL :: CPU_AXICONFIG_REG :: BROADCASTINNER [03:03] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTINNER_MASK 0x00000008 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTINNER_SHIFT 3 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTINNER_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_AXICONFIG_REG :: BROADCASTOUTER [02:02] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTOUTER_MASK 0x00000004 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTOUTER_SHIFT 2 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTOUTER_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_AXICONFIG_REG :: BROADCASTCACHEMAINT [01:01] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTCACHEMAINT_MASK 0x00000002 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTCACHEMAINT_SHIFT 1 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTCACHEMAINT_DEFAULT 0x00000001 |
| |
| /* HIF_CPUBIUCTRL :: CPU_AXICONFIG_REG :: SYSBARDISABLE [00:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_SYSBARDISABLE_MASK 0x00000001 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_SYSBARDISABLE_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_SYSBARDISABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_REVISION_REG - CPU Revision Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_REVISION_REG :: reserved0 [31:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_reserved0_MASK 0xffffff00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_reserved0_SHIFT 8 |
| |
| /* HIF_CPUBIUCTRL :: CPU_REVISION_REG :: MAJOR_REV [07:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MAJOR_REV_MASK 0x000000f0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MAJOR_REV_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MAJOR_REV_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_REVISION_REG :: MINOR_REV [03:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MINOR_REV_MASK 0x0000000f |
| #define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MINOR_REV_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MINOR_REV_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *CPU_UBUS_CFGWINDOW0 - UBUS CFG Window0 Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_UBUS_CFGWINDOW0 :: cfg_window [31:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW0_cfg_window_MASK 0xffffffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW0_cfg_window_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW0_cfg_window_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_UBUS_CFGWINDOW1 - UBUS CFG Window1 Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_UBUS_CFGWINDOW1 :: cfg_window [31:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW1_cfg_window_MASK 0xffffffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW1_cfg_window_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW1_cfg_window_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_UBUS_CFGWINDOW2 - UBUS CFG Window2 Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_UBUS_CFGWINDOW2 :: cfg_window [31:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW2_cfg_window_MASK 0xffffffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW2_cfg_window_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW2_cfg_window_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_UBUS_CFGWINDOW3 - UBUS CFG Window3 Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_UBUS_CFGWINDOW3 :: cfg_window [31:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW3_cfg_window_MASK 0xffffffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW3_cfg_window_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW3_cfg_window_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_UBUS_CFGWINDOW4 - UBUS CFG Window4 Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_UBUS_CFGWINDOW4 :: cfg_window [31:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW4_cfg_window_MASK 0xffffffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW4_cfg_window_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW4_cfg_window_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_UBUS_CFGWINDOW5 - UBUS CFG Window5 Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_UBUS_CFGWINDOW5 :: cfg_window [31:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW5_cfg_window_MASK 0xffffffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW5_cfg_window_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW5_cfg_window_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_UBUS_CFGWINDOW6 - UBUS CFG Window6 Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_UBUS_CFGWINDOW6 :: cfg_window [31:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW6_cfg_window_MASK 0xffffffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW6_cfg_window_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW6_cfg_window_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_UBUS_CFGWINDOW7 - UBUS CFG Window7 Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_UBUS_CFGWINDOW7 :: cfg_window [31:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW7_cfg_window_MASK 0xffffffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW7_cfg_window_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW7_cfg_window_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_UBUS_CONFIG - UBUS Configuration Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_UBUS_CONFIG :: reserved0 [31:08] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_reserved0_MASK 0xffffff00 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_reserved0_SHIFT 8 |
| |
| /* HIF_CPUBIUCTRL :: CPU_UBUS_CONFIG :: Uniq_pid_enable [07:07] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_Uniq_pid_enable_MASK 0x00000080 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_Uniq_pid_enable_SHIFT 7 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_Uniq_pid_enable_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_UBUS_CONFIG :: reserved1 [06:05] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_reserved1_MASK 0x00000060 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_reserved1_SHIFT 5 |
| |
| /* HIF_CPUBIUCTRL :: CPU_UBUS_CONFIG :: wr_with_ack_enable [04:04] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_wr_with_ack_enable_MASK 0x00000010 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_wr_with_ack_enable_SHIFT 4 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_wr_with_ack_enable_DEFAULT 0x00000000 |
| |
| /* HIF_CPUBIUCTRL :: CPU_UBUS_CONFIG :: cd_ctrl [03:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_cd_ctrl_MASK 0x0000000f |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_cd_ctrl_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_cd_ctrl_DEFAULT 0x00000004 |
| |
| /*************************************************************************** |
| *CPU_SCRATCH_REG - Scratch Register |
| ***************************************************************************/ |
| /* HIF_CPUBIUCTRL :: CPU_SCRATCH_REG :: scratch [31:00] */ |
| #define BCHP_HIF_CPUBIUCTRL_CPU_SCRATCH_REG_scratch_MASK 0xffffffff |
| #define BCHP_HIF_CPUBIUCTRL_CPU_SCRATCH_REG_scratch_SHIFT 0 |
| #define BCHP_HIF_CPUBIUCTRL_CPU_SCRATCH_REG_scratch_DEFAULT 0x00000000 |
| |
| #endif /* #ifndef BCHP_HIF_CPUBIUCTRL_H__ */ |
| |
| /* End of File */ |
