| /*************************************************************************** |
| * Copyright (c) 1999-2012, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Thu Mar 15 03:09:23 2012 |
| * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008005 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: $ |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_FLASH_DMA_H__ |
| #define BCHP_FLASH_DMA_H__ |
| |
| /*************************************************************************** |
| *FLASH_DMA - Descriptor Flash DMA Registers |
| ***************************************************************************/ |
| #define BCHP_FLASH_DMA_REVISION 0x0041d000 /* NAND Revision */ |
| #define BCHP_FLASH_DMA_FIRST_DESC 0x0041d004 /* DMA First descriptor address */ |
| #define BCHP_FLASH_DMA_CTRL 0x0041d008 /* DMA CTRL */ |
| #define BCHP_FLASH_DMA_MODE 0x0041d00c /* DMA MODE */ |
| #define BCHP_FLASH_DMA_STATUS 0x0041d010 /* DMA STATUS */ |
| #define BCHP_FLASH_DMA_INTERRUPT_DESC 0x0041d014 /* DMA INTERRUPT DESC */ |
| #define BCHP_FLASH_DMA_ERROR_STATUS 0x0041d018 /* DMA ERROR STATUS */ |
| #define BCHP_FLASH_DMA_CURRENT_DESC 0x0041d01c /* DMA CURRENT DESC */ |
| |
| /*************************************************************************** |
| *REVISION - NAND Revision |
| ***************************************************************************/ |
| /* FLASH_DMA :: REVISION :: reserved0 [31:16] */ |
| #define BCHP_FLASH_DMA_REVISION_reserved0_MASK 0xffff0000 |
| #define BCHP_FLASH_DMA_REVISION_reserved0_SHIFT 16 |
| |
| /* FLASH_DMA :: REVISION :: MAJOR [15:08] */ |
| #define BCHP_FLASH_DMA_REVISION_MAJOR_MASK 0x0000ff00 |
| #define BCHP_FLASH_DMA_REVISION_MAJOR_SHIFT 8 |
| #define BCHP_FLASH_DMA_REVISION_MAJOR_DEFAULT 0x00000000 |
| |
| /* FLASH_DMA :: REVISION :: MINOR [07:00] */ |
| #define BCHP_FLASH_DMA_REVISION_MINOR_MASK 0x000000ff |
| #define BCHP_FLASH_DMA_REVISION_MINOR_SHIFT 0 |
| #define BCHP_FLASH_DMA_REVISION_MINOR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FIRST_DESC - DMA First descriptor address |
| ***************************************************************************/ |
| /* FLASH_DMA :: FIRST_DESC :: ADDR [31:00] */ |
| #define BCHP_FLASH_DMA_FIRST_DESC_ADDR_MASK 0xffffffff |
| #define BCHP_FLASH_DMA_FIRST_DESC_ADDR_SHIFT 0 |
| #define BCHP_FLASH_DMA_FIRST_DESC_ADDR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CTRL - DMA CTRL |
| ***************************************************************************/ |
| /* FLASH_DMA :: CTRL :: reserved0 [31:02] */ |
| #define BCHP_FLASH_DMA_CTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_FLASH_DMA_CTRL_reserved0_SHIFT 2 |
| |
| /* FLASH_DMA :: CTRL :: WAKE [01:01] */ |
| #define BCHP_FLASH_DMA_CTRL_WAKE_MASK 0x00000002 |
| #define BCHP_FLASH_DMA_CTRL_WAKE_SHIFT 1 |
| #define BCHP_FLASH_DMA_CTRL_WAKE_DEFAULT 0x00000000 |
| |
| /* FLASH_DMA :: CTRL :: RUN [00:00] */ |
| #define BCHP_FLASH_DMA_CTRL_RUN_MASK 0x00000001 |
| #define BCHP_FLASH_DMA_CTRL_RUN_SHIFT 0 |
| #define BCHP_FLASH_DMA_CTRL_RUN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MODE - DMA MODE |
| ***************************************************************************/ |
| /* FLASH_DMA :: MODE :: reserved0 [31:02] */ |
| #define BCHP_FLASH_DMA_MODE_reserved0_MASK 0xfffffffc |
| #define BCHP_FLASH_DMA_MODE_reserved0_SHIFT 2 |
| |
| /* FLASH_DMA :: MODE :: STOP_ON_ERROR [01:01] */ |
| #define BCHP_FLASH_DMA_MODE_STOP_ON_ERROR_MASK 0x00000002 |
| #define BCHP_FLASH_DMA_MODE_STOP_ON_ERROR_SHIFT 1 |
| #define BCHP_FLASH_DMA_MODE_STOP_ON_ERROR_DEFAULT 0x00000000 |
| |
| /* FLASH_DMA :: MODE :: MODE [00:00] */ |
| #define BCHP_FLASH_DMA_MODE_MODE_MASK 0x00000001 |
| #define BCHP_FLASH_DMA_MODE_MODE_SHIFT 0 |
| #define BCHP_FLASH_DMA_MODE_MODE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *STATUS - DMA STATUS |
| ***************************************************************************/ |
| /* FLASH_DMA :: STATUS :: reserved0 [31:28] */ |
| #define BCHP_FLASH_DMA_STATUS_reserved0_MASK 0xf0000000 |
| #define BCHP_FLASH_DMA_STATUS_reserved0_SHIFT 28 |
| |
| /* FLASH_DMA :: STATUS :: RBUS_STATE [27:19] */ |
| #define BCHP_FLASH_DMA_STATUS_RBUS_STATE_MASK 0x0ff80000 |
| #define BCHP_FLASH_DMA_STATUS_RBUS_STATE_SHIFT 19 |
| |
| /* FLASH_DMA :: STATUS :: SCB_STATE [18:14] */ |
| #define BCHP_FLASH_DMA_STATUS_SCB_STATE_MASK 0x0007c000 |
| #define BCHP_FLASH_DMA_STATUS_SCB_STATE_SHIFT 14 |
| |
| /* FLASH_DMA :: STATUS :: PROCESS_STATE [13:07] */ |
| #define BCHP_FLASH_DMA_STATUS_PROCESS_STATE_MASK 0x00003f80 |
| #define BCHP_FLASH_DMA_STATUS_PROCESS_STATE_SHIFT 7 |
| |
| /* FLASH_DMA :: STATUS :: DMA_STATE [06:02] */ |
| #define BCHP_FLASH_DMA_STATUS_DMA_STATE_MASK 0x0000007c |
| #define BCHP_FLASH_DMA_STATUS_DMA_STATE_SHIFT 2 |
| |
| /* FLASH_DMA :: STATUS :: WAKE [01:00] */ |
| #define BCHP_FLASH_DMA_STATUS_WAKE_MASK 0x00000003 |
| #define BCHP_FLASH_DMA_STATUS_WAKE_SHIFT 0 |
| |
| /*************************************************************************** |
| *INTERRUPT_DESC - DMA INTERRUPT DESC |
| ***************************************************************************/ |
| /* FLASH_DMA :: INTERRUPT_DESC :: ADDR [31:00] */ |
| #define BCHP_FLASH_DMA_INTERRUPT_DESC_ADDR_MASK 0xffffffff |
| #define BCHP_FLASH_DMA_INTERRUPT_DESC_ADDR_SHIFT 0 |
| |
| /*************************************************************************** |
| *ERROR_STATUS - DMA ERROR STATUS |
| ***************************************************************************/ |
| /* FLASH_DMA :: ERROR_STATUS :: reserved0 [31:03] */ |
| #define BCHP_FLASH_DMA_ERROR_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_FLASH_DMA_ERROR_STATUS_reserved0_SHIFT 3 |
| |
| /* FLASH_DMA :: ERROR_STATUS :: NAND_ECCuncor [02:02] */ |
| #define BCHP_FLASH_DMA_ERROR_STATUS_NAND_ECCuncor_MASK 0x00000004 |
| #define BCHP_FLASH_DMA_ERROR_STATUS_NAND_ECCuncor_SHIFT 2 |
| |
| /* FLASH_DMA :: ERROR_STATUS :: MISMATCH [01:01] */ |
| #define BCHP_FLASH_DMA_ERROR_STATUS_MISMATCH_MASK 0x00000002 |
| #define BCHP_FLASH_DMA_ERROR_STATUS_MISMATCH_SHIFT 1 |
| |
| /* FLASH_DMA :: ERROR_STATUS :: TIMEOUT [00:00] */ |
| #define BCHP_FLASH_DMA_ERROR_STATUS_TIMEOUT_MASK 0x00000001 |
| #define BCHP_FLASH_DMA_ERROR_STATUS_TIMEOUT_SHIFT 0 |
| |
| /*************************************************************************** |
| *CURRENT_DESC - DMA CURRENT DESC |
| ***************************************************************************/ |
| /* FLASH_DMA :: CURRENT_DESC :: ADDR [31:00] */ |
| #define BCHP_FLASH_DMA_CURRENT_DESC_ADDR_MASK 0xffffffff |
| #define BCHP_FLASH_DMA_CURRENT_DESC_ADDR_SHIFT 0 |
| |
| #endif /* #ifndef BCHP_FLASH_DMA_H__ */ |
| |
| /* End of File */ |
