| /*************************************************************************** |
| * Copyright (c) 1999-2013, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Tue Apr 16 03:27:39 2013 |
| * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: $ |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_HIF_CPU_INTR1_H__ |
| #define BCHP_HIF_CPU_INTR1_H__ |
| |
| /*************************************************************************** |
| *HIF_CPU_INTR1 - HIF CPU Thread Processor 0 Level 1 Interrupt Controller Registers |
| ***************************************************************************/ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS 0x00411400 /* Interrupt Status Register */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS 0x00411404 /* Interrupt Status Register */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS 0x00411408 /* Interrupt Status Register */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS 0x0041140c /* Interrupt Mask Status Register */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS 0x00411410 /* Interrupt Mask Status Register */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS 0x00411414 /* Interrupt Mask Status Register */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET 0x00411418 /* Interrupt Mask Set Register */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET 0x0041141c /* Interrupt Mask Set Register */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET 0x00411420 /* Interrupt Mask Set Register */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR 0x00411424 /* Interrupt Mask Clear Register */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR 0x00411428 /* Interrupt Mask Clear Register */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR 0x0041142c /* Interrupt Mask Clear Register */ |
| |
| /*************************************************************************** |
| *INTR_W0_STATUS - Interrupt Status Register |
| ***************************************************************************/ |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HDMI_TX_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: M2MC_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: SPARE_01_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: SPARE_00_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: SPARE_25_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_25_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_25_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_25_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: SPARE_24_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_24_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_24_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_24_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: SPARE_23_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_23_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_23_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_23_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: SPARE_22_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_22_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_22_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_22_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *INTR_W1_STATUS - Interrupt Status Register |
| ***************************************************************************/ |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART2_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART1_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART0_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_08_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_07_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_32_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_32_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_32_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_32_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_06_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_05_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_04_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_03_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_31_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_31_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_31_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_31_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_30_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_30_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_30_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_30_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_29_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_29_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_29_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_29_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_28_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_28_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_28_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_28_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_27_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_27_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_27_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_27_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_26_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_26_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_26_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_26_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: NMI_PIN_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_02_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: MEMC_0_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI1_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI0_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *INTR_W2_STATUS - Interrupt Status Register |
| ***************************************************************************/ |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_21_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: DFE_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_DFE_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_DFE_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_DFE_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: MEM_DMA_0_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_MEM_DMA_0_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_MEM_DMA_0_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_MEM_DMA_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_38_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_38_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_38_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_38_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_37_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_37_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_37_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_37_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_36_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_36_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_36_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_36_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_35_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_35_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_35_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_35_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_34_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_34_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_34_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_34_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_33_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_33_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_33_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_33_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_18_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_17_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: AVD0_0_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_16_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SDIO0_0_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_15_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_14_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_13_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_12_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_11_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_10_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_09_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_OHCI_0_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_EHCI_0_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_BRIDGE_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *INTR_W0_MASK_STATUS - Interrupt Mask Status Register |
| ***************************************************************************/ |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_TX_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: M2MC_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: SPARE_01_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: SPARE_00_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: SPARE_25_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_25_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_25_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_25_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: SPARE_24_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_24_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_24_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_24_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: SPARE_23_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_23_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_23_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_23_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: SPARE_22_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_22_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_22_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_22_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *INTR_W1_MASK_STATUS - Interrupt Mask Status Register |
| ***************************************************************************/ |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART2_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART1_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART0_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_08_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_07_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_32_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_32_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_32_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_32_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_06_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_05_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_04_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_03_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_31_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_31_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_31_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_31_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_30_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_30_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_30_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_30_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_29_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_29_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_29_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_29_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_28_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_28_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_28_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_28_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_27_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_27_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_27_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_27_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_26_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_26_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_26_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_26_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: NMI_PIN_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_02_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: MEMC_0_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI1_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI0_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *INTR_W2_MASK_STATUS - Interrupt Mask Status Register |
| ***************************************************************************/ |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_21_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: DFE_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_DFE_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_DFE_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_DFE_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: MEM_DMA_0_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_MEM_DMA_0_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_MEM_DMA_0_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_MEM_DMA_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_38_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_38_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_38_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_38_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_37_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_37_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_37_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_37_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_36_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_36_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_36_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_36_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_35_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_35_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_35_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_35_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_34_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_34_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_34_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_34_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_33_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_33_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_33_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_33_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_18_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_17_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: AVD0_0_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_16_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SDIO0_0_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_15_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_14_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_13_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_12_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_11_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_10_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_09_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_OHCI_0_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_EHCI_0_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_BRIDGE_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *INTR_W0_MASK_SET - Interrupt Mask Set Register |
| ***************************************************************************/ |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HDMI_TX_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: M2MC_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: SPARE_01_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: SPARE_00_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: SPARE_25_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_25_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_25_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_25_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: SPARE_24_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_24_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_24_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_24_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: SPARE_23_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_23_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_23_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_23_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_14_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_13_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_12_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_11_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_10_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_09_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_08_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_07_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_06_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: SPARE_22_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_22_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_22_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_22_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *INTR_W1_MASK_SET - Interrupt Mask Set Register |
| ***************************************************************************/ |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART2_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART1_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART0_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_08_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_07_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_32_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_32_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_32_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_32_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_06_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_05_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_04_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_03_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_31_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_31_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_31_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_31_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_30_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_30_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_30_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_30_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_29_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_29_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_29_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_29_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_28_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_28_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_28_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_28_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_27_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_27_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_27_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_27_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_26_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_26_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_26_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_26_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: NMI_PIN_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_02_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: MEMC_0_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI1_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI0_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *INTR_W2_MASK_SET - Interrupt Mask Set Register |
| ***************************************************************************/ |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_21_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: DFE_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_DFE_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_DFE_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_DFE_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: MEM_DMA_0_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_MEM_DMA_0_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_MEM_DMA_0_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_MEM_DMA_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_38_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_38_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_38_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_38_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_37_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_37_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_37_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_37_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_36_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_36_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_36_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_36_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_35_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_35_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_35_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_35_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_34_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_34_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_34_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_34_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_33_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_33_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_33_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_33_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_18_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_17_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: AVD0_0_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_16_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SDIO0_0_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_15_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_14_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_13_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_12_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_11_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_10_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_09_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_OHCI_0_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_EHCI_0_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_BRIDGE_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register |
| ***************************************************************************/ |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_TX_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: M2MC_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: SPARE_01_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: SPARE_00_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: SPARE_25_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_25_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_25_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_25_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: SPARE_24_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_24_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_24_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_24_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: SPARE_23_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_23_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_23_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_23_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_14_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_13_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_12_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_11_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_10_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_09_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_08_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_07_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_06_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: SPARE_22_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_22_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_22_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_22_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register |
| ***************************************************************************/ |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART2_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART1_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART0_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_08_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_07_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_32_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_32_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_32_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_32_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_06_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_05_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_04_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_03_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_31_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_31_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_31_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_31_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_30_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_30_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_30_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_30_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_29_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_29_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_29_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_29_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_28_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_28_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_28_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_28_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_27_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_27_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_27_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_27_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_26_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_26_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_26_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_26_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: NMI_PIN_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_02_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: MEMC_0_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI1_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI0_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register |
| ***************************************************************************/ |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_21_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: DFE_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_DFE_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_DFE_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_DFE_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: MEM_DMA_0_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_MEM_DMA_0_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_MEM_DMA_0_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_MEM_DMA_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_38_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_38_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_38_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_38_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_37_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_37_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_37_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_37_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_36_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_36_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_36_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_36_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_35_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_35_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_35_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_35_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_34_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_34_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_34_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_34_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_33_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_33_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_33_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_33_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_18_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_17_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: AVD0_0_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_16_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SDIO0_0_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_15_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_14_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_13_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_12_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_11_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_10_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_09_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_OHCI_0_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_EHCI_0_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_BRIDGE_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000001 |
| |
| #endif /* #ifndef BCHP_HIF_CPU_INTR1_H__ */ |
| |
| /* End of File */ |