| /*************************************************************************** |
| * Copyright (c) 1999-2011, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Fri Apr 1 16:36:59 2011 |
| * MD5 Checksum d03d08c4839c3311c9d35c4cd5e10373 |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_nand.h $ |
| * |
| * Hydra_Software_Devel/1 4/4/11 2:02p albertl |
| * SW7344-40: Initial revision. |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_NAND_H__ |
| #define BCHP_NAND_H__ |
| |
| /*************************************************************************** |
| *NAND - Nand Flash Control Registers |
| ***************************************************************************/ |
| #define BCHP_NAND_REVISION 0x00002800 /* NAND Revision */ |
| #define BCHP_NAND_CMD_START 0x00002804 /* Nand Flash Command Start */ |
| #define BCHP_NAND_CMD_EXT_ADDRESS 0x00002808 /* Nand Flash Command Extended Address */ |
| #define BCHP_NAND_CMD_ADDRESS 0x0000280c /* Nand Flash Command Address */ |
| #define BCHP_NAND_CMD_END_ADDRESS 0x00002810 /* Nand Flash Command End Address */ |
| #define BCHP_NAND_CS_NAND_SELECT 0x00002814 /* Nand Flash EBI CS Select */ |
| #define BCHP_NAND_CS_NAND_XOR 0x00002818 /* Nand Flash EBI CS Address XOR with 1FC0 Control */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_0 0x00002820 /* Nand Flash Spare Area Read Bytes 0-3 */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_4 0x00002824 /* Nand Flash Spare Area Read Bytes 4-7 */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_8 0x00002828 /* Nand Flash Spare Area Read Bytes 8-11 */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_C 0x0000282c /* Nand Flash Spare Area Read Bytes 12-15 */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_0 0x00002830 /* Nand Flash Spare Area Write Bytes 0-3 */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_4 0x00002834 /* Nand Flash Spare Area Write Bytes 4-7 */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_8 0x00002838 /* Nand Flash Spare Area Write Bytes 8-11 */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_C 0x0000283c /* Nand Flash Spare Area Write Bytes 12-15 */ |
| #define BCHP_NAND_ACC_CONTROL 0x00002840 /* Nand Flash Access Control */ |
| #define BCHP_NAND_CONFIG 0x00002848 /* Nand Flash Config */ |
| #define BCHP_NAND_TIMING_1 0x00002850 /* Nand Flash Timing Parameters 1 */ |
| #define BCHP_NAND_TIMING_2 0x00002854 /* Nand Flash Timing Parameters 2 */ |
| #define BCHP_NAND_SEMAPHORE 0x00002858 /* Semaphore */ |
| #define BCHP_NAND_FLASH_DEVICE_ID 0x00002860 /* Nand Flash Device ID */ |
| #define BCHP_NAND_FLASH_DEVICE_ID_EXT 0x00002864 /* Nand Flash Extended Device ID */ |
| #define BCHP_NAND_BLOCK_LOCK_STATUS 0x00002868 /* Nand Flash Block Lock Status */ |
| #define BCHP_NAND_INTFC_STATUS 0x0000286c /* Nand Flash Interface Status */ |
| #define BCHP_NAND_ECC_CORR_EXT_ADDR 0x00002870 /* ECC Correctable Error Extended Address */ |
| #define BCHP_NAND_ECC_CORR_ADDR 0x00002874 /* ECC Correctable Error Address */ |
| #define BCHP_NAND_ECC_UNC_EXT_ADDR 0x00002878 /* ECC Uncorrectable Error Extended Address */ |
| #define BCHP_NAND_ECC_UNC_ADDR 0x0000287c /* ECC Uncorrectable Error Address */ |
| #define BCHP_NAND_READ_ERROR_COUNT 0x00002880 /* Read Error Count */ |
| #define BCHP_NAND_CORR_STAT_THRESHOLD 0x00002884 /* Correctable Error Reporting Threshold */ |
| #define BCHP_NAND_ONFI_STATUS 0x00002888 /* ONFI Status */ |
| #define BCHP_NAND_ONFI_DEBUG_DATA 0x0000288c /* ONFI Debug Data */ |
| #define BCHP_NAND_FLASH_READ_EXT_ADDR 0x00002890 /* Flash Read Data Extended Address */ |
| #define BCHP_NAND_FLASH_READ_ADDR 0x00002894 /* Flash Read Data Address */ |
| #define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR 0x00002898 /* Page Program Extended Address */ |
| #define BCHP_NAND_PROGRAM_PAGE_ADDR 0x0000289c /* Page Program Address */ |
| #define BCHP_NAND_COPY_BACK_EXT_ADDR 0x000028a0 /* Copy Back Extended Address */ |
| #define BCHP_NAND_COPY_BACK_ADDR 0x000028a4 /* Copy Back Address */ |
| #define BCHP_NAND_BLOCK_ERASE_EXT_ADDR 0x000028a8 /* Block Erase Extended Address */ |
| #define BCHP_NAND_BLOCK_ERASE_ADDR 0x000028ac /* Block Erase Address */ |
| #define BCHP_NAND_INV_READ_EXT_ADDR 0x000028b0 /* Flash Invalid Data Extended Address */ |
| #define BCHP_NAND_INV_READ_ADDR 0x000028b4 /* Flash Invalid Data Address */ |
| #define BCHP_NAND_BLK_WR_PROTECT 0x000028c0 /* Block Write Protect Enable and Size for EBI_CS0b */ |
| #define BCHP_NAND_ACC_CONTROL_CS1 0x000028d0 /* Nand Flash Access Control */ |
| #define BCHP_NAND_CONFIG_CS1 0x000028d4 /* Nand Flash Config */ |
| #define BCHP_NAND_TIMING_1_CS1 0x000028d8 /* Nand Flash Timing Parameters 1 */ |
| #define BCHP_NAND_TIMING_2_CS1 0x000028dc /* Nand Flash Timing Parameters 2 */ |
| #define BCHP_NAND_ACC_CONTROL_CS2 0x000028e0 /* Nand Flash Access Control */ |
| #define BCHP_NAND_CONFIG_CS2 0x000028e4 /* Nand Flash Config */ |
| #define BCHP_NAND_TIMING_1_CS2 0x000028e8 /* Nand Flash Timing Parameters 1 */ |
| #define BCHP_NAND_TIMING_2_CS2 0x000028ec /* Nand Flash Timing Parameters 2 */ |
| #define BCHP_NAND_ACC_CONTROL_CS3 0x000028f0 /* Nand Flash Access Control */ |
| #define BCHP_NAND_CONFIG_CS3 0x000028f4 /* Nand Flash Config */ |
| #define BCHP_NAND_TIMING_1_CS3 0x000028f8 /* Nand Flash Timing Parameters 1 */ |
| #define BCHP_NAND_TIMING_2_CS3 0x000028fc /* Nand Flash Timing Parameters 2 */ |
| #define BCHP_NAND_ACC_CONTROL_CS4 0x00002900 /* Nand Flash Access Control */ |
| #define BCHP_NAND_CONFIG_CS4 0x00002904 /* Nand Flash Config */ |
| #define BCHP_NAND_TIMING_1_CS4 0x00002908 /* Nand Flash Timing Parameters 1 */ |
| #define BCHP_NAND_TIMING_2_CS4 0x0000290c /* Nand Flash Timing Parameters 2 */ |
| #define BCHP_NAND_ACC_CONTROL_CS5 0x00002910 /* Nand Flash Access Control */ |
| #define BCHP_NAND_CONFIG_CS5 0x00002914 /* Nand Flash Config */ |
| #define BCHP_NAND_TIMING_1_CS5 0x00002918 /* Nand Flash Timing Parameters 1 */ |
| #define BCHP_NAND_TIMING_2_CS5 0x0000291c /* Nand Flash Timing Parameters 2 */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_10 0x00002930 /* Nand Flash Spare Area Read Bytes 16-19 */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_14 0x00002934 /* Nand Flash Spare Area Read Bytes 20-23 */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_18 0x00002938 /* Nand Flash Spare Area Read Bytes 24-27 */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_1C 0x0000293c /* Nand Flash Spare Area Read Bytes 28-31 */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_10 0x00002940 /* Nand Flash Spare Area Write Bytes 16-19 */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_14 0x00002944 /* Nand Flash Spare Area Write Bytes 20-23 */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_18 0x00002948 /* Nand Flash Spare Area Write Bytes 24-27 */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C 0x0000294c /* Nand Flash Spare Area Write Bytes 28-31 */ |
| #define BCHP_NAND_LL_OP 0x00002978 /* Nand Flash Low Level Operation */ |
| #define BCHP_NAND_LL_RDDATA 0x0000297c /* Nand Flash Low Level Read Data */ |
| |
| /*************************************************************************** |
| *REVISION - NAND Revision |
| ***************************************************************************/ |
| /* NAND :: REVISION :: 8KB_PAGE_SUPPORT [31:31] */ |
| #define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_MASK 0x80000000 |
| #define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_SHIFT 31 |
| #define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_DEFAULT 1 |
| |
| /* NAND :: REVISION :: reserved0 [30:16] */ |
| #define BCHP_NAND_REVISION_reserved0_MASK 0x7fff0000 |
| #define BCHP_NAND_REVISION_reserved0_SHIFT 16 |
| |
| /* NAND :: REVISION :: MAJOR [15:08] */ |
| #define BCHP_NAND_REVISION_MAJOR_MASK 0x0000ff00 |
| #define BCHP_NAND_REVISION_MAJOR_SHIFT 8 |
| #define BCHP_NAND_REVISION_MAJOR_DEFAULT 5 |
| |
| /* NAND :: REVISION :: MINOR [07:00] */ |
| #define BCHP_NAND_REVISION_MINOR_MASK 0x000000ff |
| #define BCHP_NAND_REVISION_MINOR_SHIFT 0 |
| #define BCHP_NAND_REVISION_MINOR_DEFAULT 0 |
| |
| /*************************************************************************** |
| *CMD_START - Nand Flash Command Start |
| ***************************************************************************/ |
| /* NAND :: CMD_START :: reserved0 [31:29] */ |
| #define BCHP_NAND_CMD_START_reserved0_MASK 0xe0000000 |
| #define BCHP_NAND_CMD_START_reserved0_SHIFT 29 |
| |
| /* NAND :: CMD_START :: OPCODE [28:24] */ |
| #define BCHP_NAND_CMD_START_OPCODE_MASK 0x1f000000 |
| #define BCHP_NAND_CMD_START_OPCODE_SHIFT 24 |
| #define BCHP_NAND_CMD_START_OPCODE_DEFAULT 0 |
| #define BCHP_NAND_CMD_START_OPCODE_NULL 0 |
| #define BCHP_NAND_CMD_START_OPCODE_PAGE_READ 1 |
| #define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ 2 |
| #define BCHP_NAND_CMD_START_OPCODE_STATUS_READ 3 |
| #define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE 4 |
| #define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA 5 |
| #define BCHP_NAND_CMD_START_OPCODE_COPY_BACK 6 |
| #define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ 7 |
| #define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE 8 |
| #define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET 9 |
| #define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK 10 |
| #define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN 11 |
| #define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK 12 |
| #define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS 13 |
| #define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ 14 |
| #define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL 15 |
| #define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP 16 |
| |
| /* NAND :: CMD_START :: reserved1 [23:00] */ |
| #define BCHP_NAND_CMD_START_reserved1_MASK 0x00ffffff |
| #define BCHP_NAND_CMD_START_reserved1_SHIFT 0 |
| |
| /*************************************************************************** |
| *CMD_EXT_ADDRESS - Nand Flash Command Extended Address |
| ***************************************************************************/ |
| /* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */ |
| #define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK 0xfff80000 |
| #define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT 19 |
| |
| /* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */ |
| #define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK 0x00070000 |
| #define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT 16 |
| #define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT 0 |
| |
| /* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */ |
| #define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK 0x0000ffff |
| #define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT 0 |
| #define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *CMD_ADDRESS - Nand Flash Command Address |
| ***************************************************************************/ |
| /* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */ |
| #define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK 0xffffffff |
| #define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT 0 |
| #define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *CMD_END_ADDRESS - Nand Flash Command End Address |
| ***************************************************************************/ |
| /* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */ |
| #define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK 0xffffffff |
| #define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT 0 |
| #define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *CS_NAND_SELECT - Nand Flash EBI CS Select |
| ***************************************************************************/ |
| /* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */ |
| #define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK 0x80000000 |
| #define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT 31 |
| #define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */ |
| #define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK 0x40000000 |
| #define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT 30 |
| |
| /* NAND :: CS_NAND_SELECT :: reserved0 [29:29] */ |
| #define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK 0x20000000 |
| #define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT 29 |
| |
| /* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */ |
| #define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK 0x10000000 |
| #define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT 28 |
| #define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_SELECT :: reserved1 [27:16] */ |
| #define BCHP_NAND_CS_NAND_SELECT_reserved1_MASK 0x0fff0000 |
| #define BCHP_NAND_CS_NAND_SELECT_reserved1_SHIFT 16 |
| |
| /* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */ |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK 0x00008000 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT 15 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */ |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK 0x00004000 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT 14 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */ |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK 0x00002000 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT 13 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */ |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK 0x00001000 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT 12 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */ |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK 0x00000800 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT 11 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */ |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK 0x00000400 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT 10 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */ |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK 0x00000200 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT 9 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */ |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK 0x00000100 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT 8 |
| |
| /* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */ |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK 0x00000080 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT 7 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */ |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK 0x00000040 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT 6 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */ |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK 0x00000020 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT 5 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */ |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK 0x00000010 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT 4 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */ |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK 0x00000008 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT 3 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */ |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK 0x00000004 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT 2 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */ |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK 0x00000002 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT 1 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */ |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK 0x00000001 |
| #define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT 0 |
| |
| /*************************************************************************** |
| *CS_NAND_XOR - Nand Flash EBI CS Address XOR with 1FC0 Control |
| ***************************************************************************/ |
| /* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_1FC0_XOR [31:31] */ |
| #define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_MASK 0x80000000 |
| #define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_SHIFT 31 |
| #define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_XOR :: reserved0 [30:08] */ |
| #define BCHP_NAND_CS_NAND_XOR_reserved0_MASK 0x7fffff00 |
| #define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT 8 |
| |
| /* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_1FC0_XOR [07:07] */ |
| #define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_MASK 0x00000080 |
| #define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_SHIFT 7 |
| #define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_1FC0_XOR [06:06] */ |
| #define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_MASK 0x00000040 |
| #define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_SHIFT 6 |
| #define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_1FC0_XOR [05:05] */ |
| #define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_MASK 0x00000020 |
| #define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_SHIFT 5 |
| #define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_1FC0_XOR [04:04] */ |
| #define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_MASK 0x00000010 |
| #define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_SHIFT 4 |
| #define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_1FC0_XOR [03:03] */ |
| #define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_MASK 0x00000008 |
| #define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_SHIFT 3 |
| #define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_1FC0_XOR [02:02] */ |
| #define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_MASK 0x00000004 |
| #define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_SHIFT 2 |
| #define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_1FC0_XOR [01:01] */ |
| #define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_MASK 0x00000002 |
| #define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_SHIFT 1 |
| #define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_DEFAULT 0 |
| |
| /* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_1FC0_XOR [00:00] */ |
| #define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_MASK 0x00000001 |
| #define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_SHIFT 0 |
| |
| /*************************************************************************** |
| *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3 |
| ***************************************************************************/ |
| /* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK 0xff000000 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT 24 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK 0x00ff0000 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT 16 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK 0x0000ff00 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT 8 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK 0x000000ff |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT 0 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT 255 |
| |
| /*************************************************************************** |
| *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7 |
| ***************************************************************************/ |
| /* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK 0xff000000 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT 24 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK 0x00ff0000 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT 16 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK 0x0000ff00 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT 8 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK 0x000000ff |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT 0 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT 255 |
| |
| /*************************************************************************** |
| *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11 |
| ***************************************************************************/ |
| /* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK 0xff000000 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT 24 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK 0x00ff0000 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT 16 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK 0x0000ff00 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT 8 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK 0x000000ff |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT 0 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT 255 |
| |
| /*************************************************************************** |
| *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15 |
| ***************************************************************************/ |
| /* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK 0xff000000 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT 24 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK 0x00ff0000 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT 16 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK 0x0000ff00 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT 8 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK 0x000000ff |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT 0 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT 255 |
| |
| /*************************************************************************** |
| *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3 |
| ***************************************************************************/ |
| /* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK 0xff000000 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT 24 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK 0x00ff0000 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT 16 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK 0x0000ff00 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT 8 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK 0x000000ff |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT 0 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT 255 |
| |
| /*************************************************************************** |
| *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7 |
| ***************************************************************************/ |
| /* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK 0xff000000 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT 24 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK 0x00ff0000 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT 16 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK 0x0000ff00 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT 8 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK 0x000000ff |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT 0 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT 255 |
| |
| /*************************************************************************** |
| *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11 |
| ***************************************************************************/ |
| /* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK 0xff000000 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT 24 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK 0x00ff0000 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT 16 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK 0x0000ff00 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT 8 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK 0x000000ff |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT 0 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT 255 |
| |
| /*************************************************************************** |
| *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15 |
| ***************************************************************************/ |
| /* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK 0xff000000 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT 24 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK 0x00ff0000 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT 16 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK 0x0000ff00 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT 8 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK 0x000000ff |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT 0 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT 255 |
| |
| /*************************************************************************** |
| *ACC_CONTROL - Nand Flash Access Control |
| ***************************************************************************/ |
| /* NAND :: ACC_CONTROL :: RD_ECC_EN [31:31] */ |
| #define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_MASK 0x80000000 |
| #define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_SHIFT 31 |
| #define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL :: WR_ECC_EN [30:30] */ |
| #define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_MASK 0x40000000 |
| #define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_SHIFT 30 |
| #define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL :: RD_ECC_BLK0_EN [29:29] */ |
| #define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_MASK 0x20000000 |
| #define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_SHIFT 29 |
| |
| /* NAND :: ACC_CONTROL :: FAST_PGM_RDIN [28:28] */ |
| #define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_MASK 0x10000000 |
| #define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_SHIFT 28 |
| #define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL :: RD_ERASED_ECC_EN [27:27] */ |
| #define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_MASK 0x08000000 |
| #define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_SHIFT 27 |
| #define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_DEFAULT 0 |
| |
| /* NAND :: ACC_CONTROL :: PARTIAL_PAGE_EN [26:26] */ |
| #define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_MASK 0x04000000 |
| #define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_SHIFT 26 |
| #define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL :: WR_PREEMPT_EN [25:25] */ |
| #define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_MASK 0x02000000 |
| #define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_SHIFT 25 |
| #define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL :: PAGE_HIT_EN [24:24] */ |
| #define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_MASK 0x01000000 |
| #define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_SHIFT 24 |
| #define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL :: ECC_LEVEL_0 [23:20] */ |
| #define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_MASK 0x00f00000 |
| #define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_SHIFT 20 |
| #define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_DEFAULT 15 |
| |
| /* NAND :: ACC_CONTROL :: ECC_LEVEL [19:16] */ |
| #define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_MASK 0x000f0000 |
| #define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_SHIFT 16 |
| #define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_DEFAULT 15 |
| |
| /* NAND :: ACC_CONTROL :: reserved0 [15:15] */ |
| #define BCHP_NAND_ACC_CONTROL_reserved0_MASK 0x00008000 |
| #define BCHP_NAND_ACC_CONTROL_reserved0_SHIFT 15 |
| |
| /* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K_0 [14:14] */ |
| #define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_MASK 0x00004000 |
| #define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_SHIFT 14 |
| #define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_DEFAULT 0 |
| |
| /* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE_0 [13:08] */ |
| #define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_MASK 0x00003f00 |
| #define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_SHIFT 8 |
| #define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_DEFAULT 16 |
| |
| /* NAND :: ACC_CONTROL :: reserved1 [07:07] */ |
| #define BCHP_NAND_ACC_CONTROL_reserved1_MASK 0x00000080 |
| #define BCHP_NAND_ACC_CONTROL_reserved1_SHIFT 7 |
| |
| /* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K [06:06] */ |
| #define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_MASK 0x00000040 |
| #define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_SHIFT 6 |
| #define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_DEFAULT 0 |
| |
| /* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE [05:00] */ |
| #define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_MASK 0x0000003f |
| #define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_SHIFT 0 |
| #define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_DEFAULT 16 |
| |
| /*************************************************************************** |
| *CONFIG - Nand Flash Config |
| ***************************************************************************/ |
| /* NAND :: CONFIG :: CONFIG_LOCK [31:31] */ |
| #define BCHP_NAND_CONFIG_CONFIG_LOCK_MASK 0x80000000 |
| #define BCHP_NAND_CONFIG_CONFIG_LOCK_SHIFT 31 |
| #define BCHP_NAND_CONFIG_CONFIG_LOCK_DEFAULT 0 |
| |
| /* NAND :: CONFIG :: BLOCK_SIZE [30:28] */ |
| #define BCHP_NAND_CONFIG_BLOCK_SIZE_MASK 0x70000000 |
| #define BCHP_NAND_CONFIG_BLOCK_SIZE_SHIFT 28 |
| #define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_2048KB 6 |
| #define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_1024KB 5 |
| #define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_512KB 3 |
| #define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_128KB 1 |
| #define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_16KB 0 |
| #define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_8KB 2 |
| #define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_256KB 4 |
| |
| /* NAND :: CONFIG :: DEVICE_SIZE [27:24] */ |
| #define BCHP_NAND_CONFIG_DEVICE_SIZE_MASK 0x0f000000 |
| #define BCHP_NAND_CONFIG_DEVICE_SIZE_SHIFT 24 |
| #define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4MB 0 |
| #define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8MB 1 |
| #define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16MB 2 |
| #define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32MB 3 |
| #define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64MB 4 |
| #define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128MB 5 |
| #define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_256MB 6 |
| #define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_512MB 7 |
| #define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_1GB 8 |
| #define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_2GB 9 |
| #define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4GB 10 |
| #define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8GB 11 |
| #define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16GB 12 |
| #define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32GB 13 |
| #define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64GB 14 |
| #define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128GB 15 |
| |
| /* NAND :: CONFIG :: DEVICE_WIDTH [23:23] */ |
| #define BCHP_NAND_CONFIG_DEVICE_WIDTH_MASK 0x00800000 |
| #define BCHP_NAND_CONFIG_DEVICE_WIDTH_SHIFT 23 |
| #define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_8 0 |
| #define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_16 1 |
| |
| /* NAND :: CONFIG :: reserved0 [22:22] */ |
| #define BCHP_NAND_CONFIG_reserved0_MASK 0x00400000 |
| #define BCHP_NAND_CONFIG_reserved0_SHIFT 22 |
| |
| /* NAND :: CONFIG :: PAGE_SIZE [21:20] */ |
| #define BCHP_NAND_CONFIG_PAGE_SIZE_MASK 0x00300000 |
| #define BCHP_NAND_CONFIG_PAGE_SIZE_SHIFT 20 |
| #define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_512 0 |
| #define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_2KB 1 |
| #define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_4KB 2 |
| #define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_8KB 3 |
| |
| /* NAND :: CONFIG :: reserved1 [19:19] */ |
| #define BCHP_NAND_CONFIG_reserved1_MASK 0x00080000 |
| #define BCHP_NAND_CONFIG_reserved1_SHIFT 19 |
| |
| /* NAND :: CONFIG :: FUL_ADR_BYTES [18:16] */ |
| #define BCHP_NAND_CONFIG_FUL_ADR_BYTES_MASK 0x00070000 |
| #define BCHP_NAND_CONFIG_FUL_ADR_BYTES_SHIFT 16 |
| |
| /* NAND :: CONFIG :: reserved2 [15:15] */ |
| #define BCHP_NAND_CONFIG_reserved2_MASK 0x00008000 |
| #define BCHP_NAND_CONFIG_reserved2_SHIFT 15 |
| |
| /* NAND :: CONFIG :: COL_ADR_BYTES [14:12] */ |
| #define BCHP_NAND_CONFIG_COL_ADR_BYTES_MASK 0x00007000 |
| #define BCHP_NAND_CONFIG_COL_ADR_BYTES_SHIFT 12 |
| |
| /* NAND :: CONFIG :: reserved3 [11:11] */ |
| #define BCHP_NAND_CONFIG_reserved3_MASK 0x00000800 |
| #define BCHP_NAND_CONFIG_reserved3_SHIFT 11 |
| |
| /* NAND :: CONFIG :: BLK_ADR_BYTES [10:08] */ |
| #define BCHP_NAND_CONFIG_BLK_ADR_BYTES_MASK 0x00000700 |
| #define BCHP_NAND_CONFIG_BLK_ADR_BYTES_SHIFT 8 |
| |
| /* NAND :: CONFIG :: reserved4 [07:00] */ |
| #define BCHP_NAND_CONFIG_reserved4_MASK 0x000000ff |
| #define BCHP_NAND_CONFIG_reserved4_SHIFT 0 |
| |
| /*************************************************************************** |
| *TIMING_1 - Nand Flash Timing Parameters 1 |
| ***************************************************************************/ |
| /* NAND :: TIMING_1 :: tWP [31:28] */ |
| #define BCHP_NAND_TIMING_1_tWP_MASK 0xf0000000 |
| #define BCHP_NAND_TIMING_1_tWP_SHIFT 28 |
| #define BCHP_NAND_TIMING_1_tWP_DEFAULT 6 |
| |
| /* NAND :: TIMING_1 :: tWH [27:24] */ |
| #define BCHP_NAND_TIMING_1_tWH_MASK 0x0f000000 |
| #define BCHP_NAND_TIMING_1_tWH_SHIFT 24 |
| #define BCHP_NAND_TIMING_1_tWH_DEFAULT 5 |
| |
| /* NAND :: TIMING_1 :: tRP [23:20] */ |
| #define BCHP_NAND_TIMING_1_tRP_MASK 0x00f00000 |
| #define BCHP_NAND_TIMING_1_tRP_SHIFT 20 |
| #define BCHP_NAND_TIMING_1_tRP_DEFAULT 7 |
| |
| /* NAND :: TIMING_1 :: tREH [19:16] */ |
| #define BCHP_NAND_TIMING_1_tREH_MASK 0x000f0000 |
| #define BCHP_NAND_TIMING_1_tREH_SHIFT 16 |
| #define BCHP_NAND_TIMING_1_tREH_DEFAULT 4 |
| |
| /* NAND :: TIMING_1 :: tCS [15:12] */ |
| #define BCHP_NAND_TIMING_1_tCS_MASK 0x0000f000 |
| #define BCHP_NAND_TIMING_1_tCS_SHIFT 12 |
| #define BCHP_NAND_TIMING_1_tCS_DEFAULT 8 |
| |
| /* NAND :: TIMING_1 :: tCLH [11:08] */ |
| #define BCHP_NAND_TIMING_1_tCLH_MASK 0x00000f00 |
| #define BCHP_NAND_TIMING_1_tCLH_SHIFT 8 |
| #define BCHP_NAND_TIMING_1_tCLH_DEFAULT 4 |
| |
| /* NAND :: TIMING_1 :: tALH [07:04] */ |
| #define BCHP_NAND_TIMING_1_tALH_MASK 0x000000f0 |
| #define BCHP_NAND_TIMING_1_tALH_SHIFT 4 |
| #define BCHP_NAND_TIMING_1_tALH_DEFAULT 5 |
| |
| /* NAND :: TIMING_1 :: tADL [03:00] */ |
| #define BCHP_NAND_TIMING_1_tADL_MASK 0x0000000f |
| #define BCHP_NAND_TIMING_1_tADL_SHIFT 0 |
| #define BCHP_NAND_TIMING_1_tADL_DEFAULT 11 |
| |
| /*************************************************************************** |
| *TIMING_2 - Nand Flash Timing Parameters 2 |
| ***************************************************************************/ |
| /* NAND :: TIMING_2 :: CLK_SELECT [31:31] */ |
| #define BCHP_NAND_TIMING_2_CLK_SELECT_MASK 0x80000000 |
| #define BCHP_NAND_TIMING_2_CLK_SELECT_SHIFT 31 |
| #define BCHP_NAND_TIMING_2_CLK_SELECT_DEFAULT 0 |
| #define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_108 0 |
| #define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_216 1 |
| |
| /* NAND :: TIMING_2 :: reserved0 [30:13] */ |
| #define BCHP_NAND_TIMING_2_reserved0_MASK 0x7fffe000 |
| #define BCHP_NAND_TIMING_2_reserved0_SHIFT 13 |
| |
| /* NAND :: TIMING_2 :: tWB [12:09] */ |
| #define BCHP_NAND_TIMING_2_tWB_MASK 0x00001e00 |
| #define BCHP_NAND_TIMING_2_tWB_SHIFT 9 |
| #define BCHP_NAND_TIMING_2_tWB_DEFAULT 15 |
| |
| /* NAND :: TIMING_2 :: tWHR [08:04] */ |
| #define BCHP_NAND_TIMING_2_tWHR_MASK 0x000001f0 |
| #define BCHP_NAND_TIMING_2_tWHR_SHIFT 4 |
| #define BCHP_NAND_TIMING_2_tWHR_DEFAULT 9 |
| |
| /* NAND :: TIMING_2 :: tREAD [03:00] */ |
| #define BCHP_NAND_TIMING_2_tREAD_MASK 0x0000000f |
| #define BCHP_NAND_TIMING_2_tREAD_SHIFT 0 |
| #define BCHP_NAND_TIMING_2_tREAD_DEFAULT 6 |
| |
| /*************************************************************************** |
| *SEMAPHORE - Semaphore |
| ***************************************************************************/ |
| /* NAND :: SEMAPHORE :: reserved0 [31:08] */ |
| #define BCHP_NAND_SEMAPHORE_reserved0_MASK 0xffffff00 |
| #define BCHP_NAND_SEMAPHORE_reserved0_SHIFT 8 |
| |
| /* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */ |
| #define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT 0 |
| #define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT 0 |
| |
| /*************************************************************************** |
| *FLASH_DEVICE_ID - Nand Flash Device ID |
| ***************************************************************************/ |
| /* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */ |
| #define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK 0xff000000 |
| #define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT 24 |
| |
| /* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */ |
| #define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK 0x00ff0000 |
| #define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT 16 |
| |
| /* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */ |
| #define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK 0x0000ff00 |
| #define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT 8 |
| |
| /* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */ |
| #define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK 0x000000ff |
| #define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT 0 |
| |
| /*************************************************************************** |
| *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID |
| ***************************************************************************/ |
| /* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */ |
| #define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK 0xff000000 |
| #define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT 24 |
| |
| /* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */ |
| #define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK 0x00ff0000 |
| #define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT 16 |
| |
| /* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */ |
| #define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK 0x0000ff00 |
| #define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT 8 |
| |
| /* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */ |
| #define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK 0x000000ff |
| #define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT 0 |
| |
| /*************************************************************************** |
| *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status |
| ***************************************************************************/ |
| /* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */ |
| #define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK 0xffffff00 |
| #define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT 8 |
| |
| /* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */ |
| #define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK 0x000000ff |
| #define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT 0 |
| #define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *INTFC_STATUS - Nand Flash Interface Status |
| ***************************************************************************/ |
| /* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */ |
| #define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK 0x80000000 |
| #define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT 31 |
| |
| /* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */ |
| #define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK 0x40000000 |
| #define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT 30 |
| |
| /* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */ |
| #define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK 0x20000000 |
| #define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT 29 |
| |
| /* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */ |
| #define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK 0x10000000 |
| #define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT 28 |
| |
| /* NAND :: INTFC_STATUS :: ERASED [27:27] */ |
| #define BCHP_NAND_INTFC_STATUS_ERASED_MASK 0x08000000 |
| #define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT 27 |
| |
| /* NAND :: INTFC_STATUS :: reserved0 [26:08] */ |
| #define BCHP_NAND_INTFC_STATUS_reserved0_MASK 0x07ffff00 |
| #define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT 8 |
| |
| /* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */ |
| #define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK 0x000000ff |
| #define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT 0 |
| #define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address |
| ***************************************************************************/ |
| /* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */ |
| #define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK 0xfff80000 |
| #define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT 19 |
| |
| /* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */ |
| #define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK 0x00070000 |
| #define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT 16 |
| #define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT 0 |
| |
| /* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */ |
| #define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff |
| #define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT 0 |
| #define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *ECC_CORR_ADDR - ECC Correctable Error Address |
| ***************************************************************************/ |
| /* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */ |
| #define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK 0xffffffff |
| #define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT 0 |
| #define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address |
| ***************************************************************************/ |
| /* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */ |
| #define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK 0xfff80000 |
| #define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT 19 |
| |
| /* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */ |
| #define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK 0x00070000 |
| #define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT 16 |
| #define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT 0 |
| |
| /* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */ |
| #define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff |
| #define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT 0 |
| #define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *ECC_UNC_ADDR - ECC Uncorrectable Error Address |
| ***************************************************************************/ |
| /* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */ |
| #define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK 0xffffffff |
| #define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT 0 |
| #define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *READ_ERROR_COUNT - Read Error Count |
| ***************************************************************************/ |
| /* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */ |
| #define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK 0xffffffff |
| #define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT 0 |
| #define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT 0 |
| |
| /*************************************************************************** |
| *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold |
| ***************************************************************************/ |
| /* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:05] */ |
| #define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK 0xffffffe0 |
| #define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT 5 |
| |
| /* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD [04:00] */ |
| #define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_MASK 0x0000001f |
| #define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_SHIFT 0 |
| #define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_DEFAULT 1 |
| |
| /*************************************************************************** |
| *ONFI_STATUS - ONFI Status |
| ***************************************************************************/ |
| /* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */ |
| #define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK 0xf0000000 |
| #define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT 28 |
| #define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT 0 |
| |
| /* NAND :: ONFI_STATUS :: reserved0 [27:06] */ |
| #define BCHP_NAND_ONFI_STATUS_reserved0_MASK 0x0fffffc0 |
| #define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT 6 |
| |
| /* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */ |
| #define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK 0x00000020 |
| #define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT 5 |
| |
| /* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */ |
| #define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK 0x00000010 |
| #define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT 4 |
| |
| /* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */ |
| #define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK 0x00000008 |
| #define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT 3 |
| |
| /* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */ |
| #define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK 0x00000004 |
| #define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT 2 |
| |
| /* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */ |
| #define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK 0x00000002 |
| #define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT 1 |
| |
| /* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */ |
| #define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK 0x00000001 |
| #define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT 0 |
| |
| /*************************************************************************** |
| *ONFI_DEBUG_DATA - ONFI Debug Data |
| ***************************************************************************/ |
| /* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */ |
| #define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK 0xffffffff |
| #define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT 0 |
| |
| /*************************************************************************** |
| *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address |
| ***************************************************************************/ |
| /* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */ |
| #define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK 0xfff80000 |
| #define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT 19 |
| |
| /* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */ |
| #define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK 0x00070000 |
| #define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT 16 |
| #define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT 0 |
| |
| /* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */ |
| #define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff |
| #define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT 0 |
| #define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *FLASH_READ_ADDR - Flash Read Data Address |
| ***************************************************************************/ |
| /* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */ |
| #define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK 0xffffffff |
| #define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT 0 |
| #define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address |
| ***************************************************************************/ |
| /* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */ |
| #define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK 0xfff80000 |
| #define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT 19 |
| |
| /* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */ |
| #define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK 0x00070000 |
| #define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT 16 |
| #define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT 0 |
| |
| /* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */ |
| #define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff |
| #define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT 0 |
| #define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PROGRAM_PAGE_ADDR - Page Program Address |
| ***************************************************************************/ |
| /* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */ |
| #define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK 0xffffffff |
| #define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT 0 |
| #define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *COPY_BACK_EXT_ADDR - Copy Back Extended Address |
| ***************************************************************************/ |
| /* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */ |
| #define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK 0xfff80000 |
| #define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT 19 |
| |
| /* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */ |
| #define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK 0x00070000 |
| #define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT 16 |
| #define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT 0 |
| |
| /* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */ |
| #define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff |
| #define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT 0 |
| #define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *COPY_BACK_ADDR - Copy Back Address |
| ***************************************************************************/ |
| /* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */ |
| #define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK 0xffffffff |
| #define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT 0 |
| #define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address |
| ***************************************************************************/ |
| /* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */ |
| #define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK 0xfff80000 |
| #define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT 19 |
| |
| /* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */ |
| #define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK 0x00070000 |
| #define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT 16 |
| #define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT 0 |
| |
| /* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */ |
| #define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff |
| #define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT 0 |
| #define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *BLOCK_ERASE_ADDR - Block Erase Address |
| ***************************************************************************/ |
| /* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */ |
| #define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK 0xffffffff |
| #define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT 0 |
| #define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address |
| ***************************************************************************/ |
| /* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */ |
| #define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK 0xfff80000 |
| #define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT 19 |
| |
| /* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */ |
| #define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK 0x00070000 |
| #define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT 16 |
| #define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT 0 |
| |
| /* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */ |
| #define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff |
| #define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT 0 |
| #define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *INV_READ_ADDR - Flash Invalid Data Address |
| ***************************************************************************/ |
| /* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */ |
| #define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK 0xffffffff |
| #define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT 0 |
| #define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b |
| ***************************************************************************/ |
| /* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */ |
| #define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK 0xffffffff |
| #define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT 0 |
| #define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT 0 |
| |
| /*************************************************************************** |
| *ACC_CONTROL_CS1 - Nand Flash Access Control |
| ***************************************************************************/ |
| /* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */ |
| #define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK 0x80000000 |
| #define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT 31 |
| #define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */ |
| #define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK 0x40000000 |
| #define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT 30 |
| #define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS1 :: reserved0 [29:29] */ |
| #define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK 0x20000000 |
| #define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT 29 |
| |
| /* NAND :: ACC_CONTROL_CS1 :: FAST_PGM_RDIN [28:28] */ |
| #define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_MASK 0x10000000 |
| #define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_SHIFT 28 |
| #define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */ |
| #define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK 0x08000000 |
| #define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT 27 |
| #define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT 0 |
| |
| /* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */ |
| #define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK 0x04000000 |
| #define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT 26 |
| #define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */ |
| #define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK 0x02000000 |
| #define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT 25 |
| #define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */ |
| #define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK 0x01000000 |
| #define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT 24 |
| #define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS1 :: reserved1 [23:20] */ |
| #define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK 0x00f00000 |
| #define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT 20 |
| |
| /* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [19:16] */ |
| #define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK 0x000f0000 |
| #define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT 16 |
| #define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT 15 |
| |
| /* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:07] */ |
| #define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK 0x0000ff80 |
| #define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT 7 |
| |
| /* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [06:06] */ |
| #define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK 0x00000040 |
| #define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT 6 |
| #define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT 0 |
| |
| /* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [05:00] */ |
| #define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK 0x0000003f |
| #define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT 0 |
| #define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT 16 |
| |
| /*************************************************************************** |
| *CONFIG_CS1 - Nand Flash Config |
| ***************************************************************************/ |
| /* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */ |
| #define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK 0x80000000 |
| #define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT 31 |
| #define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT 0 |
| |
| /* NAND :: CONFIG_CS1 :: BLOCK_SIZE [30:28] */ |
| #define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_MASK 0x70000000 |
| #define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_SHIFT 28 |
| #define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_2048KB 6 |
| #define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_1024KB 5 |
| #define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_512KB 3 |
| #define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_128KB 1 |
| #define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_16KB 0 |
| #define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_8KB 2 |
| #define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_256KB 4 |
| |
| /* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */ |
| #define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK 0x0f000000 |
| #define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT 24 |
| #define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB 0 |
| #define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB 1 |
| #define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB 2 |
| #define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB 3 |
| #define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB 4 |
| #define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB 5 |
| #define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB 6 |
| #define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB 7 |
| #define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB 8 |
| #define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB 9 |
| #define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB 10 |
| #define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB 11 |
| #define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB 12 |
| #define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB 13 |
| #define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB 14 |
| #define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB 15 |
| |
| /* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */ |
| #define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK 0x00800000 |
| #define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT 23 |
| #define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8 0 |
| #define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16 1 |
| |
| /* NAND :: CONFIG_CS1 :: reserved0 [22:22] */ |
| #define BCHP_NAND_CONFIG_CS1_reserved0_MASK 0x00400000 |
| #define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT 22 |
| |
| /* NAND :: CONFIG_CS1 :: PAGE_SIZE [21:20] */ |
| #define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_MASK 0x00300000 |
| #define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_SHIFT 20 |
| #define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_512 0 |
| #define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_2KB 1 |
| #define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_4KB 2 |
| #define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_8KB 3 |
| |
| /* NAND :: CONFIG_CS1 :: reserved1 [19:19] */ |
| #define BCHP_NAND_CONFIG_CS1_reserved1_MASK 0x00080000 |
| #define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT 19 |
| |
| /* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */ |
| #define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK 0x00070000 |
| #define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT 16 |
| |
| /* NAND :: CONFIG_CS1 :: reserved2 [15:15] */ |
| #define BCHP_NAND_CONFIG_CS1_reserved2_MASK 0x00008000 |
| #define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT 15 |
| |
| /* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */ |
| #define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK 0x00007000 |
| #define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT 12 |
| |
| /* NAND :: CONFIG_CS1 :: reserved3 [11:11] */ |
| #define BCHP_NAND_CONFIG_CS1_reserved3_MASK 0x00000800 |
| #define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT 11 |
| |
| /* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */ |
| #define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK 0x00000700 |
| #define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT 8 |
| |
| /* NAND :: CONFIG_CS1 :: reserved4 [07:00] */ |
| #define BCHP_NAND_CONFIG_CS1_reserved4_MASK 0x000000ff |
| #define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT 0 |
| |
| /*************************************************************************** |
| *TIMING_1_CS1 - Nand Flash Timing Parameters 1 |
| ***************************************************************************/ |
| /* NAND :: TIMING_1_CS1 :: tWP [31:28] */ |
| #define BCHP_NAND_TIMING_1_CS1_tWP_MASK 0xf0000000 |
| #define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT 28 |
| #define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT 6 |
| |
| /* NAND :: TIMING_1_CS1 :: tWH [27:24] */ |
| #define BCHP_NAND_TIMING_1_CS1_tWH_MASK 0x0f000000 |
| #define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT 24 |
| #define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT 5 |
| |
| /* NAND :: TIMING_1_CS1 :: tRP [23:20] */ |
| #define BCHP_NAND_TIMING_1_CS1_tRP_MASK 0x00f00000 |
| #define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT 20 |
| #define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT 7 |
| |
| /* NAND :: TIMING_1_CS1 :: tREH [19:16] */ |
| #define BCHP_NAND_TIMING_1_CS1_tREH_MASK 0x000f0000 |
| #define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT 16 |
| #define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT 4 |
| |
| /* NAND :: TIMING_1_CS1 :: tCS [15:12] */ |
| #define BCHP_NAND_TIMING_1_CS1_tCS_MASK 0x0000f000 |
| #define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT 12 |
| #define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT 8 |
| |
| /* NAND :: TIMING_1_CS1 :: tCLH [11:08] */ |
| #define BCHP_NAND_TIMING_1_CS1_tCLH_MASK 0x00000f00 |
| #define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT 8 |
| #define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT 4 |
| |
| /* NAND :: TIMING_1_CS1 :: tALH [07:04] */ |
| #define BCHP_NAND_TIMING_1_CS1_tALH_MASK 0x000000f0 |
| #define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT 4 |
| #define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT 5 |
| |
| /* NAND :: TIMING_1_CS1 :: tADL [03:00] */ |
| #define BCHP_NAND_TIMING_1_CS1_tADL_MASK 0x0000000f |
| #define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT 0 |
| #define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT 11 |
| |
| /*************************************************************************** |
| *TIMING_2_CS1 - Nand Flash Timing Parameters 2 |
| ***************************************************************************/ |
| /* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */ |
| #define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK 0x80000000 |
| #define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT 31 |
| #define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT 0 |
| #define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108 0 |
| #define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216 1 |
| |
| /* NAND :: TIMING_2_CS1 :: reserved0 [30:13] */ |
| #define BCHP_NAND_TIMING_2_CS1_reserved0_MASK 0x7fffe000 |
| #define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT 13 |
| |
| /* NAND :: TIMING_2_CS1 :: tWB [12:09] */ |
| #define BCHP_NAND_TIMING_2_CS1_tWB_MASK 0x00001e00 |
| #define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT 9 |
| #define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT 15 |
| |
| /* NAND :: TIMING_2_CS1 :: tWHR [08:04] */ |
| #define BCHP_NAND_TIMING_2_CS1_tWHR_MASK 0x000001f0 |
| #define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT 4 |
| #define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT 9 |
| |
| /* NAND :: TIMING_2_CS1 :: tREAD [03:00] */ |
| #define BCHP_NAND_TIMING_2_CS1_tREAD_MASK 0x0000000f |
| #define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT 0 |
| #define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT 6 |
| |
| /*************************************************************************** |
| *ACC_CONTROL_CS2 - Nand Flash Access Control |
| ***************************************************************************/ |
| /* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */ |
| #define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK 0x80000000 |
| #define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT 31 |
| #define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */ |
| #define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK 0x40000000 |
| #define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT 30 |
| #define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS2 :: reserved0 [29:29] */ |
| #define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK 0x20000000 |
| #define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT 29 |
| |
| /* NAND :: ACC_CONTROL_CS2 :: FAST_PGM_RDIN [28:28] */ |
| #define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_MASK 0x10000000 |
| #define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_SHIFT 28 |
| #define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */ |
| #define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK 0x08000000 |
| #define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT 27 |
| #define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT 0 |
| |
| /* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */ |
| #define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK 0x04000000 |
| #define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT 26 |
| #define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */ |
| #define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK 0x02000000 |
| #define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT 25 |
| #define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */ |
| #define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK 0x01000000 |
| #define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT 24 |
| #define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS2 :: reserved1 [23:20] */ |
| #define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK 0x00f00000 |
| #define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT 20 |
| |
| /* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [19:16] */ |
| #define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK 0x000f0000 |
| #define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT 16 |
| #define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT 15 |
| |
| /* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:07] */ |
| #define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK 0x0000ff80 |
| #define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT 7 |
| |
| /* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [06:06] */ |
| #define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK 0x00000040 |
| #define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT 6 |
| #define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT 0 |
| |
| /* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [05:00] */ |
| #define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK 0x0000003f |
| #define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT 0 |
| #define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT 16 |
| |
| /*************************************************************************** |
| *CONFIG_CS2 - Nand Flash Config |
| ***************************************************************************/ |
| /* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */ |
| #define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK 0x80000000 |
| #define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT 31 |
| #define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT 0 |
| |
| /* NAND :: CONFIG_CS2 :: BLOCK_SIZE [30:28] */ |
| #define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_MASK 0x70000000 |
| #define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_SHIFT 28 |
| #define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_2048KB 6 |
| #define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_1024KB 5 |
| #define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_512KB 3 |
| #define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_128KB 1 |
| #define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_16KB 0 |
| #define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_8KB 2 |
| #define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_256KB 4 |
| |
| /* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */ |
| #define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK 0x0f000000 |
| #define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT 24 |
| #define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB 0 |
| #define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB 1 |
| #define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB 2 |
| #define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB 3 |
| #define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB 4 |
| #define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB 5 |
| #define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB 6 |
| #define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB 7 |
| #define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB 8 |
| #define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB 9 |
| #define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB 10 |
| #define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB 11 |
| #define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB 12 |
| #define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB 13 |
| #define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB 14 |
| #define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB 15 |
| |
| /* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */ |
| #define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK 0x00800000 |
| #define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT 23 |
| #define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8 0 |
| #define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16 1 |
| |
| /* NAND :: CONFIG_CS2 :: reserved0 [22:22] */ |
| #define BCHP_NAND_CONFIG_CS2_reserved0_MASK 0x00400000 |
| #define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT 22 |
| |
| /* NAND :: CONFIG_CS2 :: PAGE_SIZE [21:20] */ |
| #define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_MASK 0x00300000 |
| #define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_SHIFT 20 |
| #define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_512 0 |
| #define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_2KB 1 |
| #define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_4KB 2 |
| #define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_8KB 3 |
| |
| /* NAND :: CONFIG_CS2 :: reserved1 [19:19] */ |
| #define BCHP_NAND_CONFIG_CS2_reserved1_MASK 0x00080000 |
| #define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT 19 |
| |
| /* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */ |
| #define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK 0x00070000 |
| #define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT 16 |
| |
| /* NAND :: CONFIG_CS2 :: reserved2 [15:15] */ |
| #define BCHP_NAND_CONFIG_CS2_reserved2_MASK 0x00008000 |
| #define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT 15 |
| |
| /* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */ |
| #define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK 0x00007000 |
| #define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT 12 |
| |
| /* NAND :: CONFIG_CS2 :: reserved3 [11:11] */ |
| #define BCHP_NAND_CONFIG_CS2_reserved3_MASK 0x00000800 |
| #define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT 11 |
| |
| /* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */ |
| #define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK 0x00000700 |
| #define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT 8 |
| |
| /* NAND :: CONFIG_CS2 :: reserved4 [07:00] */ |
| #define BCHP_NAND_CONFIG_CS2_reserved4_MASK 0x000000ff |
| #define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT 0 |
| |
| /*************************************************************************** |
| *TIMING_1_CS2 - Nand Flash Timing Parameters 1 |
| ***************************************************************************/ |
| /* NAND :: TIMING_1_CS2 :: tWP [31:28] */ |
| #define BCHP_NAND_TIMING_1_CS2_tWP_MASK 0xf0000000 |
| #define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT 28 |
| #define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT 6 |
| |
| /* NAND :: TIMING_1_CS2 :: tWH [27:24] */ |
| #define BCHP_NAND_TIMING_1_CS2_tWH_MASK 0x0f000000 |
| #define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT 24 |
| #define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT 5 |
| |
| /* NAND :: TIMING_1_CS2 :: tRP [23:20] */ |
| #define BCHP_NAND_TIMING_1_CS2_tRP_MASK 0x00f00000 |
| #define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT 20 |
| #define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT 7 |
| |
| /* NAND :: TIMING_1_CS2 :: tREH [19:16] */ |
| #define BCHP_NAND_TIMING_1_CS2_tREH_MASK 0x000f0000 |
| #define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT 16 |
| #define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT 4 |
| |
| /* NAND :: TIMING_1_CS2 :: tCS [15:12] */ |
| #define BCHP_NAND_TIMING_1_CS2_tCS_MASK 0x0000f000 |
| #define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT 12 |
| #define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT 8 |
| |
| /* NAND :: TIMING_1_CS2 :: tCLH [11:08] */ |
| #define BCHP_NAND_TIMING_1_CS2_tCLH_MASK 0x00000f00 |
| #define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT 8 |
| #define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT 4 |
| |
| /* NAND :: TIMING_1_CS2 :: tALH [07:04] */ |
| #define BCHP_NAND_TIMING_1_CS2_tALH_MASK 0x000000f0 |
| #define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT 4 |
| #define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT 5 |
| |
| /* NAND :: TIMING_1_CS2 :: tADL [03:00] */ |
| #define BCHP_NAND_TIMING_1_CS2_tADL_MASK 0x0000000f |
| #define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT 0 |
| #define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT 11 |
| |
| /*************************************************************************** |
| *TIMING_2_CS2 - Nand Flash Timing Parameters 2 |
| ***************************************************************************/ |
| /* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */ |
| #define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK 0x80000000 |
| #define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT 31 |
| #define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT 0 |
| #define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108 0 |
| #define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216 1 |
| |
| /* NAND :: TIMING_2_CS2 :: reserved0 [30:13] */ |
| #define BCHP_NAND_TIMING_2_CS2_reserved0_MASK 0x7fffe000 |
| #define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT 13 |
| |
| /* NAND :: TIMING_2_CS2 :: tWB [12:09] */ |
| #define BCHP_NAND_TIMING_2_CS2_tWB_MASK 0x00001e00 |
| #define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT 9 |
| #define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT 15 |
| |
| /* NAND :: TIMING_2_CS2 :: tWHR [08:04] */ |
| #define BCHP_NAND_TIMING_2_CS2_tWHR_MASK 0x000001f0 |
| #define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT 4 |
| #define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT 9 |
| |
| /* NAND :: TIMING_2_CS2 :: tREAD [03:00] */ |
| #define BCHP_NAND_TIMING_2_CS2_tREAD_MASK 0x0000000f |
| #define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT 0 |
| #define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT 6 |
| |
| /*************************************************************************** |
| *ACC_CONTROL_CS3 - Nand Flash Access Control |
| ***************************************************************************/ |
| /* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */ |
| #define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK 0x80000000 |
| #define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT 31 |
| #define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */ |
| #define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK 0x40000000 |
| #define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT 30 |
| #define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS3 :: reserved0 [29:29] */ |
| #define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK 0x20000000 |
| #define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT 29 |
| |
| /* NAND :: ACC_CONTROL_CS3 :: FAST_PGM_RDIN [28:28] */ |
| #define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_MASK 0x10000000 |
| #define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_SHIFT 28 |
| #define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */ |
| #define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK 0x08000000 |
| #define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT 27 |
| #define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT 0 |
| |
| /* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */ |
| #define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK 0x04000000 |
| #define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT 26 |
| #define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */ |
| #define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK 0x02000000 |
| #define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT 25 |
| #define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */ |
| #define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK 0x01000000 |
| #define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT 24 |
| #define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS3 :: reserved1 [23:20] */ |
| #define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK 0x00f00000 |
| #define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT 20 |
| |
| /* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [19:16] */ |
| #define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK 0x000f0000 |
| #define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT 16 |
| #define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT 15 |
| |
| /* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:07] */ |
| #define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK 0x0000ff80 |
| #define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT 7 |
| |
| /* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [06:06] */ |
| #define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK 0x00000040 |
| #define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT 6 |
| #define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT 0 |
| |
| /* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [05:00] */ |
| #define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK 0x0000003f |
| #define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT 0 |
| #define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT 16 |
| |
| /*************************************************************************** |
| *CONFIG_CS3 - Nand Flash Config |
| ***************************************************************************/ |
| /* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */ |
| #define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK 0x80000000 |
| #define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT 31 |
| #define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT 0 |
| |
| /* NAND :: CONFIG_CS3 :: BLOCK_SIZE [30:28] */ |
| #define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_MASK 0x70000000 |
| #define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_SHIFT 28 |
| #define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_2048KB 6 |
| #define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_1024KB 5 |
| #define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_512KB 3 |
| #define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_128KB 1 |
| #define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_16KB 0 |
| #define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_8KB 2 |
| #define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_256KB 4 |
| |
| /* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */ |
| #define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK 0x0f000000 |
| #define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT 24 |
| #define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB 0 |
| #define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB 1 |
| #define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB 2 |
| #define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB 3 |
| #define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB 4 |
| #define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB 5 |
| #define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB 6 |
| #define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB 7 |
| #define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB 8 |
| #define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB 9 |
| #define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB 10 |
| #define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB 11 |
| #define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB 12 |
| #define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB 13 |
| #define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB 14 |
| #define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB 15 |
| |
| /* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */ |
| #define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK 0x00800000 |
| #define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT 23 |
| #define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8 0 |
| #define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16 1 |
| |
| /* NAND :: CONFIG_CS3 :: reserved0 [22:22] */ |
| #define BCHP_NAND_CONFIG_CS3_reserved0_MASK 0x00400000 |
| #define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT 22 |
| |
| /* NAND :: CONFIG_CS3 :: PAGE_SIZE [21:20] */ |
| #define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_MASK 0x00300000 |
| #define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_SHIFT 20 |
| #define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_512 0 |
| #define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_2KB 1 |
| #define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_4KB 2 |
| #define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_8KB 3 |
| |
| /* NAND :: CONFIG_CS3 :: reserved1 [19:19] */ |
| #define BCHP_NAND_CONFIG_CS3_reserved1_MASK 0x00080000 |
| #define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT 19 |
| |
| /* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */ |
| #define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK 0x00070000 |
| #define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT 16 |
| |
| /* NAND :: CONFIG_CS3 :: reserved2 [15:15] */ |
| #define BCHP_NAND_CONFIG_CS3_reserved2_MASK 0x00008000 |
| #define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT 15 |
| |
| /* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */ |
| #define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK 0x00007000 |
| #define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT 12 |
| |
| /* NAND :: CONFIG_CS3 :: reserved3 [11:11] */ |
| #define BCHP_NAND_CONFIG_CS3_reserved3_MASK 0x00000800 |
| #define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT 11 |
| |
| /* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */ |
| #define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK 0x00000700 |
| #define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT 8 |
| |
| /* NAND :: CONFIG_CS3 :: reserved4 [07:00] */ |
| #define BCHP_NAND_CONFIG_CS3_reserved4_MASK 0x000000ff |
| #define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT 0 |
| |
| /*************************************************************************** |
| *TIMING_1_CS3 - Nand Flash Timing Parameters 1 |
| ***************************************************************************/ |
| /* NAND :: TIMING_1_CS3 :: tWP [31:28] */ |
| #define BCHP_NAND_TIMING_1_CS3_tWP_MASK 0xf0000000 |
| #define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT 28 |
| #define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT 6 |
| |
| /* NAND :: TIMING_1_CS3 :: tWH [27:24] */ |
| #define BCHP_NAND_TIMING_1_CS3_tWH_MASK 0x0f000000 |
| #define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT 24 |
| #define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT 5 |
| |
| /* NAND :: TIMING_1_CS3 :: tRP [23:20] */ |
| #define BCHP_NAND_TIMING_1_CS3_tRP_MASK 0x00f00000 |
| #define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT 20 |
| #define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT 7 |
| |
| /* NAND :: TIMING_1_CS3 :: tREH [19:16] */ |
| #define BCHP_NAND_TIMING_1_CS3_tREH_MASK 0x000f0000 |
| #define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT 16 |
| #define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT 4 |
| |
| /* NAND :: TIMING_1_CS3 :: tCS [15:12] */ |
| #define BCHP_NAND_TIMING_1_CS3_tCS_MASK 0x0000f000 |
| #define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT 12 |
| #define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT 8 |
| |
| /* NAND :: TIMING_1_CS3 :: tCLH [11:08] */ |
| #define BCHP_NAND_TIMING_1_CS3_tCLH_MASK 0x00000f00 |
| #define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT 8 |
| #define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT 4 |
| |
| /* NAND :: TIMING_1_CS3 :: tALH [07:04] */ |
| #define BCHP_NAND_TIMING_1_CS3_tALH_MASK 0x000000f0 |
| #define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT 4 |
| #define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT 5 |
| |
| /* NAND :: TIMING_1_CS3 :: tADL [03:00] */ |
| #define BCHP_NAND_TIMING_1_CS3_tADL_MASK 0x0000000f |
| #define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT 0 |
| #define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT 11 |
| |
| /*************************************************************************** |
| *TIMING_2_CS3 - Nand Flash Timing Parameters 2 |
| ***************************************************************************/ |
| /* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */ |
| #define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK 0x80000000 |
| #define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT 31 |
| #define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT 0 |
| #define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108 0 |
| #define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216 1 |
| |
| /* NAND :: TIMING_2_CS3 :: reserved0 [30:13] */ |
| #define BCHP_NAND_TIMING_2_CS3_reserved0_MASK 0x7fffe000 |
| #define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT 13 |
| |
| /* NAND :: TIMING_2_CS3 :: tWB [12:09] */ |
| #define BCHP_NAND_TIMING_2_CS3_tWB_MASK 0x00001e00 |
| #define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT 9 |
| #define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT 15 |
| |
| /* NAND :: TIMING_2_CS3 :: tWHR [08:04] */ |
| #define BCHP_NAND_TIMING_2_CS3_tWHR_MASK 0x000001f0 |
| #define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT 4 |
| #define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT 9 |
| |
| /* NAND :: TIMING_2_CS3 :: tREAD [03:00] */ |
| #define BCHP_NAND_TIMING_2_CS3_tREAD_MASK 0x0000000f |
| #define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT 0 |
| #define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT 6 |
| |
| /*************************************************************************** |
| *ACC_CONTROL_CS4 - Nand Flash Access Control |
| ***************************************************************************/ |
| /* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */ |
| #define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK 0x80000000 |
| #define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT 31 |
| #define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */ |
| #define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK 0x40000000 |
| #define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT 30 |
| #define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS4 :: reserved0 [29:29] */ |
| #define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK 0x20000000 |
| #define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT 29 |
| |
| /* NAND :: ACC_CONTROL_CS4 :: FAST_PGM_RDIN [28:28] */ |
| #define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_MASK 0x10000000 |
| #define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_SHIFT 28 |
| #define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */ |
| #define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK 0x08000000 |
| #define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT 27 |
| #define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT 0 |
| |
| /* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */ |
| #define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK 0x04000000 |
| #define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT 26 |
| #define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */ |
| #define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK 0x02000000 |
| #define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT 25 |
| #define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */ |
| #define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK 0x01000000 |
| #define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT 24 |
| #define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS4 :: reserved1 [23:20] */ |
| #define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK 0x00f00000 |
| #define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT 20 |
| |
| /* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [19:16] */ |
| #define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK 0x000f0000 |
| #define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT 16 |
| #define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT 15 |
| |
| /* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:07] */ |
| #define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK 0x0000ff80 |
| #define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT 7 |
| |
| /* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [06:06] */ |
| #define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK 0x00000040 |
| #define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT 6 |
| #define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT 0 |
| |
| /* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [05:00] */ |
| #define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK 0x0000003f |
| #define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT 0 |
| #define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT 16 |
| |
| /*************************************************************************** |
| *CONFIG_CS4 - Nand Flash Config |
| ***************************************************************************/ |
| /* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */ |
| #define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK 0x80000000 |
| #define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT 31 |
| #define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT 0 |
| |
| /* NAND :: CONFIG_CS4 :: BLOCK_SIZE [30:28] */ |
| #define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_MASK 0x70000000 |
| #define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_SHIFT 28 |
| #define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_2048KB 6 |
| #define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_1024KB 5 |
| #define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_512KB 3 |
| #define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_128KB 1 |
| #define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_16KB 0 |
| #define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_8KB 2 |
| #define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_256KB 4 |
| |
| /* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */ |
| #define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK 0x0f000000 |
| #define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT 24 |
| #define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB 0 |
| #define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB 1 |
| #define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB 2 |
| #define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB 3 |
| #define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB 4 |
| #define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB 5 |
| #define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB 6 |
| #define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB 7 |
| #define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB 8 |
| #define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB 9 |
| #define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB 10 |
| #define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB 11 |
| #define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB 12 |
| #define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB 13 |
| #define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB 14 |
| #define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB 15 |
| |
| /* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */ |
| #define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK 0x00800000 |
| #define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT 23 |
| #define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8 0 |
| #define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16 1 |
| |
| /* NAND :: CONFIG_CS4 :: reserved0 [22:22] */ |
| #define BCHP_NAND_CONFIG_CS4_reserved0_MASK 0x00400000 |
| #define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT 22 |
| |
| /* NAND :: CONFIG_CS4 :: PAGE_SIZE [21:20] */ |
| #define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_MASK 0x00300000 |
| #define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_SHIFT 20 |
| #define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_512 0 |
| #define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_2KB 1 |
| #define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_4KB 2 |
| #define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_8KB 3 |
| |
| /* NAND :: CONFIG_CS4 :: reserved1 [19:19] */ |
| #define BCHP_NAND_CONFIG_CS4_reserved1_MASK 0x00080000 |
| #define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT 19 |
| |
| /* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */ |
| #define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK 0x00070000 |
| #define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT 16 |
| |
| /* NAND :: CONFIG_CS4 :: reserved2 [15:15] */ |
| #define BCHP_NAND_CONFIG_CS4_reserved2_MASK 0x00008000 |
| #define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT 15 |
| |
| /* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */ |
| #define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK 0x00007000 |
| #define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT 12 |
| |
| /* NAND :: CONFIG_CS4 :: reserved3 [11:11] */ |
| #define BCHP_NAND_CONFIG_CS4_reserved3_MASK 0x00000800 |
| #define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT 11 |
| |
| /* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */ |
| #define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK 0x00000700 |
| #define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT 8 |
| |
| /* NAND :: CONFIG_CS4 :: reserved4 [07:00] */ |
| #define BCHP_NAND_CONFIG_CS4_reserved4_MASK 0x000000ff |
| #define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT 0 |
| |
| /*************************************************************************** |
| *TIMING_1_CS4 - Nand Flash Timing Parameters 1 |
| ***************************************************************************/ |
| /* NAND :: TIMING_1_CS4 :: tWP [31:28] */ |
| #define BCHP_NAND_TIMING_1_CS4_tWP_MASK 0xf0000000 |
| #define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT 28 |
| #define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT 6 |
| |
| /* NAND :: TIMING_1_CS4 :: tWH [27:24] */ |
| #define BCHP_NAND_TIMING_1_CS4_tWH_MASK 0x0f000000 |
| #define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT 24 |
| #define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT 5 |
| |
| /* NAND :: TIMING_1_CS4 :: tRP [23:20] */ |
| #define BCHP_NAND_TIMING_1_CS4_tRP_MASK 0x00f00000 |
| #define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT 20 |
| #define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT 7 |
| |
| /* NAND :: TIMING_1_CS4 :: tREH [19:16] */ |
| #define BCHP_NAND_TIMING_1_CS4_tREH_MASK 0x000f0000 |
| #define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT 16 |
| #define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT 4 |
| |
| /* NAND :: TIMING_1_CS4 :: tCS [15:12] */ |
| #define BCHP_NAND_TIMING_1_CS4_tCS_MASK 0x0000f000 |
| #define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT 12 |
| #define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT 8 |
| |
| /* NAND :: TIMING_1_CS4 :: tCLH [11:08] */ |
| #define BCHP_NAND_TIMING_1_CS4_tCLH_MASK 0x00000f00 |
| #define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT 8 |
| #define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT 4 |
| |
| /* NAND :: TIMING_1_CS4 :: tALH [07:04] */ |
| #define BCHP_NAND_TIMING_1_CS4_tALH_MASK 0x000000f0 |
| #define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT 4 |
| #define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT 5 |
| |
| /* NAND :: TIMING_1_CS4 :: tADL [03:00] */ |
| #define BCHP_NAND_TIMING_1_CS4_tADL_MASK 0x0000000f |
| #define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT 0 |
| #define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT 11 |
| |
| /*************************************************************************** |
| *TIMING_2_CS4 - Nand Flash Timing Parameters 2 |
| ***************************************************************************/ |
| /* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */ |
| #define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK 0x80000000 |
| #define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT 31 |
| #define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT 0 |
| #define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108 0 |
| #define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216 1 |
| |
| /* NAND :: TIMING_2_CS4 :: reserved0 [30:13] */ |
| #define BCHP_NAND_TIMING_2_CS4_reserved0_MASK 0x7fffe000 |
| #define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT 13 |
| |
| /* NAND :: TIMING_2_CS4 :: tWB [12:09] */ |
| #define BCHP_NAND_TIMING_2_CS4_tWB_MASK 0x00001e00 |
| #define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT 9 |
| #define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT 15 |
| |
| /* NAND :: TIMING_2_CS4 :: tWHR [08:04] */ |
| #define BCHP_NAND_TIMING_2_CS4_tWHR_MASK 0x000001f0 |
| #define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT 4 |
| #define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT 9 |
| |
| /* NAND :: TIMING_2_CS4 :: tREAD [03:00] */ |
| #define BCHP_NAND_TIMING_2_CS4_tREAD_MASK 0x0000000f |
| #define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT 0 |
| #define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT 6 |
| |
| /*************************************************************************** |
| *ACC_CONTROL_CS5 - Nand Flash Access Control |
| ***************************************************************************/ |
| /* NAND :: ACC_CONTROL_CS5 :: RD_ECC_EN [31:31] */ |
| #define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_MASK 0x80000000 |
| #define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_SHIFT 31 |
| #define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS5 :: WR_ECC_EN [30:30] */ |
| #define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_MASK 0x40000000 |
| #define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_SHIFT 30 |
| #define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS5 :: reserved0 [29:29] */ |
| #define BCHP_NAND_ACC_CONTROL_CS5_reserved0_MASK 0x20000000 |
| #define BCHP_NAND_ACC_CONTROL_CS5_reserved0_SHIFT 29 |
| |
| /* NAND :: ACC_CONTROL_CS5 :: FAST_PGM_RDIN [28:28] */ |
| #define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_MASK 0x10000000 |
| #define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_SHIFT 28 |
| #define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS5 :: RD_ERASED_ECC_EN [27:27] */ |
| #define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_MASK 0x08000000 |
| #define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_SHIFT 27 |
| #define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_DEFAULT 0 |
| |
| /* NAND :: ACC_CONTROL_CS5 :: PARTIAL_PAGE_EN [26:26] */ |
| #define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_MASK 0x04000000 |
| #define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_SHIFT 26 |
| #define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS5 :: WR_PREEMPT_EN [25:25] */ |
| #define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_MASK 0x02000000 |
| #define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_SHIFT 25 |
| #define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS5 :: PAGE_HIT_EN [24:24] */ |
| #define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_MASK 0x01000000 |
| #define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_SHIFT 24 |
| #define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_DEFAULT 1 |
| |
| /* NAND :: ACC_CONTROL_CS5 :: reserved1 [23:20] */ |
| #define BCHP_NAND_ACC_CONTROL_CS5_reserved1_MASK 0x00f00000 |
| #define BCHP_NAND_ACC_CONTROL_CS5_reserved1_SHIFT 20 |
| |
| /* NAND :: ACC_CONTROL_CS5 :: ECC_LEVEL [19:16] */ |
| #define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_MASK 0x000f0000 |
| #define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_SHIFT 16 |
| #define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_DEFAULT 15 |
| |
| /* NAND :: ACC_CONTROL_CS5 :: reserved2 [15:07] */ |
| #define BCHP_NAND_ACC_CONTROL_CS5_reserved2_MASK 0x0000ff80 |
| #define BCHP_NAND_ACC_CONTROL_CS5_reserved2_SHIFT 7 |
| |
| /* NAND :: ACC_CONTROL_CS5 :: SECTOR_SIZE_1K [06:06] */ |
| #define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_MASK 0x00000040 |
| #define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_SHIFT 6 |
| #define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_DEFAULT 0 |
| |
| /* NAND :: ACC_CONTROL_CS5 :: SPARE_AREA_SIZE [05:00] */ |
| #define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_MASK 0x0000003f |
| #define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_SHIFT 0 |
| #define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_DEFAULT 16 |
| |
| /*************************************************************************** |
| *CONFIG_CS5 - Nand Flash Config |
| ***************************************************************************/ |
| /* NAND :: CONFIG_CS5 :: CONFIG_LOCK [31:31] */ |
| #define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_MASK 0x80000000 |
| #define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_SHIFT 31 |
| #define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_DEFAULT 0 |
| |
| /* NAND :: CONFIG_CS5 :: BLOCK_SIZE [30:28] */ |
| #define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_MASK 0x70000000 |
| #define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_SHIFT 28 |
| #define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_2048KB 6 |
| #define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_1024KB 5 |
| #define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_512KB 3 |
| #define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_128KB 1 |
| #define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_16KB 0 |
| #define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_8KB 2 |
| #define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_256KB 4 |
| |
| /* NAND :: CONFIG_CS5 :: DEVICE_SIZE [27:24] */ |
| #define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_MASK 0x0f000000 |
| #define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_SHIFT 24 |
| #define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4MB 0 |
| #define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8MB 1 |
| #define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16MB 2 |
| #define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32MB 3 |
| #define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64MB 4 |
| #define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128MB 5 |
| #define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_256MB 6 |
| #define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_512MB 7 |
| #define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_1GB 8 |
| #define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_2GB 9 |
| #define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4GB 10 |
| #define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8GB 11 |
| #define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16GB 12 |
| #define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32GB 13 |
| #define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64GB 14 |
| #define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128GB 15 |
| |
| /* NAND :: CONFIG_CS5 :: DEVICE_WIDTH [23:23] */ |
| #define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_MASK 0x00800000 |
| #define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_SHIFT 23 |
| #define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_8 0 |
| #define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_16 1 |
| |
| /* NAND :: CONFIG_CS5 :: reserved0 [22:22] */ |
| #define BCHP_NAND_CONFIG_CS5_reserved0_MASK 0x00400000 |
| #define BCHP_NAND_CONFIG_CS5_reserved0_SHIFT 22 |
| |
| /* NAND :: CONFIG_CS5 :: PAGE_SIZE [21:20] */ |
| #define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_MASK 0x00300000 |
| #define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_SHIFT 20 |
| #define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_512 0 |
| #define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_2KB 1 |
| #define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_4KB 2 |
| #define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_8KB 3 |
| |
| /* NAND :: CONFIG_CS5 :: reserved1 [19:19] */ |
| #define BCHP_NAND_CONFIG_CS5_reserved1_MASK 0x00080000 |
| #define BCHP_NAND_CONFIG_CS5_reserved1_SHIFT 19 |
| |
| /* NAND :: CONFIG_CS5 :: FUL_ADR_BYTES [18:16] */ |
| #define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_MASK 0x00070000 |
| #define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_SHIFT 16 |
| |
| /* NAND :: CONFIG_CS5 :: reserved2 [15:15] */ |
| #define BCHP_NAND_CONFIG_CS5_reserved2_MASK 0x00008000 |
| #define BCHP_NAND_CONFIG_CS5_reserved2_SHIFT 15 |
| |
| /* NAND :: CONFIG_CS5 :: COL_ADR_BYTES [14:12] */ |
| #define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_MASK 0x00007000 |
| #define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_SHIFT 12 |
| |
| /* NAND :: CONFIG_CS5 :: reserved3 [11:11] */ |
| #define BCHP_NAND_CONFIG_CS5_reserved3_MASK 0x00000800 |
| #define BCHP_NAND_CONFIG_CS5_reserved3_SHIFT 11 |
| |
| /* NAND :: CONFIG_CS5 :: BLK_ADR_BYTES [10:08] */ |
| #define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_MASK 0x00000700 |
| #define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_SHIFT 8 |
| |
| /* NAND :: CONFIG_CS5 :: reserved4 [07:00] */ |
| #define BCHP_NAND_CONFIG_CS5_reserved4_MASK 0x000000ff |
| #define BCHP_NAND_CONFIG_CS5_reserved4_SHIFT 0 |
| |
| /*************************************************************************** |
| *TIMING_1_CS5 - Nand Flash Timing Parameters 1 |
| ***************************************************************************/ |
| /* NAND :: TIMING_1_CS5 :: tWP [31:28] */ |
| #define BCHP_NAND_TIMING_1_CS5_tWP_MASK 0xf0000000 |
| #define BCHP_NAND_TIMING_1_CS5_tWP_SHIFT 28 |
| #define BCHP_NAND_TIMING_1_CS5_tWP_DEFAULT 6 |
| |
| /* NAND :: TIMING_1_CS5 :: tWH [27:24] */ |
| #define BCHP_NAND_TIMING_1_CS5_tWH_MASK 0x0f000000 |
| #define BCHP_NAND_TIMING_1_CS5_tWH_SHIFT 24 |
| #define BCHP_NAND_TIMING_1_CS5_tWH_DEFAULT 5 |
| |
| /* NAND :: TIMING_1_CS5 :: tRP [23:20] */ |
| #define BCHP_NAND_TIMING_1_CS5_tRP_MASK 0x00f00000 |
| #define BCHP_NAND_TIMING_1_CS5_tRP_SHIFT 20 |
| #define BCHP_NAND_TIMING_1_CS5_tRP_DEFAULT 7 |
| |
| /* NAND :: TIMING_1_CS5 :: tREH [19:16] */ |
| #define BCHP_NAND_TIMING_1_CS5_tREH_MASK 0x000f0000 |
| #define BCHP_NAND_TIMING_1_CS5_tREH_SHIFT 16 |
| #define BCHP_NAND_TIMING_1_CS5_tREH_DEFAULT 4 |
| |
| /* NAND :: TIMING_1_CS5 :: tCS [15:12] */ |
| #define BCHP_NAND_TIMING_1_CS5_tCS_MASK 0x0000f000 |
| #define BCHP_NAND_TIMING_1_CS5_tCS_SHIFT 12 |
| #define BCHP_NAND_TIMING_1_CS5_tCS_DEFAULT 8 |
| |
| /* NAND :: TIMING_1_CS5 :: tCLH [11:08] */ |
| #define BCHP_NAND_TIMING_1_CS5_tCLH_MASK 0x00000f00 |
| #define BCHP_NAND_TIMING_1_CS5_tCLH_SHIFT 8 |
| #define BCHP_NAND_TIMING_1_CS5_tCLH_DEFAULT 4 |
| |
| /* NAND :: TIMING_1_CS5 :: tALH [07:04] */ |
| #define BCHP_NAND_TIMING_1_CS5_tALH_MASK 0x000000f0 |
| #define BCHP_NAND_TIMING_1_CS5_tALH_SHIFT 4 |
| #define BCHP_NAND_TIMING_1_CS5_tALH_DEFAULT 5 |
| |
| /* NAND :: TIMING_1_CS5 :: tADL [03:00] */ |
| #define BCHP_NAND_TIMING_1_CS5_tADL_MASK 0x0000000f |
| #define BCHP_NAND_TIMING_1_CS5_tADL_SHIFT 0 |
| #define BCHP_NAND_TIMING_1_CS5_tADL_DEFAULT 11 |
| |
| /*************************************************************************** |
| *TIMING_2_CS5 - Nand Flash Timing Parameters 2 |
| ***************************************************************************/ |
| /* NAND :: TIMING_2_CS5 :: CLK_SELECT [31:31] */ |
| #define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_MASK 0x80000000 |
| #define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_SHIFT 31 |
| #define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_DEFAULT 0 |
| #define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_108 0 |
| #define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_216 1 |
| |
| /* NAND :: TIMING_2_CS5 :: reserved0 [30:13] */ |
| #define BCHP_NAND_TIMING_2_CS5_reserved0_MASK 0x7fffe000 |
| #define BCHP_NAND_TIMING_2_CS5_reserved0_SHIFT 13 |
| |
| /* NAND :: TIMING_2_CS5 :: tWB [12:09] */ |
| #define BCHP_NAND_TIMING_2_CS5_tWB_MASK 0x00001e00 |
| #define BCHP_NAND_TIMING_2_CS5_tWB_SHIFT 9 |
| #define BCHP_NAND_TIMING_2_CS5_tWB_DEFAULT 15 |
| |
| /* NAND :: TIMING_2_CS5 :: tWHR [08:04] */ |
| #define BCHP_NAND_TIMING_2_CS5_tWHR_MASK 0x000001f0 |
| #define BCHP_NAND_TIMING_2_CS5_tWHR_SHIFT 4 |
| #define BCHP_NAND_TIMING_2_CS5_tWHR_DEFAULT 9 |
| |
| /* NAND :: TIMING_2_CS5 :: tREAD [03:00] */ |
| #define BCHP_NAND_TIMING_2_CS5_tREAD_MASK 0x0000000f |
| #define BCHP_NAND_TIMING_2_CS5_tREAD_SHIFT 0 |
| #define BCHP_NAND_TIMING_2_CS5_tREAD_DEFAULT 6 |
| |
| /*************************************************************************** |
| *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19 |
| ***************************************************************************/ |
| /* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK 0xff000000 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT 24 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK 0x00ff0000 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT 16 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK 0x0000ff00 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT 8 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK 0x000000ff |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT 0 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT 255 |
| |
| /*************************************************************************** |
| *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23 |
| ***************************************************************************/ |
| /* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK 0xff000000 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT 24 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK 0x00ff0000 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT 16 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK 0x0000ff00 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT 8 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK 0x000000ff |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT 0 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT 255 |
| |
| /*************************************************************************** |
| *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27 |
| ***************************************************************************/ |
| /* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK 0xff000000 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT 24 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK 0x00ff0000 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT 16 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK 0x0000ff00 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT 8 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK 0x000000ff |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT 0 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT 255 |
| |
| /*************************************************************************** |
| *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31 |
| ***************************************************************************/ |
| /* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK 0xff000000 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT 24 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK 0x00ff0000 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT 16 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK 0x0000ff00 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT 8 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */ |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK 0x000000ff |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT 0 |
| #define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT 255 |
| |
| /*************************************************************************** |
| *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19 |
| ***************************************************************************/ |
| /* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK 0xff000000 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT 24 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK 0x00ff0000 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT 16 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK 0x0000ff00 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT 8 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK 0x000000ff |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT 0 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT 255 |
| |
| /*************************************************************************** |
| *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23 |
| ***************************************************************************/ |
| /* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK 0xff000000 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT 24 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK 0x00ff0000 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT 16 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK 0x0000ff00 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT 8 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK 0x000000ff |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT 0 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT 255 |
| |
| /*************************************************************************** |
| *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27 |
| ***************************************************************************/ |
| /* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK 0xff000000 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT 24 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK 0x00ff0000 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT 16 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK 0x0000ff00 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT 8 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK 0x000000ff |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT 0 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT 255 |
| |
| /*************************************************************************** |
| *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31 |
| ***************************************************************************/ |
| /* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK 0xff000000 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT 24 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK 0x00ff0000 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT 16 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK 0x0000ff00 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT 8 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT 255 |
| |
| /* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */ |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK 0x000000ff |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT 0 |
| #define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT 255 |
| |
| /*************************************************************************** |
| *LL_OP - Nand Flash Low Level Operation |
| ***************************************************************************/ |
| /* NAND :: LL_OP :: RETURN_IDLE [31:31] */ |
| #define BCHP_NAND_LL_OP_RETURN_IDLE_MASK 0x80000000 |
| #define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT 31 |
| #define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT 0 |
| |
| /* NAND :: LL_OP :: reserved0 [30:20] */ |
| #define BCHP_NAND_LL_OP_reserved0_MASK 0x7ff00000 |
| #define BCHP_NAND_LL_OP_reserved0_SHIFT 20 |
| |
| /* NAND :: LL_OP :: CLE [19:19] */ |
| #define BCHP_NAND_LL_OP_CLE_MASK 0x00080000 |
| #define BCHP_NAND_LL_OP_CLE_SHIFT 19 |
| #define BCHP_NAND_LL_OP_CLE_DEFAULT 0 |
| |
| /* NAND :: LL_OP :: ALE [18:18] */ |
| #define BCHP_NAND_LL_OP_ALE_MASK 0x00040000 |
| #define BCHP_NAND_LL_OP_ALE_SHIFT 18 |
| #define BCHP_NAND_LL_OP_ALE_DEFAULT 0 |
| |
| /* NAND :: LL_OP :: WE [17:17] */ |
| #define BCHP_NAND_LL_OP_WE_MASK 0x00020000 |
| #define BCHP_NAND_LL_OP_WE_SHIFT 17 |
| #define BCHP_NAND_LL_OP_WE_DEFAULT 0 |
| |
| /* NAND :: LL_OP :: RE [16:16] */ |
| #define BCHP_NAND_LL_OP_RE_MASK 0x00010000 |
| #define BCHP_NAND_LL_OP_RE_SHIFT 16 |
| #define BCHP_NAND_LL_OP_RE_DEFAULT 0 |
| |
| /* NAND :: LL_OP :: DATA [15:00] */ |
| #define BCHP_NAND_LL_OP_DATA_MASK 0x0000ffff |
| #define BCHP_NAND_LL_OP_DATA_SHIFT 0 |
| #define BCHP_NAND_LL_OP_DATA_DEFAULT 0 |
| |
| /*************************************************************************** |
| *LL_RDDATA - Nand Flash Low Level Read Data |
| ***************************************************************************/ |
| /* NAND :: LL_RDDATA :: reserved0 [31:16] */ |
| #define BCHP_NAND_LL_RDDATA_reserved0_MASK 0xffff0000 |
| #define BCHP_NAND_LL_RDDATA_reserved0_SHIFT 16 |
| |
| /* NAND :: LL_RDDATA :: DATA [15:00] */ |
| #define BCHP_NAND_LL_RDDATA_DATA_MASK 0x0000ffff |
| #define BCHP_NAND_LL_RDDATA_DATA_SHIFT 0 |
| #define BCHP_NAND_LL_RDDATA_DATA_DEFAULT 0 |
| |
| /*************************************************************************** |
| *FLASH_CACHE%i - Flash Cache Buffer Read Access |
| ***************************************************************************/ |
| #define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE 0x00002a00 |
| #define BCHP_NAND_FLASH_CACHEi_ARRAY_START 0 |
| #define BCHP_NAND_FLASH_CACHEi_ARRAY_END 127 |
| #define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE 32 |
| |
| /*************************************************************************** |
| *FLASH_CACHE%i - Flash Cache Buffer Read Access |
| ***************************************************************************/ |
| /* NAND :: FLASH_CACHEi :: WORD [31:00] */ |
| #define BCHP_NAND_FLASH_CACHEi_WORD_MASK 0xffffffff |
| #define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT 0 |
| |
| |
| #endif /* #ifndef BCHP_NAND_H__ */ |
| |
| /* End of File */ |
