| /*************************************************************************** |
| * Copyright (c) 1999-2011, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Fri Jul 8 19:13:13 2011 |
| * MD5 Checksum 6d43009b3dfb16bef651d8873360bc15 |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_common.h $ |
| * |
| * Hydra_Software_Devel/3 7/11/11 12:10p albertl |
| * SW7344-40: Updated to match RDB. |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_COMMON_H__ |
| #define BCHP_COMMON_H__ |
| |
| /*************************************************************************** |
| *BCM7344_B0 |
| ***************************************************************************/ |
| #define BCHP_PHYSICAL_OFFSET 0x10000000 |
| #define BCHP_REGISTER_START 0x00000800 /* EBI is first */ |
| #define BCHP_REGISTER_END 0x01410348 /* FTM_SW_SPARE is last */ |
| #define BCHP_REGISTER_SIZE 0x00503ed2 /* Number of registers */ |
| |
| /**************************************************************************** |
| * Core instance register start address. |
| ***************************************************************************/ |
| #define BCHP_EBI_REG_START 0x00000800 |
| #define BCHP_EBI_REG_END 0x00000bfc |
| #define BCHP_HIF_INTR2_REG_START 0x00001000 |
| #define BCHP_HIF_INTR2_REG_END 0x0000102c |
| #define BCHP_IPI0_INTR2_REG_START 0x00001100 |
| #define BCHP_IPI0_INTR2_REG_END 0x0000112c |
| #define BCHP_IPI1_INTR2_REG_START 0x00001200 |
| #define BCHP_IPI1_INTR2_REG_END 0x0000122c |
| #define BCHP_HIF_CPU_INTR1_REG_START 0x00001400 |
| #define BCHP_HIF_CPU_INTR1_REG_END 0x0000142c |
| #define BCHP_HIF_CPU_TP1_INTR1_REG_START 0x00001600 |
| #define BCHP_HIF_CPU_TP1_INTR1_REG_END 0x0000162c |
| #define BCHP_HIF_RGR_REG_START 0x00001800 |
| #define BCHP_HIF_RGR_REG_END 0x00001810 |
| #define BCHP_HIF_SPI_INTR2_REG_START 0x00001d00 |
| #define BCHP_HIF_SPI_INTR2_REG_END 0x00001d2c |
| #define BCHP_HIF_TOP_CTRL_REG_START 0x00002400 |
| #define BCHP_HIF_TOP_CTRL_REG_END 0x00002418 |
| #define BCHP_NAND_REG_START 0x00002800 |
| #define BCHP_NAND_REG_END 0x00002bfc |
| #define BCHP_BSPI_REG_START 0x00003000 |
| #define BCHP_BSPI_REG_END 0x0000304c |
| #define BCHP_BSPI_RAF_REG_START 0x00003100 |
| #define BCHP_BSPI_RAF_REG_END 0x00003120 |
| #define BCHP_HIF_MSPI_REG_START 0x00003200 |
| #define BCHP_HIF_MSPI_REG_END 0x00003384 |
| #define BCHP_SDIO_0_HOST_REG_START 0x00003500 |
| #define BCHP_SDIO_0_HOST_REG_END 0x000035fc |
| #define BCHP_SDIO_0_CFG_REG_START 0x00003600 |
| #define BCHP_SDIO_0_CFG_REG_END 0x000036fc |
| #define BCHP_MICH_REG_START 0x00020000 |
| #define BCHP_MICH_REG_END 0x00020000 |
| #define BCHP_HIF_SECURE_CTRL_REG_START 0x00020100 |
| #define BCHP_HIF_SECURE_CTRL_REG_END 0x00020100 |
| #define BCHP_HIF_SECURE_BSPI_REG_START 0x00020200 |
| #define BCHP_HIF_SECURE_BSPI_REG_END 0x00020200 |
| #define BCHP_HIF_SECURE_LR_SPI_REG_START 0x00020300 |
| #define BCHP_HIF_SECURE_LR_SPI_REG_END 0x00020300 |
| #define BCHP_NAND_SECURE_REG_START 0x00020400 |
| #define BCHP_NAND_SECURE_REG_END 0x00020400 |
| #define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_START 0x00020800 |
| #define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_END 0x00020800 |
| #define BCHP_CLKGEN_REG_START 0x00040000 |
| #define BCHP_CLKGEN_REG_END 0x00040408 |
| #define BCHP_VCXO_RM_REG_START 0x00042800 |
| #define BCHP_VCXO_RM_REG_END 0x0004282c |
| #define BCHP_AVS_HW_MNTR_REG_START 0x00043000 |
| #define BCHP_AVS_HW_MNTR_REG_END 0x00043074 |
| #define BCHP_AVS_PVT_MNTR_CONFIG_REG_START 0x00043100 |
| #define BCHP_AVS_PVT_MNTR_CONFIG_REG_END 0x0004311c |
| #define BCHP_AVS_ASB_REGISTERS_REG_START 0x00043200 |
| #define BCHP_AVS_ASB_REGISTERS_REG_END 0x00043218 |
| #define BCHP_AVS_RO_REGISTERS_0_REG_START 0x00043300 |
| #define BCHP_AVS_RO_REGISTERS_0_REG_END 0x000433dc |
| #define BCHP_AVS_RO_REGISTERS_1_REG_START 0x00043400 |
| #define BCHP_AVS_RO_REGISTERS_1_REG_END 0x0004348c |
| #define BCHP_AVS_ROSC_THRESHOLD_1_REG_START 0x00043500 |
| #define BCHP_AVS_ROSC_THRESHOLD_1_REG_END 0x000435e4 |
| #define BCHP_AVS_ROSC_THRESHOLD_2_REG_START 0x00043600 |
| #define BCHP_AVS_ROSC_THRESHOLD_2_REG_END 0x000436e4 |
| #define BCHP_CLKGEN_INTR2_REG_START 0x00044000 |
| #define BCHP_CLKGEN_INTR2_REG_END 0x0004402c |
| #define BCHP_CLKGEN_GR_REG_START 0x00044800 |
| #define BCHP_CLKGEN_GR_REG_END 0x0004480c |
| #define BCHP_GENET_0_SYS_REG_START 0x00080000 |
| #define BCHP_GENET_0_SYS_REG_END 0x0008000c |
| #define BCHP_GENET_0_GR_BRIDGE_REG_START 0x00080040 |
| #define BCHP_GENET_0_GR_BRIDGE_REG_END 0x0008004c |
| #define BCHP_GENET_0_EXT_REG_START 0x00080080 |
| #define BCHP_GENET_0_EXT_REG_END 0x00080098 |
| #define BCHP_GENET_0_INTRL2_0_REG_START 0x00080200 |
| #define BCHP_GENET_0_INTRL2_0_REG_END 0x0008022c |
| #define BCHP_GENET_0_INTRL2_1_REG_START 0x00080240 |
| #define BCHP_GENET_0_INTRL2_1_REG_END 0x0008026c |
| #define BCHP_GENET_0_RBUF_REG_START 0x00080300 |
| #define BCHP_GENET_0_RBUF_REG_END 0x000803ec |
| #define BCHP_GENET_0_TBUF_REG_START 0x00080600 |
| #define BCHP_GENET_0_TBUF_REG_END 0x00080628 |
| #define BCHP_GENET_0_UMAC_REG_START 0x00080800 |
| #define BCHP_GENET_0_UMAC_REG_END 0x00080ed8 |
| #define BCHP_GENET_0_HFB_REG_START 0x00081000 |
| #define BCHP_GENET_0_HFB_REG_END 0x00082010 |
| #define BCHP_GENET_0_RDMA_REG_START 0x00083000 |
| #define BCHP_GENET_0_RDMA_REG_END 0x00083cb4 |
| #define BCHP_GENET_0_TDMA_REG_START 0x00084000 |
| #define BCHP_GENET_0_TDMA_REG_END 0x00084c88 |
| #define BCHP_GENET_1_SYS_REG_START 0x00090000 |
| #define BCHP_GENET_1_SYS_REG_END 0x0009000c |
| #define BCHP_GENET_1_GR_BRIDGE_REG_START 0x00090040 |
| #define BCHP_GENET_1_GR_BRIDGE_REG_END 0x0009004c |
| #define BCHP_GENET_1_EXT_REG_START 0x00090080 |
| #define BCHP_GENET_1_EXT_REG_END 0x00090098 |
| #define BCHP_GENET_1_INTRL2_0_REG_START 0x00090200 |
| #define BCHP_GENET_1_INTRL2_0_REG_END 0x0009022c |
| #define BCHP_GENET_1_INTRL2_1_REG_START 0x00090240 |
| #define BCHP_GENET_1_INTRL2_1_REG_END 0x0009026c |
| #define BCHP_GENET_1_RBUF_REG_START 0x00090300 |
| #define BCHP_GENET_1_RBUF_REG_END 0x000903ec |
| #define BCHP_GENET_1_TBUF_REG_START 0x00090600 |
| #define BCHP_GENET_1_TBUF_REG_END 0x00090628 |
| #define BCHP_GENET_1_UMAC_REG_START 0x00090800 |
| #define BCHP_GENET_1_UMAC_REG_END 0x00090ed8 |
| #define BCHP_GENET_1_HFB_REG_START 0x00091000 |
| #define BCHP_GENET_1_HFB_REG_END 0x00092010 |
| #define BCHP_GENET_1_RDMA_REG_START 0x00093000 |
| #define BCHP_GENET_1_RDMA_REG_END 0x00093cb4 |
| #define BCHP_GENET_1_TDMA_REG_START 0x00094000 |
| #define BCHP_GENET_1_TDMA_REG_END 0x00094c88 |
| #define BCHP_XPT_SECURITY_REG_START 0x000a0000 |
| #define BCHP_XPT_SECURITY_REG_END 0x000afffc |
| #define BCHP_MMSCRAM_REG_START 0x000b0000 |
| #define BCHP_MMSCRAM_REG_END 0x000b1ffc |
| #define BCHP_MEM_DMA_SECURE_REG_START 0x000b2000 |
| #define BCHP_MEM_DMA_SECURE_REG_END 0x000b200c |
| #define BCHP_SECTOP_GRB_REG_START 0x000b4000 |
| #define BCHP_SECTOP_GRB_REG_END 0x000b400c |
| #define BCHP_JTAG_OTP_REG_START 0x000b4100 |
| #define BCHP_JTAG_OTP_REG_END 0x000b4138 |
| #define BCHP_MEM_DMA_0_REG_START 0x000b4200 |
| #define BCHP_MEM_DMA_0_REG_END 0x000b4224 |
| #define BCHP_XPT_SECURITY_NS_REG_START 0x000b4300 |
| #define BCHP_XPT_SECURITY_NS_REG_END 0x000b4310 |
| #define BCHP_SYS_GISB_ARB_SEC_REG_START 0x000c0000 |
| #define BCHP_SYS_GISB_ARB_SEC_REG_END 0x000c00b4 |
| #define BCHP_SYS_TOP_CTRL_SEC_REG_START 0x000c0700 |
| #define BCHP_SYS_TOP_CTRL_SEC_REG_END 0x000c0704 |
| #define BCHP_AON_CTRL_SECURE_REG_START 0x000c0800 |
| #define BCHP_AON_CTRL_SECURE_REG_END 0x000c087c |
| #define BCHP_S_MEMC_0_REG_START 0x000e0000 |
| #define BCHP_S_MEMC_0_REG_END 0x000e0220 |
| #define BCHP_MFD_0_REG_START 0x00100000 |
| #define BCHP_MFD_0_REG_END 0x00100264 |
| #define BCHP_MFD_1_REG_START 0x00100400 |
| #define BCHP_MFD_1_REG_END 0x001005fc |
| #define BCHP_VFD_0_REG_START 0x00101000 |
| #define BCHP_VFD_0_REG_END 0x001011fc |
| #define BCHP_VFD_1_REG_START 0x00101200 |
| #define BCHP_VFD_1_REG_END 0x001013fc |
| #define BCHP_VFD_2_REG_START 0x00101400 |
| #define BCHP_VFD_2_REG_END 0x001015fc |
| #define BCHP_VFD_3_REG_START 0x00101600 |
| #define BCHP_VFD_3_REG_END 0x001017fc |
| #define BCHP_RDC_REG_START 0x00102000 |
| #define BCHP_RDC_REG_END 0x001029fc |
| #define BCHP_BVNF_INTR2_0_REG_START 0x00103000 |
| #define BCHP_BVNF_INTR2_0_REG_END 0x0010302c |
| #define BCHP_BVNF_INTR2_1_REG_START 0x00103100 |
| #define BCHP_BVNF_INTR2_1_REG_END 0x0010312c |
| #define BCHP_BVNF_INTR2_3_REG_START 0x00103300 |
| #define BCHP_BVNF_INTR2_3_REG_END 0x0010332c |
| #define BCHP_BVNF_INTR2_4_REG_START 0x00103400 |
| #define BCHP_BVNF_INTR2_4_REG_END 0x0010342c |
| #define BCHP_BVNF_INTR2_5_REG_START 0x00103500 |
| #define BCHP_BVNF_INTR2_5_REG_END 0x0010352c |
| #define BCHP_FMISC_REG_START 0x00104000 |
| #define BCHP_FMISC_REG_END 0x00104020 |
| #define BCHP_SCL_0_REG_START 0x00120000 |
| #define BCHP_SCL_0_REG_END 0x001203fc |
| #define BCHP_SCL_1_REG_START 0x00120400 |
| #define BCHP_SCL_1_REG_END 0x001207fc |
| #define BCHP_SCL_2_REG_START 0x00120800 |
| #define BCHP_SCL_2_REG_END 0x00120bfc |
| #define BCHP_SCL_3_REG_START 0x00120c00 |
| #define BCHP_SCL_3_REG_END 0x00120ffc |
| #define BCHP_VNET_F_REG_START 0x00122000 |
| #define BCHP_VNET_F_REG_END 0x001220ac |
| #define BCHP_VNET_B_REG_START 0x00122200 |
| #define BCHP_VNET_B_REG_END 0x001222bc |
| #define BCHP_MMISC_REG_START 0x00122800 |
| #define BCHP_MMISC_REG_END 0x00122820 |
| #define BCHP_LBOX_0_REG_START 0x00125000 |
| #define BCHP_LBOX_0_REG_END 0x00125070 |
| #define BCHP_LBOX_1_REG_START 0x00125200 |
| #define BCHP_LBOX_1_REG_END 0x00125270 |
| #define BCHP_BVNM_INTR2_0_REG_START 0x00126000 |
| #define BCHP_BVNM_INTR2_0_REG_END 0x0012602c |
| #define BCHP_DNR_0_REG_START 0x00127000 |
| #define BCHP_DNR_0_REG_END 0x001270a4 |
| #define BCHP_CAP_0_REG_START 0x00140000 |
| #define BCHP_CAP_0_REG_END 0x0014007c |
| #define BCHP_CAP_1_REG_START 0x00140200 |
| #define BCHP_CAP_1_REG_END 0x0014027c |
| #define BCHP_CAP_2_REG_START 0x00140400 |
| #define BCHP_CAP_2_REG_END 0x0014047c |
| #define BCHP_CAP_3_REG_START 0x00140600 |
| #define BCHP_CAP_3_REG_END 0x0014067c |
| #define BCHP_GFD_0_REG_START 0x00141000 |
| #define BCHP_GFD_0_REG_END 0x00141228 |
| #define BCHP_GFD_1_REG_START 0x00141400 |
| #define BCHP_GFD_1_REG_END 0x00141554 |
| #define BCHP_CMP_0_REG_START 0x00142000 |
| #define BCHP_CMP_0_REG_END 0x001424b4 |
| #define BCHP_CMP_1_REG_START 0x00142800 |
| #define BCHP_CMP_1_REG_END 0x00142cb4 |
| #define BCHP_TNT_CMP_0_V0_REG_START 0x00143000 |
| #define BCHP_TNT_CMP_0_V0_REG_END 0x001430a4 |
| #define BCHP_MASK_0_REG_START 0x00143400 |
| #define BCHP_MASK_0_REG_END 0x00143420 |
| #define BCHP_PEP_CMP_0_V0_REG_START 0x00144000 |
| #define BCHP_PEP_CMP_0_V0_REG_END 0x00145484 |
| #define BCHP_BVNB_INTR2_REG_START 0x00146000 |
| #define BCHP_BVNB_INTR2_REG_END 0x0014602c |
| #define BCHP_BMISC_REG_START 0x00146400 |
| #define BCHP_BMISC_REG_END 0x0014641c |
| #define BCHP_MVP_TOP_0_REG_START 0x00160000 |
| #define BCHP_MVP_TOP_0_REG_END 0x0016002c |
| #define BCHP_SIOB_0_REG_START 0x00160200 |
| #define BCHP_SIOB_0_REG_END 0x001602fc |
| #define BCHP_HSCL_0_REG_START 0x00160400 |
| #define BCHP_HSCL_0_REG_END 0x001607fc |
| #define BCHP_MDI_TOP_0_REG_START 0x00162000 |
| #define BCHP_MDI_TOP_0_REG_END 0x00162044 |
| #define BCHP_MDI_PPB_0_REG_START 0x00162800 |
| #define BCHP_MDI_PPB_0_REG_END 0x00162bfc |
| #define BCHP_MDI_FCN_0_REG_START 0x00162c00 |
| #define BCHP_MDI_FCN_0_REG_END 0x00162ffc |
| #define BCHP_MISC_REG_START 0x00180000 |
| #define BCHP_MISC_REG_END 0x0018009c |
| #define BCHP_IT_0_REG_START 0x00181000 |
| #define BCHP_IT_0_REG_END 0x001817fc |
| #define BCHP_IT_1_REG_START 0x00182000 |
| #define BCHP_IT_1_REG_END 0x001827fc |
| #define BCHP_VF_0_REG_START 0x00183000 |
| #define BCHP_VF_0_REG_END 0x00183134 |
| #define BCHP_VF_1_REG_START 0x00183200 |
| #define BCHP_VF_1_REG_END 0x00183334 |
| #define BCHP_SECAM_0_REG_START 0x00183400 |
| #define BCHP_SECAM_0_REG_END 0x00183414 |
| #define BCHP_SM_0_REG_START 0x00183480 |
| #define BCHP_SM_0_REG_END 0x001834ac |
| #define BCHP_SDSRC_0_REG_START 0x00183500 |
| #define BCHP_SDSRC_0_REG_END 0x0018350c |
| #define BCHP_HDSRC_0_REG_START 0x00183520 |
| #define BCHP_HDSRC_0_REG_END 0x0018353c |
| #define BCHP_CSC_0_REG_START 0x00183580 |
| #define BCHP_CSC_0_REG_END 0x001835b0 |
| #define BCHP_CSC_1_REG_START 0x00183600 |
| #define BCHP_CSC_1_REG_END 0x00183630 |
| #define BCHP_RM_0_REG_START 0x00183680 |
| #define BCHP_RM_0_REG_END 0x001836a4 |
| #define BCHP_RM_1_REG_START 0x001836c0 |
| #define BCHP_RM_1_REG_END 0x001836e4 |
| #define BCHP_ANA_DEBUG_0_REG_START 0x00183700 |
| #define BCHP_ANA_DEBUG_0_REG_END 0x00183744 |
| #define BCHP_GRPD_0_REG_START 0x00183800 |
| #define BCHP_GRPD_0_REG_END 0x001838ec |
| #define BCHP_DTRAM_0_REG_START 0x00184000 |
| #define BCHP_DTRAM_0_REG_END 0x0018447c |
| #define BCHP_DVI_DTG_0_REG_START 0x00184800 |
| #define BCHP_DVI_DTG_0_REG_END 0x00184954 |
| #define BCHP_DVI_CSC_0_REG_START 0x00184a00 |
| #define BCHP_DVI_CSC_0_REG_END 0x00184a30 |
| #define BCHP_DVI_DVF_0_REG_START 0x00184b00 |
| #define BCHP_DVI_DVF_0_REG_END 0x00184b14 |
| #define BCHP_DVI_DEBUG_0_REG_START 0x00184c00 |
| #define BCHP_DVI_DEBUG_0_REG_END 0x00184c44 |
| #define BCHP_ITU656_DTG_0_REG_START 0x00185000 |
| #define BCHP_ITU656_DTG_0_REG_END 0x00185154 |
| #define BCHP_ITU656_CSC_0_REG_START 0x00185200 |
| #define BCHP_ITU656_CSC_0_REG_END 0x00185230 |
| #define BCHP_ITU656_DVF_0_REG_START 0x00185300 |
| #define BCHP_ITU656_DVF_0_REG_END 0x00185314 |
| #define BCHP_ITU656_0_REG_START 0x00185400 |
| #define BCHP_ITU656_0_REG_END 0x00185420 |
| #define BCHP_VEC_CFG_REG_START 0x00185600 |
| #define BCHP_VEC_CFG_REG_END 0x00185708 |
| #define BCHP_VIDEO_ENC_INTR2_REG_START 0x00185a00 |
| #define BCHP_VIDEO_ENC_INTR2_REG_END 0x00185a2c |
| #define BCHP_VIDEO_ENC_TPG_0_REG_START 0x00185b00 |
| #define BCHP_VIDEO_ENC_TPG_0_REG_END 0x00185b18 |
| #define BCHP_VIDEO_ENC_DECIM_0_REG_START 0x00185c00 |
| #define BCHP_VIDEO_ENC_DECIM_0_REG_END 0x00185c08 |
| #define BCHP_DVP_TVG_0_REG_START 0x00185d00 |
| #define BCHP_DVP_TVG_0_REG_END 0x00185d88 |
| #define BCHP_VBI_ENC_REG_START 0x00186000 |
| #define BCHP_VBI_ENC_REG_END 0x00186074 |
| #define BCHP_CCE_0_REG_START 0x00186400 |
| #define BCHP_CCE_0_REG_END 0x00186458 |
| #define BCHP_CCE_1_REG_START 0x00186500 |
| #define BCHP_CCE_1_REG_END 0x00186558 |
| #define BCHP_WSE_0_REG_START 0x00186600 |
| #define BCHP_WSE_0_REG_END 0x00186614 |
| #define BCHP_WSE_1_REG_START 0x00186700 |
| #define BCHP_WSE_1_REG_END 0x00186714 |
| #define BCHP_CGMSAE_0_REG_START 0x00186800 |
| #define BCHP_CGMSAE_0_REG_END 0x00186858 |
| #define BCHP_CGMSAE_1_REG_START 0x00186900 |
| #define BCHP_CGMSAE_1_REG_END 0x00186958 |
| #define BCHP_TTE_0_REG_START 0x00186a00 |
| #define BCHP_TTE_0_REG_END 0x00186a28 |
| #define BCHP_TTE_1_REG_START 0x00186b00 |
| #define BCHP_TTE_1_REG_END 0x00186b28 |
| #define BCHP_GSE_0_REG_START 0x00186c00 |
| #define BCHP_GSE_0_REG_END 0x00186c80 |
| #define BCHP_GSE_1_REG_START 0x00186d00 |
| #define BCHP_GSE_1_REG_END 0x00186d80 |
| #define BCHP_AMOLE_0_REG_START 0x00186e00 |
| #define BCHP_AMOLE_0_REG_END 0x00186e8c |
| #define BCHP_AMOLE_1_REG_START 0x00186f00 |
| #define BCHP_AMOLE_1_REG_END 0x00186f8c |
| #define BCHP_CCE_ANCIL_0_REG_START 0x00187000 |
| #define BCHP_CCE_ANCIL_0_REG_END 0x00187054 |
| #define BCHP_WSE_ANCIL_0_REG_START 0x00187100 |
| #define BCHP_WSE_ANCIL_0_REG_END 0x0018710c |
| #define BCHP_TTE_ANCIL_0_REG_START 0x00187200 |
| #define BCHP_TTE_ANCIL_0_REG_END 0x00187228 |
| #define BCHP_GSE_ANCIL_0_REG_START 0x00187300 |
| #define BCHP_GSE_ANCIL_0_REG_END 0x00187380 |
| #define BCHP_AMOLE_ANCIL_0_REG_START 0x00187400 |
| #define BCHP_AMOLE_ANCIL_0_REG_END 0x0018748c |
| #define BCHP_ANCI656_ANCIL_0_REG_START 0x00187500 |
| #define BCHP_ANCI656_ANCIL_0_REG_END 0x00187524 |
| #define BCHP_DVP_HT_REG_START 0x001a0000 |
| #define BCHP_DVP_HT_REG_END 0x001a00d4 |
| #define BCHP_HDMI_REG_START 0x001a0800 |
| #define BCHP_HDMI_REG_END 0x001a0994 |
| #define BCHP_HDMI_TX_PHY_REG_START 0x001a0a80 |
| #define BCHP_HDMI_TX_PHY_REG_END 0x001a0ad8 |
| #define BCHP_HDMI_RM_REG_START 0x001a0b00 |
| #define BCHP_HDMI_RM_REG_END 0x001a0b2c |
| #define BCHP_HDMI_TX_INTR2_REG_START 0x001a0b40 |
| #define BCHP_HDMI_TX_INTR2_REG_END 0x001a0b6c |
| #define BCHP_HDMI_RAM_REG_START 0x001a0c00 |
| #define BCHP_HDMI_RAM_REG_END 0x001a0dfc |
| #define BCHP_BVN_RGR_REG_START 0x001a8000 |
| #define BCHP_BVN_RGR_REG_END 0x001a8010 |
| #define BCHP_DATA_MEM_REG_START 0x00200000 |
| #define BCHP_DATA_MEM_REG_END 0x0023fffc |
| #define BCHP_CNTL_MEM_REG_START 0x00240000 |
| #define BCHP_CNTL_MEM_REG_END 0x0025fffc |
| #define BCHP_MOCA_DMA_Channel0_REG_START 0x00280000 |
| #define BCHP_MOCA_DMA_Channel0_REG_END 0x0028000c |
| #define BCHP_MOCA_DMA_Channel1_REG_START 0x00280010 |
| #define BCHP_MOCA_DMA_Channel1_REG_END 0x0028001c |
| #define BCHP_MOCA_DMA_Channel2_REG_START 0x00280020 |
| #define BCHP_MOCA_DMA_Channel2_REG_END 0x0028002c |
| #define BCHP_MOCA_DMA_Channel3_REG_START 0x00280030 |
| #define BCHP_MOCA_DMA_Channel3_REG_END 0x0028003c |
| #define BCHP_MOCA_DMA_Channel4_REG_START 0x00280040 |
| #define BCHP_MOCA_DMA_Channel4_REG_END 0x0028004c |
| #define BCHP_MOCA_DMA_Channel5_REG_START 0x00280050 |
| #define BCHP_MOCA_DMA_Channel5_REG_END 0x0028005c |
| #define BCHP_MOCA_DMA_Channel6_REG_START 0x00280060 |
| #define BCHP_MOCA_DMA_Channel6_REG_END 0x0028006c |
| #define BCHP_MOCA_MAC_REG_START 0x00280400 |
| #define BCHP_MOCA_MAC_REG_END 0x00280480 |
| #define BCHP_MOCA_PHY_REG_START 0x00288000 |
| #define BCHP_MOCA_PHY_REG_END 0x0028a9fc |
| #define BCHP_MOCA_TRX_REG_START 0x0028c000 |
| #define BCHP_MOCA_TRX_REG_END 0x0028c0d0 |
| #define BCHP_MOCA_GMII_REG_START 0x00290000 |
| #define BCHP_MOCA_GMII_REG_END 0x00290058 |
| #define BCHP_MOCA_DMA_Channel_rx_REG_START 0x00290400 |
| #define BCHP_MOCA_DMA_Channel_rx_REG_END 0x0029040c |
| #define BCHP_MOCA_DMA_Channel_tx_REG_START 0x00290410 |
| #define BCHP_MOCA_DMA_Channel_tx_REG_END 0x0029041c |
| #define BCHP_MOCA_ECL_REG_START 0x00290800 |
| #define BCHP_MOCA_ECL_REG_END 0x00290848 |
| #define BCHP_MOCA_PRI_REG_START 0x00292000 |
| #define BCHP_MOCA_PRI_REG_END 0x0029207c |
| #define BCHP_MOCA_NID_REG_START 0x00294000 |
| #define BCHP_MOCA_NID_REG_END 0x002943fc |
| #define BCHP_MOCA_TIMER_0_REG_START 0x002a0000 |
| #define BCHP_MOCA_TIMER_0_REG_END 0x002a0010 |
| #define BCHP_MOCA_TIMER_1_REG_START 0x002a0020 |
| #define BCHP_MOCA_TIMER_1_REG_END 0x002a0030 |
| #define BCHP_MOCA_TIMER_2_REG_START 0x002a0040 |
| #define BCHP_MOCA_TIMER_2_REG_END 0x002a0050 |
| #define BCHP_MOCA_GPIO_REG_START 0x002a1000 |
| #define BCHP_MOCA_GPIO_REG_END 0x002a1018 |
| #define BCHP_MOCA_EXTRAS_REG_START 0x002a1400 |
| #define BCHP_MOCA_EXTRAS_REG_END 0x002a1494 |
| #define BCHP_MOCA_HOSTM2M_REG_START 0x002a2000 |
| #define BCHP_MOCA_HOSTM2M_REG_END 0x002a200c |
| #define BCHP_MOCA_HOSTMISC_REG_START 0x002a2040 |
| #define BCHP_MOCA_HOSTMISC_REG_END 0x002a2064 |
| #define BCHP_MOCA_L2_REG_START 0x002a2080 |
| #define BCHP_MOCA_L2_REG_END 0x002a20ac |
| #define BCHP_MOCA_GR_BRIDGE_REG_START 0x002a20c0 |
| #define BCHP_MOCA_GR_BRIDGE_REG_END 0x002a20cc |
| #define BCHP_MOCA_HOSTMISC_MMP_REG_START 0x002a2100 |
| #define BCHP_MOCA_HOSTMISC_MMP_REG_END 0x002a212c |
| #define BCHP_BSP_CMDBUF_REG_START 0x00329800 |
| #define BCHP_BSP_CMDBUF_REG_END 0x00329ffc |
| #define BCHP_BSP_GLB_CONTROL_REG_START 0x0032b000 |
| #define BCHP_BSP_GLB_CONTROL_REG_END 0x0032b098 |
| #define BCHP_BSP_PKL_REG_START 0x0032b300 |
| #define BCHP_BSP_PKL_REG_END 0x0032b37c |
| #define BCHP_BSP_INST_PATCH_CTRL_REG_START 0x0032b400 |
| #define BCHP_BSP_INST_PATCH_CTRL_REG_END 0x0032b404 |
| #define BCHP_BSP_CONTROL_INTR2_REG_START 0x0032b800 |
| #define BCHP_BSP_CONTROL_INTR2_REG_END 0x0032b82c |
| #define BCHP_BSP_INST_PATCHRAM_REG_START 0x0032c000 |
| #define BCHP_BSP_INST_PATCHRAM_REG_END 0x0032fffc |
| #define BCHP_XPT_BUS_IF_REG_START 0x00380000 |
| #define BCHP_XPT_BUS_IF_REG_END 0x00380088 |
| #define BCHP_XPT_XMEMIF_REG_START 0x00381000 |
| #define BCHP_XPT_XMEMIF_REG_END 0x0038109c |
| #define BCHP_XPT_PMU_REG_START 0x00381800 |
| #define BCHP_XPT_PMU_REG_END 0x00381808 |
| #define BCHP_XPT_WAKEUP_REG_START 0x00382000 |
| #define BCHP_XPT_WAKEUP_REG_END 0x00382fbc |
| #define BCHP_XPT_RMX0_IO_REG_START 0x00383000 |
| #define BCHP_XPT_RMX0_IO_REG_END 0x00383020 |
| #define BCHP_XPT_RMX1_IO_REG_START 0x00383100 |
| #define BCHP_XPT_RMX1_IO_REG_END 0x00383120 |
| #define BCHP_XPT_FE_REG_START 0x00384000 |
| #define BCHP_XPT_FE_REG_END 0x00384ffc |
| #define BCHP_XPT_DPCR0_REG_START 0x00386000 |
| #define BCHP_XPT_DPCR0_REG_END 0x00386074 |
| #define BCHP_XPT_DPCR1_REG_START 0x00386080 |
| #define BCHP_XPT_DPCR1_REG_END 0x003860f4 |
| #define BCHP_XPT_DPCR2_REG_START 0x00386100 |
| #define BCHP_XPT_DPCR2_REG_END 0x00386174 |
| #define BCHP_XPT_DPCR3_REG_START 0x00386180 |
| #define BCHP_XPT_DPCR3_REG_END 0x003861f4 |
| #define BCHP_XPT_DPCR_PP_REG_START 0x00386400 |
| #define BCHP_XPT_DPCR_PP_REG_END 0x00386404 |
| #define BCHP_XPT_PSUB_REG_START 0x00386600 |
| #define BCHP_XPT_PSUB_REG_END 0x003866c8 |
| #define BCHP_XPT_RSBUFF_REG_START 0x00386800 |
| #define BCHP_XPT_RSBUFF_REG_END 0x00386f2c |
| #define BCHP_XPT_PB0_REG_START 0x00387000 |
| #define BCHP_XPT_PB0_REG_END 0x00387060 |
| #define BCHP_XPT_PB1_REG_START 0x00387080 |
| #define BCHP_XPT_PB1_REG_END 0x003870e0 |
| #define BCHP_XPT_PB2_REG_START 0x00387100 |
| #define BCHP_XPT_PB2_REG_END 0x00387160 |
| #define BCHP_XPT_PB3_REG_START 0x00387180 |
| #define BCHP_XPT_PB3_REG_END 0x003871e0 |
| #define BCHP_XPT_MPOD_REG_START 0x00388000 |
| #define BCHP_XPT_MPOD_REG_END 0x00388020 |
| #define BCHP_XPT_RMX0_REG_START 0x00388400 |
| #define BCHP_XPT_RMX0_REG_END 0x00388408 |
| #define BCHP_XPT_RMX1_REG_START 0x00388500 |
| #define BCHP_XPT_RMX1_REG_END 0x00388508 |
| #define BCHP_XPT_XCBUFF_REG_START 0x0038a000 |
| #define BCHP_XPT_XCBUFF_REG_END 0x0038bcc8 |
| #define BCHP_XPT_RAVE_REG_START 0x00390000 |
| #define BCHP_XPT_RAVE_REG_END 0x0039a69c |
| #define BCHP_XPT_PCROFFSET_REG_START 0x0039b000 |
| #define BCHP_XPT_PCROFFSET_REG_END 0x0039bffc |
| #define BCHP_XPT_MSG_REG_START 0x003a0000 |
| #define BCHP_XPT_MSG_REG_END 0x003a4814 |
| #define BCHP_XPT_GR_REG_START 0x003a5000 |
| #define BCHP_XPT_GR_REG_END 0x003a500c |
| #define BCHP_XPT_FULL_PID_PARSER_REG_START 0x003a6000 |
| #define BCHP_XPT_FULL_PID_PARSER_REG_END 0x003a7050 |
| #define BCHP_XPT_XPU_REG_START 0x003a8000 |
| #define BCHP_XPT_XPU_REG_END 0x003ac7fc |
| #define BCHP_XPT_SECURE_BUS_IF_REG_START 0x003b8000 |
| #define BCHP_XPT_SECURE_BUS_IF_REG_END 0x003b8000 |
| #define BCHP_SUN_GISB_ARB_REG_START 0x00400000 |
| #define BCHP_SUN_GISB_ARB_REG_END 0x004000d8 |
| #define BCHP_SUN_RGR_REG_START 0x00400400 |
| #define BCHP_SUN_RGR_REG_END 0x00400410 |
| #define BCHP_SUN_RG_REG_START 0x00400800 |
| #define BCHP_SUN_RG_REG_END 0x0040080c |
| #define BCHP_TPCAP_REG_START 0x00400c00 |
| #define BCHP_TPCAP_REG_END 0x00400c84 |
| #define BCHP_SUN_L2_REG_START 0x00403000 |
| #define BCHP_SUN_L2_REG_END 0x0040302c |
| #define BCHP_SM_L2_REG_START 0x00403400 |
| #define BCHP_SM_L2_REG_END 0x0040342c |
| #define BCHP_SM_REG_START 0x00403800 |
| #define BCHP_SM_REG_END 0x00403824 |
| #define BCHP_SM_FAST_REG_START 0x00403c00 |
| #define BCHP_SM_FAST_REG_END 0x00403c18 |
| #define BCHP_SUN_TOP_CTRL_REG_START 0x00404000 |
| #define BCHP_SUN_TOP_CTRL_REG_END 0x00404518 |
| #define BCHP_IRB_REG_START 0x00406000 |
| #define BCHP_IRB_REG_END 0x00406138 |
| #define BCHP_PM_REG_START 0x00406180 |
| #define BCHP_PM_REG_END 0x00406188 |
| #define BCHP_BSCA_REG_START 0x00406200 |
| #define BCHP_BSCA_REG_END 0x00406254 |
| #define BCHP_BSCB_REG_START 0x00406280 |
| #define BCHP_BSCB_REG_END 0x004062d4 |
| #define BCHP_BSCD_REG_START 0x00406300 |
| #define BCHP_BSCD_REG_END 0x00406354 |
| #define BCHP_PWM_REG_START 0x00406580 |
| #define BCHP_PWM_REG_END 0x004065a4 |
| #define BCHP_PWMB_REG_START 0x004066c0 |
| #define BCHP_PWMB_REG_END 0x004066e4 |
| #define BCHP_GIO_REG_START 0x00406700 |
| #define BCHP_GIO_REG_END 0x0040675c |
| #define BCHP_IRQ0_REG_START 0x00406780 |
| #define BCHP_IRQ0_REG_END 0x00406784 |
| #define BCHP_IRQ1_REG_START 0x00406788 |
| #define BCHP_IRQ1_REG_END 0x0040678c |
| #define BCHP_TIMER_REG_START 0x004067c0 |
| #define BCHP_TIMER_REG_END 0x004067fc |
| #define BCHP_UARTA_REG_START 0x00406900 |
| #define BCHP_UARTA_REG_END 0x0040691c |
| #define BCHP_UARTB_REG_START 0x00406940 |
| #define BCHP_UARTB_REG_END 0x0040695c |
| #define BCHP_UARTC_REG_START 0x00406980 |
| #define BCHP_UARTC_REG_END 0x0040699c |
| #define BCHP_SCA_REG_START 0x00406a00 |
| #define BCHP_SCA_REG_END 0x00406abc |
| #define BCHP_SCB_REG_START 0x00406ac0 |
| #define BCHP_SCB_REG_END 0x00406b7c |
| #define BCHP_SCIRQ0_REG_START 0x00406c40 |
| #define BCHP_SCIRQ0_REG_END 0x00406c44 |
| #define BCHP_SCIRQ1_REG_START 0x00406c48 |
| #define BCHP_SCIRQ1_REG_END 0x00406c4c |
| #define BCHP_MCIF_REG_START 0x00406e00 |
| #define BCHP_MCIF_REG_END 0x00406e20 |
| #define BCHP_MCIF_INTR2_REG_START 0x00406e40 |
| #define BCHP_MCIF_INTR2_REG_END 0x00406e6c |
| #define BCHP_UPG_AUX_INTR2_REG_START 0x00406e80 |
| #define BCHP_UPG_AUX_INTR2_REG_END 0x00406eac |
| #define BCHP_TMON_REG_START 0x00406f00 |
| #define BCHP_TMON_REG_END 0x00406f50 |
| #define BCHP_AON_CTRL_REG_START 0x00408000 |
| #define BCHP_AON_CTRL_REG_END 0x004083fc |
| #define BCHP_AON_L2_REG_START 0x00408400 |
| #define BCHP_AON_L2_REG_END 0x0040842c |
| #define BCHP_AON_PM_L2_REG_START 0x00408440 |
| #define BCHP_AON_PM_L2_REG_END 0x0040846c |
| #define BCHP_AON_PIN_CTRL_REG_START 0x00408500 |
| #define BCHP_AON_PIN_CTRL_REG_END 0x0040851c |
| #define BCHP_AON_HDMI_TX_REG_START 0x00408600 |
| #define BCHP_AON_HDMI_TX_REG_END 0x00408698 |
| #define BCHP_LDK_REG_START 0x00408800 |
| #define BCHP_LDK_REG_END 0x0040883c |
| #define BCHP_PM_AON_REG_START 0x00408840 |
| #define BCHP_PM_AON_REG_END 0x00408848 |
| #define BCHP_ICAP_REG_START 0x00408880 |
| #define BCHP_ICAP_REG_END 0x004088bc |
| #define BCHP_KBD1_REG_START 0x004088c0 |
| #define BCHP_KBD1_REG_END 0x004088fc |
| #define BCHP_KBD2_REG_START 0x00408900 |
| #define BCHP_KBD2_REG_END 0x0040893c |
| #define BCHP_KBD3_REG_START 0x00408940 |
| #define BCHP_KBD3_REG_END 0x0040897c |
| #define BCHP_BSCC_REG_START 0x00408980 |
| #define BCHP_BSCC_REG_END 0x004089d4 |
| #define BCHP_MSPI_REG_START 0x00408a00 |
| #define BCHP_MSPI_REG_END 0x00408b7c |
| #define BCHP_IRQ0_AON_REG_START 0x00408b80 |
| #define BCHP_IRQ0_AON_REG_END 0x00408b84 |
| #define BCHP_IRQ1_AON_REG_START 0x00408b88 |
| #define BCHP_IRQ1_AON_REG_END 0x00408b8c |
| #define BCHP_GIO_AON_REG_START 0x00408c00 |
| #define BCHP_GIO_AON_REG_END 0x00408c3c |
| #define BCHP_BICAP_REG_START 0x00408e00 |
| #define BCHP_BICAP_REG_END 0x00408e38 |
| #define BCHP_UPG_AUX_AON_INTR2_REG_START 0x00408e40 |
| #define BCHP_UPG_AUX_AON_INTR2_REG_END 0x00408e6c |
| #define BCHP_WKTMR_REG_START 0x00408e80 |
| #define BCHP_WKTMR_REG_END 0x00408e90 |
| #define BCHP_USB_CAPS_REG_START 0x00480000 |
| #define BCHP_USB_CAPS_REG_END 0x0048002c |
| #define BCHP_USB_GR_BRIDGE_REG_START 0x00480100 |
| #define BCHP_USB_GR_BRIDGE_REG_END 0x0048010c |
| #define BCHP_USB_INTR2_REG_START 0x00480180 |
| #define BCHP_USB_INTR2_REG_END 0x004801ac |
| #define BCHP_USB_CTRL_REG_START 0x00480200 |
| #define BCHP_USB_CTRL_REG_END 0x00480238 |
| #define BCHP_USB_EHCI_REG_START 0x00480300 |
| #define BCHP_USB_EHCI_REG_END 0x004803a4 |
| #define BCHP_USB_OHCI_REG_START 0x00480400 |
| #define BCHP_USB_OHCI_REG_END 0x00480454 |
| #define BCHP_USB_EHCI1_REG_START 0x00480500 |
| #define BCHP_USB_EHCI1_REG_END 0x004805a4 |
| #define BCHP_USB_OHCI1_REG_START 0x00480600 |
| #define BCHP_USB_OHCI1_REG_END 0x00480654 |
| #define BCHP_USB1_CAPS_REG_START 0x00490000 |
| #define BCHP_USB1_CAPS_REG_END 0x0049002c |
| #define BCHP_USB1_GR_BRIDGE_REG_START 0x00490100 |
| #define BCHP_USB1_GR_BRIDGE_REG_END 0x0049010c |
| #define BCHP_USB1_INTR2_REG_START 0x00490180 |
| #define BCHP_USB1_INTR2_REG_END 0x004901ac |
| #define BCHP_USB1_CTRL_REG_START 0x00490200 |
| #define BCHP_USB1_CTRL_REG_END 0x00490238 |
| #define BCHP_USB1_EHCI_REG_START 0x00490300 |
| #define BCHP_USB1_EHCI_REG_END 0x004903a4 |
| #define BCHP_USB1_OHCI_REG_START 0x00490400 |
| #define BCHP_USB1_OHCI_REG_END 0x00490454 |
| #define BCHP_USB1_EHCI1_REG_START 0x00490500 |
| #define BCHP_USB1_EHCI1_REG_END 0x004905a4 |
| #define BCHP_USB1_OHCI1_REG_START 0x00490600 |
| #define BCHP_USB1_OHCI1_REG_END 0x00490654 |
| #define BCHP_BOOTROM_REG_START 0x00500000 |
| #define BCHP_BOOTROM_REG_END 0x00500ffc |
| #define BCHP_DECODE_RBNODE_REGS_0_REG_START 0x00800000 |
| #define BCHP_DECODE_RBNODE_REGS_0_REG_END 0x0080007c |
| #define BCHP_DECODE_MAIN_0_REG_START 0x00800100 |
| #define BCHP_DECODE_MAIN_0_REG_END 0x008001fc |
| #define BCHP_SDRAM_DEBUG_0_REG_START 0x00800200 |
| #define BCHP_SDRAM_DEBUG_0_REG_END 0x0080027c |
| #define BCHP_DECODE_MCOM_0_REG_START 0x00800300 |
| #define BCHP_DECODE_MCOM_0_REG_END 0x0080031c |
| #define BCHP_DECODE_SPRE_0_REG_START 0x00800320 |
| #define BCHP_DECODE_SPRE_0_REG_END 0x0080033c |
| #define BCHP_DECODE_WPRD_0_REG_START 0x00800340 |
| #define BCHP_DECODE_WPRD_0_REG_END 0x0080035c |
| #define BCHP_DECODE_DQNT_0_REG_START 0x00800400 |
| #define BCHP_DECODE_DQNT_0_REG_END 0x0080045c |
| #define BCHP_DECODE_DQNT_8X8_0_REG_START 0x00800500 |
| #define BCHP_DECODE_DQNT_8X8_0_REG_END 0x0080057c |
| #define BCHP_DECODE_VP8_XFRM_0_REG_START 0x00800600 |
| #define BCHP_DECODE_VP8_XFRM_0_REG_END 0x0080060c |
| #define BCHP_DECODE_XFRM_0_REG_START 0x00800700 |
| #define BCHP_DECODE_XFRM_0_REG_END 0x0080071c |
| #define BCHP_DECODE_DBLK_0_REG_START 0x00800720 |
| #define BCHP_DECODE_DBLK_0_REG_END 0x0080073c |
| #define BCHP_DECODE_MB_0_REG_START 0x00800740 |
| #define BCHP_DECODE_MB_0_REG_END 0x0080075c |
| #define BCHP_REG_CABAC2BINS_0_REG_START 0x00800b00 |
| #define BCHP_REG_CABAC2BINS_0_REG_END 0x00800bfc |
| #define BCHP_DECODE_SINT_0_REG_START 0x00800c00 |
| #define BCHP_DECODE_SINT_0_REG_END 0x00800dfc |
| #define BCHP_DECODE_RVC_0_REG_START 0x00800e00 |
| #define BCHP_DECODE_RVC_0_REG_END 0x00800efc |
| #define BCHP_DECODE_CPUREGS_0_REG_START 0x00800f00 |
| #define BCHP_DECODE_CPUREGS_0_REG_END 0x00800f7c |
| #define BCHP_DECODE_CPUREGS2_0_REG_START 0x00800f80 |
| #define BCHP_DECODE_CPUREGS2_0_REG_END 0x00800ffc |
| #define BCHP_DECODE_CPUDMA_0_REG_START 0x00801800 |
| #define BCHP_DECODE_CPUDMA_0_REG_END 0x008018fc |
| #define BCHP_DECODE_DMAMEM_0_REG_START 0x00801a00 |
| #define BCHP_DECODE_DMAMEM_0_REG_END 0x008021fc |
| #define BCHP_REG_CABAC2BINS2_0_REG_START 0x00802400 |
| #define BCHP_REG_CABAC2BINS2_0_REG_END 0x008027fc |
| #define BCHP_DECODE_WPTBL_0_REG_START 0x00803000 |
| #define BCHP_DECODE_WPTBL_0_REG_END 0x008031fc |
| #define BCHP_DECODE_SINT_OLOOP_0_REG_START 0x0080cc00 |
| #define BCHP_DECODE_SINT_OLOOP_0_REG_END 0x0080ccfc |
| #define BCHP_DECODE_SD_0_REG_START 0x00840800 |
| #define BCHP_DECODE_SD_0_REG_END 0x00840ffc |
| #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_START 0x00841000 |
| #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_END 0x0084107c |
| #define BCHP_DECODE_CPUCORE_0_REG_START 0x00844000 |
| #define BCHP_DECODE_CPUCORE_0_REG_END 0x00844ffc |
| #define BCHP_DECODE_CPUAUX_0_REG_START 0x00845000 |
| #define BCHP_DECODE_CPUAUX_0_REG_END 0x00845ffc |
| #define BCHP_DECODE_CPUIMEM_0_REG_START 0x00846000 |
| #define BCHP_DECODE_CPUIMEM_0_REG_END 0x00847ffc |
| #define BCHP_DECODE_CPUDMEM_0_REG_START 0x00848000 |
| #define BCHP_DECODE_CPUDMEM_0_REG_END 0x0084fffc |
| #define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_START 0x00851000 |
| #define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_END 0x0085107c |
| #define BCHP_DECODE_CPUDMA2_0_REG_START 0x00851800 |
| #define BCHP_DECODE_CPUDMA2_0_REG_END 0x008518fc |
| #define BCHP_DECODE_DMAMEM2_0_REG_START 0x00851a00 |
| #define BCHP_DECODE_DMAMEM2_0_REG_END 0x008521fc |
| #define BCHP_DECODE_CPUCORE2_0_REG_START 0x00854000 |
| #define BCHP_DECODE_CPUCORE2_0_REG_END 0x00854ffc |
| #define BCHP_DECODE_CPUAUX2_0_REG_START 0x00855000 |
| #define BCHP_DECODE_CPUAUX2_0_REG_END 0x00855ffc |
| #define BCHP_DECODE_CPUIMEM2_0_REG_START 0x00856000 |
| #define BCHP_DECODE_CPUIMEM2_0_REG_END 0x00857ffc |
| #define BCHP_DECODE_CPUDMEM2_0_REG_START 0x00858000 |
| #define BCHP_DECODE_CPUDMEM2_0_REG_END 0x0085fffc |
| #define BCHP_DECODE_IP_SHIM_0_REG_START 0x00860000 |
| #define BCHP_DECODE_IP_SHIM_0_REG_END 0x00860084 |
| #define BCHP_AVD_CACHE_0_REG_START 0x00862000 |
| #define BCHP_AVD_CACHE_0_REG_END 0x0086203c |
| #define BCHP_ILS_REGS_0_REG_START 0x00870000 |
| #define BCHP_ILS_REGS_0_REG_END 0x0087007c |
| #define BCHP_ILS_SCALE_ADDR_0_REG_START 0x00870100 |
| #define BCHP_ILS_SCALE_ADDR_0_REG_END 0x0087010c |
| #define BCHP_ILS_SPSCALE_FILL_0_REG_START 0x00870180 |
| #define BCHP_ILS_SPSCALE_FILL_0_REG_END 0x00870180 |
| #define BCHP_ILS_MVSCALE_0_REG_START 0x00870200 |
| #define BCHP_ILS_MVSCALE_0_REG_END 0x0087038c |
| #define BCHP_SVD_INTR2_0_REG_START 0x00880000 |
| #define BCHP_SVD_INTR2_0_REG_END 0x0088002c |
| #define BCHP_SVD_RGR_0_REG_START 0x00880400 |
| #define BCHP_SVD_RGR_0_REG_END 0x00880410 |
| #define BCHP_BLD_DECODE_RBNODE_REGS_0_REG_START 0x00900000 |
| #define BCHP_BLD_DECODE_RBNODE_REGS_0_REG_END 0x0090007c |
| #define BCHP_BLD_DECODE_MAIN_0_REG_START 0x00900100 |
| #define BCHP_BLD_DECODE_MAIN_0_REG_END 0x009001fc |
| #define BCHP_BLD_SDRAM_DEBUG_0_REG_START 0x00900200 |
| #define BCHP_BLD_SDRAM_DEBUG_0_REG_END 0x0090027c |
| #define BCHP_BLD_DECODE_MCOM_0_REG_START 0x00900300 |
| #define BCHP_BLD_DECODE_MCOM_0_REG_END 0x0090031c |
| #define BCHP_BLD_DECODE_SPRE_0_REG_START 0x00900320 |
| #define BCHP_BLD_DECODE_SPRE_0_REG_END 0x0090033c |
| #define BCHP_BLD_DECODE_WPRD_0_REG_START 0x00900340 |
| #define BCHP_BLD_DECODE_WPRD_0_REG_END 0x0090035c |
| #define BCHP_BLD_DECODE_DQNT_0_REG_START 0x00900400 |
| #define BCHP_BLD_DECODE_DQNT_0_REG_END 0x0090045c |
| #define BCHP_BLD_DECODE_DQNT_8X8_0_REG_START 0x00900500 |
| #define BCHP_BLD_DECODE_DQNT_8X8_0_REG_END 0x0090057c |
| #define BCHP_BLD_DECODE_VP8_XFRM_0_REG_START 0x00900600 |
| #define BCHP_BLD_DECODE_VP8_XFRM_0_REG_END 0x0090060c |
| #define BCHP_BLD_DECODE_XFRM_0_REG_START 0x00900700 |
| #define BCHP_BLD_DECODE_XFRM_0_REG_END 0x0090071c |
| #define BCHP_BLD_DECODE_DBLK_0_REG_START 0x00900720 |
| #define BCHP_BLD_DECODE_DBLK_0_REG_END 0x0090073c |
| #define BCHP_BLD_DECODE_MB_0_REG_START 0x00900740 |
| #define BCHP_BLD_DECODE_MB_0_REG_END 0x0090075c |
| #define BCHP_BLD_REG_CABAC2BINS_0_REG_START 0x00900b00 |
| #define BCHP_BLD_REG_CABAC2BINS_0_REG_END 0x00900bfc |
| #define BCHP_BLD_DECODE_SINT_0_REG_START 0x00900c00 |
| #define BCHP_BLD_DECODE_SINT_0_REG_END 0x00900dfc |
| #define BCHP_BLD_DECODE_RVC_0_REG_START 0x00900e00 |
| #define BCHP_BLD_DECODE_RVC_0_REG_END 0x00900efc |
| #define BCHP_BLD_DECODE_CPUREGS_0_REG_START 0x00900f00 |
| #define BCHP_BLD_DECODE_CPUREGS_0_REG_END 0x00900f7c |
| #define BCHP_BLD_DECODE_CPUREGS2_0_REG_START 0x00900f80 |
| #define BCHP_BLD_DECODE_CPUREGS2_0_REG_END 0x00900ffc |
| #define BCHP_BLD_DECODE_CPUDMA_0_REG_START 0x00901800 |
| #define BCHP_BLD_DECODE_CPUDMA_0_REG_END 0x009018fc |
| #define BCHP_BLD_DECODE_DMAMEM_0_REG_START 0x00901a00 |
| #define BCHP_BLD_DECODE_DMAMEM_0_REG_END 0x009021fc |
| #define BCHP_BLD_REG_CABAC2BINS2_0_REG_START 0x00902400 |
| #define BCHP_BLD_REG_CABAC2BINS2_0_REG_END 0x009027fc |
| #define BCHP_BLD_DECODE_WPTBL_0_REG_START 0x00903000 |
| #define BCHP_BLD_DECODE_WPTBL_0_REG_END 0x009031fc |
| #define BCHP_BLD_DECODE_SINT_OLOOP_0_REG_START 0x0090cc00 |
| #define BCHP_BLD_DECODE_SINT_OLOOP_0_REG_END 0x0090ccfc |
| #define BCHP_BLD_DECODE_SD_0_REG_START 0x00940800 |
| #define BCHP_BLD_DECODE_SD_0_REG_END 0x00940ffc |
| #define BCHP_BLD_DECODE_IND_SDRAM_REGS_0_REG_START 0x00941000 |
| #define BCHP_BLD_DECODE_IND_SDRAM_REGS_0_REG_END 0x0094107c |
| #define BCHP_BLD_DECODE_CPUCORE_0_REG_START 0x00944000 |
| #define BCHP_BLD_DECODE_CPUCORE_0_REG_END 0x00944ffc |
| #define BCHP_BLD_DECODE_CPUAUX_0_REG_START 0x00945000 |
| #define BCHP_BLD_DECODE_CPUAUX_0_REG_END 0x00945ffc |
| #define BCHP_BLD_DECODE_CPUIMEM_0_REG_START 0x00946000 |
| #define BCHP_BLD_DECODE_CPUIMEM_0_REG_END 0x00947ffc |
| #define BCHP_BLD_DECODE_CPUDMEM_0_REG_START 0x00948000 |
| #define BCHP_BLD_DECODE_CPUDMEM_0_REG_END 0x0094fffc |
| #define BCHP_BLD_DECODE_IND_SDRAM_REGS2_0_REG_START 0x00951000 |
| #define BCHP_BLD_DECODE_IND_SDRAM_REGS2_0_REG_END 0x0095107c |
| #define BCHP_BLD_DECODE_CPUDMA2_0_REG_START 0x00951800 |
| #define BCHP_BLD_DECODE_CPUDMA2_0_REG_END 0x009518fc |
| #define BCHP_BLD_DECODE_DMAMEM2_0_REG_START 0x00951a00 |
| #define BCHP_BLD_DECODE_DMAMEM2_0_REG_END 0x009521fc |
| #define BCHP_BLD_DECODE_CPUCORE2_0_REG_START 0x00954000 |
| #define BCHP_BLD_DECODE_CPUCORE2_0_REG_END 0x00954ffc |
| #define BCHP_BLD_DECODE_CPUAUX2_0_REG_START 0x00955000 |
| #define BCHP_BLD_DECODE_CPUAUX2_0_REG_END 0x00955ffc |
| #define BCHP_BLD_DECODE_CPUIMEM2_0_REG_START 0x00956000 |
| #define BCHP_BLD_DECODE_CPUIMEM2_0_REG_END 0x00957ffc |
| #define BCHP_BLD_DECODE_CPUDMEM2_0_REG_START 0x00958000 |
| #define BCHP_BLD_DECODE_CPUDMEM2_0_REG_END 0x0095fffc |
| #define BCHP_BLD_DECODE_IP_SHIM_0_REG_START 0x00960000 |
| #define BCHP_BLD_DECODE_IP_SHIM_0_REG_END 0x00960084 |
| #define BCHP_BLD_AVD_CACHE_0_REG_START 0x00962000 |
| #define BCHP_BLD_AVD_CACHE_0_REG_END 0x0096203c |
| #define BCHP_MEMC_GEN_0_REG_START 0x00a00000 |
| #define BCHP_MEMC_GEN_0_REG_END 0x00a004f4 |
| #define BCHP_MEMC_ARB_0_REG_START 0x00a01000 |
| #define BCHP_MEMC_ARB_0_REG_END 0x00a01244 |
| #define BCHP_MEMC_DDR_0_REG_START 0x00a02000 |
| #define BCHP_MEMC_DDR_0_REG_END 0x00a022fc |
| #define BCHP_MEMC_L2_0_REG_START 0x00a03000 |
| #define BCHP_MEMC_L2_0_REG_END 0x00a0302c |
| #define BCHP_MEMC_L2_1_0_REG_START 0x00a03800 |
| #define BCHP_MEMC_L2_1_0_REG_END 0x00a0382c |
| #define BCHP_MEMC_RGRB_0_REG_START 0x00a04000 |
| #define BCHP_MEMC_RGRB_0_REG_END 0x00a04010 |
| #define BCHP_MEMC_MISC_0_REG_START 0x00a05000 |
| #define BCHP_MEMC_MISC_0_REG_END 0x00a05010 |
| #define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_START 0x00a06000 |
| #define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_END 0x00a060c4 |
| #define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_START 0x00a06200 |
| #define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_END 0x00a063b0 |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_REG_START 0x00a06400 |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_REG_END 0x00a065b0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_START 0x00a08000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_END 0x00a08138 |
| #define BCHP_VICH_0_REG_START 0x00b00000 |
| #define BCHP_VICH_0_REG_END 0x00b0008b |
| #define BCHP_SID_REG_START 0x00c00100 |
| #define BCHP_SID_REG_END 0x00c0019c |
| #define BCHP_SID_RLE_REG_START 0x00c00300 |
| #define BCHP_SID_RLE_REG_END 0x00c0039c |
| #define BCHP_SID_DQ_REG_START 0x00c00400 |
| #define BCHP_SID_DQ_REG_END 0x00c004bc |
| #define BCHP_SID_STRM_REG_START 0x00c00800 |
| #define BCHP_SID_STRM_REG_END 0x00c0087c |
| #define BCHP_SID_OUTPUT_REG_START 0x00c00c00 |
| #define BCHP_SID_OUTPUT_REG_END 0x00c00c40 |
| #define BCHP_SID_ARC_REG_START 0x00c00f00 |
| #define BCHP_SID_ARC_REG_END 0x00c00f3c |
| #define BCHP_SID_ARCDMA_REG_START 0x00c01800 |
| #define BCHP_SID_ARCDMA_REG_END 0x00c01840 |
| #define BCHP_SID_DMARAM_REG_START 0x00c01a00 |
| #define BCHP_SID_DMARAM_REG_END 0x00c01bfc |
| #define BCHP_SID_PEEK_BITS_REG_START 0x00c02b00 |
| #define BCHP_SID_PEEK_BITS_REG_END 0x00c02b3c |
| #define BCHP_SID_EXTRACT_BITS_REG_START 0x00c02b40 |
| #define BCHP_SID_EXTRACT_BITS_REG_END 0x00c02b7c |
| #define BCHP_SID_HUFF_SYMB_REG_START 0x00c03000 |
| #define BCHP_SID_HUFF_SYMB_REG_END 0x00c037fc |
| #define BCHP_SID_HUFF_CODE_REG_START 0x00c03900 |
| #define BCHP_SID_HUFF_CODE_REG_END 0x00c039fc |
| #define BCHP_SID_SYMB_REG_START 0x00c03a00 |
| #define BCHP_SID_SYMB_REG_END 0x00c03a10 |
| #define BCHP_SID_SYMB_JPEG_REG_START 0x00c03a80 |
| #define BCHP_SID_SYMB_JPEG_REG_END 0x00c03a8c |
| #define BCHP_SID_BIGRAM_REG_START 0x00c08000 |
| #define BCHP_SID_BIGRAM_REG_END 0x00c0fffc |
| #define BCHP_SID_ARC_DBG_REG_START 0x00c11000 |
| #define BCHP_SID_ARC_DBG_REG_END 0x00c11010 |
| #define BCHP_SID_ARC_CORE_REG_START 0x00c15000 |
| #define BCHP_SID_ARC_CORE_REG_END 0x00c15014 |
| #define BCHP_M2MC_REG_START 0x00c20000 |
| #define BCHP_M2MC_REG_END 0x00c207fc |
| #define BCHP_V3D_CTL_REG_START 0x00c21000 |
| #define BCHP_V3D_CTL_REG_END 0x00c21040 |
| #define BCHP_V3D_CLE_REG_START 0x00c21100 |
| #define BCHP_V3D_CLE_REG_END 0x00c21138 |
| #define BCHP_V3D_PTB_REG_START 0x00c21300 |
| #define BCHP_V3D_PTB_REG_END 0x00c21310 |
| #define BCHP_V3D_QPS_REG_START 0x00c21400 |
| #define BCHP_V3D_QPS_REG_END 0x00c2143c |
| #define BCHP_V3D_VPM_REG_START 0x00c21500 |
| #define BCHP_V3D_VPM_REG_END 0x00c21504 |
| #define BCHP_V3D_PCTR_REG_START 0x00c21600 |
| #define BCHP_V3D_PCTR_REG_END 0x00c216fc |
| #define BCHP_V3D_GCA_REG_START 0x00c21a00 |
| #define BCHP_V3D_GCA_REG_END 0x00c21a54 |
| #define BCHP_V3D_DBG_REG_START 0x00c21e00 |
| #define BCHP_V3D_DBG_REG_END 0x00c21f20 |
| #define BCHP_GFX_L2_REG_START 0x00c23000 |
| #define BCHP_GFX_L2_REG_END 0x00c2302c |
| #define BCHP_GFX_GR_REG_START 0x00c24000 |
| #define BCHP_GFX_GR_REG_END 0x00c2400c |
| #define BCHP_SICH_REG_START 0x00c50000 |
| #define BCHP_SICH_REG_END 0x00c5003c |
| #define BCHP_UHFR_REG_START 0x00d00000 |
| #define BCHP_UHFR_REG_END 0x00d000f8 |
| #define BCHP_UHFR_INTR2_REG_START 0x00d00200 |
| #define BCHP_UHFR_INTR2_REG_END 0x00d0022c |
| #define BCHP_UHFR_GR_BRIDGE_REG_START 0x00d00300 |
| #define BCHP_UHFR_GR_BRIDGE_REG_END 0x00d0030c |
| #define BCHP_SDS_CG_REG_START 0x01100000 |
| #define BCHP_SDS_CG_REG_END 0x01100038 |
| #define BCHP_SDS_FE_REG_START 0x01100080 |
| #define BCHP_SDS_FE_REG_END 0x011000bc |
| #define BCHP_SDS_AGC_REG_START 0x01100100 |
| #define BCHP_SDS_AGC_REG_END 0x01100124 |
| #define BCHP_SDS_BL_REG_START 0x01100140 |
| #define BCHP_SDS_BL_REG_END 0x01100160 |
| #define BCHP_SDS_CL_REG_START 0x01100180 |
| #define BCHP_SDS_CL_REG_END 0x011001fc |
| #define BCHP_SDS_EQ_REG_START 0x01100200 |
| #define BCHP_SDS_EQ_REG_END 0x0110028c |
| #define BCHP_SDS_HP_REG_START 0x01100300 |
| #define BCHP_SDS_HP_REG_END 0x011003d4 |
| #define BCHP_SDS_VIT_REG_START 0x01100400 |
| #define BCHP_SDS_VIT_REG_END 0x01100428 |
| #define BCHP_SDS_FEC_REG_START 0x01100440 |
| #define BCHP_SDS_FEC_REG_END 0x01100454 |
| #define BCHP_SDS_OI_REG_START 0x01100480 |
| #define BCHP_SDS_OI_REG_END 0x011004c8 |
| #define BCHP_SDS_SNR_REG_START 0x01100500 |
| #define BCHP_SDS_SNR_REG_END 0x01100518 |
| #define BCHP_SDS_BERT_REG_START 0x01100540 |
| #define BCHP_SDS_BERT_REG_END 0x0110055c |
| #define BCHP_SDS_DFT_REG_START 0x01100580 |
| #define BCHP_SDS_DFT_REG_END 0x011005a8 |
| #define BCHP_SDS_CWC_REG_START 0x01100600 |
| #define BCHP_SDS_CWC_REG_END 0x01100694 |
| #define BCHP_SDS_MISC_REG_START 0x01100700 |
| #define BCHP_SDS_MISC_REG_END 0x01100798 |
| #define BCHP_SDS_DSEC_REG_START 0x01100800 |
| #define BCHP_SDS_DSEC_REG_END 0x011008c8 |
| #define BCHP_SDS_TUNER_REG_START 0x01100900 |
| #define BCHP_SDS_TUNER_REG_END 0x011009fc |
| #define BCHP_SDS_INTR2_0_REG_START 0x01100a00 |
| #define BCHP_SDS_INTR2_0_REG_END 0x01100a2c |
| #define BCHP_SDS_INTR2_1_REG_START 0x01100b00 |
| #define BCHP_SDS_INTR2_1_REG_END 0x01100b2c |
| #define BCHP_SDS_GR_BRIDGE_REG_START 0x01100c00 |
| #define BCHP_SDS_GR_BRIDGE_REG_END 0x01100c0c |
| #define BCHP_TFEC_REG_START 0x01130000 |
| #define BCHP_TFEC_REG_END 0x01130060 |
| #define BCHP_TFEC_MISC_REG_START 0x01130100 |
| #define BCHP_TFEC_MISC_REG_END 0x01130108 |
| #define BCHP_TFEC_INTR2_REG_START 0x01130200 |
| #define BCHP_TFEC_INTR2_REG_END 0x0113022c |
| #define BCHP_TFEC_GR_BRIDGE_REG_START 0x01130300 |
| #define BCHP_TFEC_GR_BRIDGE_REG_END 0x0113030c |
| #define BCHP_AFEC_REG_START 0x01200000 |
| #define BCHP_AFEC_REG_END 0x012003fc |
| #define BCHP_AFEC_INTR_CTRL2_REG_START 0x01200800 |
| #define BCHP_AFEC_INTR_CTRL2_REG_END 0x0120082c |
| #define BCHP_AFEC_GR_BRIDGE_REG_START 0x01200900 |
| #define BCHP_AFEC_GR_BRIDGE_REG_END 0x0120090c |
| #define BCHP_AFEC_GLOBAL_REG_START 0x01200a00 |
| #define BCHP_AFEC_GLOBAL_REG_END 0x01200a0c |
| #define BCHP_RAAGA_DSP_RGR_REG_START 0x01300000 |
| #define BCHP_RAAGA_DSP_RGR_REG_END 0x01300008 |
| #define BCHP_RAAGA_DSP_MISC_REG_START 0x01320000 |
| #define BCHP_RAAGA_DSP_MISC_REG_END 0x0132044c |
| #define BCHP_RAAGA_DSP_TIMERS_REG_START 0x01321000 |
| #define BCHP_RAAGA_DSP_TIMERS_REG_END 0x01321058 |
| #define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START 0x01321080 |
| #define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END 0x0132109c |
| #define BCHP_RAAGA_DSP_PERI_SW_REG_START 0x01321100 |
| #define BCHP_RAAGA_DSP_PERI_SW_REG_END 0x01321154 |
| #define BCHP_RAAGA_DSP_DMA_REG_START 0x01321400 |
| #define BCHP_RAAGA_DSP_DMA_REG_END 0x01321664 |
| #define BCHP_RAAGA_DSP_ESR_SI_REG_START 0x01322000 |
| #define BCHP_RAAGA_DSP_ESR_SI_REG_END 0x01322014 |
| #define BCHP_RAAGA_DSP_INTH_REG_START 0x01322200 |
| #define BCHP_RAAGA_DSP_INTH_REG_END 0x0132222c |
| #define BCHP_RAAGA_DSP_FW_INTH_REG_START 0x01322400 |
| #define BCHP_RAAGA_DSP_FW_INTH_REG_END 0x0132242c |
| #define BCHP_RAAGA_DSP_FW_CFG_REG_START 0x01323000 |
| #define BCHP_RAAGA_DSP_FW_CFG_REG_END 0x0132357c |
| #define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START 0x01330000 |
| #define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END 0x0133bffc |
| #define BCHP_AIO_MISC_REG_START 0x01380000 |
| #define BCHP_AIO_MISC_REG_END 0x01380010 |
| #define BCHP_AIO_INTH_REG_START 0x01380800 |
| #define BCHP_AIO_INTH_REG_END 0x0138082c |
| #define BCHP_AIO_INTD0_REG_START 0x01380a00 |
| #define BCHP_AIO_INTD0_REG_END 0x01380a14 |
| #define BCHP_AUD_FMM_MISC_REG_START 0x013a0000 |
| #define BCHP_AUD_FMM_MISC_REG_END 0x013a010c |
| #define BCHP_AUD_FMM_BF_CTRL_REG_START 0x013a2000 |
| #define BCHP_AUD_FMM_BF_CTRL_REG_END 0x013a2b7c |
| #define BCHP_AUD_FMM_BF_ESR0_H_REG_START 0x013a3000 |
| #define BCHP_AUD_FMM_BF_ESR0_H_REG_END 0x013a3014 |
| #define BCHP_AUD_FMM_BF_ESR1_H_REG_START 0x013a3020 |
| #define BCHP_AUD_FMM_BF_ESR1_H_REG_END 0x013a3034 |
| #define BCHP_AUD_FMM_BF_ESR2_H_REG_START 0x013a3040 |
| #define BCHP_AUD_FMM_BF_ESR2_H_REG_END 0x013a3054 |
| #define BCHP_AUD_FMM_BF_ESR0_D0_REG_START 0x013a3100 |
| #define BCHP_AUD_FMM_BF_ESR0_D0_REG_END 0x013a3114 |
| #define BCHP_AUD_FMM_BF_ESR1_D0_REG_START 0x013a3120 |
| #define BCHP_AUD_FMM_BF_ESR1_D0_REG_END 0x013a3134 |
| #define BCHP_AUD_FMM_BF_ESR2_D0_REG_START 0x013a3140 |
| #define BCHP_AUD_FMM_BF_ESR2_D0_REG_END 0x013a3154 |
| #define BCHP_AUD_FMM_SRC_CTRL0_REG_START 0x013a4000 |
| #define BCHP_AUD_FMM_SRC_CTRL0_REG_END 0x013a4bfc |
| #define BCHP_AUD_FMM_SRC_ESR0_REG_START 0x013a5000 |
| #define BCHP_AUD_FMM_SRC_ESR0_REG_END 0x013a5014 |
| #define BCHP_AUD_FMM_DP_CTRL0_REG_START 0x013a8000 |
| #define BCHP_AUD_FMM_DP_CTRL0_REG_END 0x013a98ec |
| #define BCHP_AUD_FMM_DP_ESR00_REG_START 0x013abc00 |
| #define BCHP_AUD_FMM_DP_ESR00_REG_END 0x013abc14 |
| #define BCHP_AUD_FMM_DP_ESR20_REG_START 0x013abc80 |
| #define BCHP_AUD_FMM_DP_ESR20_REG_END 0x013abc94 |
| #define BCHP_AUD_FMM_IOP_CTRL_REG_START 0x013b8000 |
| #define BCHP_AUD_FMM_IOP_CTRL_REG_END 0x013b8144 |
| #define BCHP_AUD_FMM_IOP_ESR_REG_START 0x013b8400 |
| #define BCHP_AUD_FMM_IOP_ESR_REG_END 0x013b8414 |
| #define BCHP_AUD_FMM_OP_CTRL_REG_START 0x013ba000 |
| #define BCHP_AUD_FMM_OP_CTRL_REG_END 0x013ba1fc |
| #define BCHP_AUD_FMM_OP_ESR_REG_START 0x013ba400 |
| #define BCHP_AUD_FMM_OP_ESR_REG_END 0x013ba414 |
| #define BCHP_AUD_FMM_PLL0_REG_START 0x013ba800 |
| #define BCHP_AUD_FMM_PLL0_REG_END 0x013ba834 |
| #define BCHP_AUD_FMM_PLL1_REG_START 0x013ba900 |
| #define BCHP_AUD_FMM_PLL1_REG_END 0x013ba934 |
| #define BCHP_HIFIDAC_CTRL0_REG_START 0x013bb000 |
| #define BCHP_HIFIDAC_CTRL0_REG_END 0x013bb1fc |
| #define BCHP_HIFIDAC_RM0_REG_START 0x013bb200 |
| #define BCHP_HIFIDAC_RM0_REG_END 0x013bb224 |
| #define BCHP_HIFIDAC_ESR0_REG_START 0x013bb300 |
| #define BCHP_HIFIDAC_ESR0_REG_END 0x013bb314 |
| #define BCHP_AUD_FMM_MS_CTRL_REG_START 0x013bc000 |
| #define BCHP_AUD_FMM_MS_CTRL_REG_END 0x013bdbfc |
| #define BCHP_AUD_FMM_MS_ESR_REG_START 0x013be000 |
| #define BCHP_AUD_FMM_MS_ESR_REG_END 0x013be014 |
| #define BCHP_RAAGA_DSP_SEC0_REG_START 0x01400000 |
| #define BCHP_RAAGA_DSP_SEC0_REG_END 0x01400000 |
| #define BCHP_FTM_UART_REG_START 0x01410000 |
| #define BCHP_FTM_UART_REG_END 0x014100fc |
| #define BCHP_FTM_PHY_REG_START 0x01410000 |
| #define BCHP_FTM_PHY_REG_END 0x014101fc |
| #define BCHP_FTM_PHY_ANA_REG_START 0x01410000 |
| #define BCHP_FTM_PHY_ANA_REG_END 0x01410210 |
| #define BCHP_FTM_SKIT_REG_START 0x01410000 |
| #define BCHP_FTM_SKIT_REG_END 0x01410248 |
| #define BCHP_FTM_INTR2_REG_START 0x01410000 |
| #define BCHP_FTM_INTR2_REG_END 0x0141032c |
| #define BCHP_FTM_GR_BRIDGE_REG_START 0x01410000 |
| #define BCHP_FTM_GR_BRIDGE_REG_END 0x0141033c |
| #define BCHP_FTM_SW_SPARE_REG_START 0x01410000 |
| #define BCHP_FTM_SW_SPARE_REG_END 0x01410344 |
| |
| |
| /*************************************************************************** |
| *AUD_FMM_MS_CTRL |
| ***************************************************************************/ |
| /*************************************************************************** |
| *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer |
| ***************************************************************************/ |
| /* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */ |
| #define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff |
| #define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0 |
| |
| /*************************************************************************** |
| *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits |
| ***************************************************************************/ |
| /* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */ |
| #define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK 0xffffffff |
| #define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0 |
| |
| /*************************************************************************** |
| *AUD_FMM_OP_CTRL |
| ***************************************************************************/ |
| /*************************************************************************** |
| *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI |
| ***************************************************************************/ |
| /* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */ |
| #define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff |
| #define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0 |
| |
| /*************************************************************************** |
| *BVN_MVFD_MFD |
| ***************************************************************************/ |
| /*************************************************************************** |
| *DRAM_DATA_STRUCTURE - DRAM Data Structure |
| ***************************************************************************/ |
| /* BVN_MVFD_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */ |
| #define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff |
| #define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0 |
| |
| /*************************************************************************** |
| *BVN_MVFD_MFD1 |
| ***************************************************************************/ |
| /*************************************************************************** |
| *DRAM_DATA_STRUCTURE - DRAM Data Structure |
| ***************************************************************************/ |
| /* BVN_MVFD_MFD1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */ |
| #define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff |
| #define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0 |
| |
| /*************************************************************************** |
| *BVN_MVFD_VFD |
| ***************************************************************************/ |
| /*************************************************************************** |
| *DRAM_DATA_STRUCTURE - DRAM Data Structure |
| ***************************************************************************/ |
| /* BVN_MVFD_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */ |
| #define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff |
| #define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0 |
| |
| /*************************************************************************** |
| *GFD |
| ***************************************************************************/ |
| /*************************************************************************** |
| *DRAM_DATA_STRUCTURE - DRAM Data Structure |
| ***************************************************************************/ |
| /* GFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */ |
| #define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff |
| #define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0 |
| |
| /*************************************************************************** |
| *GFD_1 |
| ***************************************************************************/ |
| /*************************************************************************** |
| *DRAM_DATA_STRUCTURE - DRAM Data Structure |
| ***************************************************************************/ |
| /* GFD_1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */ |
| #define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff |
| #define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0 |
| |
| /*************************************************************************** |
| *HIFIDAC_CTRL |
| ***************************************************************************/ |
| /*************************************************************************** |
| *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset |
| ***************************************************************************/ |
| /* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */ |
| #define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff |
| #define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0 |
| |
| /*************************************************************************** |
| *ABSTRACT_02_MUTE_USAGE - Mute usage |
| ***************************************************************************/ |
| /* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */ |
| #define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff |
| #define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0 |
| |
| /*************************************************************************** |
| *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change |
| ***************************************************************************/ |
| /* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */ |
| #define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff |
| #define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0 |
| |
| /*************************************************************************** |
| *M2MC |
| ***************************************************************************/ |
| /*************************************************************************** |
| *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract |
| ***************************************************************************/ |
| /* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */ |
| #define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0 |
| ***************************************************************************/ |
| /* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK 0xf0000000 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT 28 |
| |
| /* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK 0x0fffffe0 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT 5 |
| |
| /* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK 0x0000001e |
| #define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT 1 |
| |
| /* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK 0x00000001 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT 0 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid 0 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1 |
| |
| /*************************************************************************** |
| *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1 |
| ***************************************************************************/ |
| /* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK 0xffff8000 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT 15 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK 0x00004000 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT 14 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK 0x00002000 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT 13 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK 0x00000800 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT 11 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK 0x00000400 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK 0x00000200 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK 0x00000100 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT 8 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK 0x00000020 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT 5 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK 0x00000002 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK 0x00000001 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT 0 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_11_DST_COLOR_MATRIX_N - Linked-List Packet Word N for group DST_COLOR_MATRIX |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_11_DST_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_12_OUTPUT_COLOR_MATRIX_N - Linked-List Packet Word N for group OUTPUT_COLOR_MATRIX |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_12_OUTPUT_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_13_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_13_SRC_CLUT :: reserved0 [31:29] */ |
| #define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_MASK 0xe0000000 |
| #define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_SHIFT 29 |
| |
| /* M2MC :: LIST_PKT_13_SRC_CLUT :: REGISTER_CONTENTS [28:00] */ |
| #define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_MASK 0x1fffffff |
| #define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_14_DST_CLUT - Linked-List Packet Word for group DST_CLUT |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_14_DST_CLUT :: reserved0 [31:29] */ |
| #define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_MASK 0xe0000000 |
| #define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_SHIFT 29 |
| |
| /* M2MC :: LIST_PKT_14_DST_CLUT :: REGISTER_CONTENTS [28:00] */ |
| #define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_MASK 0x1fffffff |
| #define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *TYPE_CLUT_COLOR_DATA - color data for color look up table |
| ***************************************************************************/ |
| /* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */ |
| #define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK 0xff000000 |
| #define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT 24 |
| |
| /* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */ |
| #define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK 0x00ff0000 |
| #define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT 16 |
| |
| /* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */ |
| #define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK 0x0000ff00 |
| #define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT 8 |
| |
| /* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */ |
| #define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK 0x000000ff |
| #define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT 0 |
| |
| /*************************************************************************** |
| *MEM_DMA |
| ***************************************************************************/ |
| /*************************************************************************** |
| *DESC_WORD0 - MEM DMA Descriptor Word 0 |
| ***************************************************************************/ |
| /* MEM_DMA :: DESC_WORD0 :: READ_ADDR [31:00] */ |
| #define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_MASK 0xffffffff |
| #define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_SHIFT 0 |
| |
| /*************************************************************************** |
| *DESC_WORD1 - MEM DMA Descriptor Word 1 |
| ***************************************************************************/ |
| /* MEM_DMA :: DESC_WORD1 :: WRITE_ADDR [31:00] */ |
| #define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_MASK 0xffffffff |
| #define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_SHIFT 0 |
| |
| /*************************************************************************** |
| *DESC_WORD2 - MEM DMA Descriptor Word 2 |
| ***************************************************************************/ |
| /* MEM_DMA :: DESC_WORD2 :: INTR_ENABLE [31:31] */ |
| #define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK 0x80000000 |
| #define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_SHIFT 31 |
| |
| /* MEM_DMA :: DESC_WORD2 :: LAST [30:30] */ |
| #define BCHP_MEM_DMA_DESC_WORD2_LAST_MASK 0x40000000 |
| #define BCHP_MEM_DMA_DESC_WORD2_LAST_SHIFT 30 |
| |
| /* MEM_DMA :: DESC_WORD2 :: AUTO_APPEND [29:29] */ |
| #define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_MASK 0x20000000 |
| #define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_SHIFT 29 |
| |
| /* MEM_DMA :: DESC_WORD2 :: reserved0 [28:25] */ |
| #define BCHP_MEM_DMA_DESC_WORD2_reserved0_MASK 0x1e000000 |
| #define BCHP_MEM_DMA_DESC_WORD2_reserved0_SHIFT 25 |
| |
| /* MEM_DMA :: DESC_WORD2 :: TRANSFER_SIZE [24:00] */ |
| #define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK 0x01ffffff |
| #define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_SHIFT 0 |
| |
| /*************************************************************************** |
| *DESC_WORD3 - MEM DMA Descriptor Word 3 |
| ***************************************************************************/ |
| /* MEM_DMA :: DESC_WORD3 :: NEXT_DESC_ADDR [31:05] */ |
| #define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK 0xffffffe0 |
| #define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_SHIFT 5 |
| |
| /* MEM_DMA :: DESC_WORD3 :: reserved0 [04:03] */ |
| #define BCHP_MEM_DMA_DESC_WORD3_reserved0_MASK 0x00000018 |
| #define BCHP_MEM_DMA_DESC_WORD3_reserved0_SHIFT 3 |
| |
| /* MEM_DMA :: DESC_WORD3 :: READ_ENDIAN_MODE [02:02] */ |
| #define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_MASK 0x00000004 |
| #define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_SHIFT 2 |
| #define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_BIG_ENDIAN 0 |
| #define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_LITTLE_ENDIAN 1 |
| |
| /* MEM_DMA :: DESC_WORD3 :: WRITE_ENDIAN_XLATE_MODE [01:00] */ |
| #define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_MASK 0x00000003 |
| #define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_SHIFT 0 |
| #define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_WORD_ALIGNED 0 |
| #define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_HALF_WORD_ALIGNED 1 |
| #define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_BYTE_ALIGNED 2 |
| #define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_reserved 3 |
| |
| /*************************************************************************** |
| *DESC_WORD4 - MEM DMA Descriptor Word 4 |
| ***************************************************************************/ |
| /* MEM_DMA :: DESC_WORD4 :: reserved0 [31:16] */ |
| #define BCHP_MEM_DMA_DESC_WORD4_reserved0_MASK 0xffff0000 |
| #define BCHP_MEM_DMA_DESC_WORD4_reserved0_SHIFT 16 |
| |
| /* MEM_DMA :: DESC_WORD4 :: SCRAM_CTRL_RSV [15:14] */ |
| #define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_MASK 0x0000c000 |
| #define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_SHIFT 14 |
| |
| /* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_END [13:13] */ |
| #define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_MASK 0x00002000 |
| #define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_SHIFT 13 |
| |
| /* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_START [12:12] */ |
| #define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_MASK 0x00001000 |
| #define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_SHIFT 12 |
| |
| /* MEM_DMA :: DESC_WORD4 :: SG_ENABLE [11:11] */ |
| #define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_MASK 0x00000800 |
| #define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_SHIFT 11 |
| |
| /* MEM_DMA :: DESC_WORD4 :: ENC_DEC_INIT [10:10] */ |
| #define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_MASK 0x00000400 |
| #define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_SHIFT 10 |
| |
| /* MEM_DMA :: DESC_WORD4 :: MODE_SEL [09:08] */ |
| #define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_MASK 0x00000300 |
| #define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_SHIFT 8 |
| |
| /* MEM_DMA :: DESC_WORD4 :: KEY_SELECT [07:00] */ |
| #define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_MASK 0x000000ff |
| #define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_SHIFT 0 |
| |
| /*************************************************************************** |
| *DESC_WORD5 - MEM DMA Descriptor Word 5 |
| ***************************************************************************/ |
| /* MEM_DMA :: DESC_WORD5 :: reserved0 [31:00] */ |
| #define BCHP_MEM_DMA_DESC_WORD5_reserved0_MASK 0xffffffff |
| #define BCHP_MEM_DMA_DESC_WORD5_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *DESC_WORD6 - MEM DMA Descriptor Word 6 |
| ***************************************************************************/ |
| /* MEM_DMA :: DESC_WORD6 :: reserved0 [31:00] */ |
| #define BCHP_MEM_DMA_DESC_WORD6_reserved0_MASK 0xffffffff |
| #define BCHP_MEM_DMA_DESC_WORD6_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *DESC_WORD7 - MEM DMA Descriptor Word 7 |
| ***************************************************************************/ |
| /* MEM_DMA :: DESC_WORD7 :: reserved0 [31:00] */ |
| #define BCHP_MEM_DMA_DESC_WORD7_reserved0_MASK 0xffffffff |
| #define BCHP_MEM_DMA_DESC_WORD7_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *RAAGA_REGSET_DSP_CFG |
| ***************************************************************************/ |
| /*************************************************************************** |
| *AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0 |
| |
| /*************************************************************************** |
| *AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0 |
| |
| /*************************************************************************** |
| *AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0 |
| |
| /*************************************************************************** |
| *AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0 |
| |
| /*************************************************************************** |
| *AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0 |
| |
| /*************************************************************************** |
| *AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo 2 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono 1 |
| |
| /*************************************************************************** |
| *AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3 |
| |
| /*************************************************************************** |
| *AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0 |
| |
| /*************************************************************************** |
| *AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3 |
| |
| /*************************************************************************** |
| *AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0 |
| |
| /*************************************************************************** |
| *AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0 |
| |
| /*************************************************************************** |
| *AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0 |
| |
| /*************************************************************************** |
| *AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right 2147483648 |
| |
| /*************************************************************************** |
| *AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0 |
| |
| /*************************************************************************** |
| *AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right 2147483648 |
| |
| /*************************************************************************** |
| *AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0 |
| |
| /*************************************************************************** |
| *AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right 2147483648 |
| |
| /*************************************************************************** |
| *AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767 |
| |
| /*************************************************************************** |
| *AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767 |
| |
| /*************************************************************************** |
| *AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0 |
| |
| /*************************************************************************** |
| *AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK 0xffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3 |
| |
| /*************************************************************************** |
| *AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3 |
| |
| /*************************************************************************** |
| *AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK 0xffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7 |
| |
| /*************************************************************************** |
| *AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK 0xffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On 1 |
| |
| /*************************************************************************** |
| *AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3 |
| |
| /*************************************************************************** |
| *AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1 |
| |
| /*************************************************************************** |
| *AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0 |
| |
| /*************************************************************************** |
| *AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768 |
| |
| /*************************************************************************** |
| *AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0 |
| |
| /*************************************************************************** |
| *AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768 |
| |
| /*************************************************************************** |
| *AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0 |
| |
| /*************************************************************************** |
| *AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768 |
| |
| /*************************************************************************** |
| *AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK 0xffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt 1 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo 2 |
| |
| /*************************************************************************** |
| *AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1 |
| |
| /*************************************************************************** |
| *AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0 |
| |
| /*************************************************************************** |
| *AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK 0xffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT 0 |
| |
| /*************************************************************************** |
| *DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1 |
| |
| /*************************************************************************** |
| *DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0 |
| |
| /*************************************************************************** |
| *DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3 |
| |
| /*************************************************************************** |
| *DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2 |
| |
| /*************************************************************************** |
| *DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0 |
| |
| /*************************************************************************** |
| *DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0 |
| |
| /*************************************************************************** |
| *LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0 |
| |
| /*************************************************************************** |
| *LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0 |
| |
| /*************************************************************************** |
| *MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono 1 |
| |
| /*************************************************************************** |
| *MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK 0xffffffff |
| #define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2 |
| #define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3 |
| |
| /*************************************************************************** |
| *RDC |
| ***************************************************************************/ |
| /*************************************************************************** |
| *RUL - RUL Command. |
| ***************************************************************************/ |
| /* RDC :: RUL :: opcode [31:24] */ |
| #define BCHP_RDC_RUL_opcode_MASK 0xff000000 |
| #define BCHP_RDC_RUL_opcode_SHIFT 24 |
| #define BCHP_RDC_RUL_opcode_NOP 0 |
| #define BCHP_RDC_RUL_opcode_REG_WRITE_IMM 1 |
| #define BCHP_RDC_RUL_opcode_REG_WRITE 2 |
| #define BCHP_RDC_RUL_opcode_REG_READ 3 |
| #define BCHP_RDC_RUL_opcode_LOAD_IMM 4 |
| #define BCHP_RDC_RUL_opcode_WINDOW_WRITE 5 |
| #define BCHP_RDC_RUL_opcode_BLOCK_WRITE 6 |
| #define BCHP_RDC_RUL_opcode_WINDOW_COPY 7 |
| #define BCHP_RDC_RUL_opcode_BLOCK_COPY 8 |
| #define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK 9 |
| #define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW 10 |
| #define BCHP_RDC_RUL_opcode_AND 11 |
| #define BCHP_RDC_RUL_opcode_AND_IMM 12 |
| #define BCHP_RDC_RUL_opcode_OR 13 |
| #define BCHP_RDC_RUL_opcode_OR_IMM 14 |
| #define BCHP_RDC_RUL_opcode_XOR 15 |
| #define BCHP_RDC_RUL_opcode_XOR_IMM 16 |
| #define BCHP_RDC_RUL_opcode_NOT 17 |
| #define BCHP_RDC_RUL_opcode_ROTATE_RIGHT 18 |
| #define BCHP_RDC_RUL_opcode_SUM 19 |
| #define BCHP_RDC_RUL_opcode_SUM_IMM 20 |
| #define BCHP_RDC_RUL_opcode_COND_SKIP 21 |
| #define BCHP_RDC_RUL_opcode_SKIP 22 |
| #define BCHP_RDC_RUL_opcode_EXIT 23 |
| #define BCHP_RDC_RUL_opcode_PLACEHOLDER 255 |
| |
| /* RDC :: RUL :: reserved0 [23:23] */ |
| #define BCHP_RDC_RUL_reserved0_MASK 0x00800000 |
| #define BCHP_RDC_RUL_reserved0_SHIFT 23 |
| |
| /* union - case rdc_args [22:00] */ |
| /* RDC :: RUL :: rdc_args :: rotation [22:18] */ |
| #define BCHP_RDC_RUL_rdc_args_rotation_MASK 0x007c0000 |
| #define BCHP_RDC_RUL_rdc_args_rotation_SHIFT 18 |
| |
| /* RDC :: RUL :: rdc_args :: src1 [17:12] */ |
| #define BCHP_RDC_RUL_rdc_args_src1_MASK 0x0003f000 |
| #define BCHP_RDC_RUL_rdc_args_src1_SHIFT 12 |
| |
| /* RDC :: RUL :: rdc_args :: src2 [11:06] */ |
| #define BCHP_RDC_RUL_rdc_args_src2_MASK 0x00000fc0 |
| #define BCHP_RDC_RUL_rdc_args_src2_SHIFT 6 |
| |
| /* RDC :: RUL :: rdc_args :: dest [05:00] */ |
| #define BCHP_RDC_RUL_rdc_args_dest_MASK 0x0000003f |
| #define BCHP_RDC_RUL_rdc_args_dest_SHIFT 0 |
| |
| /* union - case reg_args [22:00] */ |
| /* RDC :: RUL :: reg_args :: rotation [22:18] */ |
| #define BCHP_RDC_RUL_reg_args_rotation_MASK 0x007c0000 |
| #define BCHP_RDC_RUL_reg_args_rotation_SHIFT 18 |
| |
| /* RDC :: RUL :: reg_args :: src1 [17:12] */ |
| #define BCHP_RDC_RUL_reg_args_src1_MASK 0x0003f000 |
| #define BCHP_RDC_RUL_reg_args_src1_SHIFT 12 |
| |
| /* RDC :: RUL :: reg_args :: count [11:00] */ |
| #define BCHP_RDC_RUL_reg_args_count_MASK 0x00000fff |
| #define BCHP_RDC_RUL_reg_args_count_SHIFT 0 |
| |
| /*************************************************************************** |
| *XPT_PB |
| ***************************************************************************/ |
| /*************************************************************************** |
| *DESCRIPTOR_ABSTRACT - Playback Linked-List Descriptor Abstract |
| ***************************************************************************/ |
| /* XPT_PB :: DESCRIPTOR_ABSTRACT :: DESCRIPTOR_FORMAT [31:00] */ |
| #define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_MASK 0xffffffff |
| #define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_SHIFT 0 |
| |
| /*************************************************************************** |
| *DESC_0 - Playback Linked-List Descriptor Word 0 |
| ***************************************************************************/ |
| /* XPT_PB :: DESC_0 :: PB_BUFFER_START_ADDR [31:00] */ |
| #define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_MASK 0xffffffff |
| #define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_SHIFT 0 |
| |
| /*************************************************************************** |
| *DESC_1 - Playback Linked-List Descriptor Word 1 |
| ***************************************************************************/ |
| /* XPT_PB :: DESC_1 :: PB_BUFFER_LENGTH [31:00] */ |
| #define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_MASK 0xffffffff |
| #define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_SHIFT 0 |
| |
| /*************************************************************************** |
| *DESC_2 - Playback Linked-List Descriptor Word 2 |
| ***************************************************************************/ |
| /* XPT_PB :: DESC_2 :: PB_INTERRUPT_ENABLE [31:31] */ |
| #define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_MASK 0x80000000 |
| #define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_SHIFT 31 |
| |
| /* XPT_PB :: DESC_2 :: PB_FORCE_RESYNC [30:30] */ |
| #define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_MASK 0x40000000 |
| #define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_SHIFT 30 |
| |
| /* XPT_PB :: DESC_2 :: PB_HOST_DATA_INS_EN [29:29] */ |
| #define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_MASK 0x20000000 |
| #define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_SHIFT 29 |
| |
| /* XPT_PB :: DESC_2 :: reserved0 [28:28] */ |
| #define BCHP_XPT_PB_DESC_2_reserved0_MASK 0x10000000 |
| #define BCHP_XPT_PB_DESC_2_reserved0_SHIFT 28 |
| |
| /* XPT_PB :: DESC_2 :: PB_DESC_TAG_ID [27:24] */ |
| #define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_MASK 0x0f000000 |
| #define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_SHIFT 24 |
| |
| /* XPT_PB :: DESC_2 :: reserved1 [23:00] */ |
| #define BCHP_XPT_PB_DESC_2_reserved1_MASK 0x00ffffff |
| #define BCHP_XPT_PB_DESC_2_reserved1_SHIFT 0 |
| |
| /*************************************************************************** |
| *DESC_3 - Playback Linked-List Descriptor Word 3 |
| ***************************************************************************/ |
| /* XPT_PB :: DESC_3 :: PB_NEXT_DESC_ADDR [31:04] */ |
| #define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_MASK 0xfffffff0 |
| #define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_SHIFT 4 |
| |
| /* XPT_PB :: DESC_3 :: reserved0 [03:01] */ |
| #define BCHP_XPT_PB_DESC_3_reserved0_MASK 0x0000000e |
| #define BCHP_XPT_PB_DESC_3_reserved0_SHIFT 1 |
| |
| /* XPT_PB :: DESC_3 :: PB_LAST_DESC_IND [00:00] */ |
| #define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_MASK 0x00000001 |
| #define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_SHIFT 0 |
| |
| /*************************************************************************** |
| *XPT_RAVE |
| ***************************************************************************/ |
| /*************************************************************************** |
| *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples |
| ***************************************************************************/ |
| /* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */ |
| #define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff |
| #define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0 |
| |
| /*************************************************************************** |
| *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup |
| ***************************************************************************/ |
| /* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */ |
| #define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff |
| #define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0 |
| |
| /*************************************************************************** |
| *NOTEC_PES_LAYER_SELECTION - PES Layer Selection |
| ***************************************************************************/ |
| /* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */ |
| #define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff |
| #define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0 |
| |
| /*************************************************************************** |
| *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general |
| ***************************************************************************/ |
| /* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */ |
| #define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff |
| #define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0 |
| |
| /*************************************************************************** |
| *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video |
| ***************************************************************************/ |
| /* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */ |
| #define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff |
| #define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0 |
| |
| /*************************************************************************** |
| *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video |
| ***************************************************************************/ |
| /* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */ |
| #define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff |
| #define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0 |
| |
| /*************************************************************************** |
| *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio |
| ***************************************************************************/ |
| /* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */ |
| #define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff |
| #define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0 |
| |
| /*************************************************************************** |
| *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio |
| ***************************************************************************/ |
| /* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */ |
| #define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff |
| #define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0 |
| |
| /*************************************************************************** |
| *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio |
| ***************************************************************************/ |
| /* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */ |
| #define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff |
| #define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0 |
| |
| /*************************************************************************** |
| *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio |
| ***************************************************************************/ |
| /* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */ |
| #define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff |
| #define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0 |
| |
| /*************************************************************************** |
| *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio |
| ***************************************************************************/ |
| /* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */ |
| #define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff |
| #define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0 |
| |
| #endif /* #ifndef BCHP_COMMON_H__ */ |
| |
| /* End of File */ |
