| /*************************************************************************** |
| * Copyright (c) 1999-2007, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Thu Dec 20 11:15:25 2007 |
| * MD5 Checksum ad07b612435a4b2c5f818e72f5e3d1cd |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: /magnum/basemodules/chp/7405/rdb/b0/bchp_clk.h $ |
| * |
| * Hydra_Software_Devel/2 12/20/07 2:54p yuxiaz |
| * PR36288: Updated B0 header files. |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_CLK_H__ |
| #define BCHP_CLK_H__ |
| |
| /*************************************************************************** |
| *CLK - CLOCK_GEN Registers |
| ***************************************************************************/ |
| #define BCHP_CLK_REVISION 0x00040000 /* clock_gen Revision register */ |
| #define BCHP_CLK_PM_CTRL 0x00040004 /* Software power management control to turn off 108 MHz clocks */ |
| #define BCHP_CLK_PM_CTRL_1 0x00040008 /* Software power management control to turn off 200, 81, 54, 32.4, 27, 25, 20.25 and 40.5 MHz clocks */ |
| #define BCHP_CLK_PM_CTRL_2 0x0004000c /* Software power management control to turn off audio DSP, MIPS, SATA_PCI clocks */ |
| #define BCHP_CLK_MISC 0x00040010 /* clock_gen block output clock selection */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1 0x00040014 /* Low 3rd Overtone Oscillator Control registers */ |
| #define BCHP_CLK_PLL_LOCK_STATUS 0x00040024 /* current lock status of main PLL */ |
| #define BCHP_CLK_SYS_PLL_1_CTLBUS_HI 0x00040030 /* SYS 1 PLL control bus lower word */ |
| #define BCHP_CLK_SYS_PLL_1_CTLBUS_LO 0x00040034 /* SYS 1 PLL control bus lower word */ |
| #define BCHP_CLK_SCRATCH 0x00040070 /* clock_gen Scratch register */ |
| |
| /*************************************************************************** |
| *REVISION - clock_gen Revision register |
| ***************************************************************************/ |
| /* CLK :: REVISION :: reserved0 [31:16] */ |
| #define BCHP_CLK_REVISION_reserved0_MASK 0xffff0000 |
| #define BCHP_CLK_REVISION_reserved0_SHIFT 16 |
| |
| /* CLK :: REVISION :: MAJOR [15:08] */ |
| #define BCHP_CLK_REVISION_MAJOR_MASK 0x0000ff00 |
| #define BCHP_CLK_REVISION_MAJOR_SHIFT 8 |
| |
| /* CLK :: REVISION :: MINOR [07:00] */ |
| #define BCHP_CLK_REVISION_MINOR_MASK 0x000000ff |
| #define BCHP_CLK_REVISION_MINOR_SHIFT 0 |
| |
| /*************************************************************************** |
| *PM_CTRL - Software power management control to turn off 108 MHz clocks |
| ***************************************************************************/ |
| /* CLK :: PM_CTRL :: reserved0 [31:26] */ |
| #define BCHP_CLK_PM_CTRL_reserved0_MASK 0xfc000000 |
| #define BCHP_CLK_PM_CTRL_reserved0_SHIFT 26 |
| |
| /* CLK :: PM_CTRL :: DIS_BVNM_108M_CLK [25:25] */ |
| #define BCHP_CLK_PM_CTRL_DIS_BVNM_108M_CLK_MASK 0x02000000 |
| #define BCHP_CLK_PM_CTRL_DIS_BVNM_108M_CLK_SHIFT 25 |
| |
| /* CLK :: PM_CTRL :: DIS_ENET_108M_CLK [24:24] */ |
| #define BCHP_CLK_PM_CTRL_DIS_ENET_108M_CLK_MASK 0x01000000 |
| #define BCHP_CLK_PM_CTRL_DIS_ENET_108M_CLK_SHIFT 24 |
| |
| /* CLK :: PM_CTRL :: DIS_RPTD_108M_CLK [23:23] */ |
| #define BCHP_CLK_PM_CTRL_DIS_RPTD_108M_CLK_MASK 0x00800000 |
| #define BCHP_CLK_PM_CTRL_DIS_RPTD_108M_CLK_SHIFT 23 |
| |
| /* CLK :: PM_CTRL :: DIS_VEC_DAC_108M_CLK [22:22] */ |
| #define BCHP_CLK_PM_CTRL_DIS_VEC_DAC_108M_CLK_MASK 0x00400000 |
| #define BCHP_CLK_PM_CTRL_DIS_VEC_DAC_108M_CLK_SHIFT 22 |
| |
| /* CLK :: PM_CTRL :: reserved1 [21:21] */ |
| #define BCHP_CLK_PM_CTRL_reserved1_MASK 0x00200000 |
| #define BCHP_CLK_PM_CTRL_reserved1_SHIFT 21 |
| |
| /* CLK :: PM_CTRL :: DIS_TDAC_1_108M_CLK [20:20] */ |
| #define BCHP_CLK_PM_CTRL_DIS_TDAC_1_108M_CLK_MASK 0x00100000 |
| #define BCHP_CLK_PM_CTRL_DIS_TDAC_1_108M_CLK_SHIFT 20 |
| |
| /* CLK :: PM_CTRL :: DIS_TDAC_0_108M_CLK [19:19] */ |
| #define BCHP_CLK_PM_CTRL_DIS_TDAC_0_108M_CLK_MASK 0x00080000 |
| #define BCHP_CLK_PM_CTRL_DIS_TDAC_0_108M_CLK_SHIFT 19 |
| |
| /* CLK :: PM_CTRL :: reserved2 [18:18] */ |
| #define BCHP_CLK_PM_CTRL_reserved2_MASK 0x00040000 |
| #define BCHP_CLK_PM_CTRL_reserved2_SHIFT 18 |
| |
| /* CLK :: PM_CTRL :: DIS_AVD0_108M_CLK [17:17] */ |
| #define BCHP_CLK_PM_CTRL_DIS_AVD0_108M_CLK_MASK 0x00020000 |
| #define BCHP_CLK_PM_CTRL_DIS_AVD0_108M_CLK_SHIFT 17 |
| |
| /* CLK :: PM_CTRL :: DIS_SATA_108M_CLK [16:16] */ |
| #define BCHP_CLK_PM_CTRL_DIS_SATA_108M_CLK_MASK 0x00010000 |
| #define BCHP_CLK_PM_CTRL_DIS_SATA_108M_CLK_SHIFT 16 |
| |
| /* CLK :: PM_CTRL :: DIS_USB_108M_CLK [15:15] */ |
| #define BCHP_CLK_PM_CTRL_DIS_USB_108M_CLK_MASK 0x00008000 |
| #define BCHP_CLK_PM_CTRL_DIS_USB_108M_CLK_SHIFT 15 |
| |
| /* CLK :: PM_CTRL :: reserved3 [14:13] */ |
| #define BCHP_CLK_PM_CTRL_reserved3_MASK 0x00006000 |
| #define BCHP_CLK_PM_CTRL_reserved3_SHIFT 13 |
| |
| /* CLK :: PM_CTRL :: DIS_MEMC_GFX_108M_CLK [12:12] */ |
| #define BCHP_CLK_PM_CTRL_DIS_MEMC_GFX_108M_CLK_MASK 0x00001000 |
| #define BCHP_CLK_PM_CTRL_DIS_MEMC_GFX_108M_CLK_SHIFT 12 |
| |
| /* CLK :: PM_CTRL :: reserved4 [11:10] */ |
| #define BCHP_CLK_PM_CTRL_reserved4_MASK 0x00000c00 |
| #define BCHP_CLK_PM_CTRL_reserved4_SHIFT 10 |
| |
| /* CLK :: PM_CTRL :: DIS_XPT_108M_CLK [09:09] */ |
| #define BCHP_CLK_PM_CTRL_DIS_XPT_108M_CLK_MASK 0x00000200 |
| #define BCHP_CLK_PM_CTRL_DIS_XPT_108M_CLK_SHIFT 9 |
| |
| /* CLK :: PM_CTRL :: reserved5 [08:08] */ |
| #define BCHP_CLK_PM_CTRL_reserved5_MASK 0x00000100 |
| #define BCHP_CLK_PM_CTRL_reserved5_SHIFT 8 |
| |
| /* CLK :: PM_CTRL :: DIS_SUN_UART_108M_CLK [07:07] */ |
| #define BCHP_CLK_PM_CTRL_DIS_SUN_UART_108M_CLK_MASK 0x00000080 |
| #define BCHP_CLK_PM_CTRL_DIS_SUN_UART_108M_CLK_SHIFT 7 |
| |
| /* CLK :: PM_CTRL :: DIS_AIO_108M_CLK [06:06] */ |
| #define BCHP_CLK_PM_CTRL_DIS_AIO_108M_CLK_MASK 0x00000040 |
| #define BCHP_CLK_PM_CTRL_DIS_AIO_108M_CLK_SHIFT 6 |
| |
| /* CLK :: PM_CTRL :: DIS_VEC_108M_CLK [05:05] */ |
| #define BCHP_CLK_PM_CTRL_DIS_VEC_108M_CLK_MASK 0x00000020 |
| #define BCHP_CLK_PM_CTRL_DIS_VEC_108M_CLK_SHIFT 5 |
| |
| /* CLK :: PM_CTRL :: DIS_BVND_108M_CLK [04:04] */ |
| #define BCHP_CLK_PM_CTRL_DIS_BVND_108M_CLK_MASK 0x00000010 |
| #define BCHP_CLK_PM_CTRL_DIS_BVND_108M_CLK_SHIFT 4 |
| |
| /* CLK :: PM_CTRL :: DIS_BVNE_108M_CLK [03:03] */ |
| #define BCHP_CLK_PM_CTRL_DIS_BVNE_108M_CLK_MASK 0x00000008 |
| #define BCHP_CLK_PM_CTRL_DIS_BVNE_108M_CLK_SHIFT 3 |
| |
| /* CLK :: PM_CTRL :: DIS_RFM_108M_CLK [02:02] */ |
| #define BCHP_CLK_PM_CTRL_DIS_RFM_108M_CLK_MASK 0x00000004 |
| #define BCHP_CLK_PM_CTRL_DIS_RFM_108M_CLK_SHIFT 2 |
| |
| /* CLK :: PM_CTRL :: reserved6 [01:01] */ |
| #define BCHP_CLK_PM_CTRL_reserved6_MASK 0x00000002 |
| #define BCHP_CLK_PM_CTRL_reserved6_SHIFT 1 |
| |
| /* CLK :: PM_CTRL :: DIS_HDMI_108M_CLK [00:00] */ |
| #define BCHP_CLK_PM_CTRL_DIS_HDMI_108M_CLK_MASK 0x00000001 |
| #define BCHP_CLK_PM_CTRL_DIS_HDMI_108M_CLK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PM_CTRL_1 - Software power management control to turn off 200, 81, 54, 32.4, 27, 25, 20.25 and 40.5 MHz clocks |
| ***************************************************************************/ |
| /* CLK :: PM_CTRL_1 :: reserved0 [31:30] */ |
| #define BCHP_CLK_PM_CTRL_1_reserved0_MASK 0xc0000000 |
| #define BCHP_CLK_PM_CTRL_1_reserved0_SHIFT 30 |
| |
| /* CLK :: PM_CTRL_1 :: DIS_XPT_40P5M_CLK [29:29] */ |
| #define BCHP_CLK_PM_CTRL_1_DIS_XPT_40P5M_CLK_MASK 0x20000000 |
| #define BCHP_CLK_PM_CTRL_1_DIS_XPT_40P5M_CLK_SHIFT 29 |
| |
| /* CLK :: PM_CTRL_1 :: DIS_XPT_20P25M_CLK [28:28] */ |
| #define BCHP_CLK_PM_CTRL_1_DIS_XPT_20P25M_CLK_MASK 0x10000000 |
| #define BCHP_CLK_PM_CTRL_1_DIS_XPT_20P25M_CLK_SHIFT 28 |
| |
| /* CLK :: PM_CTRL_1 :: reserved1 [27:27] */ |
| #define BCHP_CLK_PM_CTRL_1_reserved1_MASK 0x08000000 |
| #define BCHP_CLK_PM_CTRL_1_reserved1_SHIFT 27 |
| |
| /* CLK :: PM_CTRL_1 :: DIS_XPT_81M_CLK [26:26] */ |
| #define BCHP_CLK_PM_CTRL_1_DIS_XPT_81M_CLK_MASK 0x04000000 |
| #define BCHP_CLK_PM_CTRL_1_DIS_XPT_81M_CLK_SHIFT 26 |
| |
| /* CLK :: PM_CTRL_1 :: reserved2 [25:22] */ |
| #define BCHP_CLK_PM_CTRL_1_reserved2_MASK 0x03c00000 |
| #define BCHP_CLK_PM_CTRL_1_reserved2_SHIFT 22 |
| |
| /* CLK :: PM_CTRL_1 :: DIS_AVD0_PROG_CLK [21:21] */ |
| #define BCHP_CLK_PM_CTRL_1_DIS_AVD0_PROG_CLK_MASK 0x00200000 |
| #define BCHP_CLK_PM_CTRL_1_DIS_AVD0_PROG_CLK_SHIFT 21 |
| |
| /* CLK :: PM_CTRL_1 :: reserved3 [20:19] */ |
| #define BCHP_CLK_PM_CTRL_1_reserved3_MASK 0x00180000 |
| #define BCHP_CLK_PM_CTRL_1_reserved3_SHIFT 19 |
| |
| /* CLK :: PM_CTRL_1 :: DIS_ENET_25M_CLK [18:18] */ |
| #define BCHP_CLK_PM_CTRL_1_DIS_ENET_25M_CLK_MASK 0x00040000 |
| #define BCHP_CLK_PM_CTRL_1_DIS_ENET_25M_CLK_SHIFT 18 |
| |
| /* CLK :: PM_CTRL_1 :: DIS_XPT_54M_CLK [17:17] */ |
| #define BCHP_CLK_PM_CTRL_1_DIS_XPT_54M_CLK_MASK 0x00020000 |
| #define BCHP_CLK_PM_CTRL_1_DIS_XPT_54M_CLK_SHIFT 17 |
| |
| /* CLK :: PM_CTRL_1 :: DIS_HIF_54M_CLK [16:16] */ |
| #define BCHP_CLK_PM_CTRL_1_DIS_HIF_54M_CLK_MASK 0x00010000 |
| #define BCHP_CLK_PM_CTRL_1_DIS_HIF_54M_CLK_SHIFT 16 |
| |
| /* CLK :: PM_CTRL_1 :: reserved4 [15:05] */ |
| #define BCHP_CLK_PM_CTRL_1_reserved4_MASK 0x0000ffe0 |
| #define BCHP_CLK_PM_CTRL_1_reserved4_SHIFT 5 |
| |
| /* CLK :: PM_CTRL_1 :: DIS_SUN_DAA_32P4M_CLK [04:04] */ |
| #define BCHP_CLK_PM_CTRL_1_DIS_SUN_DAA_32P4M_CLK_MASK 0x00000010 |
| #define BCHP_CLK_PM_CTRL_1_DIS_SUN_DAA_32P4M_CLK_SHIFT 4 |
| |
| /* CLK :: PM_CTRL_1 :: DIS_SUN_SM_27M_CLK [03:03] */ |
| #define BCHP_CLK_PM_CTRL_1_DIS_SUN_SM_27M_CLK_MASK 0x00000008 |
| #define BCHP_CLK_PM_CTRL_1_DIS_SUN_SM_27M_CLK_SHIFT 3 |
| |
| /* CLK :: PM_CTRL_1 :: DIS_XPT_27M_CLK [02:02] */ |
| #define BCHP_CLK_PM_CTRL_1_DIS_XPT_27M_CLK_MASK 0x00000004 |
| #define BCHP_CLK_PM_CTRL_1_DIS_XPT_27M_CLK_SHIFT 2 |
| |
| /* CLK :: PM_CTRL_1 :: DIS_SUN_27M_CLK [01:01] */ |
| #define BCHP_CLK_PM_CTRL_1_DIS_SUN_27M_CLK_MASK 0x00000002 |
| #define BCHP_CLK_PM_CTRL_1_DIS_SUN_27M_CLK_SHIFT 1 |
| |
| /* CLK :: PM_CTRL_1 :: reserved5 [00:00] */ |
| #define BCHP_CLK_PM_CTRL_1_reserved5_MASK 0x00000001 |
| #define BCHP_CLK_PM_CTRL_1_reserved5_SHIFT 0 |
| |
| /*************************************************************************** |
| *PM_CTRL_2 - Software power management control to turn off audio DSP, MIPS, SATA_PCI clocks |
| ***************************************************************************/ |
| /* CLK :: PM_CTRL_2 :: reserved0 [31:19] */ |
| #define BCHP_CLK_PM_CTRL_2_reserved0_MASK 0xfff80000 |
| #define BCHP_CLK_PM_CTRL_2_reserved0_SHIFT 19 |
| |
| /* CLK :: PM_CTRL_2 :: DIS_BVND_216M_CLK [18:18] */ |
| #define BCHP_CLK_PM_CTRL_2_DIS_BVND_216M_CLK_MASK 0x00040000 |
| #define BCHP_CLK_PM_CTRL_2_DIS_BVND_216M_CLK_SHIFT 18 |
| |
| /* CLK :: PM_CTRL_2 :: DIS_USB_216M_CLK [17:17] */ |
| #define BCHP_CLK_PM_CTRL_2_DIS_USB_216M_CLK_MASK 0x00020000 |
| #define BCHP_CLK_PM_CTRL_2_DIS_USB_216M_CLK_SHIFT 17 |
| |
| /* CLK :: PM_CTRL_2 :: DIS_VEC_216M_CLK [16:16] */ |
| #define BCHP_CLK_PM_CTRL_2_DIS_VEC_216M_CLK_MASK 0x00010000 |
| #define BCHP_CLK_PM_CTRL_2_DIS_VEC_216M_CLK_SHIFT 16 |
| |
| /* CLK :: PM_CTRL_2 :: RESERVED_0 [15:15] */ |
| #define BCHP_CLK_PM_CTRL_2_RESERVED_0_MASK 0x00008000 |
| #define BCHP_CLK_PM_CTRL_2_RESERVED_0_SHIFT 15 |
| |
| /* CLK :: PM_CTRL_2 :: DIS_SATA_216M_CLK [14:14] */ |
| #define BCHP_CLK_PM_CTRL_2_DIS_SATA_216M_CLK_MASK 0x00004000 |
| #define BCHP_CLK_PM_CTRL_2_DIS_SATA_216M_CLK_SHIFT 14 |
| |
| /* CLK :: PM_CTRL_2 :: DIS_RPTD_216M_CLK [13:13] */ |
| #define BCHP_CLK_PM_CTRL_2_DIS_RPTD_216M_CLK_MASK 0x00002000 |
| #define BCHP_CLK_PM_CTRL_2_DIS_RPTD_216M_CLK_SHIFT 13 |
| |
| /* CLK :: PM_CTRL_2 :: reserved1 [12:12] */ |
| #define BCHP_CLK_PM_CTRL_2_reserved1_MASK 0x00001000 |
| #define BCHP_CLK_PM_CTRL_2_reserved1_SHIFT 12 |
| |
| /* CLK :: PM_CTRL_2 :: DIS_MEMC_GFX_216M_CLK [11:11] */ |
| #define BCHP_CLK_PM_CTRL_2_DIS_MEMC_GFX_216M_CLK_MASK 0x00000800 |
| #define BCHP_CLK_PM_CTRL_2_DIS_MEMC_GFX_216M_CLK_SHIFT 11 |
| |
| /* CLK :: PM_CTRL_2 :: DIS_ENET_216M_CLK [10:10] */ |
| #define BCHP_CLK_PM_CTRL_2_DIS_ENET_216M_CLK_MASK 0x00000400 |
| #define BCHP_CLK_PM_CTRL_2_DIS_ENET_216M_CLK_SHIFT 10 |
| |
| /* CLK :: PM_CTRL_2 :: DIS_XPT_216M_CLK [09:09] */ |
| #define BCHP_CLK_PM_CTRL_2_DIS_XPT_216M_CLK_MASK 0x00000200 |
| #define BCHP_CLK_PM_CTRL_2_DIS_XPT_216M_CLK_SHIFT 9 |
| |
| /* CLK :: PM_CTRL_2 :: DIS_BVNM_216M_CLK [08:08] */ |
| #define BCHP_CLK_PM_CTRL_2_DIS_BVNM_216M_CLK_MASK 0x00000100 |
| #define BCHP_CLK_PM_CTRL_2_DIS_BVNM_216M_CLK_SHIFT 8 |
| |
| /* CLK :: PM_CTRL_2 :: DIS_BVNE_216M_CLK [07:07] */ |
| #define BCHP_CLK_PM_CTRL_2_DIS_BVNE_216M_CLK_MASK 0x00000080 |
| #define BCHP_CLK_PM_CTRL_2_DIS_BVNE_216M_CLK_SHIFT 7 |
| |
| /* CLK :: PM_CTRL_2 :: DIS_AVD_216M_CLK [06:06] */ |
| #define BCHP_CLK_PM_CTRL_2_DIS_AVD_216M_CLK_MASK 0x00000040 |
| #define BCHP_CLK_PM_CTRL_2_DIS_AVD_216M_CLK_SHIFT 6 |
| |
| /* CLK :: PM_CTRL_2 :: DIS_AIO_216M_CLK [05:05] */ |
| #define BCHP_CLK_PM_CTRL_2_DIS_AIO_216M_CLK_MASK 0x00000020 |
| #define BCHP_CLK_PM_CTRL_2_DIS_AIO_216M_CLK_SHIFT 5 |
| |
| /* CLK :: PM_CTRL_2 :: DIS_SATA_PCI_CLK [04:04] */ |
| #define BCHP_CLK_PM_CTRL_2_DIS_SATA_PCI_CLK_MASK 0x00000010 |
| #define BCHP_CLK_PM_CTRL_2_DIS_SATA_PCI_CLK_SHIFT 4 |
| |
| /* CLK :: PM_CTRL_2 :: DIS_AUD_DSP_PROG_CLK [03:03] */ |
| #define BCHP_CLK_PM_CTRL_2_DIS_AUD_DSP_PROG_CLK_MASK 0x00000008 |
| #define BCHP_CLK_PM_CTRL_2_DIS_AUD_DSP_PROG_CLK_SHIFT 3 |
| |
| /* CLK :: PM_CTRL_2 :: DIS_PCI_OUT_CLK [02:02] */ |
| #define BCHP_CLK_PM_CTRL_2_DIS_PCI_OUT_CLK_MASK 0x00000004 |
| #define BCHP_CLK_PM_CTRL_2_DIS_PCI_OUT_CLK_SHIFT 2 |
| |
| /* CLK :: PM_CTRL_2 :: DIS_CPU_297_CLK [01:01] */ |
| #define BCHP_CLK_PM_CTRL_2_DIS_CPU_297_CLK_MASK 0x00000002 |
| #define BCHP_CLK_PM_CTRL_2_DIS_CPU_297_CLK_SHIFT 1 |
| |
| /* CLK :: PM_CTRL_2 :: DIS_HIF_297_CLK [00:00] */ |
| #define BCHP_CLK_PM_CTRL_2_DIS_HIF_297_CLK_MASK 0x00000001 |
| #define BCHP_CLK_PM_CTRL_2_DIS_HIF_297_CLK_SHIFT 0 |
| |
| /*************************************************************************** |
| *MISC - clock_gen block output clock selection |
| ***************************************************************************/ |
| /* CLK :: MISC :: reserved0 [31:12] */ |
| #define BCHP_CLK_MISC_reserved0_MASK 0xfffff000 |
| #define BCHP_CLK_MISC_reserved0_SHIFT 12 |
| |
| /* CLK :: MISC :: DIS_XPT_DGP_CLK [11:11] */ |
| #define BCHP_CLK_MISC_DIS_XPT_DGP_CLK_MASK 0x00000800 |
| #define BCHP_CLK_MISC_DIS_XPT_DGP_CLK_SHIFT 11 |
| |
| /* CLK :: MISC :: DIS_BVNE_DGP_CLK [10:10] */ |
| #define BCHP_CLK_MISC_DIS_BVNE_DGP_CLK_MASK 0x00000400 |
| #define BCHP_CLK_MISC_DIS_BVNE_DGP_CLK_SHIFT 10 |
| |
| /* CLK :: MISC :: FORCE_NO_RAP_PLL_BYPASS [09:09] */ |
| #define BCHP_CLK_MISC_FORCE_NO_RAP_PLL_BYPASS_MASK 0x00000200 |
| #define BCHP_CLK_MISC_FORCE_NO_RAP_PLL_BYPASS_SHIFT 9 |
| |
| /* CLK :: MISC :: VCXO_TEST_IN_SEL [08:08] */ |
| #define BCHP_CLK_MISC_VCXO_TEST_IN_SEL_MASK 0x00000100 |
| #define BCHP_CLK_MISC_VCXO_TEST_IN_SEL_SHIFT 8 |
| |
| /* CLK :: MISC :: INV_VCXO_OUTCLK_SRCA [07:07] */ |
| #define BCHP_CLK_MISC_INV_VCXO_OUTCLK_SRCA_MASK 0x00000080 |
| #define BCHP_CLK_MISC_INV_VCXO_OUTCLK_SRCA_SHIFT 7 |
| |
| /* CLK :: MISC :: DIS_ANA_UHFR_CLK [06:06] */ |
| #define BCHP_CLK_MISC_DIS_ANA_UHFR_CLK_MASK 0x00000040 |
| #define BCHP_CLK_MISC_DIS_ANA_UHFR_CLK_SHIFT 6 |
| |
| /* CLK :: MISC :: DIS_DIGI_UHFR_CLK [05:05] */ |
| #define BCHP_CLK_MISC_DIS_DIGI_UHFR_CLK_MASK 0x00000020 |
| #define BCHP_CLK_MISC_DIS_DIGI_UHFR_CLK_SHIFT 5 |
| |
| /* CLK :: MISC :: UHFR_CLK_INV_SEL [04:04] */ |
| #define BCHP_CLK_MISC_UHFR_CLK_INV_SEL_MASK 0x00000010 |
| #define BCHP_CLK_MISC_UHFR_CLK_INV_SEL_SHIFT 4 |
| |
| /* CLK :: MISC :: UHFR_CLK_SEL [03:03] */ |
| #define BCHP_CLK_MISC_UHFR_CLK_SEL_MASK 0x00000008 |
| #define BCHP_CLK_MISC_UHFR_CLK_SEL_SHIFT 3 |
| |
| /* CLK :: MISC :: reserved1 [02:02] */ |
| #define BCHP_CLK_MISC_reserved1_MASK 0x00000004 |
| #define BCHP_CLK_MISC_reserved1_SHIFT 2 |
| |
| /* CLK :: MISC :: DIS_VEC_VCXO_656_CLK [01:01] */ |
| #define BCHP_CLK_MISC_DIS_VEC_VCXO_656_CLK_MASK 0x00000002 |
| #define BCHP_CLK_MISC_DIS_VEC_VCXO_656_CLK_SHIFT 1 |
| |
| /* CLK :: MISC :: reserved2 [00:00] */ |
| #define BCHP_CLK_MISC_reserved2_MASK 0x00000001 |
| #define BCHP_CLK_MISC_reserved2_SHIFT 0 |
| |
| /*************************************************************************** |
| *THIRD_OT_CONTROL_1 - Low 3rd Overtone Oscillator Control registers |
| ***************************************************************************/ |
| /* CLK :: THIRD_OT_CONTROL_1 :: reserved0 [31:16] */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_reserved0_MASK 0xffff0000 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_reserved0_SHIFT 16 |
| |
| /* CLK :: THIRD_OT_CONTROL_1 :: GAIN_AMPLIFIER_CURRENT_CTRL [15:14] */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_GAIN_AMPLIFIER_CURRENT_CTRL_MASK 0x0000c000 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_GAIN_AMPLIFIER_CURRENT_CTRL_SHIFT 14 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_GAIN_AMPLIFIER_CURRENT_CTRL_ONE_HUNDRED_FIFTY_MICRO_AMP 0 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_GAIN_AMPLIFIER_CURRENT_CTRL_TWO_HUNDRED_MICRO_AMP 1 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_GAIN_AMPLIFIER_CURRENT_CTRL_TWO_HUNDRED_FIFTY_MICRO_AMP 2 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_GAIN_AMPLIFIER_CURRENT_CTRL_THREE_HUNDRED_MICRO_AMP 3 |
| |
| /* CLK :: THIRD_OT_CONTROL_1 :: ICBUF_CURRENT_CTRL [13:12] */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_ICBUF_CURRENT_CTRL_MASK 0x00003000 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_ICBUF_CURRENT_CTRL_SHIFT 12 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_ICBUF_CURRENT_CTRL_ONE_HUNDRED_FIFTY_MICRO_AMP 0 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_ICBUF_CURRENT_CTRL_TWO_HUNDRED_MICRO_AMP 1 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_ICBUF_CURRENT_CTRL_TWO_HUNDRED_FIFTY_MICRO_AMP 2 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_ICBUF_CURRENT_CTRL_THREE_HUNDRED_MICRO_AMP 3 |
| |
| /* CLK :: THIRD_OT_CONTROL_1 :: FREQ_DUBLER_CURRENT_CTRL [11:11] */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_DUBLER_CURRENT_CTRL_MASK 0x00000800 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_DUBLER_CURRENT_CTRL_SHIFT 11 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_DUBLER_CURRENT_CTRL_TWO_HUNDRED_MICRO_AMP 0 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_DUBLER_CURRENT_CTRL_THREE_HUNDRED_MICRO_AMP 1 |
| |
| /* CLK :: THIRD_OT_CONTROL_1 :: AMPLITUDE_LIMITER_ACTIVE [10:10] */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_AMPLITUDE_LIMITER_ACTIVE_MASK 0x00000400 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_AMPLITUDE_LIMITER_ACTIVE_SHIFT 10 |
| |
| /* CLK :: THIRD_OT_CONTROL_1 :: COMMON_MODE_VOLT_CTRL [09:08] */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_COMMON_MODE_VOLT_CTRL_MASK 0x00000300 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_COMMON_MODE_VOLT_CTRL_SHIFT 8 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_COMMON_MODE_VOLT_CTRL_ONE_POINT_FOUR_FIVE_VOLT 1 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_COMMON_MODE_VOLT_CTRL_ONE_POINT_FIVE_FOUR_VOLT 0 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_COMMON_MODE_VOLT_CTRL_ONE_POINT_SIX_TWO_VOLT 2 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_COMMON_MODE_VOLT_CTRL_ONE_POINT_SIX_SIX_VOLT 3 |
| |
| /* CLK :: THIRD_OT_CONTROL_1 :: FREQ_DOUBLER_BYPASS_EN [07:07] */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_DOUBLER_BYPASS_EN_MASK 0x00000080 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_DOUBLER_BYPASS_EN_SHIFT 7 |
| |
| /* CLK :: THIRD_OT_CONTROL_1 :: FREQ_MONITOR_OUTPUT_EN [06:06] */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_MONITOR_OUTPUT_EN_MASK 0x00000040 |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_MONITOR_OUTPUT_EN_SHIFT 6 |
| |
| /* CLK :: THIRD_OT_CONTROL_1 :: reserved1 [05:00] */ |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_reserved1_MASK 0x0000003f |
| #define BCHP_CLK_THIRD_OT_CONTROL_1_reserved1_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_LOCK_STATUS - current lock status of main PLL |
| ***************************************************************************/ |
| /* CLK :: PLL_LOCK_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLK_PLL_LOCK_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLK_PLL_LOCK_STATUS_reserved0_SHIFT 3 |
| |
| /* CLK :: PLL_LOCK_STATUS :: MIPS_PLL_LOCK [02:02] */ |
| #define BCHP_CLK_PLL_LOCK_STATUS_MIPS_PLL_LOCK_MASK 0x00000004 |
| #define BCHP_CLK_PLL_LOCK_STATUS_MIPS_PLL_LOCK_SHIFT 2 |
| |
| /* CLK :: PLL_LOCK_STATUS :: SYSTEM_PLL_0_LOCK [01:01] */ |
| #define BCHP_CLK_PLL_LOCK_STATUS_SYSTEM_PLL_0_LOCK_MASK 0x00000002 |
| #define BCHP_CLK_PLL_LOCK_STATUS_SYSTEM_PLL_0_LOCK_SHIFT 1 |
| |
| /* CLK :: PLL_LOCK_STATUS :: SYSTEM_PLL_1_LOCK [00:00] */ |
| #define BCHP_CLK_PLL_LOCK_STATUS_SYSTEM_PLL_1_LOCK_MASK 0x00000001 |
| #define BCHP_CLK_PLL_LOCK_STATUS_SYSTEM_PLL_1_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *SYS_PLL_1_CTLBUS_HI - SYS 1 PLL control bus lower word |
| ***************************************************************************/ |
| /* CLK :: SYS_PLL_1_CTLBUS_HI :: reserved0 [31:06] */ |
| #define BCHP_CLK_SYS_PLL_1_CTLBUS_HI_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLK_SYS_PLL_1_CTLBUS_HI_reserved0_SHIFT 6 |
| |
| /* CLK :: SYS_PLL_1_CTLBUS_HI :: CTL_BITS_37_32 [05:00] */ |
| #define BCHP_CLK_SYS_PLL_1_CTLBUS_HI_CTL_BITS_37_32_MASK 0x0000003f |
| #define BCHP_CLK_SYS_PLL_1_CTLBUS_HI_CTL_BITS_37_32_SHIFT 0 |
| |
| /*************************************************************************** |
| *SYS_PLL_1_CTLBUS_LO - SYS 1 PLL control bus lower word |
| ***************************************************************************/ |
| /* CLK :: SYS_PLL_1_CTLBUS_LO :: CTL_BITS_31_0 [31:00] */ |
| #define BCHP_CLK_SYS_PLL_1_CTLBUS_LO_CTL_BITS_31_0_MASK 0xffffffff |
| #define BCHP_CLK_SYS_PLL_1_CTLBUS_LO_CTL_BITS_31_0_SHIFT 0 |
| #define BCHP_CLK_SYS_PLL_1_CTLBUS_LO_CTL_BITS_31_0_Above_1p6GHz 939525888 |
| |
| /*************************************************************************** |
| *SCRATCH - clock_gen Scratch register |
| ***************************************************************************/ |
| /* CLK :: SCRATCH :: VALUE [31:00] */ |
| #define BCHP_CLK_SCRATCH_VALUE_MASK 0xffffffff |
| #define BCHP_CLK_SCRATCH_VALUE_SHIFT 0 |
| |
| #endif /* #ifndef BCHP_CLK_H__ */ |
| |
| /* End of File */ |
