| /*************************************************************************** |
| * Copyright (c) 1999-2011, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Fri Apr 1 16:38:02 2011 |
| * MD5 Checksum d03d08c4839c3311c9d35c4cd5e10373 |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_ddr40_phy_word_lane_1_0.h $ |
| * |
| * Hydra_Software_Devel/1 4/4/11 1:09p albertl |
| * SW7344-40: Initial revision. |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_DDR40_PHY_WORD_LANE_1_0_H__ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_H__ |
| |
| /*************************************************************************** |
| *DDR40_PHY_WORD_LANE_1_0 - DDR40 DDR40 word lane #1 control registers 0 |
| ***************************************************************************/ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN 0x00a06400 /* Read Enable Byte VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W 0x00a06404 /* Write Byte VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P 0x00a06408 /* Read Byte DQSP VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N 0x00a0640c /* Read Byte DQSN VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W 0x00a06410 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W 0x00a06414 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W 0x00a06418 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W 0x00a0641c /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W 0x00a06420 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W 0x00a06424 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W 0x00a06428 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W 0x00a0642c /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W 0x00a06430 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x00a06434 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x00a06438 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x00a0643c /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x00a06440 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x00a06444 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x00a06448 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x00a0644c /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x00a06450 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x00a06454 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x00a06458 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x00a0645c /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x00a06460 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x00a06464 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x00a06468 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x00a0646c /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x00a06470 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x00a06474 /* Read Enable Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W 0x00a064a4 /* Write Byte VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P 0x00a064a8 /* Read Byte DQSP VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N 0x00a064ac /* Read Byte DQSN VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W 0x00a064b0 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W 0x00a064b4 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W 0x00a064b8 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W 0x00a064bc /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W 0x00a064c0 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W 0x00a064c4 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W 0x00a064c8 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W 0x00a064cc /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W 0x00a064d0 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x00a064d4 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x00a064d8 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x00a064dc /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x00a064e0 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x00a064e4 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x00a064e8 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x00a064ec /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x00a064f0 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x00a064f4 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x00a064f8 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x00a064fc /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x00a06500 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x00a06504 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x00a06508 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x00a0650c /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x00a06510 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x00a06514 /* Read Enable Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x00a06528 /* Read DQSP VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x00a0652c /* Read DQSN VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x00a06530 /* Read DQ-P VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x00a06534 /* Read DQ-N VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W 0x00a06538 /* Write DQ Byte VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x00a0653c /* Write DQ Bit VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x00a06548 /* Read DQSP VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x00a0654c /* Read DQSN VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x00a06550 /* Read DQ-P VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x00a06554 /* Read DQ-N VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W 0x00a06558 /* Write DQ Byte VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x00a0655c /* Write DQ Bit VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_DATA_DLY 0x00a06560 /* Word Lane read channel control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_CONTROL 0x00a06564 /* Word Lane read channel control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_0 0x00a06570 /* Read fifo data register, first data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_1 0x00a06574 /* Read fifo data register, second data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_2 0x00a06578 /* Read fifo data register, third data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_3 0x00a0657c /* Read fifo data register, fourth data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_0 0x00a06580 /* Read fifo data register, first data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_1 0x00a06584 /* Read fifo data register, second data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_2 0x00a06588 /* Read fifo data register, third data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_3 0x00a0658c /* Read fifo data register, fourth data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_STATUS 0x00a06590 /* Read fifo status register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_CLEAR 0x00a06594 /* Read fifo status clear register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL 0x00a065a0 /* Idle mode SSTL pad control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL 0x00a065a4 /* SSTL pad drive characteristics control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_CLOCK_PAD_DISABLE 0x00a065a8 /* Clock pad disable register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_WR_PREAMBLE_MODE 0x00a065ac /* Write cycle preamble control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ 0x00a065b0 /* PHYBIST mode VDL step select adjustment register */ |
| |
| #endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_1_0_H__ */ |
| |
| /* End of File */ |