| /*************************************************************************** |
| * Copyright (c) 1999-2009, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Wed Nov 18 01:13:54 2009 |
| * MD5 Checksum 8e4822e2d8c445f841e653dc06da5e41 |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: /magnum/basemodules/chp/7340/rdb/b0/bchp_pm_l2.h $ |
| * |
| * Hydra_Software_Devel/1 11/18/09 9:25a albertl |
| * SW7340-102: Initial revision. |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_PM_L2_H__ |
| #define BCHP_PM_L2_H__ |
| |
| /*************************************************************************** |
| *PM_L2 - Registers for the power management block's L2 interrupt controller |
| ***************************************************************************/ |
| #define BCHP_PM_L2_CPU_STATUS 0x00401c00 /* CPU interrupt Status Register */ |
| #define BCHP_PM_L2_CPU_SET 0x00401c04 /* CPU interrupt Set Register */ |
| #define BCHP_PM_L2_CPU_CLEAR 0x00401c08 /* CPU interrupt Clear Register */ |
| #define BCHP_PM_L2_CPU_MASK_STATUS 0x00401c0c /* CPU interrupt Mask Status Register */ |
| #define BCHP_PM_L2_CPU_MASK_SET 0x00401c10 /* CPU interrupt Mask Set Register */ |
| #define BCHP_PM_L2_CPU_MASK_CLEAR 0x00401c14 /* CPU interrupt Mask Clear Register */ |
| #define BCHP_PM_L2_PCI_STATUS 0x00401c18 /* PCI interrupt Status Register */ |
| #define BCHP_PM_L2_PCI_SET 0x00401c1c /* PCI interrupt Set Register */ |
| #define BCHP_PM_L2_PCI_CLEAR 0x00401c20 /* PCI interrupt Clear Register */ |
| #define BCHP_PM_L2_PCI_MASK_STATUS 0x00401c24 /* PCI interrupt Mask Status Register */ |
| #define BCHP_PM_L2_PCI_MASK_SET 0x00401c28 /* PCI interrupt Mask Set Register */ |
| #define BCHP_PM_L2_PCI_MASK_CLEAR 0x00401c2c /* PCI interrupt Mask Clear Register */ |
| |
| /*************************************************************************** |
| *CPU_STATUS - CPU interrupt Status Register |
| ***************************************************************************/ |
| /* PM_L2 :: CPU_STATUS :: reserved0 [31:18] */ |
| #define BCHP_PM_L2_CPU_STATUS_reserved0_MASK 0xfffc0000 |
| #define BCHP_PM_L2_CPU_STATUS_reserved0_SHIFT 18 |
| |
| /* PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_0 [17:17] */ |
| #define BCHP_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x00020000 |
| #define BCHP_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 17 |
| |
| /* PM_L2 :: CPU_STATUS :: XPT_PMU [16:16] */ |
| #define BCHP_PM_L2_CPU_STATUS_XPT_PMU_MASK 0x00010000 |
| #define BCHP_PM_L2_CPU_STATUS_XPT_PMU_SHIFT 16 |
| |
| /* PM_L2 :: CPU_STATUS :: FTM [15:15] */ |
| #define BCHP_PM_L2_CPU_STATUS_FTM_MASK 0x00008000 |
| #define BCHP_PM_L2_CPU_STATUS_FTM_SHIFT 15 |
| |
| /* PM_L2 :: CPU_STATUS :: QPSK_RCVR_1 [14:14] */ |
| #define BCHP_PM_L2_CPU_STATUS_QPSK_RCVR_1_MASK 0x00004000 |
| #define BCHP_PM_L2_CPU_STATUS_QPSK_RCVR_1_SHIFT 14 |
| |
| /* PM_L2 :: CPU_STATUS :: QPSK_RCVR_0 [13:13] */ |
| #define BCHP_PM_L2_CPU_STATUS_QPSK_RCVR_0_MASK 0x00002000 |
| #define BCHP_PM_L2_CPU_STATUS_QPSK_RCVR_0_SHIFT 13 |
| |
| /* PM_L2 :: CPU_STATUS :: SDS0_AFEC [12:12] */ |
| #define BCHP_PM_L2_CPU_STATUS_SDS0_AFEC_MASK 0x00001000 |
| #define BCHP_PM_L2_CPU_STATUS_SDS0_AFEC_SHIFT 12 |
| |
| /* PM_L2 :: CPU_STATUS :: SDS0_TFEC [11:11] */ |
| #define BCHP_PM_L2_CPU_STATUS_SDS0_TFEC_MASK 0x00000800 |
| #define BCHP_PM_L2_CPU_STATUS_SDS0_TFEC_SHIFT 11 |
| |
| /* PM_L2 :: CPU_STATUS :: SDS0_RCVR_1 [10:10] */ |
| #define BCHP_PM_L2_CPU_STATUS_SDS0_RCVR_1_MASK 0x00000400 |
| #define BCHP_PM_L2_CPU_STATUS_SDS0_RCVR_1_SHIFT 10 |
| |
| /* PM_L2 :: CPU_STATUS :: SDS0_RCVR_0 [09:09] */ |
| #define BCHP_PM_L2_CPU_STATUS_SDS0_RCVR_0_MASK 0x00000200 |
| #define BCHP_PM_L2_CPU_STATUS_SDS0_RCVR_0_SHIFT 9 |
| |
| /* PM_L2 :: CPU_STATUS :: WOL_ENET [08:08] */ |
| #define BCHP_PM_L2_CPU_STATUS_WOL_ENET_MASK 0x00000100 |
| #define BCHP_PM_L2_CPU_STATUS_WOL_ENET_SHIFT 8 |
| |
| /* PM_L2 :: CPU_STATUS :: WOL_MOCA [07:07] */ |
| #define BCHP_PM_L2_CPU_STATUS_WOL_MOCA_MASK 0x00000080 |
| #define BCHP_PM_L2_CPU_STATUS_WOL_MOCA_SHIFT 7 |
| |
| /* PM_L2 :: CPU_STATUS :: UHFR [06:06] */ |
| #define BCHP_PM_L2_CPU_STATUS_UHFR_MASK 0x00000040 |
| #define BCHP_PM_L2_CPU_STATUS_UHFR_SHIFT 6 |
| |
| /* PM_L2 :: CPU_STATUS :: GPIO [05:05] */ |
| #define BCHP_PM_L2_CPU_STATUS_GPIO_MASK 0x00000020 |
| #define BCHP_PM_L2_CPU_STATUS_GPIO_SHIFT 5 |
| |
| /* PM_L2 :: CPU_STATUS :: NMI_B_INTR [04:04] */ |
| #define BCHP_PM_L2_CPU_STATUS_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_PM_L2_CPU_STATUS_NMI_B_INTR_SHIFT 4 |
| |
| /* PM_L2 :: CPU_STATUS :: TIMER_INTR [03:03] */ |
| #define BCHP_PM_L2_CPU_STATUS_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_PM_L2_CPU_STATUS_TIMER_INTR_SHIFT 3 |
| |
| /* PM_L2 :: CPU_STATUS :: KPD_INTR [02:02] */ |
| #define BCHP_PM_L2_CPU_STATUS_KPD_INTR_MASK 0x00000004 |
| #define BCHP_PM_L2_CPU_STATUS_KPD_INTR_SHIFT 2 |
| |
| /* PM_L2 :: CPU_STATUS :: IRR_INTR [01:01] */ |
| #define BCHP_PM_L2_CPU_STATUS_IRR_INTR_MASK 0x00000002 |
| #define BCHP_PM_L2_CPU_STATUS_IRR_INTR_SHIFT 1 |
| |
| /* PM_L2 :: CPU_STATUS :: CEC_INTR [00:00] */ |
| #define BCHP_PM_L2_CPU_STATUS_CEC_INTR_MASK 0x00000001 |
| #define BCHP_PM_L2_CPU_STATUS_CEC_INTR_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU_SET - CPU interrupt Set Register |
| ***************************************************************************/ |
| /* PM_L2 :: CPU_SET :: reserved0 [31:18] */ |
| #define BCHP_PM_L2_CPU_SET_reserved0_MASK 0xfffc0000 |
| #define BCHP_PM_L2_CPU_SET_reserved0_SHIFT 18 |
| |
| /* PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_0 [17:17] */ |
| #define BCHP_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_MASK 0x00020000 |
| #define BCHP_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_SHIFT 17 |
| |
| /* PM_L2 :: CPU_SET :: XPT_PMU [16:16] */ |
| #define BCHP_PM_L2_CPU_SET_XPT_PMU_MASK 0x00010000 |
| #define BCHP_PM_L2_CPU_SET_XPT_PMU_SHIFT 16 |
| |
| /* PM_L2 :: CPU_SET :: FTM [15:15] */ |
| #define BCHP_PM_L2_CPU_SET_FTM_MASK 0x00008000 |
| #define BCHP_PM_L2_CPU_SET_FTM_SHIFT 15 |
| |
| /* PM_L2 :: CPU_SET :: QPSK_RCVR_1 [14:14] */ |
| #define BCHP_PM_L2_CPU_SET_QPSK_RCVR_1_MASK 0x00004000 |
| #define BCHP_PM_L2_CPU_SET_QPSK_RCVR_1_SHIFT 14 |
| |
| /* PM_L2 :: CPU_SET :: QPSK_RCVR_0 [13:13] */ |
| #define BCHP_PM_L2_CPU_SET_QPSK_RCVR_0_MASK 0x00002000 |
| #define BCHP_PM_L2_CPU_SET_QPSK_RCVR_0_SHIFT 13 |
| |
| /* PM_L2 :: CPU_SET :: SDS0_AFEC [12:12] */ |
| #define BCHP_PM_L2_CPU_SET_SDS0_AFEC_MASK 0x00001000 |
| #define BCHP_PM_L2_CPU_SET_SDS0_AFEC_SHIFT 12 |
| |
| /* PM_L2 :: CPU_SET :: SDS0_TFEC [11:11] */ |
| #define BCHP_PM_L2_CPU_SET_SDS0_TFEC_MASK 0x00000800 |
| #define BCHP_PM_L2_CPU_SET_SDS0_TFEC_SHIFT 11 |
| |
| /* PM_L2 :: CPU_SET :: SDS0_RCVR_1 [10:10] */ |
| #define BCHP_PM_L2_CPU_SET_SDS0_RCVR_1_MASK 0x00000400 |
| #define BCHP_PM_L2_CPU_SET_SDS0_RCVR_1_SHIFT 10 |
| |
| /* PM_L2 :: CPU_SET :: SDS0_RCVR_0 [09:09] */ |
| #define BCHP_PM_L2_CPU_SET_SDS0_RCVR_0_MASK 0x00000200 |
| #define BCHP_PM_L2_CPU_SET_SDS0_RCVR_0_SHIFT 9 |
| |
| /* PM_L2 :: CPU_SET :: WOL_ENET [08:08] */ |
| #define BCHP_PM_L2_CPU_SET_WOL_ENET_MASK 0x00000100 |
| #define BCHP_PM_L2_CPU_SET_WOL_ENET_SHIFT 8 |
| |
| /* PM_L2 :: CPU_SET :: WOL_MOCA [07:07] */ |
| #define BCHP_PM_L2_CPU_SET_WOL_MOCA_MASK 0x00000080 |
| #define BCHP_PM_L2_CPU_SET_WOL_MOCA_SHIFT 7 |
| |
| /* PM_L2 :: CPU_SET :: UHFR [06:06] */ |
| #define BCHP_PM_L2_CPU_SET_UHFR_MASK 0x00000040 |
| #define BCHP_PM_L2_CPU_SET_UHFR_SHIFT 6 |
| |
| /* PM_L2 :: CPU_SET :: GPIO [05:05] */ |
| #define BCHP_PM_L2_CPU_SET_GPIO_MASK 0x00000020 |
| #define BCHP_PM_L2_CPU_SET_GPIO_SHIFT 5 |
| |
| /* PM_L2 :: CPU_SET :: NMI_B_INTR [04:04] */ |
| #define BCHP_PM_L2_CPU_SET_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_PM_L2_CPU_SET_NMI_B_INTR_SHIFT 4 |
| |
| /* PM_L2 :: CPU_SET :: TIMER_INTR [03:03] */ |
| #define BCHP_PM_L2_CPU_SET_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_PM_L2_CPU_SET_TIMER_INTR_SHIFT 3 |
| |
| /* PM_L2 :: CPU_SET :: KPD_INTR [02:02] */ |
| #define BCHP_PM_L2_CPU_SET_KPD_INTR_MASK 0x00000004 |
| #define BCHP_PM_L2_CPU_SET_KPD_INTR_SHIFT 2 |
| |
| /* PM_L2 :: CPU_SET :: IRR_INTR [01:01] */ |
| #define BCHP_PM_L2_CPU_SET_IRR_INTR_MASK 0x00000002 |
| #define BCHP_PM_L2_CPU_SET_IRR_INTR_SHIFT 1 |
| |
| /* PM_L2 :: CPU_SET :: CEC_INTR [00:00] */ |
| #define BCHP_PM_L2_CPU_SET_CEC_INTR_MASK 0x00000001 |
| #define BCHP_PM_L2_CPU_SET_CEC_INTR_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU_CLEAR - CPU interrupt Clear Register |
| ***************************************************************************/ |
| /* PM_L2 :: CPU_CLEAR :: reserved0 [31:18] */ |
| #define BCHP_PM_L2_CPU_CLEAR_reserved0_MASK 0xfffc0000 |
| #define BCHP_PM_L2_CPU_CLEAR_reserved0_SHIFT 18 |
| |
| /* PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_0 [17:17] */ |
| #define BCHP_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x00020000 |
| #define BCHP_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 17 |
| |
| /* PM_L2 :: CPU_CLEAR :: XPT_PMU [16:16] */ |
| #define BCHP_PM_L2_CPU_CLEAR_XPT_PMU_MASK 0x00010000 |
| #define BCHP_PM_L2_CPU_CLEAR_XPT_PMU_SHIFT 16 |
| |
| /* PM_L2 :: CPU_CLEAR :: FTM [15:15] */ |
| #define BCHP_PM_L2_CPU_CLEAR_FTM_MASK 0x00008000 |
| #define BCHP_PM_L2_CPU_CLEAR_FTM_SHIFT 15 |
| |
| /* PM_L2 :: CPU_CLEAR :: QPSK_RCVR_1 [14:14] */ |
| #define BCHP_PM_L2_CPU_CLEAR_QPSK_RCVR_1_MASK 0x00004000 |
| #define BCHP_PM_L2_CPU_CLEAR_QPSK_RCVR_1_SHIFT 14 |
| |
| /* PM_L2 :: CPU_CLEAR :: QPSK_RCVR_0 [13:13] */ |
| #define BCHP_PM_L2_CPU_CLEAR_QPSK_RCVR_0_MASK 0x00002000 |
| #define BCHP_PM_L2_CPU_CLEAR_QPSK_RCVR_0_SHIFT 13 |
| |
| /* PM_L2 :: CPU_CLEAR :: SDS0_AFEC [12:12] */ |
| #define BCHP_PM_L2_CPU_CLEAR_SDS0_AFEC_MASK 0x00001000 |
| #define BCHP_PM_L2_CPU_CLEAR_SDS0_AFEC_SHIFT 12 |
| |
| /* PM_L2 :: CPU_CLEAR :: SDS0_TFEC [11:11] */ |
| #define BCHP_PM_L2_CPU_CLEAR_SDS0_TFEC_MASK 0x00000800 |
| #define BCHP_PM_L2_CPU_CLEAR_SDS0_TFEC_SHIFT 11 |
| |
| /* PM_L2 :: CPU_CLEAR :: SDS0_RCVR_1 [10:10] */ |
| #define BCHP_PM_L2_CPU_CLEAR_SDS0_RCVR_1_MASK 0x00000400 |
| #define BCHP_PM_L2_CPU_CLEAR_SDS0_RCVR_1_SHIFT 10 |
| |
| /* PM_L2 :: CPU_CLEAR :: SDS0_RCVR_0 [09:09] */ |
| #define BCHP_PM_L2_CPU_CLEAR_SDS0_RCVR_0_MASK 0x00000200 |
| #define BCHP_PM_L2_CPU_CLEAR_SDS0_RCVR_0_SHIFT 9 |
| |
| /* PM_L2 :: CPU_CLEAR :: WOL_ENET [08:08] */ |
| #define BCHP_PM_L2_CPU_CLEAR_WOL_ENET_MASK 0x00000100 |
| #define BCHP_PM_L2_CPU_CLEAR_WOL_ENET_SHIFT 8 |
| |
| /* PM_L2 :: CPU_CLEAR :: WOL_MOCA [07:07] */ |
| #define BCHP_PM_L2_CPU_CLEAR_WOL_MOCA_MASK 0x00000080 |
| #define BCHP_PM_L2_CPU_CLEAR_WOL_MOCA_SHIFT 7 |
| |
| /* PM_L2 :: CPU_CLEAR :: UHFR [06:06] */ |
| #define BCHP_PM_L2_CPU_CLEAR_UHFR_MASK 0x00000040 |
| #define BCHP_PM_L2_CPU_CLEAR_UHFR_SHIFT 6 |
| |
| /* PM_L2 :: CPU_CLEAR :: GPIO [05:05] */ |
| #define BCHP_PM_L2_CPU_CLEAR_GPIO_MASK 0x00000020 |
| #define BCHP_PM_L2_CPU_CLEAR_GPIO_SHIFT 5 |
| |
| /* PM_L2 :: CPU_CLEAR :: NMI_B_INTR [04:04] */ |
| #define BCHP_PM_L2_CPU_CLEAR_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_PM_L2_CPU_CLEAR_NMI_B_INTR_SHIFT 4 |
| |
| /* PM_L2 :: CPU_CLEAR :: TIMER_INTR [03:03] */ |
| #define BCHP_PM_L2_CPU_CLEAR_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_PM_L2_CPU_CLEAR_TIMER_INTR_SHIFT 3 |
| |
| /* PM_L2 :: CPU_CLEAR :: KPD_INTR [02:02] */ |
| #define BCHP_PM_L2_CPU_CLEAR_KPD_INTR_MASK 0x00000004 |
| #define BCHP_PM_L2_CPU_CLEAR_KPD_INTR_SHIFT 2 |
| |
| /* PM_L2 :: CPU_CLEAR :: IRR_INTR [01:01] */ |
| #define BCHP_PM_L2_CPU_CLEAR_IRR_INTR_MASK 0x00000002 |
| #define BCHP_PM_L2_CPU_CLEAR_IRR_INTR_SHIFT 1 |
| |
| /* PM_L2 :: CPU_CLEAR :: CEC_INTR [00:00] */ |
| #define BCHP_PM_L2_CPU_CLEAR_CEC_INTR_MASK 0x00000001 |
| #define BCHP_PM_L2_CPU_CLEAR_CEC_INTR_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU_MASK_STATUS - CPU interrupt Mask Status Register |
| ***************************************************************************/ |
| /* PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:18] */ |
| #define BCHP_PM_L2_CPU_MASK_STATUS_reserved0_MASK 0xfffc0000 |
| #define BCHP_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT 18 |
| |
| /* PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [17:17] */ |
| #define BCHP_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x00020000 |
| #define BCHP_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 17 |
| |
| /* PM_L2 :: CPU_MASK_STATUS :: XPT_PMU [16:16] */ |
| #define BCHP_PM_L2_CPU_MASK_STATUS_XPT_PMU_MASK 0x00010000 |
| #define BCHP_PM_L2_CPU_MASK_STATUS_XPT_PMU_SHIFT 16 |
| |
| /* PM_L2 :: CPU_MASK_STATUS :: FTM [15:15] */ |
| #define BCHP_PM_L2_CPU_MASK_STATUS_FTM_MASK 0x00008000 |
| #define BCHP_PM_L2_CPU_MASK_STATUS_FTM_SHIFT 15 |
| |
| /* PM_L2 :: CPU_MASK_STATUS :: QPSK_RCVR_1 [14:14] */ |
| #define BCHP_PM_L2_CPU_MASK_STATUS_QPSK_RCVR_1_MASK 0x00004000 |
| #define BCHP_PM_L2_CPU_MASK_STATUS_QPSK_RCVR_1_SHIFT 14 |
| |
| /* PM_L2 :: CPU_MASK_STATUS :: QPSK_RCVR_0 [13:13] */ |
| #define BCHP_PM_L2_CPU_MASK_STATUS_QPSK_RCVR_0_MASK 0x00002000 |
| #define BCHP_PM_L2_CPU_MASK_STATUS_QPSK_RCVR_0_SHIFT 13 |
| |
| /* PM_L2 :: CPU_MASK_STATUS :: SDS0_AFEC [12:12] */ |
| #define BCHP_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_MASK 0x00001000 |
| #define BCHP_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_SHIFT 12 |
| |
| /* PM_L2 :: CPU_MASK_STATUS :: SDS0_TFEC [11:11] */ |
| #define BCHP_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_MASK 0x00000800 |
| #define BCHP_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_SHIFT 11 |
| |
| /* PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_1 [10:10] */ |
| #define BCHP_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_MASK 0x00000400 |
| #define BCHP_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_SHIFT 10 |
| |
| /* PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_0 [09:09] */ |
| #define BCHP_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_MASK 0x00000200 |
| #define BCHP_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_SHIFT 9 |
| |
| /* PM_L2 :: CPU_MASK_STATUS :: WOL_ENET [08:08] */ |
| #define BCHP_PM_L2_CPU_MASK_STATUS_WOL_ENET_MASK 0x00000100 |
| #define BCHP_PM_L2_CPU_MASK_STATUS_WOL_ENET_SHIFT 8 |
| |
| /* PM_L2 :: CPU_MASK_STATUS :: WOL_MOCA [07:07] */ |
| #define BCHP_PM_L2_CPU_MASK_STATUS_WOL_MOCA_MASK 0x00000080 |
| #define BCHP_PM_L2_CPU_MASK_STATUS_WOL_MOCA_SHIFT 7 |
| |
| /* PM_L2 :: CPU_MASK_STATUS :: UHFR [06:06] */ |
| #define BCHP_PM_L2_CPU_MASK_STATUS_UHFR_MASK 0x00000040 |
| #define BCHP_PM_L2_CPU_MASK_STATUS_UHFR_SHIFT 6 |
| |
| /* PM_L2 :: CPU_MASK_STATUS :: GPIO [05:05] */ |
| #define BCHP_PM_L2_CPU_MASK_STATUS_GPIO_MASK 0x00000020 |
| #define BCHP_PM_L2_CPU_MASK_STATUS_GPIO_SHIFT 5 |
| |
| /* PM_L2 :: CPU_MASK_STATUS :: NMI_B_INTR [04:04] */ |
| #define BCHP_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_SHIFT 4 |
| |
| /* PM_L2 :: CPU_MASK_STATUS :: TIMER_INTR [03:03] */ |
| #define BCHP_PM_L2_CPU_MASK_STATUS_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_PM_L2_CPU_MASK_STATUS_TIMER_INTR_SHIFT 3 |
| |
| /* PM_L2 :: CPU_MASK_STATUS :: KPD_INTR [02:02] */ |
| #define BCHP_PM_L2_CPU_MASK_STATUS_KPD_INTR_MASK 0x00000004 |
| #define BCHP_PM_L2_CPU_MASK_STATUS_KPD_INTR_SHIFT 2 |
| |
| /* PM_L2 :: CPU_MASK_STATUS :: IRR_INTR [01:01] */ |
| #define BCHP_PM_L2_CPU_MASK_STATUS_IRR_INTR_MASK 0x00000002 |
| #define BCHP_PM_L2_CPU_MASK_STATUS_IRR_INTR_SHIFT 1 |
| |
| /* PM_L2 :: CPU_MASK_STATUS :: CEC_INTR [00:00] */ |
| #define BCHP_PM_L2_CPU_MASK_STATUS_CEC_INTR_MASK 0x00000001 |
| #define BCHP_PM_L2_CPU_MASK_STATUS_CEC_INTR_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU_MASK_SET - CPU interrupt Mask Set Register |
| ***************************************************************************/ |
| /* PM_L2 :: CPU_MASK_SET :: reserved0 [31:18] */ |
| #define BCHP_PM_L2_CPU_MASK_SET_reserved0_MASK 0xfffc0000 |
| #define BCHP_PM_L2_CPU_MASK_SET_reserved0_SHIFT 18 |
| |
| /* PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_0 [17:17] */ |
| #define BCHP_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK 0x00020000 |
| #define BCHP_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT 17 |
| |
| /* PM_L2 :: CPU_MASK_SET :: XPT_PMU [16:16] */ |
| #define BCHP_PM_L2_CPU_MASK_SET_XPT_PMU_MASK 0x00010000 |
| #define BCHP_PM_L2_CPU_MASK_SET_XPT_PMU_SHIFT 16 |
| |
| /* PM_L2 :: CPU_MASK_SET :: FTM [15:15] */ |
| #define BCHP_PM_L2_CPU_MASK_SET_FTM_MASK 0x00008000 |
| #define BCHP_PM_L2_CPU_MASK_SET_FTM_SHIFT 15 |
| |
| /* PM_L2 :: CPU_MASK_SET :: QPSK_RCVR_1 [14:14] */ |
| #define BCHP_PM_L2_CPU_MASK_SET_QPSK_RCVR_1_MASK 0x00004000 |
| #define BCHP_PM_L2_CPU_MASK_SET_QPSK_RCVR_1_SHIFT 14 |
| |
| /* PM_L2 :: CPU_MASK_SET :: QPSK_RCVR_0 [13:13] */ |
| #define BCHP_PM_L2_CPU_MASK_SET_QPSK_RCVR_0_MASK 0x00002000 |
| #define BCHP_PM_L2_CPU_MASK_SET_QPSK_RCVR_0_SHIFT 13 |
| |
| /* PM_L2 :: CPU_MASK_SET :: SDS0_AFEC [12:12] */ |
| #define BCHP_PM_L2_CPU_MASK_SET_SDS0_AFEC_MASK 0x00001000 |
| #define BCHP_PM_L2_CPU_MASK_SET_SDS0_AFEC_SHIFT 12 |
| |
| /* PM_L2 :: CPU_MASK_SET :: SDS0_TFEC [11:11] */ |
| #define BCHP_PM_L2_CPU_MASK_SET_SDS0_TFEC_MASK 0x00000800 |
| #define BCHP_PM_L2_CPU_MASK_SET_SDS0_TFEC_SHIFT 11 |
| |
| /* PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_1 [10:10] */ |
| #define BCHP_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_MASK 0x00000400 |
| #define BCHP_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_SHIFT 10 |
| |
| /* PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_0 [09:09] */ |
| #define BCHP_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_MASK 0x00000200 |
| #define BCHP_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_SHIFT 9 |
| |
| /* PM_L2 :: CPU_MASK_SET :: WOL_ENET [08:08] */ |
| #define BCHP_PM_L2_CPU_MASK_SET_WOL_ENET_MASK 0x00000100 |
| #define BCHP_PM_L2_CPU_MASK_SET_WOL_ENET_SHIFT 8 |
| |
| /* PM_L2 :: CPU_MASK_SET :: WOL_MOCA [07:07] */ |
| #define BCHP_PM_L2_CPU_MASK_SET_WOL_MOCA_MASK 0x00000080 |
| #define BCHP_PM_L2_CPU_MASK_SET_WOL_MOCA_SHIFT 7 |
| |
| /* PM_L2 :: CPU_MASK_SET :: UHFR [06:06] */ |
| #define BCHP_PM_L2_CPU_MASK_SET_UHFR_MASK 0x00000040 |
| #define BCHP_PM_L2_CPU_MASK_SET_UHFR_SHIFT 6 |
| |
| /* PM_L2 :: CPU_MASK_SET :: GPIO [05:05] */ |
| #define BCHP_PM_L2_CPU_MASK_SET_GPIO_MASK 0x00000020 |
| #define BCHP_PM_L2_CPU_MASK_SET_GPIO_SHIFT 5 |
| |
| /* PM_L2 :: CPU_MASK_SET :: NMI_B_INTR [04:04] */ |
| #define BCHP_PM_L2_CPU_MASK_SET_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_PM_L2_CPU_MASK_SET_NMI_B_INTR_SHIFT 4 |
| |
| /* PM_L2 :: CPU_MASK_SET :: TIMER_INTR [03:03] */ |
| #define BCHP_PM_L2_CPU_MASK_SET_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_PM_L2_CPU_MASK_SET_TIMER_INTR_SHIFT 3 |
| |
| /* PM_L2 :: CPU_MASK_SET :: KPD_INTR [02:02] */ |
| #define BCHP_PM_L2_CPU_MASK_SET_KPD_INTR_MASK 0x00000004 |
| #define BCHP_PM_L2_CPU_MASK_SET_KPD_INTR_SHIFT 2 |
| |
| /* PM_L2 :: CPU_MASK_SET :: IRR_INTR [01:01] */ |
| #define BCHP_PM_L2_CPU_MASK_SET_IRR_INTR_MASK 0x00000002 |
| #define BCHP_PM_L2_CPU_MASK_SET_IRR_INTR_SHIFT 1 |
| |
| /* PM_L2 :: CPU_MASK_SET :: CEC_INTR [00:00] */ |
| #define BCHP_PM_L2_CPU_MASK_SET_CEC_INTR_MASK 0x00000001 |
| #define BCHP_PM_L2_CPU_MASK_SET_CEC_INTR_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register |
| ***************************************************************************/ |
| /* PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:18] */ |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_reserved0_MASK 0xfffc0000 |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT 18 |
| |
| /* PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [17:17] */ |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x00020000 |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 17 |
| |
| /* PM_L2 :: CPU_MASK_CLEAR :: XPT_PMU [16:16] */ |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_XPT_PMU_MASK 0x00010000 |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_XPT_PMU_SHIFT 16 |
| |
| /* PM_L2 :: CPU_MASK_CLEAR :: FTM [15:15] */ |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_FTM_MASK 0x00008000 |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_FTM_SHIFT 15 |
| |
| /* PM_L2 :: CPU_MASK_CLEAR :: QPSK_RCVR_1 [14:14] */ |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_QPSK_RCVR_1_MASK 0x00004000 |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_QPSK_RCVR_1_SHIFT 14 |
| |
| /* PM_L2 :: CPU_MASK_CLEAR :: QPSK_RCVR_0 [13:13] */ |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_QPSK_RCVR_0_MASK 0x00002000 |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_QPSK_RCVR_0_SHIFT 13 |
| |
| /* PM_L2 :: CPU_MASK_CLEAR :: SDS0_AFEC [12:12] */ |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_MASK 0x00001000 |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_SHIFT 12 |
| |
| /* PM_L2 :: CPU_MASK_CLEAR :: SDS0_TFEC [11:11] */ |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_MASK 0x00000800 |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_SHIFT 11 |
| |
| /* PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_1 [10:10] */ |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_MASK 0x00000400 |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_SHIFT 10 |
| |
| /* PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_0 [09:09] */ |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_MASK 0x00000200 |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_SHIFT 9 |
| |
| /* PM_L2 :: CPU_MASK_CLEAR :: WOL_ENET [08:08] */ |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_WOL_ENET_MASK 0x00000100 |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_WOL_ENET_SHIFT 8 |
| |
| /* PM_L2 :: CPU_MASK_CLEAR :: WOL_MOCA [07:07] */ |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_WOL_MOCA_MASK 0x00000080 |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_WOL_MOCA_SHIFT 7 |
| |
| /* PM_L2 :: CPU_MASK_CLEAR :: UHFR [06:06] */ |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_UHFR_MASK 0x00000040 |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_UHFR_SHIFT 6 |
| |
| /* PM_L2 :: CPU_MASK_CLEAR :: GPIO [05:05] */ |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_GPIO_MASK 0x00000020 |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_GPIO_SHIFT 5 |
| |
| /* PM_L2 :: CPU_MASK_CLEAR :: NMI_B_INTR [04:04] */ |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_SHIFT 4 |
| |
| /* PM_L2 :: CPU_MASK_CLEAR :: TIMER_INTR [03:03] */ |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_SHIFT 3 |
| |
| /* PM_L2 :: CPU_MASK_CLEAR :: KPD_INTR [02:02] */ |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_KPD_INTR_MASK 0x00000004 |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_KPD_INTR_SHIFT 2 |
| |
| /* PM_L2 :: CPU_MASK_CLEAR :: IRR_INTR [01:01] */ |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK 0x00000002 |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_IRR_INTR_SHIFT 1 |
| |
| /* PM_L2 :: CPU_MASK_CLEAR :: CEC_INTR [00:00] */ |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_CEC_INTR_MASK 0x00000001 |
| #define BCHP_PM_L2_CPU_MASK_CLEAR_CEC_INTR_SHIFT 0 |
| |
| /*************************************************************************** |
| *PCI_STATUS - PCI interrupt Status Register |
| ***************************************************************************/ |
| /* PM_L2 :: PCI_STATUS :: reserved0 [31:18] */ |
| #define BCHP_PM_L2_PCI_STATUS_reserved0_MASK 0xfffc0000 |
| #define BCHP_PM_L2_PCI_STATUS_reserved0_SHIFT 18 |
| |
| /* PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_0 [17:17] */ |
| #define BCHP_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x00020000 |
| #define BCHP_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 17 |
| |
| /* PM_L2 :: PCI_STATUS :: XPT_PMU [16:16] */ |
| #define BCHP_PM_L2_PCI_STATUS_XPT_PMU_MASK 0x00010000 |
| #define BCHP_PM_L2_PCI_STATUS_XPT_PMU_SHIFT 16 |
| |
| /* PM_L2 :: PCI_STATUS :: FTM [15:15] */ |
| #define BCHP_PM_L2_PCI_STATUS_FTM_MASK 0x00008000 |
| #define BCHP_PM_L2_PCI_STATUS_FTM_SHIFT 15 |
| |
| /* PM_L2 :: PCI_STATUS :: QPSK_RCVR_1 [14:14] */ |
| #define BCHP_PM_L2_PCI_STATUS_QPSK_RCVR_1_MASK 0x00004000 |
| #define BCHP_PM_L2_PCI_STATUS_QPSK_RCVR_1_SHIFT 14 |
| |
| /* PM_L2 :: PCI_STATUS :: QPSK_RCVR_0 [13:13] */ |
| #define BCHP_PM_L2_PCI_STATUS_QPSK_RCVR_0_MASK 0x00002000 |
| #define BCHP_PM_L2_PCI_STATUS_QPSK_RCVR_0_SHIFT 13 |
| |
| /* PM_L2 :: PCI_STATUS :: SDS0_AFEC [12:12] */ |
| #define BCHP_PM_L2_PCI_STATUS_SDS0_AFEC_MASK 0x00001000 |
| #define BCHP_PM_L2_PCI_STATUS_SDS0_AFEC_SHIFT 12 |
| |
| /* PM_L2 :: PCI_STATUS :: SDS0_TFEC [11:11] */ |
| #define BCHP_PM_L2_PCI_STATUS_SDS0_TFEC_MASK 0x00000800 |
| #define BCHP_PM_L2_PCI_STATUS_SDS0_TFEC_SHIFT 11 |
| |
| /* PM_L2 :: PCI_STATUS :: SDS0_RCVR_1 [10:10] */ |
| #define BCHP_PM_L2_PCI_STATUS_SDS0_RCVR_1_MASK 0x00000400 |
| #define BCHP_PM_L2_PCI_STATUS_SDS0_RCVR_1_SHIFT 10 |
| |
| /* PM_L2 :: PCI_STATUS :: SDS0_RCVR_0 [09:09] */ |
| #define BCHP_PM_L2_PCI_STATUS_SDS0_RCVR_0_MASK 0x00000200 |
| #define BCHP_PM_L2_PCI_STATUS_SDS0_RCVR_0_SHIFT 9 |
| |
| /* PM_L2 :: PCI_STATUS :: WOL_ENET [08:08] */ |
| #define BCHP_PM_L2_PCI_STATUS_WOL_ENET_MASK 0x00000100 |
| #define BCHP_PM_L2_PCI_STATUS_WOL_ENET_SHIFT 8 |
| |
| /* PM_L2 :: PCI_STATUS :: WOL_MOCA [07:07] */ |
| #define BCHP_PM_L2_PCI_STATUS_WOL_MOCA_MASK 0x00000080 |
| #define BCHP_PM_L2_PCI_STATUS_WOL_MOCA_SHIFT 7 |
| |
| /* PM_L2 :: PCI_STATUS :: UHFR [06:06] */ |
| #define BCHP_PM_L2_PCI_STATUS_UHFR_MASK 0x00000040 |
| #define BCHP_PM_L2_PCI_STATUS_UHFR_SHIFT 6 |
| |
| /* PM_L2 :: PCI_STATUS :: GPIO [05:05] */ |
| #define BCHP_PM_L2_PCI_STATUS_GPIO_MASK 0x00000020 |
| #define BCHP_PM_L2_PCI_STATUS_GPIO_SHIFT 5 |
| |
| /* PM_L2 :: PCI_STATUS :: NMI_B_INTR [04:04] */ |
| #define BCHP_PM_L2_PCI_STATUS_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_PM_L2_PCI_STATUS_NMI_B_INTR_SHIFT 4 |
| |
| /* PM_L2 :: PCI_STATUS :: TIMER_INTR [03:03] */ |
| #define BCHP_PM_L2_PCI_STATUS_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_PM_L2_PCI_STATUS_TIMER_INTR_SHIFT 3 |
| |
| /* PM_L2 :: PCI_STATUS :: KPD_INTR [02:02] */ |
| #define BCHP_PM_L2_PCI_STATUS_KPD_INTR_MASK 0x00000004 |
| #define BCHP_PM_L2_PCI_STATUS_KPD_INTR_SHIFT 2 |
| |
| /* PM_L2 :: PCI_STATUS :: IRR_INTR [01:01] */ |
| #define BCHP_PM_L2_PCI_STATUS_IRR_INTR_MASK 0x00000002 |
| #define BCHP_PM_L2_PCI_STATUS_IRR_INTR_SHIFT 1 |
| |
| /* PM_L2 :: PCI_STATUS :: CEC_INTR [00:00] */ |
| #define BCHP_PM_L2_PCI_STATUS_CEC_INTR_MASK 0x00000001 |
| #define BCHP_PM_L2_PCI_STATUS_CEC_INTR_SHIFT 0 |
| |
| /*************************************************************************** |
| *PCI_SET - PCI interrupt Set Register |
| ***************************************************************************/ |
| /* PM_L2 :: PCI_SET :: reserved0 [31:18] */ |
| #define BCHP_PM_L2_PCI_SET_reserved0_MASK 0xfffc0000 |
| #define BCHP_PM_L2_PCI_SET_reserved0_SHIFT 18 |
| |
| /* PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_0 [17:17] */ |
| #define BCHP_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_MASK 0x00020000 |
| #define BCHP_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_SHIFT 17 |
| |
| /* PM_L2 :: PCI_SET :: XPT_PMU [16:16] */ |
| #define BCHP_PM_L2_PCI_SET_XPT_PMU_MASK 0x00010000 |
| #define BCHP_PM_L2_PCI_SET_XPT_PMU_SHIFT 16 |
| |
| /* PM_L2 :: PCI_SET :: FTM [15:15] */ |
| #define BCHP_PM_L2_PCI_SET_FTM_MASK 0x00008000 |
| #define BCHP_PM_L2_PCI_SET_FTM_SHIFT 15 |
| |
| /* PM_L2 :: PCI_SET :: QPSK_RCVR_1 [14:14] */ |
| #define BCHP_PM_L2_PCI_SET_QPSK_RCVR_1_MASK 0x00004000 |
| #define BCHP_PM_L2_PCI_SET_QPSK_RCVR_1_SHIFT 14 |
| |
| /* PM_L2 :: PCI_SET :: QPSK_RCVR_0 [13:13] */ |
| #define BCHP_PM_L2_PCI_SET_QPSK_RCVR_0_MASK 0x00002000 |
| #define BCHP_PM_L2_PCI_SET_QPSK_RCVR_0_SHIFT 13 |
| |
| /* PM_L2 :: PCI_SET :: SDS0_AFEC [12:12] */ |
| #define BCHP_PM_L2_PCI_SET_SDS0_AFEC_MASK 0x00001000 |
| #define BCHP_PM_L2_PCI_SET_SDS0_AFEC_SHIFT 12 |
| |
| /* PM_L2 :: PCI_SET :: SDS0_TFEC [11:11] */ |
| #define BCHP_PM_L2_PCI_SET_SDS0_TFEC_MASK 0x00000800 |
| #define BCHP_PM_L2_PCI_SET_SDS0_TFEC_SHIFT 11 |
| |
| /* PM_L2 :: PCI_SET :: SDS0_RCVR_1 [10:10] */ |
| #define BCHP_PM_L2_PCI_SET_SDS0_RCVR_1_MASK 0x00000400 |
| #define BCHP_PM_L2_PCI_SET_SDS0_RCVR_1_SHIFT 10 |
| |
| /* PM_L2 :: PCI_SET :: SDS0_RCVR_0 [09:09] */ |
| #define BCHP_PM_L2_PCI_SET_SDS0_RCVR_0_MASK 0x00000200 |
| #define BCHP_PM_L2_PCI_SET_SDS0_RCVR_0_SHIFT 9 |
| |
| /* PM_L2 :: PCI_SET :: WOL_ENET [08:08] */ |
| #define BCHP_PM_L2_PCI_SET_WOL_ENET_MASK 0x00000100 |
| #define BCHP_PM_L2_PCI_SET_WOL_ENET_SHIFT 8 |
| |
| /* PM_L2 :: PCI_SET :: WOL_MOCA [07:07] */ |
| #define BCHP_PM_L2_PCI_SET_WOL_MOCA_MASK 0x00000080 |
| #define BCHP_PM_L2_PCI_SET_WOL_MOCA_SHIFT 7 |
| |
| /* PM_L2 :: PCI_SET :: UHFR [06:06] */ |
| #define BCHP_PM_L2_PCI_SET_UHFR_MASK 0x00000040 |
| #define BCHP_PM_L2_PCI_SET_UHFR_SHIFT 6 |
| |
| /* PM_L2 :: PCI_SET :: GPIO [05:05] */ |
| #define BCHP_PM_L2_PCI_SET_GPIO_MASK 0x00000020 |
| #define BCHP_PM_L2_PCI_SET_GPIO_SHIFT 5 |
| |
| /* PM_L2 :: PCI_SET :: NMI_B_INTR [04:04] */ |
| #define BCHP_PM_L2_PCI_SET_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_PM_L2_PCI_SET_NMI_B_INTR_SHIFT 4 |
| |
| /* PM_L2 :: PCI_SET :: TIMER_INTR [03:03] */ |
| #define BCHP_PM_L2_PCI_SET_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_PM_L2_PCI_SET_TIMER_INTR_SHIFT 3 |
| |
| /* PM_L2 :: PCI_SET :: KPD_INTR [02:02] */ |
| #define BCHP_PM_L2_PCI_SET_KPD_INTR_MASK 0x00000004 |
| #define BCHP_PM_L2_PCI_SET_KPD_INTR_SHIFT 2 |
| |
| /* PM_L2 :: PCI_SET :: IRR_INTR [01:01] */ |
| #define BCHP_PM_L2_PCI_SET_IRR_INTR_MASK 0x00000002 |
| #define BCHP_PM_L2_PCI_SET_IRR_INTR_SHIFT 1 |
| |
| /* PM_L2 :: PCI_SET :: CEC_INTR [00:00] */ |
| #define BCHP_PM_L2_PCI_SET_CEC_INTR_MASK 0x00000001 |
| #define BCHP_PM_L2_PCI_SET_CEC_INTR_SHIFT 0 |
| |
| /*************************************************************************** |
| *PCI_CLEAR - PCI interrupt Clear Register |
| ***************************************************************************/ |
| /* PM_L2 :: PCI_CLEAR :: reserved0 [31:18] */ |
| #define BCHP_PM_L2_PCI_CLEAR_reserved0_MASK 0xfffc0000 |
| #define BCHP_PM_L2_PCI_CLEAR_reserved0_SHIFT 18 |
| |
| /* PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_0 [17:17] */ |
| #define BCHP_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x00020000 |
| #define BCHP_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 17 |
| |
| /* PM_L2 :: PCI_CLEAR :: XPT_PMU [16:16] */ |
| #define BCHP_PM_L2_PCI_CLEAR_XPT_PMU_MASK 0x00010000 |
| #define BCHP_PM_L2_PCI_CLEAR_XPT_PMU_SHIFT 16 |
| |
| /* PM_L2 :: PCI_CLEAR :: FTM [15:15] */ |
| #define BCHP_PM_L2_PCI_CLEAR_FTM_MASK 0x00008000 |
| #define BCHP_PM_L2_PCI_CLEAR_FTM_SHIFT 15 |
| |
| /* PM_L2 :: PCI_CLEAR :: QPSK_RCVR_1 [14:14] */ |
| #define BCHP_PM_L2_PCI_CLEAR_QPSK_RCVR_1_MASK 0x00004000 |
| #define BCHP_PM_L2_PCI_CLEAR_QPSK_RCVR_1_SHIFT 14 |
| |
| /* PM_L2 :: PCI_CLEAR :: QPSK_RCVR_0 [13:13] */ |
| #define BCHP_PM_L2_PCI_CLEAR_QPSK_RCVR_0_MASK 0x00002000 |
| #define BCHP_PM_L2_PCI_CLEAR_QPSK_RCVR_0_SHIFT 13 |
| |
| /* PM_L2 :: PCI_CLEAR :: SDS0_AFEC [12:12] */ |
| #define BCHP_PM_L2_PCI_CLEAR_SDS0_AFEC_MASK 0x00001000 |
| #define BCHP_PM_L2_PCI_CLEAR_SDS0_AFEC_SHIFT 12 |
| |
| /* PM_L2 :: PCI_CLEAR :: SDS0_TFEC [11:11] */ |
| #define BCHP_PM_L2_PCI_CLEAR_SDS0_TFEC_MASK 0x00000800 |
| #define BCHP_PM_L2_PCI_CLEAR_SDS0_TFEC_SHIFT 11 |
| |
| /* PM_L2 :: PCI_CLEAR :: SDS0_RCVR_1 [10:10] */ |
| #define BCHP_PM_L2_PCI_CLEAR_SDS0_RCVR_1_MASK 0x00000400 |
| #define BCHP_PM_L2_PCI_CLEAR_SDS0_RCVR_1_SHIFT 10 |
| |
| /* PM_L2 :: PCI_CLEAR :: SDS0_RCVR_0 [09:09] */ |
| #define BCHP_PM_L2_PCI_CLEAR_SDS0_RCVR_0_MASK 0x00000200 |
| #define BCHP_PM_L2_PCI_CLEAR_SDS0_RCVR_0_SHIFT 9 |
| |
| /* PM_L2 :: PCI_CLEAR :: WOL_ENET [08:08] */ |
| #define BCHP_PM_L2_PCI_CLEAR_WOL_ENET_MASK 0x00000100 |
| #define BCHP_PM_L2_PCI_CLEAR_WOL_ENET_SHIFT 8 |
| |
| /* PM_L2 :: PCI_CLEAR :: WOL_MOCA [07:07] */ |
| #define BCHP_PM_L2_PCI_CLEAR_WOL_MOCA_MASK 0x00000080 |
| #define BCHP_PM_L2_PCI_CLEAR_WOL_MOCA_SHIFT 7 |
| |
| /* PM_L2 :: PCI_CLEAR :: UHFR [06:06] */ |
| #define BCHP_PM_L2_PCI_CLEAR_UHFR_MASK 0x00000040 |
| #define BCHP_PM_L2_PCI_CLEAR_UHFR_SHIFT 6 |
| |
| /* PM_L2 :: PCI_CLEAR :: GPIO [05:05] */ |
| #define BCHP_PM_L2_PCI_CLEAR_GPIO_MASK 0x00000020 |
| #define BCHP_PM_L2_PCI_CLEAR_GPIO_SHIFT 5 |
| |
| /* PM_L2 :: PCI_CLEAR :: NMI_B_INTR [04:04] */ |
| #define BCHP_PM_L2_PCI_CLEAR_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_PM_L2_PCI_CLEAR_NMI_B_INTR_SHIFT 4 |
| |
| /* PM_L2 :: PCI_CLEAR :: TIMER_INTR [03:03] */ |
| #define BCHP_PM_L2_PCI_CLEAR_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_PM_L2_PCI_CLEAR_TIMER_INTR_SHIFT 3 |
| |
| /* PM_L2 :: PCI_CLEAR :: KPD_INTR [02:02] */ |
| #define BCHP_PM_L2_PCI_CLEAR_KPD_INTR_MASK 0x00000004 |
| #define BCHP_PM_L2_PCI_CLEAR_KPD_INTR_SHIFT 2 |
| |
| /* PM_L2 :: PCI_CLEAR :: IRR_INTR [01:01] */ |
| #define BCHP_PM_L2_PCI_CLEAR_IRR_INTR_MASK 0x00000002 |
| #define BCHP_PM_L2_PCI_CLEAR_IRR_INTR_SHIFT 1 |
| |
| /* PM_L2 :: PCI_CLEAR :: CEC_INTR [00:00] */ |
| #define BCHP_PM_L2_PCI_CLEAR_CEC_INTR_MASK 0x00000001 |
| #define BCHP_PM_L2_PCI_CLEAR_CEC_INTR_SHIFT 0 |
| |
| /*************************************************************************** |
| *PCI_MASK_STATUS - PCI interrupt Mask Status Register |
| ***************************************************************************/ |
| /* PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:18] */ |
| #define BCHP_PM_L2_PCI_MASK_STATUS_reserved0_MASK 0xfffc0000 |
| #define BCHP_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT 18 |
| |
| /* PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [17:17] */ |
| #define BCHP_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x00020000 |
| #define BCHP_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 17 |
| |
| /* PM_L2 :: PCI_MASK_STATUS :: XPT_PMU [16:16] */ |
| #define BCHP_PM_L2_PCI_MASK_STATUS_XPT_PMU_MASK 0x00010000 |
| #define BCHP_PM_L2_PCI_MASK_STATUS_XPT_PMU_SHIFT 16 |
| |
| /* PM_L2 :: PCI_MASK_STATUS :: FTM [15:15] */ |
| #define BCHP_PM_L2_PCI_MASK_STATUS_FTM_MASK 0x00008000 |
| #define BCHP_PM_L2_PCI_MASK_STATUS_FTM_SHIFT 15 |
| |
| /* PM_L2 :: PCI_MASK_STATUS :: QPSK_RCVR_1 [14:14] */ |
| #define BCHP_PM_L2_PCI_MASK_STATUS_QPSK_RCVR_1_MASK 0x00004000 |
| #define BCHP_PM_L2_PCI_MASK_STATUS_QPSK_RCVR_1_SHIFT 14 |
| |
| /* PM_L2 :: PCI_MASK_STATUS :: QPSK_RCVR_0 [13:13] */ |
| #define BCHP_PM_L2_PCI_MASK_STATUS_QPSK_RCVR_0_MASK 0x00002000 |
| #define BCHP_PM_L2_PCI_MASK_STATUS_QPSK_RCVR_0_SHIFT 13 |
| |
| /* PM_L2 :: PCI_MASK_STATUS :: SDS0_AFEC [12:12] */ |
| #define BCHP_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_MASK 0x00001000 |
| #define BCHP_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_SHIFT 12 |
| |
| /* PM_L2 :: PCI_MASK_STATUS :: SDS0_TFEC [11:11] */ |
| #define BCHP_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_MASK 0x00000800 |
| #define BCHP_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_SHIFT 11 |
| |
| /* PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_1 [10:10] */ |
| #define BCHP_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_MASK 0x00000400 |
| #define BCHP_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_SHIFT 10 |
| |
| /* PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_0 [09:09] */ |
| #define BCHP_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_MASK 0x00000200 |
| #define BCHP_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_SHIFT 9 |
| |
| /* PM_L2 :: PCI_MASK_STATUS :: WOL_ENET [08:08] */ |
| #define BCHP_PM_L2_PCI_MASK_STATUS_WOL_ENET_MASK 0x00000100 |
| #define BCHP_PM_L2_PCI_MASK_STATUS_WOL_ENET_SHIFT 8 |
| |
| /* PM_L2 :: PCI_MASK_STATUS :: WOL_MOCA [07:07] */ |
| #define BCHP_PM_L2_PCI_MASK_STATUS_WOL_MOCA_MASK 0x00000080 |
| #define BCHP_PM_L2_PCI_MASK_STATUS_WOL_MOCA_SHIFT 7 |
| |
| /* PM_L2 :: PCI_MASK_STATUS :: UHFR [06:06] */ |
| #define BCHP_PM_L2_PCI_MASK_STATUS_UHFR_MASK 0x00000040 |
| #define BCHP_PM_L2_PCI_MASK_STATUS_UHFR_SHIFT 6 |
| |
| /* PM_L2 :: PCI_MASK_STATUS :: GPIO [05:05] */ |
| #define BCHP_PM_L2_PCI_MASK_STATUS_GPIO_MASK 0x00000020 |
| #define BCHP_PM_L2_PCI_MASK_STATUS_GPIO_SHIFT 5 |
| |
| /* PM_L2 :: PCI_MASK_STATUS :: NMI_B_INTR [04:04] */ |
| #define BCHP_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_SHIFT 4 |
| |
| /* PM_L2 :: PCI_MASK_STATUS :: TIMER_INTR [03:03] */ |
| #define BCHP_PM_L2_PCI_MASK_STATUS_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_PM_L2_PCI_MASK_STATUS_TIMER_INTR_SHIFT 3 |
| |
| /* PM_L2 :: PCI_MASK_STATUS :: KPD_INTR [02:02] */ |
| #define BCHP_PM_L2_PCI_MASK_STATUS_KPD_INTR_MASK 0x00000004 |
| #define BCHP_PM_L2_PCI_MASK_STATUS_KPD_INTR_SHIFT 2 |
| |
| /* PM_L2 :: PCI_MASK_STATUS :: IRR_INTR [01:01] */ |
| #define BCHP_PM_L2_PCI_MASK_STATUS_IRR_INTR_MASK 0x00000002 |
| #define BCHP_PM_L2_PCI_MASK_STATUS_IRR_INTR_SHIFT 1 |
| |
| /* PM_L2 :: PCI_MASK_STATUS :: CEC_INTR [00:00] */ |
| #define BCHP_PM_L2_PCI_MASK_STATUS_CEC_INTR_MASK 0x00000001 |
| #define BCHP_PM_L2_PCI_MASK_STATUS_CEC_INTR_SHIFT 0 |
| |
| /*************************************************************************** |
| *PCI_MASK_SET - PCI interrupt Mask Set Register |
| ***************************************************************************/ |
| /* PM_L2 :: PCI_MASK_SET :: reserved0 [31:18] */ |
| #define BCHP_PM_L2_PCI_MASK_SET_reserved0_MASK 0xfffc0000 |
| #define BCHP_PM_L2_PCI_MASK_SET_reserved0_SHIFT 18 |
| |
| /* PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_0 [17:17] */ |
| #define BCHP_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK 0x00020000 |
| #define BCHP_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT 17 |
| |
| /* PM_L2 :: PCI_MASK_SET :: XPT_PMU [16:16] */ |
| #define BCHP_PM_L2_PCI_MASK_SET_XPT_PMU_MASK 0x00010000 |
| #define BCHP_PM_L2_PCI_MASK_SET_XPT_PMU_SHIFT 16 |
| |
| /* PM_L2 :: PCI_MASK_SET :: FTM [15:15] */ |
| #define BCHP_PM_L2_PCI_MASK_SET_FTM_MASK 0x00008000 |
| #define BCHP_PM_L2_PCI_MASK_SET_FTM_SHIFT 15 |
| |
| /* PM_L2 :: PCI_MASK_SET :: QPSK_RCVR_1 [14:14] */ |
| #define BCHP_PM_L2_PCI_MASK_SET_QPSK_RCVR_1_MASK 0x00004000 |
| #define BCHP_PM_L2_PCI_MASK_SET_QPSK_RCVR_1_SHIFT 14 |
| |
| /* PM_L2 :: PCI_MASK_SET :: QPSK_RCVR_0 [13:13] */ |
| #define BCHP_PM_L2_PCI_MASK_SET_QPSK_RCVR_0_MASK 0x00002000 |
| #define BCHP_PM_L2_PCI_MASK_SET_QPSK_RCVR_0_SHIFT 13 |
| |
| /* PM_L2 :: PCI_MASK_SET :: SDS0_AFEC [12:12] */ |
| #define BCHP_PM_L2_PCI_MASK_SET_SDS0_AFEC_MASK 0x00001000 |
| #define BCHP_PM_L2_PCI_MASK_SET_SDS0_AFEC_SHIFT 12 |
| |
| /* PM_L2 :: PCI_MASK_SET :: SDS0_TFEC [11:11] */ |
| #define BCHP_PM_L2_PCI_MASK_SET_SDS0_TFEC_MASK 0x00000800 |
| #define BCHP_PM_L2_PCI_MASK_SET_SDS0_TFEC_SHIFT 11 |
| |
| /* PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_1 [10:10] */ |
| #define BCHP_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_MASK 0x00000400 |
| #define BCHP_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_SHIFT 10 |
| |
| /* PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_0 [09:09] */ |
| #define BCHP_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_MASK 0x00000200 |
| #define BCHP_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_SHIFT 9 |
| |
| /* PM_L2 :: PCI_MASK_SET :: WOL_ENET [08:08] */ |
| #define BCHP_PM_L2_PCI_MASK_SET_WOL_ENET_MASK 0x00000100 |
| #define BCHP_PM_L2_PCI_MASK_SET_WOL_ENET_SHIFT 8 |
| |
| /* PM_L2 :: PCI_MASK_SET :: WOL_MOCA [07:07] */ |
| #define BCHP_PM_L2_PCI_MASK_SET_WOL_MOCA_MASK 0x00000080 |
| #define BCHP_PM_L2_PCI_MASK_SET_WOL_MOCA_SHIFT 7 |
| |
| /* PM_L2 :: PCI_MASK_SET :: UHFR [06:06] */ |
| #define BCHP_PM_L2_PCI_MASK_SET_UHFR_MASK 0x00000040 |
| #define BCHP_PM_L2_PCI_MASK_SET_UHFR_SHIFT 6 |
| |
| /* PM_L2 :: PCI_MASK_SET :: GPIO [05:05] */ |
| #define BCHP_PM_L2_PCI_MASK_SET_GPIO_MASK 0x00000020 |
| #define BCHP_PM_L2_PCI_MASK_SET_GPIO_SHIFT 5 |
| |
| /* PM_L2 :: PCI_MASK_SET :: NMI_B_INTR [04:04] */ |
| #define BCHP_PM_L2_PCI_MASK_SET_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_PM_L2_PCI_MASK_SET_NMI_B_INTR_SHIFT 4 |
| |
| /* PM_L2 :: PCI_MASK_SET :: TIMER_INTR [03:03] */ |
| #define BCHP_PM_L2_PCI_MASK_SET_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_PM_L2_PCI_MASK_SET_TIMER_INTR_SHIFT 3 |
| |
| /* PM_L2 :: PCI_MASK_SET :: KPD_INTR [02:02] */ |
| #define BCHP_PM_L2_PCI_MASK_SET_KPD_INTR_MASK 0x00000004 |
| #define BCHP_PM_L2_PCI_MASK_SET_KPD_INTR_SHIFT 2 |
| |
| /* PM_L2 :: PCI_MASK_SET :: IRR_INTR [01:01] */ |
| #define BCHP_PM_L2_PCI_MASK_SET_IRR_INTR_MASK 0x00000002 |
| #define BCHP_PM_L2_PCI_MASK_SET_IRR_INTR_SHIFT 1 |
| |
| /* PM_L2 :: PCI_MASK_SET :: CEC_INTR [00:00] */ |
| #define BCHP_PM_L2_PCI_MASK_SET_CEC_INTR_MASK 0x00000001 |
| #define BCHP_PM_L2_PCI_MASK_SET_CEC_INTR_SHIFT 0 |
| |
| /*************************************************************************** |
| *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register |
| ***************************************************************************/ |
| /* PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:18] */ |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_reserved0_MASK 0xfffc0000 |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT 18 |
| |
| /* PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [17:17] */ |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x00020000 |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 17 |
| |
| /* PM_L2 :: PCI_MASK_CLEAR :: XPT_PMU [16:16] */ |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_XPT_PMU_MASK 0x00010000 |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_XPT_PMU_SHIFT 16 |
| |
| /* PM_L2 :: PCI_MASK_CLEAR :: FTM [15:15] */ |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_FTM_MASK 0x00008000 |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_FTM_SHIFT 15 |
| |
| /* PM_L2 :: PCI_MASK_CLEAR :: QPSK_RCVR_1 [14:14] */ |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_QPSK_RCVR_1_MASK 0x00004000 |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_QPSK_RCVR_1_SHIFT 14 |
| |
| /* PM_L2 :: PCI_MASK_CLEAR :: QPSK_RCVR_0 [13:13] */ |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_QPSK_RCVR_0_MASK 0x00002000 |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_QPSK_RCVR_0_SHIFT 13 |
| |
| /* PM_L2 :: PCI_MASK_CLEAR :: SDS0_AFEC [12:12] */ |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_MASK 0x00001000 |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_SHIFT 12 |
| |
| /* PM_L2 :: PCI_MASK_CLEAR :: SDS0_TFEC [11:11] */ |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_MASK 0x00000800 |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_SHIFT 11 |
| |
| /* PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_1 [10:10] */ |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_MASK 0x00000400 |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_SHIFT 10 |
| |
| /* PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_0 [09:09] */ |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_MASK 0x00000200 |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_SHIFT 9 |
| |
| /* PM_L2 :: PCI_MASK_CLEAR :: WOL_ENET [08:08] */ |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_WOL_ENET_MASK 0x00000100 |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_WOL_ENET_SHIFT 8 |
| |
| /* PM_L2 :: PCI_MASK_CLEAR :: WOL_MOCA [07:07] */ |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_WOL_MOCA_MASK 0x00000080 |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_WOL_MOCA_SHIFT 7 |
| |
| /* PM_L2 :: PCI_MASK_CLEAR :: UHFR [06:06] */ |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_UHFR_MASK 0x00000040 |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_UHFR_SHIFT 6 |
| |
| /* PM_L2 :: PCI_MASK_CLEAR :: GPIO [05:05] */ |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_GPIO_MASK 0x00000020 |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_GPIO_SHIFT 5 |
| |
| /* PM_L2 :: PCI_MASK_CLEAR :: NMI_B_INTR [04:04] */ |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_SHIFT 4 |
| |
| /* PM_L2 :: PCI_MASK_CLEAR :: TIMER_INTR [03:03] */ |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_SHIFT 3 |
| |
| /* PM_L2 :: PCI_MASK_CLEAR :: KPD_INTR [02:02] */ |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_KPD_INTR_MASK 0x00000004 |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_KPD_INTR_SHIFT 2 |
| |
| /* PM_L2 :: PCI_MASK_CLEAR :: IRR_INTR [01:01] */ |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_IRR_INTR_MASK 0x00000002 |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_IRR_INTR_SHIFT 1 |
| |
| /* PM_L2 :: PCI_MASK_CLEAR :: CEC_INTR [00:00] */ |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_CEC_INTR_MASK 0x00000001 |
| #define BCHP_PM_L2_PCI_MASK_CLEAR_CEC_INTR_SHIFT 0 |
| |
| #endif /* #ifndef BCHP_PM_L2_H__ */ |
| |
| /* End of File */ |
